| 1 | /*␊ |
| 2 | * Copyright 2008 Islam Ahmed Zaid. All rights reserved. <azismed@gmail.com>␊ |
| 3 | * AsereBLN: 2009: cleanup and bugfix␊ |
| 4 | * valv: 2010: fine-tuning and additions␊ |
| 5 | */␊ |
| 6 | ␊ |
| 7 | #ifndef __LIBSAIO_CPU_H␊ |
| 8 | #define __LIBSAIO_CPU_H␊ |
| 9 | ␊ |
| 10 | #include "libsaio.h"␊ |
| 11 | ␊ |
| 12 | extern void scan_cpu(PlatformInfo_t *);␊ |
| 13 | ␊ |
| 14 | #define bit(n)␉␉␉(1UL << (n))␊ |
| 15 | #define bitmask(h,l)␉␉((bit(h)|(bit(h)-1)) & ~(bit(l)-1))␊ |
| 16 | #define bitfield(x,h,l)␉␉(((x) & bitmask(h,l)) >> l)␊ |
| 17 | ␊ |
| 18 | #define CPU_STRING_UNKNOWN␉␉"Unknown CPU Type"␊ |
| 19 | ␊ |
| 20 | #define MSR_FSB_FREQ 0xCD␊ |
| 21 | #define MSR_EBC_FREQUENCY_ID 0x2C␊ |
| 22 | #define MSR_TURBO_RATIO_LIMIT 0x1AD␊ |
| 23 | #define MSR_IA32_PLATFORM_ID 0x17␊ |
| 24 | #define␉MSR_IA32_PERF_STATUS 0x198␊ |
| 25 | #define MSR_IA32_PERF_CONTROL 0x199␊ |
| 26 | #define MSR_IA32_EXT_CONFIG 0xEE␊ |
| 27 | #define MSR_FLEX_RATIO 0x194␊ |
| 28 | #define␉MSR_PLATFORM_INFO 0xCE␊ |
| 29 | #define MSR_IA32_MISC_ENABLE 0x1A0␊ |
| 30 | #define MSR_THERMAL_STATUS 0x19C␊ |
| 31 | #define MSR_IA32_CLOCK_MODULATION 0x19A␊ |
| 32 | #define MSR_THERMAL_TARGET 0x01A2␊ |
| 33 | #define PIC_SENS_CFG 0x1aa␊ |
| 34 | #define MSR_EBL_CR_POWERON 0x02a␊ |
| 35 | #define K8_FIDVID_STATUS 0xC0010042␊ |
| 36 | #define␉AMD_10H_11H_CONFIG 0xc0010064␊ |
| 37 | #define K10_COFVID_STATUS 0xC0010071␊ |
| 38 | ␊ |
| 39 | #define DEFAULT_FSB␉␉100000 /* for now, hardcoding 100MHz for old CPUs */␊ |
| 40 | ␊ |
| 41 | // DFE: This constant comes from older xnu:␊ |
| 42 | #define CLKNUM␉␉␉1193182␉␉/* formerly 1193167 */␊ |
| 43 | ␊ |
| 44 | // DFE: These two constants come from Linux except CLOCK_TICK_RATE replaced with CLKNUM␊ |
| 45 | #define CALIBRATE_TIME_MSEC␉30␉␉/* 30 msecs */␊ |
| 46 | #define CALIBRATE_LATCH␉␉((CLKNUM * CALIBRATE_TIME_MSEC + 1000/2)/1000)␊ |
| 47 | ␊ |
| 48 | static inline uint64_t rdtsc64(void)␊ |
| 49 | {␊ |
| 50 | ␉uint64_t ret;␊ |
| 51 | ␉__asm__ volatile("rdtsc" : "=A" (ret));␊ |
| 52 | ␉return ret;␊ |
| 53 | }␊ |
| 54 | ␊ |
| 55 | static inline uint64_t rdmsr64(uint32_t msr)␊ |
| 56 | {␊ |
| 57 | uint64_t ret;␊ |
| 58 | __asm__ volatile("rdmsr" : "=A" (ret) : "c" (msr));␊ |
| 59 | return ret;␊ |
| 60 | }␊ |
| 61 | ␊ |
| 62 | static inline void wrmsr64(uint32_t msr, uint64_t val)␊ |
| 63 | {␊ |
| 64 | ␉__asm__ volatile("wrmsr" : : "c" (msr), "A" (val));␊ |
| 65 | }␊ |
| 66 | ␊ |
| 67 | typedef struct msr_struct␊ |
| 68 | {␊ |
| 69 | ␉unsigned lo;␊ |
| 70 | ␉unsigned hi;␊ |
| 71 | } msr_t;␊ |
| 72 | ␊ |
| 73 | static inline __attribute__((always_inline)) msr_t rdmsr(unsigned val)␊ |
| 74 | {␊ |
| 75 | ␉msr_t ret;␊ |
| 76 | ␉__asm__ volatile(␊ |
| 77 | ␉␉"rdmsr"␊ |
| 78 | ␉␉: "=a" (ret.lo), "=d" (ret.hi)␊ |
| 79 | ␉␉: "c" (val)␊ |
| 80 | ␉␉);␊ |
| 81 | ␉return ret;␊ |
| 82 | }␊ |
| 83 | ␊ |
| 84 | static inline __attribute__((always_inline)) void wrmsr(unsigned val, msr_t msr)␊ |
| 85 | {␊ |
| 86 | ␉__asm__ __volatile__ (␊ |
| 87 | ␉␉"wrmsr"␊ |
| 88 | ␉␉: /* No outputs */␊ |
| 89 | ␉␉: "c" (val), "a" (msr.lo), "d" (msr.hi)␊ |
| 90 | ␉␉);␊ |
| 91 | }␊ |
| 92 | ␊ |
| 93 | static inline void intel_waitforsts(void) {␊ |
| 94 | ␉uint32_t inline_timeout = 100000;␊ |
| 95 | ␉while (rdmsr64(MSR_IA32_PERF_STATUS) & (1 << 21)) { if (!inline_timeout--) break; }␊ |
| 96 | }␊ |
| 97 | ␊ |
| 98 | static inline void do_cpuid(uint32_t selector, uint32_t *data)␊ |
| 99 | {␊ |
| 100 | ␉asm volatile ("cpuid"␊ |
| 101 | ␉␉␉␉ : "=a" (data[0]),␊ |
| 102 | ␉␉␉␉ "=b" (data[1]),␊ |
| 103 | ␉␉␉␉ "=c" (data[2]),␊ |
| 104 | ␉␉␉␉ "=d" (data[3])␊ |
| 105 | ␉␉␉␉ : "a" (selector));␊ |
| 106 | }␊ |
| 107 | ␊ |
| 108 | static inline void do_cpuid2(uint32_t selector, uint32_t selector2, uint32_t *data)␊ |
| 109 | {␊ |
| 110 | ␉asm volatile ("cpuid"␊ |
| 111 | ␉␉␉␉ : "=a" (data[0]),␊ |
| 112 | ␉␉␉␉ "=b" (data[1]),␊ |
| 113 | ␉␉␉␉ "=c" (data[2]),␊ |
| 114 | ␉␉␉␉ "=d" (data[3])␊ |
| 115 | ␉␉␉␉ : "a" (selector), "c" (selector2));␊ |
| 116 | }␊ |
| 117 | ␊ |
| 118 | // DFE: enable_PIT2 and disable_PIT2 come from older xnu␊ |
| 119 | ␊ |
| 120 | /*␊ |
| 121 | * Enable or disable timer 2.␊ |
| 122 | * Port 0x61 controls timer 2:␊ |
| 123 | * bit 0 gates the clock,␊ |
| 124 | * bit 1 gates output to speaker.␊ |
| 125 | */␊ |
| 126 | static inline void enable_PIT2(void)␊ |
| 127 | {␊ |
| 128 | /* Enable gate, disable speaker */␊ |
| 129 | __asm__ volatile(␊ |
| 130 | ␉␉␉␉␉ " inb $0x61,%%al \n\t"␊ |
| 131 | ␉␉␉␉␉ " and $0xFC,%%al \n\t" /* & ~0x03 */␊ |
| 132 | ␉␉␉␉␉ " or $1,%%al \n\t"␊ |
| 133 | ␉␉␉␉␉ " outb %%al,$0x61 \n\t"␊ |
| 134 | ␉␉␉␉␉ : : : "%al" );␊ |
| 135 | }␊ |
| 136 | ␊ |
| 137 | static inline void disable_PIT2(void)␊ |
| 138 | {␊ |
| 139 | /* Disable gate and output to speaker */␊ |
| 140 | __asm__ volatile(␊ |
| 141 | ␉␉␉␉␉ " inb $0x61,%%al \n\t"␊ |
| 142 | ␉␉␉␉␉ " and $0xFC,%%al \n\t"␉/* & ~0x03 */␊ |
| 143 | ␉␉␉␉␉ " outb %%al,$0x61 \n\t"␊ |
| 144 | ␉␉␉␉␉ : : : "%al" );␊ |
| 145 | }␊ |
| 146 | ␊ |
| 147 | // DFE: set_PIT2_mode0, poll_PIT2_gate, and measure_tsc_frequency are␊ |
| 148 | // roughly based on Linux code␊ |
| 149 | ␊ |
| 150 | /* Set the 8254 channel 2 to mode 0 with the specified value.␊ |
| 151 | In mode 0, the counter will initially set its gate low when the␊ |
| 152 | timer expires. For this to be useful, you ought to set it high␊ |
| 153 | before calling this function. The enable_PIT2 function does this.␊ |
| 154 | */␊ |
| 155 | static inline void set_PIT2_mode0(uint16_t value)␊ |
| 156 | {␊ |
| 157 | __asm__ volatile(␊ |
| 158 | ␉␉␉␉␉ " movb $0xB0,%%al \n\t"␊ |
| 159 | ␉␉␉␉␉ " outb␉%%al,$0x43␉\n\t"␊ |
| 160 | ␉␉␉␉␉ " movb␉%%dl,%%al␉\n\t"␊ |
| 161 | ␉␉␉␉␉ " outb␉%%al,$0x42␉\n\t"␊ |
| 162 | ␉␉␉␉␉ " movb␉%%dh,%%al␉\n\t"␊ |
| 163 | ␉␉␉␉␉ " outb␉%%al,$0x42"␊ |
| 164 | ␉␉␉␉␉ : : "d"(value) /*: no clobber */ );␊ |
| 165 | }␊ |
| 166 | ␊ |
| 167 | /* Returns the number of times the loop ran before the PIT2 signaled */␊ |
| 168 | static inline unsigned long poll_PIT2_gate(void)␊ |
| 169 | {␊ |
| 170 | unsigned long count = 0;␊ |
| 171 | unsigned char nmi_sc_val;␊ |
| 172 | do {␊ |
| 173 | ++count;␊ |
| 174 | __asm__ volatile(␊ |
| 175 | ␉␉␉␉␉␉ "inb␉$0x61,%0"␊ |
| 176 | ␉␉␉␉␉␉ : "=q"(nmi_sc_val) /*:*/ /* no input */ /*:*/ /* no clobber */);␊ |
| 177 | } while( (nmi_sc_val & 0x20) == 0);␊ |
| 178 | return count;␊ |
| 179 | }␊ |
| 180 | ␊ |
| 181 | #endif /* !__LIBSAIO_CPU_H */␊ |
| 182 | |
