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1/*␊
2 * Copyright 2008 Islam Ahmed Zaid. All rights reserved. <azismed@gmail.com>␊
3 * AsereBLN: 2009: cleanup and bugfix␊
4 * valv: 2010: fine-tuning and additions␊
5 */␊
6␊
7#include "libsaio.h"␊
8#include "platform.h"␊
9#include "cpu.h"␊
10#include "boot.h"␊
11#include "bootstruct.h"␊
12␊
13#ifndef DEBUG_CPU␊
14#define DEBUG_CPU 0␊
15#endif␊
16␊
17#if DEBUG_CPU␊
18#define DBG(x...)␉␉printf(x)␊
19#else␊
20#define DBG(x...)␉␉msglog(x)␊
21#endif␊
22␊
23/*␊
24 * DFE: Measures the TSC frequency in Hz (64-bit) using the ACPI PM timer␊
25 */␊
26static uint64_t measure_tsc_frequency(void)␊
27{␊
28 uint64_t tscStart;␊
29 uint64_t tscEnd;␊
30 uint64_t tscDelta = 0xffffffffffffffffULL;␊
31 unsigned long pollCount;␊
32 uint64_t retval = 0;␊
33 int i;␊
34␊
35 /* Time how many TSC ticks elapse in 30 msec using the 8254 PIT␊
36 * counter 2. We run this loop 3 times to make sure the cache␊
37 * is hot and we take the minimum delta from all of the runs.␊
38 * That is to say that we're biased towards measuring the minimum␊
39 * number of TSC ticks that occur while waiting for the timer to␊
40 * expire. That theoretically helps avoid inconsistencies when␊
41 * running under a VM if the TSC is not virtualized and the host␊
42 * steals time. The TSC is normally virtualized for VMware.␊
43 */␊
44 for(i = 0; i < 10; ++i)␊
45 {␊
46 enable_PIT2();␊
47 set_PIT2_mode0(CALIBRATE_LATCH);␊
48 tscStart = rdtsc64();␊
49 pollCount = poll_PIT2_gate();␊
50 tscEnd = rdtsc64();␊
51 /* The poll loop must have run at least a few times for accuracy */␊
52 if(pollCount <= 1)␊
53 continue;␊
54 /* The TSC must increment at LEAST once every millisecond. We␊
55 * should have waited exactly 30 msec so the TSC delta should␊
56 * be >= 30. Anything less and the processor is way too slow.␊
57 */␊
58 if((tscEnd - tscStart) <= CALIBRATE_TIME_MSEC)␊
59 continue;␊
60 // tscDelta = min(tscDelta, (tscEnd - tscStart))␊
61 if( (tscEnd - tscStart) < tscDelta )␊
62 tscDelta = tscEnd - tscStart;␊
63 }␊
64 /* tscDelta is now the least number of TSC ticks the processor made in␊
65 * a timespan of 0.03 s (e.g. 30 milliseconds)␊
66 * Linux thus divides by 30 which gives the answer in kiloHertz because␊
67 * 1 / ms = kHz. But we're xnu and most of the rest of the code uses␊
68 * Hz so we need to convert our milliseconds to seconds. Since we're␊
69 * dividing by the milliseconds, we simply multiply by 1000.␊
70 */␊
71␊
72 /* Unlike linux, we're not limited to 32-bit, but we do need to take care␊
73 * that we're going to multiply by 1000 first so we do need at least some␊
74 * arithmetic headroom. For now, 32-bit should be enough.␊
75 * Also unlike Linux, our compiler can do 64-bit integer arithmetic.␊
76 */␊
77 if(tscDelta > (1ULL<<32))␊
78 retval = 0;␊
79 else␊
80 {␊
81 retval = tscDelta * 1000 / 30;␊
82 }␊
83 disable_PIT2();␊
84 return retval;␊
85}␊
86␊
87␊
88/*␊
89 * Calculates the FSB and CPU frequencies using specific MSRs for each CPU␊
90 * - multi. is read from a specific MSR. In the case of Intel, there is:␊
91 * a max multi. (used to calculate the FSB freq.),␊
92 * and a current multi. (used to calculate the CPU freq.)␊
93 * - fsbFrequency = tscFrequency / multi␊
94 * - cpuFrequency = fsbFrequency * multi␊
95 */␊
96␊
97void scan_cpu(PlatformInfo_t *p)␊
98{␊
99␉const char␉*newratio, *newfsb;␊
100␉int␉␉␉len, myfsb, i;␊
101␉uint64_t␉tscFrequency, fsbFrequency, cpuFrequency, fsbi;␊
102␉uint64_t␉msr, flex_ratio = 0;␊
103␉uint32_t␉tms, ida, max_ratio, min_ratio;␊
104␉uint8_t␉␉bus_ratio_max, maxdiv, bus_ratio_min, currdiv;␊
105␉bool␉␉fix_fsb, did, core_i, turbo, isatom, fsbad;␊
106␊
107␉max_ratio = min_ratio = myfsb = bus_ratio_max = maxdiv = bus_ratio_min = currdiv = i = 0;␊
108␊
109␉/* get cpuid values */␊
110␉for( ; i <= 3; i++)␊
111␉{␊
112␉␉do_cpuid(i, p->CPU.CPUID[i]);␊
113␉}␊
114␉␊
115␉do_cpuid2(0x00000004, 0, p->CPU.CPUID[CPUID_4]);␊
116␉do_cpuid(0x80000000, p->CPU.CPUID[CPUID_80]);␊
117␉if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 1) {␊
118␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊
119␉}␊
120#if DEBUG_CPU␊
121␉{␊
122␉␉int␉␉i;␊
123␉␉printf("CPUID Raw Values:\n");␊
124␉␉for (i=0; i<CPUID_MAX; i++) {␊
125␉␉␉printf("%02d: %08x-%08x-%08x-%08x\n", i,␊
126␉␉␉␉p->CPU.CPUID[i][0], p->CPU.CPUID[i][1],␊
127␉␉␉␉p->CPU.CPUID[i][2], p->CPU.CPUID[i][3]);␊
128␉␉}␊
129␉}␊
130#endif␊
131␉p->CPU.Vendor␉␉= p->CPU.CPUID[CPUID_0][1];␊
132␉p->CPU.Signature␉= p->CPU.CPUID[CPUID_1][0];␊
133␉p->CPU.Stepping␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 3, 0);␊
134␉p->CPU.Model␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 7, 4);␊
135␉p->CPU.Type␉␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 13, 12);␊
136␉p->CPU.Family␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 11, 8);␊
137␉p->CPU.ExtModel␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 19, 16);␊
138␉p->CPU.ExtFamily␉= bitfield(p->CPU.CPUID[CPUID_1][0], 27, 20);␊
139␉p->CPU.NoThreads␉= bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␊
140␉p->CPU.NoCores␉␉= bitfield(p->CPU.CPUID[CPUID_4][0], 31, 26) + 1;␊
141␊
142␉p->CPU.Model += (p->CPU.ExtModel << 4);␊
143␊
144␉/* get brand string (if supported) */␊
145␉/* Copyright: from Apple's XNU cpuid.c */␊
146␉if (p->CPU.CPUID[CPUID_80][0] > 0x80000004) {␊
147␉␉uint32_t␉reg[4];␊
148 char str[128], *s;␊
149␉␉/*␊
150␉␉ * The brand string 48 bytes (max), guaranteed to␊
151␉␉ * be NUL terminated.␊
152␉␉ */␊
153␉␉do_cpuid(0x80000002, reg);␊
154␉␉bcopy((char *)reg, &str[0], 16);␊
155␉␉do_cpuid(0x80000003, reg);␊
156␉␉bcopy((char *)reg, &str[16], 16);␊
157␉␉do_cpuid(0x80000004, reg);␊
158␉␉bcopy((char *)reg, &str[32], 16);␊
159␉␉for (s = str; *s != '\0'; s++) {␊
160␉␉␉if (*s != ' ') break;␊
161␉␉}␊
162␉␉␊
163␉␉strlcpy(p->CPU.BrandString,␉s, sizeof(p->CPU.BrandString));␊
164␉␉␊
165␉␉if (!strncmp(p->CPU.BrandString, CPU_STRING_UNKNOWN, min(sizeof(p->CPU.BrandString), strlen(CPU_STRING_UNKNOWN) + 1))) {␊
166␉␉␉ /*␊
167␉␉␉ * This string means we have a firmware-programmable brand string,␊
168␉␉␉ * and the firmware couldn't figure out what sort of CPU we have.␊
169␉␉␉ */␊
170␉␉␉ p->CPU.BrandString[0] = '\0';␊
171␉␉ }␊
172␉}␊
173␉␊
174␉/* setup features */␊
175␉p->CPU.Features |= (CPU_FEATURE_MMX | CPU_FEATURE_SSE | CPU_FEATURE_SSE2 | CPU_FEATURE_MSR | CPU_FEATURE_APIC | CPU_FEATURE_TM1 | CPU_FEATURE_ACPI) & p->CPU.CPUID[CPUID_1][3];␊
176␉p->CPU.Features |= (CPU_FEATURE_SSE3 | CPU_FEATURE_SSE41 | CPU_FEATURE_SSE42 | CPU_FEATURE_EST | CPU_FEATURE_TM2 | CPU_FEATURE_SSSE3 | CPU_FEATURE_xAPIC) & p->CPU.CPUID[CPUID_1][2];␊
177␉p->CPU.Features |= (CPU_FEATURE_EM64T | CPU_FEATURE_XD) & p->CPU.CPUID[CPUID_81][3];␊
178␉p->CPU.Features |= (CPU_FEATURE_LAHF) & p->CPU.CPUID[CPUID_81][2];␊
179␊
180␊
181␉//if ((CPU_FEATURE_HTT & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
182␉if (p->CPU.NoThreads > p->CPU.NoCores) {␊
183␉␉p->CPU.Features |= CPU_FEATURE_HTT;␊
184␉}␊
185␉ ␊
186␊
187␉tscFrequency = measure_tsc_frequency();␊
188␉fsbFrequency = 0;␊
189␉cpuFrequency = 0;␊
190␉fsbi = 0;␊
191␉fix_fsb = false;␊
192␉did = false;␊
193␉core_i = false;␊
194␉turbo = false;␊
195␉isatom = false;␊
196␉fsbad = false;␊
197␊
198␉if ((p->CPU.Vendor == 0x756E6547 /* Intel */) && ((p->CPU.Family == 0x06) || (p->CPU.Family == 0x0f)))␊
199␉{␊
200␉␉verbose("CPU: ");␊
201␉␉int tjmax = 0;␊
202␉␉msr = rdmsr64(MSR_IA32_PLATFORM_ID);␊
203␉␉if((((msr >> 50) & 0x01) == 1) || (rdmsr64(0x17) & (1<<28)))␊
204␉␉{␊
205␉␉␉p->CPU.Features |= CPU_FEATURE_MOBILE;␊
206␉␉␉verbose("Mobile ");␊
207␉␉}␊
208␉␉verbose("%s\n", p->CPU.BrandString);␊
209␉␉␊
210␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) || (p->CPU.Family == 0x0f && p->CPU.Model >= 0x03))␊
211␉␉{␊
212␉␉␉if (p->CPU.Family == 0x06)␊
213␉␉␉{␊
214␉␉␉␉int intelCPU = p->CPU.Model;␊
215␉␉␉␉int Stepp = p->CPU.Stepping;␊
216␉␉␉␉int bus;␊
217␊
218␉␉␉␉switch (intelCPU)␊
219␉␉␉␉{␊
220␉␉␉␉␉case 0xc:␉␉// Core i7 & Atom␊
221␉␉␉␉␉␉if (strstr(p->CPU.BrandString, "Atom")) goto teleport;␊
222␉␉␉␉␉case 0x1a:␉␉// Core i7 LGA1366, Xeon 5500, "Bloomfield", "Gainstown", 45nm␊
223␉␉␉␉␉case 0x1e:␉␉// Core i7, i5 LGA1156, "Clarksfield", "Lynnfield", "Jasper", 45nm␊
224␉␉␉␉␉case 0x1f:␉␉// Core i7, i5, Nehalem␊
225␉␉␉␉␉case 0x25:␉␉// Core i7, i5, i3 LGA1156, "Westmere", "Clarkdale", "Arrandale", 32nm␊
226␉␉␉␉␉case 0x2c:␉␉// Core i7 LGA1366, Six-core, "Westmere", "Gulftown", 32nm␊
227␉␉␉␉␉case 0x2e:␉␉// Core i7, Nehalem-Ex Xeon, "Beckton"␊
228␉␉␉␉␉case 0x2f:␉␉// Core i7, Nehalem-Ex Xeon, "Eagleton"␊
229␉␉␉␉␉␉core_i = true;␊
230␉␉␉␉␉␉tjmax = (rdmsr64(MSR_THERMAL_TARGET) >> 16) & 0xff;␊
231␉␉␉␉␉␉msr = rdmsr64(MSR_PLATFORM_INFO);␊
232␉␉␉␉␉␉bus_ratio_max = (msr >> 8) & 0xff;␊
233␉␉␉␉␉␉bus_ratio_min = (msr >> 40) & 0xff; //valv: not sure about this one (Remarq.1)␊
234␉␉␉␉␉␉verbose("CPU: Flex-Ratio = %d ", bus_ratio_max);␊
235␉␉␉␉␉␉min_ratio = bus_ratio_min * 10;␊
236␉␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊
237␉␉␉␉␉␉if ((msr >> 16) & 0x01)␊
238␉␉␉␉␉␉{␊
239␉␉␉␉␉␉␉flex_ratio = (msr >> 8) & 0xff;␊
240␉␉␉␉␉␉␉verbose(">> %d", flex_ratio);␊
241␉␉␉␉␉␉␉if(bus_ratio_max > flex_ratio) bus_ratio_max = flex_ratio;␊
242␉␉␉␉␉␉}␊
243␉␉␉␉␉␉verbose("\n");␊
244␉␉␉␉␉␉if(bus_ratio_max) fsbFrequency = (tscFrequency / bus_ratio_max);␊
245␊
246␉␉␉␉␉␉//valv: Turbo Ratio Limit␊
247␉␉␉␉␉␉if ((intelCPU != 0x2e) && (intelCPU != 0x2f))␊
248␉␉␉␉␉␉{␊
249␉␉␉␉␉␉␉turbo = true;␊
250␉␉␉␉␉␉␉msr = rdmsr64(MSR_TURBO_RATIO_LIMIT);␊
251␉␉␉␉␉␉␉␊
252␉␉␉␉␉␉␉p->CPU.Tone = (msr >> 0) & 0xff;␊
253␉␉␉␉␉␉␉p->CPU.Ttwo = (msr >> 8) & 0xff;␊
254␉␉␉␉␉␉␉p->CPU.Tthr = (msr >> 16) & 0xff;␊
255␉␉␉␉␉␉␉p->CPU.Tfor = (msr >> 24) & 0xff;␊
256␊
257␉␉␉␉␉␉␉cpuFrequency = bus_ratio_max * fsbFrequency;␊
258␉␉␉␉␉␉␉max_ratio = bus_ratio_max * 10;␊
259␉␉␉␉␉␉}␊
260␉␉␉␉␉␉else cpuFrequency = tscFrequency;␊
261␊
262␉␉␉␉␉␉if ((getValueForKey(kbusratio, &newratio, &len, &bootInfo->bootConfig)) && (len <= 4))␊
263␉␉␉␉␉␉{␊
264␉␉␉␉␉␉␉max_ratio = atoi(newratio);␊
265␉␉␉␉␉␉␉max_ratio = (max_ratio * 10);␊
266␉␉␉␉␉␉␉if (len >= 3) max_ratio = (max_ratio + 5);␊
267␊
268␉␉␉␉␉␉␉verbose("Bus-Ratio: min=%d%s, max=%d%s\n", bus_ratio_min, bus_ratio_max);␊
269␊
270␉␉␉␉␉␉␉// extreme overclockers may love 320 ;)␊
271␉␉␉␉␉␉␉if ((max_ratio >= min_ratio) && (max_ratio <= 320))␊
272␉␉␉␉␉␉␉{␊
273␉␉␉␉␉␉␉␉cpuFrequency = (fsbFrequency * max_ratio) / 10;␊
274␉␉␉␉␉␉␉␉if (len >= 3) maxdiv = 1;␊
275␉␉␉␉␉␉␉␉else maxdiv = 0;␊
276␉␉␉␉␉␉␉␉verbose("Sticking with [BCLK: %dMhz, Bus-Ratio: %s]\n", myfsb, newratio);␊
277␉␉␉␉␉␉␉}␊
278␉␉␉␉␉␉␉else max_ratio = (bus_ratio_max * 10);␊
279␉␉␉␉␉␉}␊
280␉␉␉␉␉␉//valv: to be uncommented if Remarq.1 didn't stick␊
281␉␉␉␉␉␉/*if(bus_ratio_max > 0) bus_ratio = flex_ratio;*/␊
282␉␉␉␉␉␉p->CPU.MaxRatio = max_ratio;␊
283␉␉␉␉␉␉p->CPU.MinRatio = min_ratio;␊
284␉␉␉␉␉␉␊
285␉␉␉␉␉␉//fsbi = fsbFrequency;␊
286␉␉␉␉␉␉if(getIntForKey(kForceFSB, &myfsb, &bootInfo->bootConfig)) goto forcefsb;␊
287␉␉␉␉␉␉break;␊
288␉␉␉␉␉case 0xd:␉␉// Pentium M, Dothan, 90nm␊
289␉␉␉␉␉case 0xe:␉␉// Core Duo/Solo, Pentium M DC␊
290␉␉␉␉␉␉goto teleport;␊
291␉␉␉␉␉case 0xf:␉␉// Core Xeon, Core 2 DC, 65nm␊
292␉␉␉␉␉␉switch (Stepp)␊
293␉␉␉␉␉␉{␊
294␉␉␉␉␉␉␉case 0x2:␊
295␉␉␉␉␉␉␉␉tjmax = 95;␊
296␉␉␉␉␉␉␉␉break;␊
297␉␉␉␉␉␉␉case 0x6:␊
298␉␉␉␉␉␉␉␉if (p->CPU.NoCores = 2) tjmax = 80;␊
299␉␉␉␉␉␉␉␉if (p->CPU.NoCores = 4) tjmax = 90;␊
300␉␉␉␉␉␉␉␉else tjmax = 85;␊
301␉␉␉␉␉␉␉␉break;␊
302␉␉␉␉␉␉␉case 0xb:␊
303␉␉␉␉␉␉␉␉tjmax = 90;␊
304␉␉␉␉␉␉␉␉break;␊
305␉␉␉␉␉␉␉case 0xd:␊
306␉␉␉␉␉␉␉default:␊
307␉␉␉␉␉␉␉teleport:␊
308␉␉␉␉␉␉␉␉msr = rdmsr64(MSR_IA32_EXT_CONFIG);␊
309␉␉␉␉␉␉␉␉if(msr & (1 << 30)) tjmax = 85;␊
310␉␉␉␉␉␉␉␉break;␊
311␉␉␉␉␉␉}␊
312␉␉␉␉␉case 0x1c:␉␉// Atom :)␊
313␉␉␉␉␉␉switch (Stepp)␊
314␉␉␉␉␉␉{␊
315␉␉␉␉␉␉␉case 0xa:␊
316␉␉␉␉␉␉␉␉tjmax = 100;␊
317␉␉␉␉␉␉␉␉break;␊
318␉␉␉␉␉␉␉case 0x2:␊
319␉␉␉␉␉␉␉default:␊
320␉␉␉␉␉␉␉␉tjmax = 90;␊
321␉␉␉␉␉␉␉␉break;␊
322␉␉␉␉␉␉}␊
323␉␉␉␉␉case 0x17:␉␉// Core 2 Duo/Extreme, Xeon, 45nm␊
324␉␉␉␉␉␉switch (Stepp)␊
325␉␉␉␉␉␉{␊
326␉␉␉␉␉␉␉case 0x6:␉␉// Mobile Core2 Duo␊
327␉␉␉␉␉␉␉␉tjmax = 104;␊
328␉␉␉␉␉␉␉␉break;␊
329␉␉␉␉␉␉␉case 0xa:␉␉// Mobile Centrino 2␊
330␉␉␉␉␉␉␉␉tjmax = 105;␊
331␉␉␉␉␉␉␉␉break;␊
332␉␉␉␉␉␉␉default:␊
333␉␉␉␉␉␉␉␉if (platformCPUFeature(CPU_FEATURE_MOBILE)) tjmax = 105;␊
334␉␉␉␉␉␉␉␉break;␊
335␉␉␉␉␉␉}␊
336␉␉␉␉␉case 0x16:␉␉// Celeron, Core 2 SC, 65nm␊
337␉␉␉␉␉case 0x27:␉␉// Atom Lincroft, 45nm␊
338␉␉␉␉␉␉core_i = false;␊
339␉␉␉␉␉␉//valv: todo: msr_therm2_ctl (0x19d) bit 16 (mode of automatic thermal monitor): 0=tm1, 1=tm2␊
340␉␉␉␉␉␉//also, if bit 3 of misc_enable is cleared the above would have no effect␊
341␉␉␉␉␉␉if (strstr(p->CPU.BrandString, "Atom"))␊
342␉␉␉␉␉␉␉isatom = true;␊
343␉␉␉␉␉␉if(!isatom && (platformCPUFeature(CPU_FEATURE_TM1)))␊
344␉␉␉␉␉␉{␊
345␉␉␉␉␉␉␉msr_t msr32;␊
346␉␉␉␉␉␉␉msr32 = rdmsr(MSR_IA32_MISC_ENABLE);␊
347␊
348␉␉␉␉␉␉␉//thermally-initiated on-die modulation of the stop-clock duty cycle␊
349␉␉␉␉␉␉␉if(!(rdmsr64(MSR_IA32_MISC_ENABLE) & (1 << 3))) msr32.lo |= (1 << 3);␊
350␉␉␉␉␉␉␉verbose("CPU: Thermal Monitor: TM, ");␊
351␉␉␉␉␉␉␉␊
352␉␉␉␉␉␉␉//BIOS must enable this feature if the TM2 feature flag (CPUID.1:ECX[8]) is set␊
353␉␉␉␉␉␉␉if(platformCPUFeature(CPU_FEATURE_TM2))␊
354␉␉␉␉␉␉␉{␊
355␉␉␉␉␉␉␉␉//thermally-initiated frequency transitions␊
356␉␉␉␉␉␉␉␉msr32.lo |= (1 << 13);␊
357␉␉␉␉␉␉␉␉verbose("TM2, ");␊
358␉␉␉␉␉␉␉}␊
359␉␉␉␉␉␉␉msr32.lo |= (1 << 17);␊
360␉␉␉␉␉␉␉verbose("PROCHOT, ");␊
361␉␉␉␉␉␉␉msr32.lo |= (1 << 10);␊
362␉␉␉␉␉␉␉verbose("FERR\n");␊
363␉␉␉␉␉␉␉␊
364␉␉␉␉␉␉␉bool oem_ssdt, tmpval;␊
365␉␉␉␉␉␉␉oem_ssdt = false;␊
366␉␉␉␉␉␉␉␊
367␉␉␉␉␉␉␉oem_ssdt = getBoolForKey(kOEMSSDT, &tmpval, &bootInfo->bootConfig)&&tmpval;␊
368␉␉␉␉␉␉␉if(oem_ssdt)␊
369␉␉␉␉␉␉␉{␊
370␉␉␉␉␉␉␉␉bool c2e, c4e, hc4e;␊
371␉␉␉␉␉␉␉␉c2e = c4e = hc4e = false;␊
372␊
373␉␉␉␉␉␉␉␉getBoolForKey(kC2EEnable, &c2e, &bootInfo->bootConfig);␊
374␉␉␉␉␉␉␉␉if(c2e) msr32.lo |= (1 << 26);␊
375␉␉␉␉␉␉␉␉␊
376␉␉␉␉␉␉␉␉getBoolForKey(kC4EEnable, &c4e, &bootInfo->bootConfig);␊
377␉␉␉␉␉␉␉␉if((c4e) && platformCPUFeature(CPU_FEATURE_MOBILE)) msr32.hi |= (1 << (32 - 32));␊
378␉␉␉␉␉␉␉␉getBoolForKey(kHardC4EEnable, &hc4e, &bootInfo->bootConfig);␊
379␉␉␉␉␉␉␉␉if((hc4e) && platformCPUFeature(CPU_FEATURE_MOBILE)) msr32.hi |= (1 << (33 - 32));␊
380␉␉␉␉␉␉␉}␊
381␉␉␉␉␉␉␉␊
382␉␉␉␉␉␉␉msr32.hi |= (1 << (36 - 32)); // EMTTM␊
383␊
384␉␉␉␉␉␉␉wrmsr(MSR_IA32_MISC_ENABLE, msr32);␊
385␉␉␉␉␉␉␉␊
386␉␉␉␉␉␉␉msr32 = rdmsr(PIC_SENS_CFG);␊
387␉␉␉␉␉␉␉msr32.lo |= (1 << 21);␊
388␉␉␉␉␉␉␉wrmsr(PIC_SENS_CFG, msr32);␊
389␉␉␉␉␉␉}␊
390␉␉␉␉␉␉␊
391␉␉␉␉␉␉if (rdmsr64(MSR_IA32_EXT_CONFIG) & (1 << 27))␊
392␉␉␉␉␉␉{␊
393␉␉␉␉␉␉␉wrmsr64(MSR_IA32_EXT_CONFIG, (rdmsr64(MSR_IA32_EXT_CONFIG) | (1 << 28)));␊
394␉␉␉␉␉␉␉delay(1);␊
395␉␉␉␉␉␉␉did = rdmsr64(MSR_IA32_EXT_CONFIG) & (1 << 28);␊
396␉␉␉␉␉␉}␊
397␉␉␉␉␉␉getBoolForKey(kFixFSB, &fix_fsb, &bootInfo->bootConfig);␊
398␉␉␉␉␉␉if(fix_fsb)␊
399␉␉␉␉␉␉{␊
400␉␉␉␉␉␉␉msr = rdmsr64(MSR_FSB_FREQ);␊
401␉␉␉␉␉␉␉bus = (msr >> 0) & 0x7;␊
402␉␉␉␉␉␉␉if(p->CPU.Model == 0xd && bus == 0)␊
403␉␉␉␉␉␉␉{␊
404␉␉␉␉␉␉␉␉fsbFrequency = 100000000;␊
405␉␉␉␉␉␉␉␉myfsb = 100;␊
406␉␉␉␉␉␉␉}␊
407␉␉␉␉␉␉␉else if(p->CPU.Model == 0xe && p->CPU.ExtModel == 1) goto ratio;␊
408␉␉␉␉␉␉␉else␊
409␉␉␉␉␉␉␉{␊
410␉␉␉␉␉␉␉␉switch (bus)␊
411␉␉␉␉␉␉␉␉{␊
412␉␉␉␉␉␉␉␉␉case 0:␊
413␉␉␉␉␉␉␉␉␉␉fsbFrequency = 266666667;␊
414␉␉␉␉␉␉␉␉␉␉myfsb = 266;␊
415␉␉␉␉␉␉␉␉␉␉break;␊
416␉␉␉␉␉␉␉␉␉case 1:␊
417␉␉␉␉␉␉␉␉␉␉fsbFrequency = 133333333;␊
418␉␉␉␉␉␉␉␉␉␉myfsb = 133;␊
419␉␉␉␉␉␉␉␉␉␉break;␊
420␉␉␉␉␉␉␉␉␉case 3:␊
421␉␉␉␉␉␉␉␉␉␉fsbFrequency = 166666667;␊
422␉␉␉␉␉␉␉␉␉␉myfsb = 166;␊
423␉␉␉␉␉␉␉␉␉␉break;␊
424␉␉␉␉␉␉␉␉␉case 4:␊
425␉␉␉␉␉␉␉␉␉␉fsbFrequency = 333333333;␊
426␉␉␉␉␉␉␉␉␉␉myfsb = 333;␊
427␉␉␉␉␉␉␉␉␉␉break;␊
428␉␉␉␉␉␉␉␉␉case 5:␊
429␉␉␉␉␉␉␉␉␉␉fsbFrequency = 100000000;␊
430␉␉␉␉␉␉␉␉␉␉myfsb = 100;␊
431␉␉␉␉␉␉␉␉␉␉break;␊
432␉␉␉␉␉␉␉␉␉case 6:␊
433␉␉␉␉␉␉␉␉␉␉fsbFrequency = 400000000;␊
434␉␉␉␉␉␉␉␉␉␉myfsb = 400;␊
435␉␉␉␉␉␉␉␉␉␉break;␊
436␉␉␉␉␉␉␉␉␉case 2:␊
437␉␉␉␉␉␉␉␉␉default:␊
438␉␉␉␉␉␉␉␉␉␉fsbFrequency = 200000000;␊
439␉␉␉␉␉␉␉␉␉␉myfsb = 200;␊
440␉␉␉␉␉␉␉␉␉␉break;␊
441␉␉␉␉␉␉␉␉}␊
442␉␉␉␉␉␉␉}␊
443␉␉␉␉␉␉␉uint64_t minfsb = 183000000, maxfsb = 185000000;␊
444␉␉␉␉␉␉␉if (((fsbFrequency > minfsb) && (fsbFrequency < maxfsb)) || (!fsbFrequency))␊
445␉␉␉␉␉␉␉{␊
446␉␉␉␉␉␉␉␉fsbFrequency = 200000000;␊
447␉␉␉␉␉␉␉␉fsbad = true;␊
448␉␉␉␉␉␉␉}␊
449␉␉␉␉␉␉␉goto ratio;␊
450␉␉␉␉␉␉}␊
451␉␉␉␉␉case 0x1d:␉␉// Xeon MP MP 7400␊
452␉␉␉␉␉// for 0x2a & 0x2b turbo is true;␊
453␉␉␉␉␉//case 0x2a:␉␉// SNB␊
454␉␉␉␉␉//case 0x2b:␉␉// SNB Xeon␊
455␉␉␉␉␉default:␊
456␉␉␉␉␉␉if(getIntForKey(kForceFSB, &myfsb, &bootInfo->bootConfig))␊
457␉␉␉␉␉␉{␊
458␉␉␉␉␉␉␉forcefsb:␊
459␉␉␉␉␉␉␉switch(myfsb)␊
460␉␉␉␉␉␉␉{␊
461␉␉␉␉␉␉␉␉case 133:␊
462␉␉␉␉␉␉␉␉␉fsbFrequency = 133333333;␊
463␉␉␉␉␉␉␉␉␉break;␊
464␉␉␉␉␉␉␉␉case 166:␊
465␉␉␉␉␉␉␉␉␉fsbFrequency = 166666667;␊
466␉␉␉␉␉␉␉␉␉break;␊
467␉␉␉␉␉␉␉␉case 233:␊
468␉␉␉␉␉␉␉␉␉fsbFrequency = 233333333;␊
469␉␉␉␉␉␉␉␉␉break;␊
470␉␉␉␉␉␉␉␉case 266:␊
471␉␉␉␉␉␉␉␉␉fsbFrequency = 266666667;␊
472␉␉␉␉␉␉␉␉␉break;␊
473␉␉␉␉␉␉␉␉case 333:␊
474␉␉␉␉␉␉␉␉␉fsbFrequency = 333333333;␊
475␉␉␉␉␉␉␉␉␉break;␊
476␉␉␉␉␉␉␉␉case 100:␊
477␉␉␉␉␉␉␉␉case 200:␊
478␉␉␉␉␉␉␉␉case 400:␊
479␉␉␉␉␉␉␉␉␉fsbFrequency = (myfsb * 1000000);␊
480␉␉␉␉␉␉␉␉␉break;␊
481␉␉␉␉␉␉␉␉default:␊
482␉␉␉␉␉␉␉␉␉getValueForKey(kForceFSB, &newfsb, &len, &bootInfo->bootConfig);␊
483␉␉␉␉␉␉␉␉␉if((len <= 3) && (myfsb < 400))␊
484␉␉␉␉␉␉␉␉␉{␊
485␉␉␉␉␉␉␉␉␉␉fsbFrequency = (myfsb * 1000000);␊
486␉␉␉␉␉␉␉␉␉␉verbose("Specified FSB: %dMhz. Assuming you know what you 're doing !\n", myfsb);␊
487␉␉␉␉␉␉␉␉␉}␊
488␉␉␉␉␉␉␉␉␉else if(core_i) fsbFrequency = 133333333;␊
489␉␉␉␉␉␉␉␉␉else fsbFrequency = 200000000;␊
490␉␉␉␉␉␉␉␉␉break;␊
491␉␉␉␉␉␉␉}␊
492␉␉␉␉␉␉␉if(core_i)␊
493␉␉␉␉␉␉␉{␊
494␉␉␉␉␉␉␉␉cpuFrequency = (fsbFrequency * max_ratio) / 10;␊
495␉␉␉␉␉␉␉␉verbose("Sticking with [BCLK: %dMhz, Bus-Ratio: %s]\n", myfsb, newratio);␊
496␉␉␉␉␉␉␉␉break;␊
497␉␉␉␉␉␉␉}␊
498␉␉␉␉␉␉␉fix_fsb = true;␊
499␉␉␉␉␉␉}␊
500␉␉␉␉␉␉goto ratio;␊
501␉␉␉␉␉␉break;␊
502␉␉␉␉}␊
503␉␉␉}␊
504␉␉␉else␊
505␉␉␉{␊
506␉␉␉␉ratio:␊
507␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_STATUS);␊
508␉␉␉␉maxdiv = (msr >> 46) & 0x01;␊
509␉␉␉␉//valv: this seems to be bit 15 instead of 14.␊
510␉␉␉␉currdiv = (msr >> 15) & 0x01;␊
511␉␉␉␉uint8_t XE = (msr >> 31) & 0x01;␊
512␊
513␉␉␉␉msr_t msr32;␊
514␉␉␉␉msr32 = rdmsr(MSR_IA32_PERF_STATUS);␊
515␉␉␉␉bus_ratio_min = (msr32.lo >> 24) & 0x1f;␊
516␉␉␉␉min_ratio = bus_ratio_min * 10;␊
517␉␉␉␉if(currdiv) min_ratio = min_ratio + 5;␊
518␉␉␉␉␊
519␉␉␉␉if(XE || (p->CPU.Family == 0x0f)) bus_ratio_max = (msr32.hi >> (40-32)) & 0x1f;␊
520␉␉␉␉else bus_ratio_max = ((rdmsr64(MSR_IA32_PLATFORM_ID) >> 8) & 0x1f);␊
521␉␉␉␉/* On lower models, currcoef defines TSC freq */␊
522␉␉␉␉if (((p->CPU.Family == 0x06) && (p->CPU.Model < 0x0e)) && (p->CPU.Family != 0x0f)) bus_ratio_max = bus_ratio_min;␊
523␉␉␉␉// bad hack! Could force a value relying on kpstates, but I fail to see its benefits.␊
524␉␉␉␉if(bus_ratio_min == 0) bus_ratio_min = bus_ratio_max;␊
525␉␉␉␉␊
526␉␉␉␉if(p->CPU.Family == 0x0f)␊
527␉␉␉␉{␊
528␉␉␉␉␉getBoolForKey(kFixFSB, &fix_fsb, &bootInfo->bootConfig);␊
529␉␉␉␉␉if(fix_fsb)␊
530␉␉␉␉␉{␊
531␉␉␉␉␉␉msr = rdmsr64(MSR_EBC_FREQUENCY_ID);␊
532␉␉␉␉␉␉int bus = (msr >> 16) & 0x7;␊
533␉␉␉␉␉␉switch (bus)␊
534␉␉␉␉␉␉{␊
535␉␉␉␉␉␉␉case 0:␊
536␉␉␉␉␉␉␉␉fsbFrequency = 266666667;␊
537␉␉␉␉␉␉␉␉myfsb = 266;␊
538␉␉␉␉␉␉␉␉break;␊
539␉␉␉␉␉␉␉case 1:␊
540␉␉␉␉␉␉␉␉fsbFrequency = 133333333;␊
541␉␉␉␉␉␉␉␉myfsb = 133;␊
542␉␉␉␉␉␉␉␉break;␊
543␉␉␉␉␉␉␉case 3:␊
544␉␉␉␉␉␉␉␉fsbFrequency = 166666667;␊
545␉␉␉␉␉␉␉␉myfsb = 166;␊
546␉␉␉␉␉␉␉␉break;␊
547␉␉␉␉␉␉␉case 2:␊
548␉␉␉␉␉␉␉default:␊
549␉␉␉␉␉␉␉␉fsbFrequency = 200000000;␊
550␉␉␉␉␉␉␉␉myfsb = 200;␊
551␉␉␉␉␉␉␉␉break;␊
552␉␉␉␉␉␉}␊
553␉␉␉␉␉␉uint64_t minfsb = 183000000, maxfsb = 185000000;␊
554␉␉␉␉␉␉if (((fsbFrequency > minfsb) && (fsbFrequency < maxfsb)) || (!fsbFrequency))␊
555␉␉␉␉␉␉{␊
556␉␉␉␉␉␉␉fsbFrequency = 200000000;␊
557␉␉␉␉␉␉␉fsbad = true;␊
558␉␉␉␉␉␉}␊
559␉␉␉␉␉}␊
560␉␉␉␉}␊
561␊
562␉␉␉␉if(fix_fsb)␊
563␉␉␉␉{␊
564␉␉␉␉␉if (bus_ratio_max)␊
565␉␉␉␉␉{␊
566␉␉␉␉␉␉if (maxdiv) fsbi = ((tscFrequency * 2) / ((bus_ratio_max * 2) + 1));␊
567␉␉␉␉␉␉else fsbi = (tscFrequency / bus_ratio_max);␊
568␉␉␉␉␉}␊
569␉␉␉␉␉ratio_gn:␊
570␉␉␉␉␉if ((getValueForKey(kbusratio, &newratio, &len, &bootInfo->bootConfig)) && (len <= 4))␊
571␉␉␉␉␉{␊
572␉␉␉␉␉␉max_ratio = atoi(newratio);␊
573␉␉␉␉␉␉max_ratio = (max_ratio * 10);␊
574␉␉␉␉␉␉if (len >= 3) max_ratio = (max_ratio + 5);␊
575␊
576␉␉␉␉␉␉verbose("Bus-Ratio defaults: min=%d%s, max=%d%s\n", bus_ratio_min, currdiv ? ".5" : "", bus_ratio_max, maxdiv ? ".5" : "");␊
577␉␉␉␉␉␉if ((max_ratio >= min_ratio) && (max_ratio < 200))␊
578␉␉␉␉␉␉{␊
579␉␉␉␉␉␉␉cpuFrequency = (fsbFrequency * max_ratio) / 10;␊
580␉␉␉␉␉␉␉if (len >= 3) maxdiv = 1;␊
581␉␉␉␉␉␉␉else maxdiv = 0;␊
582␉␉␉␉␉␉␉verbose("Sticking with [FSB: %dMhz, Bus-Ratio: %s]\n", myfsb, newratio);␊
583␉␉␉␉␉␉}␊
584␉␉␉␉␉␉else␊
585␉␉␉␉␉␉{␊
586␉␉␉␉␉␉␉printf("Bus-Ratio: Lowest allowed = %d%s. ", bus_ratio_min, currdiv ? ".5" : "");␊
587␉␉␉␉␉␉␉goto ratio_vldt;␊
588␉␉␉␉␉␉}␊
589␉␉␉␉␉}␊
590␉␉␉␉␉else␊
591␉␉␉␉␉{␊
592␉␉␉␉␉␉ratio_vldt:␊
593␉␉␉␉␉␉if (maxdiv)␊
594␉␉␉␉␉␉{␊
595␉␉␉␉␉␉␉cpuFrequency = ((fsbFrequency * ((bus_ratio_max * 2) + 1)) / 2);␊
596␉␉␉␉␉␉␉max_ratio = (bus_ratio_max * 10) + 5;␊
597␉␉␉␉␉␉}␊
598␉␉␉␉␉␉else␊
599␉␉␉␉␉␉{␊
600␉␉␉␉␉␉␉cpuFrequency = (fsbFrequency * bus_ratio_max);␊
601␉␉␉␉␉␉␉max_ratio = bus_ratio_max * 10;␊
602␉␉␉␉␉␉}␊
603␉␉␉␉␉␉verbose("CPU: Sticking with: [FSB: %dMhz, Bus-Ratio: %d%s] %s\n", myfsb, bus_ratio_max, maxdiv ? ".5" : "", newratio ? "instead" : "");␊
604␉␉␉␉␉}␊
605␉␉␉␉}␊
606␉␉␉␉else␊
607␉␉␉␉{␊
608␉␉␉␉␉if (bus_ratio_max)␊
609␉␉␉␉␉{␊
610␉␉␉␉␉␉if (maxdiv)␊
611␉␉␉␉␉␉{␊
612␉␉␉␉␉␉␉fsbFrequency = ((tscFrequency * 2) / ((bus_ratio_max * 2) + 1));␊
613␉␉␉␉␉␉␉max_ratio = ((bus_ratio_max * 10) + 5);␊
614␉␉␉␉␉␉}␊
615␉␉␉␉␉␉else␊
616␉␉␉␉␉␉{␊
617␉␉␉␉␉␉␉fsbFrequency = (tscFrequency / bus_ratio_max);␊
618␉␉␉␉␉␉␉max_ratio = (bus_ratio_max * 10);␊
619␉␉␉␉␉␉}␊
620␊
621␉␉␉␉␉␉myfsb = (fsbFrequency / 1000000);␊
622␉␉␉␉␉␉if (getValueForKey(kbusratio, &newratio, &len, &bootInfo->bootConfig)) goto ratio_gn;␊
623␉␉␉␉␉␉else cpuFrequency = ((fsbFrequency * max_ratio) / 10);␊
624␊
625␉␉␉␉␉␉DBG("max: %d%s current: %d%s\n", bus_ratio_max, maxdiv ? ".5" : "", bus_ratio_min, currdiv ? ".5" : "");␊
626␉␉␉␉␉}␊
627␉␉␉␉}␊
628␉␉␉␉p->CPU.MaxRatio = max_ratio;␊
629␉␉␉␉p->CPU.MinRatio = min_ratio;␊
630␉␉␉}␊
631␉␉}␊
632␊
633␉␉// on-die sensor␊
634␉␉if (p->CPU.CPUID[CPUID_0][0] >= 0x6)␊
635␉␉{␊
636␉␉␉// Highest Basic Functions Number␊
637␉␉␉do_cpuid(6, p->CPU.CPUID[CPUID_81]);␊
638␉␉␉tms = bitfield(p->CPU.CPUID[CPUID_81][0], 0, 0);␊
639␉␉␉ida = bitfield(p->CPU.CPUID[CPUID_81][0], 1, 1);␊
640␉␉␉if(tms != 0)␊
641␉␉␉{␊
642␉␉␉␉int temp, utjmax;␊
643␉␉␉␉if (tjmax == 0) tjmax = 100;␊
644␉␉␉␉if((getIntForKey(kTjmax, &utjmax, &bootInfo->bootConfig)) && ((70 <= utjmax) && (utjmax <= 110))) tjmax = utjmax;␊
645␉␉␉␉msr = rdmsr64(MSR_THERMAL_STATUS);␊
646␉␉␉␉//if ((msr & 0x3) == 0x3)␊
647␉␉␉␉if (((msr >> 31) & 0x1) == 1)␊
648␉␉␉␉{␊
649␉␉␉␉␉temp = tjmax - ((msr >> 16) & 0x7F);␊
650␉␉␉␉␉verbose("CPU: Tjmax ~ %d°C ␉ Temperature= ~ %d°C\n", tjmax, temp);␊
651␉␉␉␉}␊
652␉␉␉␉else temp = -1;␊
653␉␉␉}␊
654␉␉␉if(ida == 0)␊
655␉␉␉{␊
656␉␉␉␉verbose("CPU: Attempting to enable IDA ");␊
657␉␉␉␉msr_t msr;␊
658␉␉␉␉msr = rdmsr(MSR_IA32_MISC_ENABLE);␊
659␉␉␉␉msr.hi |= (0 << (38-32));␊
660␉␉␉␉wrmsr(MSR_IA32_MISC_ENABLE, msr);␊
661␉␉␉␉delay(1);␊
662␉␉␉␉if(bitfield(p->CPU.CPUID[CPUID_81][0], 1, 1) == 0) verbose("Failed!\n");␊
663␉␉␉␉else verbose("Succeded!\n");␊
664␉␉␉}␊
665␉␉␉else verbose("CPU: IDA: Enabled!\n");␊
666␉␉}␊
667␉}␊
668//#if 0␊
669␉else if(p->CPU.Vendor == 0x68747541 /* AMD */ && p->CPU.Family == 0x0f) // valv: work in progress␊
670␉{␊
671␉␉verbose("CPU: ");␊
672␉␉// valv: very experimental mobility check␊
673␉␉if (p->CPU.CPUID[0x80000000][0] >= 0x80000007)␊
674␉␉{␊
675␉␉␉uint32_t amo, const_tsc;␊
676␉␉␉do_cpuid(0x80000007, p->CPU.CPUID[CPUID_MAX]);␊
677␉␉␉amo = bitfield(p->CPU.CPUID[CPUID_MAX][0], 6, 6);␊
678␉␉␉const_tsc = bitfield(p->CPU.CPUID[CPUID_MAX][3], 8, 8);␊
679␉␉␉␊
680␉␉␉if (const_tsc != 0) verbose("Constant TSC!\n");␊
681␉␉␉if (amo == 1)␊
682␉␉␉{␊
683␉␉␉␉p->CPU.Features |= CPU_FEATURE_MOBILE;␊
684␉␉␉␉if (!strstr(p->CPU.BrandString, "obile")) verbose("Mobile ");␊
685␉␉␉}␊
686␉␉}␊
687␉␉//valv: 2nd attemp; just in case␊
688␉␉if (!platformCPUFeature(CPU_FEATURE_MOBILE))␊
689␉␉{␊
690␉␉␉if (strstr(p->CPU.BrandString, "obile"))␊
691␉␉␉{␊
692␉␉␉␉p->CPU.Features |= CPU_FEATURE_MOBILE;␊
693␉␉␉}␊
694␉␉}␊
695␉␉verbose("%s\n", p->CPU.BrandString);␊
696␊
697␉␉if(p->CPU.ExtFamily == 0x00 /* K8 */)␊
698␉␉{␊
699␉␉␉msr = rdmsr64(K8_FIDVID_STATUS);␊
700␉␉␉bus_ratio_max = (msr & 0x3f) / 2 + 4;␊
701␉␉␉currdiv = (msr & 0x01) * 2;␊
702␉␉␉if (bus_ratio_max)␊
703␉␉␉{␊
704␉␉␉␉if (currdiv)␊
705␉␉␉␉{␊
706␉␉␉␉␉fsbFrequency = ((tscFrequency * currdiv) / bus_ratio_max); // ?␊
707␉␉␉␉␉DBG("%d.%d\n", bus_ratio_max / currdiv, ((bus_ratio_max % currdiv) * 100) / currdiv);␊
708␉␉␉␉}␊
709␉␉␉␉else␊
710␉␉␉␉{␊
711␉␉␉␉␉fsbFrequency = (tscFrequency / bus_ratio_max);␊
712␉␉␉␉␉DBG("%d\n", bus_ratio_max);␊
713␉␉␉␉}␊
714␉␉␉␉//fsbFrequency = (tscFrequency / bus_ratio_max); // ?␊
715␉␉␉␉cpuFrequency = tscFrequency; // ?␊
716␉␉␉}␊
717␉␉}␊
718␉␉else if(p->CPU.ExtFamily >= 0x01 /* K10+ */)␊
719␉␉{␊
720␉␉␉msr = rdmsr64(K10_COFVID_STATUS);␊
721␉␉␉currdiv = (2 << ((msr >> 6) & 0x07)) / 2;␊
722␉␉␉msr = rdmsr64(AMD_10H_11H_CONFIG);␊
723␉␉␉if(p->CPU.ExtFamily == 0x01 /* K10 */)␊
724␉␉␉{␊
725␉␉␉␉bus_ratio_max = ((msr) & 0x3F);␊
726␉␉␉␉//currdiv = (((msr) >> 6) & 0x07);␊
727␉␉␉␉//cpuFrequency = 100 * (bus_ratio_max + 0x08) / (1 << currdiv);␊
728␉␉␉}␊
729␉␉␉else /* K11+ */␊
730␉␉␉{␊
731␉␉␉␉bus_ratio_max = ((msr) & 0x3F);␊
732␉␉␉␉//currdiv = (((msr) >> 6) & 0x07);␊
733␉␉␉␉//cpuFrequency = 100 * (bus_ratio_max + 0x10) / (1 << currdiv);␊
734␉␉␉}␊
735␉␉␉fsbFrequency = (tscFrequency / bus_ratio_max);␊
736␉␉␉cpuFrequency = tscFrequency;␊
737␉␉}␊
738␉␉␊
739␉␉p->CPU.MaxRatio = bus_ratio_max * 10;␊
740␉␉␊
741␉␉// valv: to be moved to acpi_patcher when ready␊
742/*␉␉msr_t amsr = rdmsr(K8_FIDVID_STATUS);␊
743␉␉uint8_t max_fid = (amsr.lo & 0x3F) >> 16;␊
744␉␉uint8_t min_fid = (amsr.lo & 0x3F) >> 8;␊
745␉␉uint8_t max_vid = (amsr.hi & 0x3F) >> 16;␊
746␉␉uint8_t min_vid = (amsr.hi & 0x3F) >> 8;␊
747␉␉verbose("AMD: max[fid: %d, vid: %d] min[fid: %d, vid: %d]\n", max_fid, max_vid, min_fid, min_vid);␊
748␊
749␊
750␉␉␉case 0x10:␉// phenom␊
751␉␉␉␉msr = rdmsr64(AMD_10H_11H_CONFIG);␊
752␉␉␉␉bus_ratio_max = ((msr) & 0x3F);␊
753␉␉␉␉currdiv = (((msr) >> 6) & 0x07);␊
754␉␉␉␉cpuFrequency = 100 * (bus_ratio_max + 0x08) / (1 << currdiv);␊
755␉␉␉␉break;␊
756␉␉␉case 0x11:␉// shangai␊
757␉␉␉␉msr = rdmsr64(AMD_10H_11H_CONFIG);␊
758␉␉␉␉bus_ratio_max = ((msr) & 0x3F);␊
759␉␉␉␉currdiv = (((msr) >> 6) & 0x07);␊
760␉␉␉␉cpuFrequency = 100 * (bus_ratio_max + 0x10) / (1 << currdiv);␊
761␉␉␉␉break;␊
762␉␉}␊
763*/␊
764␉}␊
765␉else if(p->CPU.Vendor == 0x746e6543 /* CENTAUR */ && p->CPU.Family == 6) //valv: partial!␊
766␉{␊
767␉␉msr = rdmsr64(MSR_EBL_CR_POWERON);␊
768␉␉int bus = (msr >> 18) & 0x3;␊
769␉␉switch (bus)␊
770␉␉{␊
771␉␉␉case 1:␊
772␉␉␉␉fsbFrequency = 133333333;␊
773␉␉␉␉break;␊
774␉␉␉case 2:␊
775␉␉␉␉fsbFrequency = 200000000;␊
776␉␉␉␉break;␊
777␉␉␉case 3:␊
778␉␉␉␉fsbFrequency = 166666667;␊
779␉␉␉␉break;␊
780␉␉␉case 0:␊
781␉␉␉default:␉␉␉␉␊
782␉␉␉␉fsbFrequency = 100000000;␊
783␉␉␉␉break;␊
784␉␉}␊
785␉␉msr_t msr;␊
786␉␉msr = rdmsr(MSR_IA32_PERF_STATUS);␊
787␉␉bus_ratio_min = (msr.lo >> 24) & 0x1f;␊
788␉␉min_ratio = bus_ratio_min * 10;␊
789␉␉bus_ratio_max = (msr.hi >> (40-32)) & 0x1f;␊
790␉␉max_ratio = bus_ratio_max * 10;␊
791␉␉cpuFrequency = ((fsbFrequency * max_ratio) / 10);␊
792␉}␊
793␊
794␉if (!fsbFrequency)␊
795␉{␊
796␉␉fsbFrequency = (DEFAULT_FSB * 1000);␊
797␉␉cpuFrequency = tscFrequency;␊
798␉␉DBG("0 ! using the default value for FSB !\n");␊
799␉}␊
800␊
801//#endif␊
802␊
803␉p->CPU.MaxDiv = maxdiv;␊
804␉p->CPU.CurrDiv = currdiv;␊
805␉p->CPU.TSCFrequency = tscFrequency;␊
806␉p->CPU.FSBFrequency = fsbFrequency;␊
807␉p->CPU.CPUFrequency = cpuFrequency;␊
808␉p->CPU.ISerie = false;␊
809␉p->CPU.Turbo = false;␊
810␊
811␉if(!fsbad) p->CPU.FSBIFrequency = fsbFrequency;␊
812␉else p->CPU.FSBIFrequency = fsbi;␊
813␊
814␉if (platformCPUFeature(CPU_FEATURE_EST))␊
815␉{␊
816␉␉msr_t msr32;␊
817␉␉msr32 = rdmsr(MSR_IA32_MISC_ENABLE);␊
818␉␉if (!(rdmsr64(MSR_IA32_MISC_ENABLE) & (1 << 16)))␊
819␉␉{␉//valv: we can also attempt to enable␊
820␉␉␉msr32.lo |= (1 << 16);␊
821␉␉␉// Lock till next reset!␊
822␉␉␉msr32.lo |= (1 << 20);␊
823␉␉␉wrmsr(MSR_IA32_MISC_ENABLE, msr32);␊
824␉␉␉delay(1);␊
825␉␉␉if(rdmsr64(MSR_IA32_MISC_ENABLE) & (1 << 16))␊
826␉␉␉{␊
827␉␉␉␉p->CPU.EST = 1;␊
828␉␉␉␉verbose("CPU: EIST Successfully Enabled!\n");␊
829␉␉␉}␊
830␉␉␉else␊
831␉␉␉{␊
832␉␉␉␉p->CPU.EST = 0;␊
833␉␉␉␉verbose("CPU: EIST couldn't be enabled!\n");␊
834␉␉␉}␊
835␉␉}␊
836␊
837␉␉else p->CPU.EST = 1;␊
838␉}␊
839␉␊
840␉if(core_i) p->CPU.ISerie = true;␊
841␉␉DBG("CPU: Vendor/Family/ExtFamily: 0x%x/0x%x/0x%x\n", p->CPU.Vendor, p->CPU.Family, p->CPU.ExtFamily);␊
842␉␉DBG("CPU: Model/ExtModel/Stepping: 0x%x/0x%x/0x%x\n", p->CPU.Model, p->CPU.ExtModel, p->CPU.Stepping);␊
843␉␉DBG("CPU: Multipliers x10: max=%d, min=%d\n", p->CPU.MaxRatio, p->CPU.MinRatio);␊
844␉if(turbo)␊
845␉{␊
846␉␉DBG("Turbo Ratio: %d/%d/%d/%d\n", p->CPU.Tone, p->CPU.Ttwo, p->CPU.Tthr, p->CPU.Tfor);␊
847␉␉p->CPU.Turbo = true;␊
848␉}␊
849␉␉DBG("CPU: MaxDiv/CurrDiv: 0x%x/0x%x\n", p->CPU.MaxDiv, p->CPU.CurrDiv);␊
850␉␉DBG("CPU: TSCFreq: %dMHz\n", p->CPU.TSCFrequency / 1000000);␊
851␉␉DBG("CPU: CPUFreq: %dMHz\n", p->CPU.CPUFrequency / 1000000);␊
852␉␉DBG("CPU: FSBFreq: %dMHz\n", p->CPU.FSBFrequency / 1000000);␊
853␉if(did)␊
854␉{␊
855␉␉p->CPU.SLFM = did;␊
856␉␉DBG("CPU: SLFM: %d\n", p->CPU.SLFM);␊
857␉}␊
858␉␉if(platformCPUFeature(CPU_FEATURE_EST))␊
859␉␉DBG("CPU: Enhanced SpeedStep: %d\n", p->CPU.EST);␊
860␉␉DBG("CPU: NoCores/NoThreads: %d/%d\n", p->CPU.NoCores, p->CPU.NoThreads);␊
861␉␉DBG("CPU: Features: 0x%08x\n", p->CPU.Features);␊
862}␊
863

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