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1/*␊
2 * Copyright 2008 Islam Ahmed Zaid. All rights reserved. <azismed@gmail.com>␊
3 * AsereBLN: 2009: cleanup and bugfix␊
4 * valv: 2010: fine-tuning and additions␊
5 */␊
6␊
7#include "libsaio.h"␊
8#include "platform.h"␊
9#include "cpu.h"␊
10#include "boot.h"␊
11#include "bootstruct.h"␊
12␊
13#ifndef DEBUG_CPU␊
14#define DEBUG_CPU 0␊
15#endif␊
16␊
17#if DEBUG_CPU␊
18#define DBG(x...)␉␉printf(x)␊
19#else␊
20#define DBG(x...)␉␉msglog(x)␊
21#endif␊
22␊
23/*␊
24 * DFE: Measures the TSC frequency in Hz (64-bit) using the ACPI PM timer␊
25 */␊
26static uint64_t measure_tsc_frequency(void)␊
27{␊
28 uint64_t tscStart;␊
29 uint64_t tscEnd;␊
30 uint64_t tscDelta = 0xffffffffffffffffULL;␊
31 unsigned long pollCount;␊
32 uint64_t retval = 0;␊
33 int i;␊
34␊
35 /* Time how many TSC ticks elapse in 30 msec using the 8254 PIT␊
36 * counter 2. We run this loop 3 times to make sure the cache␊
37 * is hot and we take the minimum delta from all of the runs.␊
38 * That is to say that we're biased towards measuring the minimum␊
39 * number of TSC ticks that occur while waiting for the timer to␊
40 * expire. That theoretically helps avoid inconsistencies when␊
41 * running under a VM if the TSC is not virtualized and the host␊
42 * steals time. The TSC is normally virtualized for VMware.␊
43 */␊
44 for(i = 0; i < 10; ++i)␊
45 {␊
46 enable_PIT2();␊
47 set_PIT2_mode0(CALIBRATE_LATCH);␊
48 tscStart = rdtsc64();␊
49 pollCount = poll_PIT2_gate();␊
50 tscEnd = rdtsc64();␊
51 /* The poll loop must have run at least a few times for accuracy */␊
52 if(pollCount <= 1)␊
53 continue;␊
54 /* The TSC must increment at LEAST once every millisecond. We␊
55 * should have waited exactly 30 msec so the TSC delta should␊
56 * be >= 30. Anything less and the processor is way too slow.␊
57 */␊
58 if((tscEnd - tscStart) <= CALIBRATE_TIME_MSEC)␊
59 continue;␊
60 // tscDelta = min(tscDelta, (tscEnd - tscStart))␊
61 if( (tscEnd - tscStart) < tscDelta )␊
62 tscDelta = tscEnd - tscStart;␊
63 }␊
64 /* tscDelta is now the least number of TSC ticks the processor made in␊
65 * a timespan of 0.03 s (e.g. 30 milliseconds)␊
66 * Linux thus divides by 30 which gives the answer in kiloHertz because␊
67 * 1 / ms = kHz. But we're xnu and most of the rest of the code uses␊
68 * Hz so we need to convert our milliseconds to seconds. Since we're␊
69 * dividing by the milliseconds, we simply multiply by 1000.␊
70 */␊
71␊
72 /* Unlike linux, we're not limited to 32-bit, but we do need to take care␊
73 * that we're going to multiply by 1000 first so we do need at least some␊
74 * arithmetic headroom. For now, 32-bit should be enough.␊
75 * Also unlike Linux, our compiler can do 64-bit integer arithmetic.␊
76 */␊
77 if(tscDelta > (1ULL<<32))␊
78 retval = 0;␊
79 else␊
80 {␊
81 retval = tscDelta * 1000 / 30;␊
82 }␊
83 disable_PIT2();␊
84 return retval;␊
85}␊
86␊
87␊
88/*␊
89 * Calculates the FSB and CPU frequencies using specific MSRs for each CPU␊
90 * - multi. is read from a specific MSR. In the case of Intel, there is:␊
91 * a max multi. (used to calculate the FSB freq.),␊
92 * and a current multi. (used to calculate the CPU freq.)␊
93 * - fsbFrequency = tscFrequency / multi␊
94 * - cpuFrequency = fsbFrequency * multi␊
95 */␊
96␊
97void scan_cpu(PlatformInfo_t *p)␊
98{␊
99␉const char␉*newratio, *newfsb;␊
100␉int␉␉␉len, myfsb, i;␊
101␉uint64_t␉tscFrequency, fsbFrequency, cpuFrequency, fsbi;␊
102␉uint64_t␉msr, flex_ratio = 0;␊
103␉uint32_t␉tms, ida, max_ratio, min_ratio;␊
104␉uint8_t␉␉bus_ratio_max, maxdiv, bus_ratio_min, currdiv;␊
105␉bool␉␉fix_fsb, did, core_i, turbo, isatom, fsbad;␊
106␊
107␉max_ratio = min_ratio = myfsb = bus_ratio_max = maxdiv = bus_ratio_min = currdiv = i = 0;␊
108␊
109␉/* get cpuid values */␊
110␉for( ; i <= 3; i++)␊
111␉{␊
112␉␉do_cpuid(i, p->CPU.CPUID[i]);␊
113␉}␊
114␉␊
115␉do_cpuid2(0x00000004, 0, p->CPU.CPUID[CPUID_4]);␊
116␉do_cpuid(0x80000000, p->CPU.CPUID[CPUID_80]);␊
117␉if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 1) {␊
118␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊
119␉}␊
120#if DEBUG_CPU␊
121␉{␊
122␉␉int␉␉i;␊
123␉␉printf("CPUID Raw Values:\n");␊
124␉␉for (i=0; i<CPUID_MAX; i++) {␊
125␉␉␉printf("%02d: %08x-%08x-%08x-%08x\n", i,␊
126␉␉␉␉p->CPU.CPUID[i][0], p->CPU.CPUID[i][1],␊
127␉␉␉␉p->CPU.CPUID[i][2], p->CPU.CPUID[i][3]);␊
128␉␉}␊
129␉}␊
130#endif␊
131␉p->CPU.Vendor␉␉= p->CPU.CPUID[CPUID_0][1];␊
132␉p->CPU.Signature␉= p->CPU.CPUID[CPUID_1][0];␊
133␉p->CPU.Stepping␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 3, 0);␊
134␉p->CPU.Model␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 7, 4);␊
135␉p->CPU.Type␉␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 13, 12);␊
136␉p->CPU.Family␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 11, 8);␊
137␉p->CPU.ExtModel␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 19, 16);␊
138␉p->CPU.ExtFamily␉= bitfield(p->CPU.CPUID[CPUID_1][0], 27, 20);␊
139␉p->CPU.NoThreads␉= bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␊
140␉p->CPU.NoCores␉␉= bitfield(p->CPU.CPUID[CPUID_4][0], 31, 26) + 1;␊
141␊
142␉p->CPU.Model += (p->CPU.ExtModel << 4);␊
143␊
144␉/* get brand string (if supported) */␊
145␉/* Copyright: from Apple's XNU cpuid.c */␊
146␉if (p->CPU.CPUID[CPUID_80][0] > 0x80000004) {␊
147␉␉uint32_t␉reg[4];␊
148 char str[128], *s;␊
149␉␉/*␊
150␉␉ * The brand string 48 bytes (max), guaranteed to␊
151␉␉ * be NUL terminated.␊
152␉␉ */␊
153␉␉do_cpuid(0x80000002, reg);␊
154␉␉bcopy((char *)reg, &str[0], 16);␊
155␉␉do_cpuid(0x80000003, reg);␊
156␉␉bcopy((char *)reg, &str[16], 16);␊
157␉␉do_cpuid(0x80000004, reg);␊
158␉␉bcopy((char *)reg, &str[32], 16);␊
159␉␉for (s = str; *s != '\0'; s++) {␊
160␉␉␉if (*s != ' ') break;␊
161␉␉}␊
162␉␉␊
163␉␉strlcpy(p->CPU.BrandString,␉s, sizeof(p->CPU.BrandString));␊
164␉␉␊
165␉␉if (!strncmp(p->CPU.BrandString, CPU_STRING_UNKNOWN, min(sizeof(p->CPU.BrandString), strlen(CPU_STRING_UNKNOWN) + 1))) {␊
166␉␉␉ /*␊
167␉␉␉ * This string means we have a firmware-programmable brand string,␊
168␉␉␉ * and the firmware couldn't figure out what sort of CPU we have.␊
169␉␉␉ */␊
170␉␉␉ p->CPU.BrandString[0] = '\0';␊
171␉␉ }␊
172␉}␊
173␉␊
174␉/* setup features */␊
175␉p->CPU.Features |= (CPU_FEATURE_MMX | CPU_FEATURE_SSE | CPU_FEATURE_SSE2 | CPU_FEATURE_MSR | CPU_FEATURE_APIC | CPU_FEATURE_TM1 | CPU_FEATURE_ACPI) & p->CPU.CPUID[CPUID_1][3];␊
176␉p->CPU.Features |= (CPU_FEATURE_SSE3 | CPU_FEATURE_SSE41 | CPU_FEATURE_SSE42 | CPU_FEATURE_EST | CPU_FEATURE_TM2 | CPU_FEATURE_SSSE3 | CPU_FEATURE_xAPIC) & p->CPU.CPUID[CPUID_1][2];␊
177␉p->CPU.Features |= (CPU_FEATURE_EM64T | CPU_FEATURE_XD) & p->CPU.CPUID[CPUID_81][3];␊
178␉p->CPU.Features |= (CPU_FEATURE_LAHF) & p->CPU.CPUID[CPUID_81][2];␊
179␊
180␊
181␉//if ((CPU_FEATURE_HTT & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
182␉if (p->CPU.NoThreads > p->CPU.NoCores) {␊
183␉␉p->CPU.Features |= CPU_FEATURE_HTT;␊
184␉}␊
185␉ ␊
186␊
187␉tscFrequency = measure_tsc_frequency();␊
188␉fsbFrequency = 0;␊
189␉cpuFrequency = 0;␊
190␉fsbi = 0;␊
191␉fix_fsb = false;␊
192␉did = false;␊
193␉core_i = false;␊
194␉turbo = false;␊
195␉isatom = false;␊
196␉fsbad = false;␊
197␊
198␉if ((p->CPU.Vendor == 0x756E6547 /* Intel */) && ((p->CPU.Family == 0x06) || (p->CPU.Family == 0x0f)))␊
199␉{␊
200␉␉verbose("CPU: ");␊
201␉␉int tjmax = 0;␊
202␉␉msr = rdmsr64(MSR_IA32_PLATFORM_ID);␊
203␉␉if((((msr >> 50) & 0x01) == 1) || (rdmsr64(0x17) & (1<<28)))␊
204␉␉{␊
205␉␉␉p->CPU.Features |= CPU_FEATURE_MOBILE;␊
206␉␉␉verbose("Mobile ");␊
207␉␉}␊
208␉␉verbose("%s\n", p->CPU.BrandString);␊
209␉␉␊
210␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) || (p->CPU.Family == 0x0f && p->CPU.Model >= 0x03))␊
211␉␉{␊
212␉␉␉if (p->CPU.Family == 0x06)␊
213␉␉␉{␊
214␉␉␉␉int intelCPU = p->CPU.Model;␊
215␉␉␉␉int Stepp = p->CPU.Stepping;␊
216␉␉␉␉int bus;␊
217␊
218␉␉␉␉switch (intelCPU)␊
219␉␉␉␉{␊
220␉␉␉␉␉case 0xc:␉␉// Core i7 & Atom␊
221␉␉␉␉␉␉if (strstr(p->CPU.BrandString, "Atom")) goto teleport1;␊
222␉␉␉␉␉case 0x1a:␉␉// Core i7 LGA1366, Xeon 5500, "Bloomfield", "Gainstown", 45nm␊
223␉␉␉␉␉case 0x1e:␉␉// Core i7, i5 LGA1156, "Clarksfield", "Lynnfield", "Jasper", 45nm␊
224␉␉␉␉␉case 0x1f:␉␉// Core i7, i5, Nehalem␊
225␉␉␉␉␉case 0x25:␉␉// Core i7, i5, i3 LGA1156, "Westmere", "Clarkdale", "Arrandale", 32nm␊
226␉␉␉␉␉case 0x2a:␉␉// Sandy Bridge, 32nm␊
227␉␉␉␉␉case 0x2c:␉␉// Core i7 LGA1366, Six-core, "Westmere", "Gulftown", 32nm␊
228␉␉␉␉␉case 0x2e:␉␉// Core i7, Nehalem-Ex Xeon, "Beckton"␊
229␉␉␉␉␉case 0x2f:␉␉// Core i7, Nehalem-Ex Xeon, "Eagleton"␊
230␉␉␉␉␉␉core_i = true;␊
231␉␉␉␉␉␉tjmax = (rdmsr64(MSR_THERMAL_TARGET) >> 16) & 0xff;␊
232␉␉␉␉␉␉msr = rdmsr64(MSR_PLATFORM_INFO);␊
233␉␉␉␉␉␉bus_ratio_max = (msr >> 8) & 0xff;␊
234␉␉␉␉␉␉bus_ratio_min = (msr >> 40) & 0xff; //valv: not sure about this one (Remarq.1)␊
235␉␉␉␉␉␉verbose("CPU: Flex-Ratio = %d ", bus_ratio_max);␊
236␉␉␉␉␉␉min_ratio = bus_ratio_min * 10;␊
237␉␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊
238␉␉␉␉␉␉if ((msr >> 16) & 0x01)␊
239␉␉␉␉␉␉{␊
240␉␉␉␉␉␉␉flex_ratio = (msr >> 8) & 0xff;␊
241␉␉␉␉␉␉␉verbose(">> %d", flex_ratio);␊
242␉␉␉␉␉␉␉if(bus_ratio_max > flex_ratio) bus_ratio_max = flex_ratio;␊
243␉␉␉␉␉␉}␊
244␉␉␉␉␉␉verbose("\n");␊
245␉␉␉␉␉␉if(bus_ratio_max) fsbFrequency = (tscFrequency / bus_ratio_max);␊
246␊
247␉␉␉␉␉␉//valv: Turbo Ratio Limit␊
248␉␉␉␉␉␉if ((intelCPU != 0x2e) && (intelCPU != 0x2f))␊
249␉␉␉␉␉␉{␊
250␉␉␉␉␉␉␉turbo = true;␊
251␉␉␉␉␉␉␉msr = rdmsr64(MSR_TURBO_RATIO_LIMIT);␊
252␉␉␉␉␉␉␉␊
253␉␉␉␉␉␉␉p->CPU.Tone = (msr >> 0) & 0xff;␊
254␉␉␉␉␉␉␉p->CPU.Ttwo = (msr >> 8) & 0xff;␊
255␉␉␉␉␉␉␉p->CPU.Tthr = (msr >> 16) & 0xff;␊
256␉␉␉␉␉␉␉p->CPU.Tfor = (msr >> 24) & 0xff;␊
257␊
258␉␉␉␉␉␉␉cpuFrequency = bus_ratio_max * fsbFrequency;␊
259␉␉␉␉␉␉␉max_ratio = bus_ratio_max * 10;␊
260␉␉␉␉␉␉}␊
261␉␉␉␉␉␉else cpuFrequency = tscFrequency;␊
262␊
263␉␉␉␉␉␉if ((getValueForKey(kbusratio, &newratio, &len, &bootInfo->bootConfig)) && (len <= 4))␊
264␉␉␉␉␉␉{␊
265␉␉␉␉␉␉␉max_ratio = atoi(newratio);␊
266␉␉␉␉␉␉␉max_ratio = (max_ratio * 10);␊
267␉␉␉␉␉␉␉if (len >= 3) max_ratio = (max_ratio + 5);␊
268␊
269␉␉␉␉␉␉␉verbose("Bus-Ratio: min=%d%s, max=%d%s\n", bus_ratio_min, bus_ratio_max);␊
270␊
271␉␉␉␉␉␉␉// extreme overclockers may love 320 ;)␊
272␉␉␉␉␉␉␉if ((max_ratio >= min_ratio) && (max_ratio <= 320))␊
273␉␉␉␉␉␉␉{␊
274␉␉␉␉␉␉␉␉cpuFrequency = (fsbFrequency * max_ratio) / 10;␊
275␉␉␉␉␉␉␉␉if (len >= 3) maxdiv = 1;␊
276␉␉␉␉␉␉␉␉else maxdiv = 0;␊
277␉␉␉␉␉␉␉␉verbose("Sticking with [BCLK: %dMhz, Bus-Ratio: %s]\n", myfsb, newratio);␊
278␉␉␉␉␉␉␉}␊
279␉␉␉␉␉␉␉else max_ratio = (bus_ratio_max * 10);␊
280␉␉␉␉␉␉}␊
281␉␉␉␉␉␉//valv: to be uncommented if Remarq.1 didn't stick␊
282␉␉␉␉␉␉/*if(bus_ratio_max > 0) bus_ratio = flex_ratio;*/␊
283␉␉␉␉␉␉p->CPU.MaxRatio = max_ratio;␊
284␉␉␉␉␉␉p->CPU.MinRatio = min_ratio;␊
285␉␉␉␉␉␉␊
286␉␉␉␉␉␉//fsbi = fsbFrequency;␊
287␉␉␉␉␉␉if(getIntForKey(kForceFSB, &myfsb, &bootInfo->bootConfig)) goto forcefsb;␊
288␉␉␉␉␉␉break;␊
289␉␉␉␉␉case 0xd:␉␉// Pentium M, Dothan, 90nm␊
290␉␉␉␉␉case 0xe:␉␉// Core Duo/Solo, Pentium M DC␊
291␉␉␉␉␉␉␉teleport1:␊
292␉␉␉␉␉␉␉msr = rdmsr64(MSR_IA32_EXT_CONFIG);␊
293␉␉␉␉␉␉␉if(msr & (1 << 30)) tjmax = 85;␊
294␉␉␉␉␉␉␉goto teleport2;␊
295␉␉␉␉␉case 0xf:␉␉// Core Xeon, Core 2 DC, 65nm␊
296␉␉␉␉␉␉switch (Stepp)␊
297␉␉␉␉␉␉{␊
298␉␉␉␉␉␉␉case 0x2:␊
299␉␉␉␉␉␉␉␉tjmax = 95;␊
300␉␉␉␉␉␉␉␉break;␊
301␉␉␉␉␉␉␉case 0x6:␊
302␉␉␉␉␉␉␉␉if (p->CPU.NoCores = 2) tjmax = 80;␊
303␉␉␉␉␉␉␉␉if (p->CPU.NoCores = 4) tjmax = 90;␊
304␉␉␉␉␉␉␉␉else tjmax = 85;␊
305␉␉␉␉␉␉␉␉break;␊
306␉␉␉␉␉␉␉case 0xb:␊
307␉␉␉␉␉␉␉␉tjmax = 90;␊
308␉␉␉␉␉␉␉␉break;␊
309␉␉␉␉␉␉␉case 0xd:␊
310␉␉␉␉␉␉␉default:␊
311␉␉␉␉␉␉␉␉msr = rdmsr64(MSR_IA32_EXT_CONFIG);␊
312␉␉␉␉␉␉␉␉if(msr & (1 << 30)) tjmax = 85;␊
313␉␉␉␉␉␉␉␉break;␊
314␉␉␉␉␉␉}␊
315␉␉␉␉␉case 0x1c:␉␉// Atom :)␊
316␉␉␉␉␉␉switch (Stepp)␊
317␉␉␉␉␉␉{␊
318␉␉␉␉␉␉␉case 0xa:␊
319␉␉␉␉␉␉␉␉tjmax = 100;␊
320␉␉␉␉␉␉␉␉break;␊
321␉␉␉␉␉␉␉case 0x2:␊
322␉␉␉␉␉␉␉default:␊
323␉␉␉␉␉␉␉␉tjmax = 90;␊
324␉␉␉␉␉␉␉␉break;␊
325␉␉␉␉␉␉}␊
326␉␉␉␉␉case 0x17:␉␉// Core 2 Duo/Extreme, Xeon, 45nm␊
327␉␉␉␉␉␉switch (Stepp)␊
328␉␉␉␉␉␉{␊
329␉␉␉␉␉␉␉case 0x6:␉␉// Mobile Core2 Duo␊
330␉␉␉␉␉␉␉␉tjmax = 104;␊
331␉␉␉␉␉␉␉␉break;␊
332␉␉␉␉␉␉␉case 0xa:␉␉// Mobile Centrino 2␊
333␉␉␉␉␉␉␉␉tjmax = 105;␊
334␉␉␉␉␉␉␉␉break;␊
335␉␉␉␉␉␉␉default:␊
336␉␉␉␉␉␉␉␉if (platformCPUFeature(CPU_FEATURE_MOBILE)) tjmax = 105;␊
337␉␉␉␉␉␉␉␉break;␊
338␉␉␉␉␉␉}␊
339␉␉␉␉␉case 0x16:␉␉// Celeron, Core 2 SC, 65nm␊
340␉␉␉␉␉case 0x27:␉␉// Atom Lincroft, 45nm␊
341␉␉␉␉␉␉teleport2:␊
342␉␉␉␉␉␉core_i = false;␊
343␉␉␉␉␉␉//valv: todo: msr_therm2_ctl (0x19d) bit 16 (mode of automatic thermal monitor): 0=tm1, 1=tm2␊
344␉␉␉␉␉␉//also, if bit 3 of misc_enable is cleared the above would have no effect␊
345␉␉␉␉␉␉if (strstr(p->CPU.BrandString, "Atom"))␊
346␉␉␉␉␉␉␉isatom = true;␊
347␉␉␉␉␉␉if(!isatom && (platformCPUFeature(CPU_FEATURE_TM1)))␊
348␉␉␉␉␉␉{␊
349␉␉␉␉␉␉␉msr_t msr32;␊
350␉␉␉␉␉␉␉msr32 = rdmsr(MSR_IA32_MISC_ENABLE);␊
351␉␉␉␉␉␉␉bool tmfix = false;␊
352␉␉␉␉␉␉␉getBoolForKey(kFixTM, &tmfix, &bootInfo->bootConfig);␊
353␉␉␉␉␉␉␉if(tmfix)␊
354␉␉␉␉␉␉␉{␉␊
355␉␉␉␉␉␉␉␉//thermally-initiated on-die modulation of the stop-clock duty cycle␊
356␉␉␉␉␉␉␉␉if(!(rdmsr64(MSR_IA32_MISC_ENABLE) & (1 << 3))) msr32.lo |= (1 << 3);␊
357␉␉␉␉␉␉␉␉verbose("CPU: Thermal Monitor: TM, ");␊
358␉␉␉␉␉␉␉␉␊
359␉␉␉␉␉␉␉␉//BIOS must enable this feature if the TM2 feature flag (CPUID.1:ECX[8]) is set␊
360␉␉␉␉␉␉␉␉if(platformCPUFeature(CPU_FEATURE_TM2))␊
361␉␉␉␉␉␉␉␉{␊
362␉␉␉␉␉␉␉␉␉//thermally-initiated frequency transitions␊
363␉␉␉␉␉␉␉␉␉msr32.lo |= (1 << 13);␊
364␉␉␉␉␉␉␉␉␉verbose("TM2, ");␊
365␉␉␉␉␉␉␉␉}␊
366␉␉␉␉␉␉␉␉msr32.lo |= (1 << 17);␊
367␉␉␉␉␉␉␉␉verbose("PROCHOT, ");␊
368␉␉␉␉␉␉␉␉msr32.lo |= (1 << 10);␊
369␉␉␉␉␉␉␉␉verbose("FERR\n");␊
370␉␉␉␉␉␉␉}␊
371␉␉␉␉␉␉␉bool oem_ssdt, tmpval;␊
372␉␉␉␉␉␉␉oem_ssdt = false;␊
373␉␉␉␉␉␉␉␊
374␉␉␉␉␉␉␉oem_ssdt = getBoolForKey(kOEMSSDT, &tmpval, &bootInfo->bootConfig)&&tmpval;␊
375␉␉␉␉␉␉␉if(oem_ssdt)␊
376␉␉␉␉␉␉␉{␊
377␉␉␉␉␉␉␉␉bool c2e, c4e, hc4e;␊
378␉␉␉␉␉␉␉␉c2e = c4e = hc4e = false;␊
379␊
380␉␉␉␉␉␉␉␉getBoolForKey(kC2EEnable, &c2e, &bootInfo->bootConfig);␊
381␉␉␉␉␉␉␉␉if(c2e) msr32.lo |= (1 << 26);␊
382␉␉␉␉␉␉␉␉␊
383␉␉␉␉␉␉␉␉getBoolForKey(kC4EEnable, &c4e, &bootInfo->bootConfig);␊
384␉␉␉␉␉␉␉␉if((c4e) && platformCPUFeature(CPU_FEATURE_MOBILE)) msr32.hi |= (1 << (32 - 32));␊
385␉␉␉␉␉␉␉␉getBoolForKey(kHardC4EEnable, &hc4e, &bootInfo->bootConfig);␊
386␉␉␉␉␉␉␉␉if((hc4e) && platformCPUFeature(CPU_FEATURE_MOBILE)) msr32.hi |= (1 << (33 - 32));␊
387␉␉␉␉␉␉␉␉if(c2e || c4e || hc4e) tmfix = true;␊
388␉␉␉␉␉␉␉}␊
389␉␉␉␉␉␉␉␊
390␉␉␉␉␉␉␉if(tmfix)␊
391␉␉␉␉␉␉␉{␊
392␉␉␉␉␉␉␉␉msr32.hi |= (1 << (36 - 32)); // EMTTM␊
393␉␉␉␉␉␉␉␉wrmsr(MSR_IA32_MISC_ENABLE, msr32);␊
394␉␉␉␉␉␉␉}␊
395␉␉␉␉␉␉␉if(tmfix)␊
396␉␉␉␉␉␉␉{␊
397␉␉␉␉␉␉␉␉msr32 = rdmsr(PIC_SENS_CFG);␊
398␉␉␉␉␉␉␉␉msr32.lo |= (1 << 21);␊
399␉␉␉␉␉␉␉␉wrmsr(PIC_SENS_CFG, msr32);␊
400␉␉␉␉␉␉␉}␊
401␉␉␉␉␉␉}␊
402␉␉␉␉␉␉␊
403␉␉␉␉␉␉if (rdmsr64(MSR_IA32_EXT_CONFIG) & (1 << 27))␊
404␉␉␉␉␉␉{␊
405␉␉␉␉␉␉␉wrmsr64(MSR_IA32_EXT_CONFIG, (rdmsr64(MSR_IA32_EXT_CONFIG) | (1 << 28)));␊
406␉␉␉␉␉␉␉delay(1);␊
407␉␉␉␉␉␉␉did = rdmsr64(MSR_IA32_EXT_CONFIG) & (1 << 28);␊
408␉␉␉␉␉␉}␊
409␉␉␉␉␉␉getBoolForKey(kFixFSB, &fix_fsb, &bootInfo->bootConfig);␊
410␉␉␉␉␉␉if(fix_fsb)␊
411␉␉␉␉␉␉{␊
412␉␉␉␉␉␉␉msr = rdmsr64(MSR_FSB_FREQ);␊
413␉␉␉␉␉␉␉bus = (msr >> 0) & 0x7;␊
414␉␉␉␉␉␉␉if(p->CPU.Model == 0xd && bus == 0)␊
415␉␉␉␉␉␉␉{␊
416␉␉␉␉␉␉␉␉fsbFrequency = 100000000;␊
417␉␉␉␉␉␉␉␉myfsb = 100;␊
418␉␉␉␉␉␉␉}␊
419␉␉␉␉␉␉␉else if(p->CPU.Model == 0xe && p->CPU.ExtModel == 1) goto ratio;␊
420␉␉␉␉␉␉␉else␊
421␉␉␉␉␉␉␉{␊
422␉␉␉␉␉␉␉␉switch (bus)␊
423␉␉␉␉␉␉␉␉{␊
424␉␉␉␉␉␉␉␉␉case 0:␊
425␉␉␉␉␉␉␉␉␉␉fsbFrequency = 266666667;␊
426␉␉␉␉␉␉␉␉␉␉myfsb = 266;␊
427␉␉␉␉␉␉␉␉␉␉break;␊
428␉␉␉␉␉␉␉␉␉case 1:␊
429␉␉␉␉␉␉␉␉␉␉fsbFrequency = 133333333;␊
430␉␉␉␉␉␉␉␉␉␉myfsb = 133;␊
431␉␉␉␉␉␉␉␉␉␉break;␊
432␉␉␉␉␉␉␉␉␉case 3:␊
433␉␉␉␉␉␉␉␉␉␉fsbFrequency = 166666667;␊
434␉␉␉␉␉␉␉␉␉␉myfsb = 166;␊
435␉␉␉␉␉␉␉␉␉␉break;␊
436␉␉␉␉␉␉␉␉␉case 4:␊
437␉␉␉␉␉␉␉␉␉␉fsbFrequency = 333333333;␊
438␉␉␉␉␉␉␉␉␉␉myfsb = 333;␊
439␉␉␉␉␉␉␉␉␉␉break;␊
440␉␉␉␉␉␉␉␉␉case 5:␊
441␉␉␉␉␉␉␉␉␉␉fsbFrequency = 100000000;␊
442␉␉␉␉␉␉␉␉␉␉myfsb = 100;␊
443␉␉␉␉␉␉␉␉␉␉break;␊
444␉␉␉␉␉␉␉␉␉case 6:␊
445␉␉␉␉␉␉␉␉␉␉fsbFrequency = 400000000;␊
446␉␉␉␉␉␉␉␉␉␉myfsb = 400;␊
447␉␉␉␉␉␉␉␉␉␉break;␊
448␉␉␉␉␉␉␉␉␉case 2:␊
449␉␉␉␉␉␉␉␉␉default:␊
450␉␉␉␉␉␉␉␉␉␉fsbFrequency = 200000000;␊
451␉␉␉␉␉␉␉␉␉␉myfsb = 200;␊
452␉␉␉␉␉␉␉␉␉␉break;␊
453␉␉␉␉␉␉␉␉}␊
454␉␉␉␉␉␉␉}␊
455␉␉␉␉␉␉␉uint64_t minfsb = 182000000, maxfsb = 185000000;␊
456␉␉␉␉␉␉␉if(((fsbFrequency > minfsb) && (fsbFrequency < maxfsb)) || !fsbFrequency)␊
457␉␉␉␉␉␉␉{␊
458␉␉␉␉␉␉␉␉fsbFrequency = 200000000;␊
459␉␉␉␉␉␉␉␉fsbad = true;␊
460␉␉␉␉␉␉␉}␊
461␉␉␉␉␉␉␉goto ratio;␊
462␉␉␉␉␉␉}␊
463␉␉␉␉␉case 0x1d:␉␉// Xeon MP MP 7400␊
464␉␉␉␉␉// for 0x2a & 0x2b turbo is true;␊
465␉␉␉␉␉//case 0x2a:␉␉// SNB␊
466␉␉␉␉␉//case 0x2b:␉␉// SNB Xeon␊
467␉␉␉␉␉default:␊
468␉␉␉␉␉␉if(getIntForKey(kForceFSB, &myfsb, &bootInfo->bootConfig))␊
469␉␉␉␉␉␉{␊
470␉␉␉␉␉␉␉forcefsb:␊
471␉␉␉␉␉␉␉switch(myfsb)␊
472␉␉␉␉␉␉␉{␊
473␉␉␉␉␉␉␉␉case 133:␊
474␉␉␉␉␉␉␉␉␉fsbFrequency = 133333333;␊
475␉␉␉␉␉␉␉␉␉break;␊
476␉␉␉␉␉␉␉␉case 166:␊
477␉␉␉␉␉␉␉␉␉fsbFrequency = 166666667;␊
478␉␉␉␉␉␉␉␉␉break;␊
479␉␉␉␉␉␉␉␉case 233:␊
480␉␉␉␉␉␉␉␉␉fsbFrequency = 233333333;␊
481␉␉␉␉␉␉␉␉␉break;␊
482␉␉␉␉␉␉␉␉case 266:␊
483␉␉␉␉␉␉␉␉␉fsbFrequency = 266666667;␊
484␉␉␉␉␉␉␉␉␉break;␊
485␉␉␉␉␉␉␉␉case 333:␊
486␉␉␉␉␉␉␉␉␉fsbFrequency = 333333333;␊
487␉␉␉␉␉␉␉␉␉break;␊
488␉␉␉␉␉␉␉␉case 100:␊
489␉␉␉␉␉␉␉␉case 200:␊
490␉␉␉␉␉␉␉␉case 400:␊
491␉␉␉␉␉␉␉␉␉fsbFrequency = (myfsb * 1000000);␊
492␉␉␉␉␉␉␉␉␉break;␊
493␉␉␉␉␉␉␉␉default:␊
494␉␉␉␉␉␉␉␉␉getValueForKey(kForceFSB, &newfsb, &len, &bootInfo->bootConfig);␊
495␉␉␉␉␉␉␉␉␉if((len <= 3) && (myfsb < 400))␊
496␉␉␉␉␉␉␉␉␉{␊
497␉␉␉␉␉␉␉␉␉␉fsbFrequency = (myfsb * 1000000);␊
498␉␉␉␉␉␉␉␉␉␉verbose("Specified FSB: %dMhz. Assuming you know what you 're doing !\n", myfsb);␊
499␉␉␉␉␉␉␉␉␉}␊
500␉␉␉␉␉␉␉␉␉else if(core_i) fsbFrequency = 133333333;␊
501␉␉␉␉␉␉␉␉␉else fsbFrequency = 200000000;␊
502␉␉␉␉␉␉␉␉␉break;␊
503␉␉␉␉␉␉␉}␊
504␉␉␉␉␉␉␉if(core_i)␊
505␉␉␉␉␉␉␉{␊
506␉␉␉␉␉␉␉␉cpuFrequency = (fsbFrequency * max_ratio) / 10;␊
507␉␉␉␉␉␉␉␉verbose("Sticking with [BCLK: %dMhz, Bus-Ratio: %s]\n", myfsb, newratio);␊
508␉␉␉␉␉␉␉␉break;␊
509␉␉␉␉␉␉␉}␊
510␉␉␉␉␉␉␉fix_fsb = true;␊
511␉␉␉␉␉␉}␊
512␉␉␉␉␉␉goto ratio;␊
513␉␉␉␉␉␉break;␊
514␉␉␉␉}␊
515␉␉␉}␊
516␉␉␉else␊
517␉␉␉{␊
518␉␉␉␉ratio:␊
519␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_STATUS);␊
520␉␉␉␉maxdiv = (msr >> 46) & 0x01;␊
521␉␉␉␉//valv: this seems to be bit 15 instead of 14.␊
522␉␉␉␉currdiv = (msr >> 15) & 0x01;␊
523␉␉␉␉uint8_t XE = (msr >> 31) & 0x01;␊
524␊
525␉␉␉␉msr_t msr32;␊
526␉␉␉␉msr32 = rdmsr(MSR_IA32_PERF_STATUS);␊
527␉␉␉␉bus_ratio_min = (msr32.lo >> 24) & 0x1f;␊
528␉␉␉␉min_ratio = bus_ratio_min * 10;␊
529␉␉␉␉if(currdiv) min_ratio = min_ratio + 5;␊
530␉␉␉␉␊
531␉␉␉␉if(XE || (p->CPU.Family == 0x0f)) bus_ratio_max = (msr32.hi >> (40-32)) & 0x1f;␊
532␉␉␉␉else bus_ratio_max = ((rdmsr64(MSR_IA32_PLATFORM_ID) >> 8) & 0x1f);␊
533␉␉␉␉/* On lower models, currcoef defines TSC freq */␊
534␉␉␉␉if (((p->CPU.Family == 0x06) && (p->CPU.Model < 0x0e)) && (p->CPU.Family != 0x0f)) bus_ratio_max = bus_ratio_min;␊
535␉␉␉␉// bad hack! Could force a value relying on kpstates, but I fail to see its benefits.␊
536␉␉␉␉if(bus_ratio_min == 0) bus_ratio_min = bus_ratio_max;␊
537␉␉␉␉␊
538␉␉␉␉if(p->CPU.Family == 0x0f)␊
539␉␉␉␉{␊
540␉␉␉␉␉getBoolForKey(kFixFSB, &fix_fsb, &bootInfo->bootConfig);␊
541␉␉␉␉␉if(fix_fsb)␊
542␉␉␉␉␉{␊
543␉␉␉␉␉␉msr = rdmsr64(MSR_EBC_FREQUENCY_ID);␊
544␉␉␉␉␉␉int bus = (msr >> 16) & 0x7;␊
545␉␉␉␉␉␉switch (bus)␊
546␉␉␉␉␉␉{␊
547␉␉␉␉␉␉␉case 0:␊
548␉␉␉␉␉␉␉␉fsbFrequency = 266666667;␊
549␉␉␉␉␉␉␉␉myfsb = 266;␊
550␉␉␉␉␉␉␉␉break;␊
551␉␉␉␉␉␉␉case 1:␊
552␉␉␉␉␉␉␉␉fsbFrequency = 133333333;␊
553␉␉␉␉␉␉␉␉myfsb = 133;␊
554␉␉␉␉␉␉␉␉break;␊
555␉␉␉␉␉␉␉case 3:␊
556␉␉␉␉␉␉␉␉fsbFrequency = 166666667;␊
557␉␉␉␉␉␉␉␉myfsb = 166;␊
558␉␉␉␉␉␉␉␉break;␊
559␉␉␉␉␉␉␉case 2:␊
560␉␉␉␉␉␉␉default:␊
561␉␉␉␉␉␉␉␉fsbFrequency = 200000000;␊
562␉␉␉␉␉␉␉␉myfsb = 200;␊
563␉␉␉␉␉␉␉␉break;␊
564␉␉␉␉␉␉}␊
565␉␉␉␉␉␉uint64_t minfsb = 183000000, maxfsb = 185000000;␊
566␉␉␉␉␉␉if (((fsbFrequency > minfsb) && (fsbFrequency < maxfsb)) || (!fsbFrequency))␊
567␉␉␉␉␉␉{␊
568␉␉␉␉␉␉␉fsbFrequency = 200000000;␊
569␉␉␉␉␉␉␉fsbad = true;␊
570␉␉␉␉␉␉}␊
571␉␉␉␉␉}␊
572␉␉␉␉}␊
573␊
574␉␉␉␉if(fix_fsb)␊
575␉␉␉␉{␊
576␉␉␉␉␉if (bus_ratio_max)␊
577␉␉␉␉␉{␊
578␉␉␉␉␉␉if (maxdiv) fsbi = ((tscFrequency * 2) / ((bus_ratio_max * 2) + 1));␊
579␉␉␉␉␉␉else fsbi = (tscFrequency / bus_ratio_max);␊
580␉␉␉␉␉}␊
581␉␉␉␉␉ratio_gn:␊
582␉␉␉␉␉if ((getValueForKey(kbusratio, &newratio, &len, &bootInfo->bootConfig)) && (len <= 4))␊
583␉␉␉␉␉{␊
584␉␉␉␉␉␉max_ratio = atoi(newratio);␊
585␉␉␉␉␉␉max_ratio = (max_ratio * 10);␊
586␉␉␉␉␉␉if (len >= 3) max_ratio = (max_ratio + 5);␊
587␊
588␉␉␉␉␉␉verbose("Bus-Ratio defaults: min=%d%s, max=%d%s\n", bus_ratio_min, currdiv ? ".5" : "", bus_ratio_max, maxdiv ? ".5" : "");␊
589␉␉␉␉␉␉if ((max_ratio >= min_ratio) && (max_ratio < 200))␊
590␉␉␉␉␉␉{␊
591␉␉␉␉␉␉␉cpuFrequency = (fsbFrequency * max_ratio) / 10;␊
592␉␉␉␉␉␉␉if (len >= 3) maxdiv = 1;␊
593␉␉␉␉␉␉␉else maxdiv = 0;␊
594␉␉␉␉␉␉␉verbose("Sticking with [FSB: %dMhz, Bus-Ratio: %s]\n", myfsb, newratio);␊
595␉␉␉␉␉␉}␊
596␉␉␉␉␉␉else␊
597␉␉␉␉␉␉{␊
598␉␉␉␉␉␉␉printf("Bus-Ratio: Lowest allowed = %d%s. ", bus_ratio_min, currdiv ? ".5" : "");␊
599␉␉␉␉␉␉␉goto ratio_vldt;␊
600␉␉␉␉␉␉}␊
601␉␉␉␉␉}␊
602␉␉␉␉␉else␊
603␉␉␉␉␉{␊
604␉␉␉␉␉␉ratio_vldt:␊
605␉␉␉␉␉␉if (maxdiv)␊
606␉␉␉␉␉␉{␊
607␉␉␉␉␉␉␉cpuFrequency = ((fsbFrequency * ((bus_ratio_max * 2) + 1)) / 2);␊
608␉␉␉␉␉␉␉max_ratio = (bus_ratio_max * 10) + 5;␊
609␉␉␉␉␉␉}␊
610␉␉␉␉␉␉else␊
611␉␉␉␉␉␉{␊
612␉␉␉␉␉␉␉cpuFrequency = (fsbFrequency * bus_ratio_max);␊
613␉␉␉␉␉␉␉max_ratio = bus_ratio_max * 10;␊
614␉␉␉␉␉␉}␊
615␉␉␉␉␉␉verbose("CPU: Sticking with: [FSB: %dMhz, Bus-Ratio: %d%s] %s\n", myfsb, bus_ratio_max, maxdiv ? ".5" : "", newratio ? "instead" : "");␊
616␉␉␉␉␉}␊
617␉␉␉␉}␊
618␉␉␉␉else␊
619␉␉␉␉{␊
620␉␉␉␉␉if (bus_ratio_max)␊
621␉␉␉␉␉{␊
622␉␉␉␉␉␉if (maxdiv)␊
623␉␉␉␉␉␉{␊
624␉␉␉␉␉␉␉fsbFrequency = ((tscFrequency * 2) / ((bus_ratio_max * 2) + 1));␊
625␉␉␉␉␉␉␉max_ratio = ((bus_ratio_max * 10) + 5);␊
626␉␉␉␉␉␉}␊
627␉␉␉␉␉␉else␊
628␉␉␉␉␉␉{␊
629␉␉␉␉␉␉␉fsbFrequency = (tscFrequency / bus_ratio_max);␊
630␉␉␉␉␉␉␉max_ratio = (bus_ratio_max * 10);␊
631␉␉␉␉␉␉}␊
632␊
633␉␉␉␉␉␉myfsb = (fsbFrequency / 1000000);␊
634␉␉␉␉␉␉if (getValueForKey(kbusratio, &newratio, &len, &bootInfo->bootConfig)) goto ratio_gn;␊
635␉␉␉␉␉␉else cpuFrequency = ((fsbFrequency * max_ratio) / 10);␊
636␊
637␉␉␉␉␉␉DBG("max: %d%s current: %d%s\n", bus_ratio_max, maxdiv ? ".5" : "", bus_ratio_min, currdiv ? ".5" : "");␊
638␉␉␉␉␉}␊
639␉␉␉␉}␊
640␉␉␉␉p->CPU.MaxRatio = max_ratio;␊
641␉␉␉␉p->CPU.MinRatio = min_ratio;␊
642␉␉␉}␊
643␉␉}␊
644␊
645␉␉// on-die sensor␊
646␉␉if (p->CPU.CPUID[CPUID_0][0] >= 0x6)␊
647␉␉{␊
648␉␉␉// Highest Basic Functions Number␊
649␉␉␉do_cpuid(6, p->CPU.CPUID[CPUID_81]);␊
650␉␉␉tms = bitfield(p->CPU.CPUID[CPUID_81][0], 0, 0);␊
651␉␉␉ida = bitfield(p->CPU.CPUID[CPUID_81][0], 1, 1);␊
652␉␉␉if(tms != 0)␊
653␉␉␉{␊
654␉␉␉␉int temp, utjmax;␊
655␉␉␉␉if (tjmax == 0) tjmax = 100;␊
656␉␉␉␉if((getIntForKey(kTjmax, &utjmax, &bootInfo->bootConfig)) && ((70 <= utjmax) && (utjmax <= 110))) tjmax = utjmax;␊
657␉␉␉␉msr = rdmsr64(MSR_THERMAL_STATUS);␊
658␉␉␉␉//if ((msr & 0x3) == 0x3)␊
659␉␉␉␉if (((msr >> 31) & 0x1) == 1)␊
660␉␉␉␉{␊
661␉␉␉␉␉temp = tjmax - ((msr >> 16) & 0x7F);␊
662␉␉␉␉␉verbose("CPU: Tjmax ~ %d°C ␉ Temperature= ~ %d°C\n", tjmax, temp);␊
663␉␉␉␉}␊
664␉␉␉␉else temp = -1;␊
665␉␉␉}␊
666␉␉␉if(ida == 0)␊
667␉␉␉{␊
668␉␉␉␉verbose("CPU: Attempting to enable IDA ");␊
669␉␉␉␉msr_t msr;␊
670␉␉␉␉msr = rdmsr(MSR_IA32_MISC_ENABLE);␊
671␉␉␉␉msr.hi |= (0 << (38-32));␊
672␉␉␉␉wrmsr(MSR_IA32_MISC_ENABLE, msr);␊
673␉␉␉␉delay(1);␊
674␉␉␉␉if(bitfield(p->CPU.CPUID[CPUID_81][0], 1, 1) == 0) verbose("Failed!\n");␊
675␉␉␉␉else verbose("Succeded!\n");␊
676␉␉␉}␊
677␉␉␉else verbose("CPU: IDA: Enabled!\n");␊
678␉␉}␊
679␉}␊
680//#if 0␊
681␉// valv: work in progress. Most of this code is going to be moved when ready␊
682␉else if(p->CPU.Vendor == 0x68747541 /* AMD */ && p->CPU.Family == 0x0f)␊
683␉{␊
684␉␉verbose("CPU: ");␊
685␉␉// valv: very experimental mobility check␊
686␉␉if (p->CPU.CPUID[0x80000000][0] >= 0x80000007)␊
687␉␉{␊
688␉␉␉uint32_t amo, const_tsc;␊
689␉␉␉do_cpuid(0x80000007, p->CPU.CPUID[CPUID_MAX]);␊
690␉␉␉amo = bitfield(p->CPU.CPUID[CPUID_MAX][0], 6, 6);␊
691␉␉␉const_tsc = bitfield(p->CPU.CPUID[CPUID_MAX][3], 8, 8);␊
692␉␉␉// valv: p-state support verification␊
693␉␉␉//uint32_t pstate_support = bitfield(p->CPU.CPUID[CPUID_MAX][3], 2, 1);␊
694␉␉␉//if(pstate_support != 0) verbose("supproted p-state transition\n")␊
695␉␉␉␊
696␉␉␉if (const_tsc != 0) verbose("Constant TSC!\n");␊
697␉␉␉if (amo == 1)␊
698␉␉␉{␊
699␉␉␉␉p->CPU.Features |= CPU_FEATURE_MOBILE;␊
700␉␉␉␉if (!strstr(p->CPU.BrandString, "obile")) verbose("Mobile ");␊
701␉␉␉}␊
702␉␉}␊
703␉␉//valv: 2nd attemp; just in case␊
704␉␉if (!platformCPUFeature(CPU_FEATURE_MOBILE))␊
705␉␉{␊
706␉␉␉if (strstr(p->CPU.BrandString, "obile"))␊
707␉␉␉{␊
708␉␉␉␉p->CPU.Features |= CPU_FEATURE_MOBILE;␊
709␉␉␉}␊
710␉␉}␊
711␉␉verbose("%s\n", p->CPU.BrandString);␊
712␊
713␉␉if(p->CPU.ExtFamily == 0x00 /* K8 */)␊
714␉␉{␊
715␉␉␉// valv: this section needs some work␊
716␉␉␉msr = rdmsr64(K8_FIDVID_STATUS);␊
717␉␉␉bus_ratio_max = bitfield(msr, 21, 16);␊
718␉␉␉//bus_ratio_max = (msr & 0x3f) / 2 + 4;␊
719␉␉␉bus_ratio_min = bitfield(msr, 13, 8);␊
720␉␉␉currdiv = (msr & 0x01) * 2;␊
721␉␉␉if (bus_ratio_max)␊
722␉␉␉{␊
723␉␉␉␉if (currdiv)␊
724␉␉␉␉{␊
725␉␉␉␉␉fsbFrequency = ((tscFrequency * currdiv) / bus_ratio_max); // ?␊
726␉␉␉␉␉DBG("%d.%d\n", bus_ratio_max / currdiv, ((bus_ratio_max % currdiv) * 100) / currdiv);␊
727␉␉␉␉}␊
728␉␉␉␉else␊
729␉␉␉␉{␊
730␉␉␉␉␉fsbFrequency = (tscFrequency / bus_ratio_max);␊
731␉␉␉␉␉DBG("%d\n", bus_ratio_max);␊
732␉␉␉␉}␊
733␉␉␉␉//fsbFrequency = (tscFrequency / bus_ratio_max); // ?␊
734␉␉␉␉cpuFrequency = tscFrequency; // ?␊
735␉␉␉}␊
736␉␉}␊
737␊
738␉␉else if(p->CPU.ExtFamily >= 0x01 /* K10+ */)␊
739␉␉{␊
740␉␉␉msr = rdmsr64(K10_COFVID_STATUS);␊
741␉␉␉currdiv = (2 << ((msr >> 6) & 0x07));␊
742␉␉␉msr = rdmsr64(AMD_10H_11H_CONFIG);␊
743␉␉␉bus_ratio_max = ((msr) & 0x3F);␊
744␉␉␉//verbose("max_multi: %d\n", bus_ratio_max);␊
745␊
746␉␉␉/*msr_t divmsr;␊
747␉␉␉divmsr = rdmsr(AMD_10H_11H_CONFIG);␊
748␉␉␉maxdiv = (divmsr.hi >> 0x08) & 0x01;␊
749␉␉␉verbose("maxdiv: %d, currdiv: %d\n", maxdiv, currdiv);*/␊
750␊
751␉␉␉if(p->CPU.ExtFamily == 0x01) ␊
752␉␉␉␉cpuFrequency = 100 * (bus_ratio_max + 0x10);␊
753␉␉␉else ␊
754␉␉␉␉cpuFrequency = 100 * (bus_ratio_max + 0x08);␊
755␉␉␉␊
756␉␉␉uint32_t minFreq = cpuFrequency / (1 << currdiv);␊
757␊
758␉␉␉uint8_t maxrtio = (cpuFrequency / 20);␊
759␉␉␉p->CPU.MaxRatio = maxrtio;␊
760␉␉␉␊
761␉␉␉fsbFrequency = ((tscFrequency / 100000) / maxrtio);␊
762␉␉␉verbose("fsb: %d\n", fsbFrequency);␊
763␉␉␉␊
764␉␉␉if(maxrtio == ((bus_ratio_max * 10) - 5))␊
765␉␉␉{␊
766␉␉␉␉verbose("multi: max:%d.5, ", (bus_ratio_max - 1));␊
767␉␉␉␉maxdiv = 1;␊
768␉␉␉}␊
769␉␉␉else if(maxrtio == ((bus_ratio_max - 1) * 10))␊
770␉␉␉{␊
771␉␉␉␉verbose("multi: max:%d, min:", (bus_ratio_max - 1));␊
772␉␉␉␉maxdiv = 0;␊
773␉␉␉}␊
774␊
775␉␉␉bus_ratio_min = (minFreq / fsbFrequency);␊
776␉␉␉verbose("%d", bus_ratio_min);␊
777␉␉␉while(minFreq < 800)␊
778␉␉␉{␊
779␉␉␉␉bus_ratio_min = bus_ratio_min + 1; // bus_ratio_min++; ???␊
780␉␉␉␉verbose(" >> %d", bus_ratio_min);␊
781␉␉␉}␊
782␉␉␉verbose("\n");␊
783␊
784␉␉␉struct hwpstate ␊
785␉␉␉{␊
786␉␉␉␉uint32_t␉freq;␉␉/* CPU clock in Mhz. */␊
787␉␉␉␉uint32_t␉volts;␉␉/* Voltage in mV. */␊
788␉␉␉␉uint32_t␉power;␉␉/* Power consumed in mW. */␊
789␉␉␉␉uint8_t␉lat;␉␉␉/* Transition latency in us. */␊
790␉␉␉␉uint8_t␉pstate_id;␉␉/* P-State id */␊
791␉␉␉};␊
792␉␉␉␊
793␉␉␉struct hwpstate state[32];␊
794␉␉␉int max_state, i,/* did,*/ vid;␊
795␉␉␉uint8_t fid;␊
796␉␉␉msr = rdmsr64(MSR_AMD_10H_11H_LIMIT);␊
797␉␉␉max_state = 1 + (((msr) >> 4) & 0x7);␊
798␊
799␉␉␉for(i=0; i<max_state; i++)␊
800␉␉␉{␊
801␉␉␉␉msr = rdmsr64(AMD_10H_11H_CONFIG + i);␊
802␉␉␉␉//msr_t didmsr;␊
803␉␉␉␉//didmsr = rdmsr(AMD_10H_11H_CONFIG + i);␊
804␉␉␉␉if ((msr & ((uint64_t)1 << 63)) != ((uint64_t)1 << 63)) verbose("Invalid MSR!\n");␊
805␉␉␉␉else␊
806␉␉␉␉{␊
807␉␉␉␉␉//did = (didmsr.hi >> 0x08) & 0x01;␊
808␉␉␉␉␉if(i == 0) ␊
809␉␉␉␉␉{␊
810␉␉␉␉␉␉//maxdiv = did;␊
811␉␉␉␉␉␉fid = p->CPU.MaxRatio;␊
812␉␉␉␉␉␉state[i].freq = ((fid * fsbFrequency) / 10);␊
813␉␉␉␉␉␉fid = (fid / 10);␊
814␉␉␉␉␉}␊
815␉␉␉␉␉else␊
816␉␉␉␉␉{␊
817␉␉␉␉␉␉fid = bitfield(msr, 5, 0);␊
818␉␉␉␉␉␉state[i].freq = (fid * fsbFrequency);␊
819␉␉␉␉␉}␊
820␉␉␉␉␉␊
821␉␉␉␉␉if(i == (max_state -1))␊
822␉␉␉␉␉{␊
823␉␉␉␉␉␉fid = bus_ratio_min;␊
824␉␉␉␉␉␉state[i].freq = (fid * fsbFrequency);␊
825␉␉␉␉␉}␊
826␉␉␉␉␉␊
827␉␉␉␉␉vid = bitfield(msr, 15, 9);␊
828␉␉␉␉␉␊
829␉␉␉␉␉if(i == 0) verbose("P-State %d: Frequency: %d, Multiplier: %d%s, vid: %d\n", i, state[i].freq, fid, maxdiv ? ".5" : "", vid);␊
830␉␉␉␉␉else if((state[i].freq > state[i+1].freq) || (state[i].freq < 800)) verbose("P-State %d: Removed!", i);␊
831␉␉␉␉␉else verbose("P-State %d: Frequency: %d, Multiplier: %d, vid: %d\n", i, state[i].freq, fid, vid);␊
832␉␉␉␉␉state[i].pstate_id = i;␊
833␉␉␉␉␉// valv: zeroed for now␊
834␉␉␉␉␉state[i].volts = 0;␊
835␉␉␉␉␉state[i].power = 0;␊
836␉␉␉␉␉state[i].lat = 0;␊
837␉␉␉␉}␊
838␉␉␉}␊
839␉␉␉fsbFrequency = (fsbFrequency * 1000000);␊
840␉␉␉cpuFrequency = (state[0].freq * 1000000);␊
841␉␉}␊
842␉␉␊
843␉␉p->CPU.MinRatio = bus_ratio_min * 10;␊
844␉}␊
845␉else if(p->CPU.Vendor == 0x746e6543 /* CENTAUR */ && p->CPU.Family == 6) //valv: partial!␊
846␉{␊
847␉␉msr = rdmsr64(MSR_EBL_CR_POWERON);␊
848␉␉int bus = (msr >> 18) & 0x3;␊
849␉␉switch (bus)␊
850␉␉{␊
851␉␉␉case 1:␊
852␉␉␉␉fsbFrequency = 133333333;␊
853␉␉␉␉break;␊
854␉␉␉case 2:␊
855␉␉␉␉fsbFrequency = 200000000;␊
856␉␉␉␉break;␊
857␉␉␉case 3:␊
858␉␉␉␉fsbFrequency = 166666667;␊
859␉␉␉␉break;␊
860␉␉␉case 0:␊
861␉␉␉default:␉␉␉␉␊
862␉␉␉␉fsbFrequency = 100000000;␊
863␉␉␉␉break;␊
864␉␉}␊
865␉␉msr_t msr;␊
866␉␉msr = rdmsr(MSR_IA32_PERF_STATUS);␊
867␉␉bus_ratio_min = (msr.lo >> 24) & 0x1f;␊
868␉␉min_ratio = bus_ratio_min * 10;␊
869␉␉bus_ratio_max = (msr.hi >> (40-32)) & 0x1f;␊
870␉␉max_ratio = bus_ratio_max * 10;␊
871␉␉cpuFrequency = ((fsbFrequency * max_ratio) / 10);␊
872␉}␊
873␊
874␉if (!fsbFrequency)␊
875␉{␊
876␉␉fsbFrequency = (DEFAULT_FSB * 1000);␊
877␉␉cpuFrequency = tscFrequency;␊
878␉␉DBG("0 ! using the default value for FSB !\n");␊
879␉}␊
880␊
881//#endif␊
882␊
883␉p->CPU.MaxDiv = maxdiv;␊
884␉p->CPU.CurrDiv = currdiv;␊
885␉p->CPU.TSCFrequency = tscFrequency;␊
886␉p->CPU.FSBFrequency = fsbFrequency;␊
887␉p->CPU.CPUFrequency = cpuFrequency;␊
888␉p->CPU.ISerie = false;␊
889␉p->CPU.Turbo = false;␊
890␊
891␉if(!fsbad) p->CPU.FSBIFrequency = fsbFrequency;␊
892␉else p->CPU.FSBIFrequency = fsbi;␊
893␊
894␉if (platformCPUFeature(CPU_FEATURE_EST))␊
895␉{␊
896␉␉msr_t msr32;␊
897␉␉msr32 = rdmsr(MSR_IA32_MISC_ENABLE);␊
898␉␉if (!(rdmsr64(MSR_IA32_MISC_ENABLE) & (1 << 16)))␊
899␉␉{␉//valv: we can also attempt to enable␊
900␉␉␉msr32.lo |= (1 << 16);␊
901␉␉␉// Lock till next reset!␊
902␉␉␉msr32.lo |= (1 << 20);␊
903␉␉␉wrmsr(MSR_IA32_MISC_ENABLE, msr32);␊
904␉␉␉delay(1);␊
905␉␉␉if(rdmsr64(MSR_IA32_MISC_ENABLE) & (1 << 16))␊
906␉␉␉{␊
907␉␉␉␉p->CPU.EST = 1;␊
908␉␉␉␉verbose("CPU: EIST Successfully Enabled!\n");␊
909␉␉␉}␊
910␉␉␉else␊
911␉␉␉{␊
912␉␉␉␉p->CPU.EST = 0;␊
913␉␉␉␉verbose("CPU: EIST couldn't be enabled!\n");␊
914␉␉␉}␊
915␉␉}␊
916␊
917␉␉else p->CPU.EST = 1;␊
918␉}␊
919␉␊
920␉if(core_i) p->CPU.ISerie = true;␊
921␉␉DBG("CPU: Vendor/Family/ExtFamily: 0x%x/0x%x/0x%x\n", p->CPU.Vendor, p->CPU.Family, p->CPU.ExtFamily);␊
922␉␉DBG("CPU: Model/ExtModel/Stepping: 0x%x/0x%x/0x%x\n", p->CPU.Model, p->CPU.ExtModel, p->CPU.Stepping);␊
923␉␉DBG("CPU: Multipliers x10: max=%d, min=%d\n", p->CPU.MaxRatio, p->CPU.MinRatio);␊
924␉if(turbo)␊
925␉{␊
926␉␉DBG("Turbo Ratio: %d/%d/%d/%d\n", p->CPU.Tone, p->CPU.Ttwo, p->CPU.Tthr, p->CPU.Tfor);␊
927␉␉p->CPU.Turbo = true;␊
928␉}␊
929␉␉DBG("CPU: MaxDiv/CurrDiv: 0x%x/0x%x\n", p->CPU.MaxDiv, p->CPU.CurrDiv);␊
930␉␉DBG("CPU: TSCFreq: %dMHz\n", p->CPU.TSCFrequency / 1000000);␊
931␉␉DBG("CPU: CPUFreq: %dMHz\n", p->CPU.CPUFrequency / 1000000);␊
932␉␉DBG("CPU: FSBFreq: %dMHz\n", p->CPU.FSBFrequency / 1000000);␊
933␉if(did)␊
934␉{␊
935␉␉p->CPU.SLFM = did;␊
936␉␉DBG("CPU: SLFM: %d\n", p->CPU.SLFM);␊
937␉}␊
938␉␉if(platformCPUFeature(CPU_FEATURE_EST))␊
939␉␉DBG("CPU: Enhanced SpeedStep: %d\n", p->CPU.EST);␊
940␉␉DBG("CPU: NoCores/NoThreads: %d/%d\n", p->CPU.NoCores, p->CPU.NoThreads);␊
941␉␉DBG("CPU: Features: 0x%08x\n", p->CPU.Features);␊
942}␊
943

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