1 | /*␊ |
2 | * Copyright 2008 Islam Ahmed Zaid. All rights reserved. <azismed@gmail.com>␊ |
3 | * AsereBLN: 2009: cleanup and bugfix␊ |
4 | * valv: 2010: fine-tuning and additions␊ |
5 | */␊ |
6 | ␊ |
7 | #include "libsaio.h"␊ |
8 | #include "platform.h"␊ |
9 | #include "cpu.h"␊ |
10 | #include "boot.h"␊ |
11 | #include "bootstruct.h"␊ |
12 | ␊ |
13 | #ifndef DEBUG_CPU␊ |
14 | #define DEBUG_CPU 0␊ |
15 | #endif␊ |
16 | ␊ |
17 | #if DEBUG_CPU␊ |
18 | #define DBG(x...)␉␉printf(x)␊ |
19 | #else␊ |
20 | #define DBG(x...)␉␉msglog(x)␊ |
21 | #endif␊ |
22 | ␊ |
23 | /*␊ |
24 | * DFE: Measures the TSC frequency in Hz (64-bit) using the ACPI PM timer␊ |
25 | */␊ |
26 | static uint64_t measure_tsc_frequency(void)␊ |
27 | {␊ |
28 | uint64_t tscStart;␊ |
29 | uint64_t tscEnd;␊ |
30 | uint64_t tscDelta = 0xffffffffffffffffULL;␊ |
31 | unsigned long pollCount;␊ |
32 | uint64_t retval = 0;␊ |
33 | int i;␊ |
34 | ␊ |
35 | /* Time how many TSC ticks elapse in 30 msec using the 8254 PIT␊ |
36 | * counter 2. We run this loop 3 times to make sure the cache␊ |
37 | * is hot and we take the minimum delta from all of the runs.␊ |
38 | * That is to say that we're biased towards measuring the minimum␊ |
39 | * number of TSC ticks that occur while waiting for the timer to␊ |
40 | * expire. That theoretically helps avoid inconsistencies when␊ |
41 | * running under a VM if the TSC is not virtualized and the host␊ |
42 | * steals time. The TSC is normally virtualized for VMware.␊ |
43 | */␊ |
44 | for(i = 0; i < 10; ++i)␊ |
45 | {␊ |
46 | enable_PIT2();␊ |
47 | set_PIT2_mode0(CALIBRATE_LATCH);␊ |
48 | tscStart = rdtsc64();␊ |
49 | pollCount = poll_PIT2_gate();␊ |
50 | tscEnd = rdtsc64();␊ |
51 | /* The poll loop must have run at least a few times for accuracy */␊ |
52 | if(pollCount <= 1)␊ |
53 | continue;␊ |
54 | /* The TSC must increment at LEAST once every millisecond. We␊ |
55 | * should have waited exactly 30 msec so the TSC delta should␊ |
56 | * be >= 30. Anything less and the processor is way too slow.␊ |
57 | */␊ |
58 | if((tscEnd - tscStart) <= CALIBRATE_TIME_MSEC)␊ |
59 | continue;␊ |
60 | // tscDelta = min(tscDelta, (tscEnd - tscStart))␊ |
61 | if( (tscEnd - tscStart) < tscDelta )␊ |
62 | tscDelta = tscEnd - tscStart;␊ |
63 | }␊ |
64 | /* tscDelta is now the least number of TSC ticks the processor made in␊ |
65 | * a timespan of 0.03 s (e.g. 30 milliseconds)␊ |
66 | * Linux thus divides by 30 which gives the answer in kiloHertz because␊ |
67 | * 1 / ms = kHz. But we're xnu and most of the rest of the code uses␊ |
68 | * Hz so we need to convert our milliseconds to seconds. Since we're␊ |
69 | * dividing by the milliseconds, we simply multiply by 1000.␊ |
70 | */␊ |
71 | ␊ |
72 | /* Unlike linux, we're not limited to 32-bit, but we do need to take care␊ |
73 | * that we're going to multiply by 1000 first so we do need at least some␊ |
74 | * arithmetic headroom. For now, 32-bit should be enough.␊ |
75 | * Also unlike Linux, our compiler can do 64-bit integer arithmetic.␊ |
76 | */␊ |
77 | if(tscDelta > (1ULL<<32))␊ |
78 | retval = 0;␊ |
79 | else␊ |
80 | {␊ |
81 | retval = tscDelta * 1000 / 30;␊ |
82 | }␊ |
83 | disable_PIT2();␊ |
84 | return retval;␊ |
85 | }␊ |
86 | ␊ |
87 | ␊ |
88 | /*␊ |
89 | * Calculates the FSB and CPU frequencies using specific MSRs for each CPU␊ |
90 | * - multi. is read from a specific MSR. In the case of Intel, there is:␊ |
91 | * a max multi. (used to calculate the FSB freq.),␊ |
92 | * and a current multi. (used to calculate the CPU freq.)␊ |
93 | * - fsbFrequency = tscFrequency / multi␊ |
94 | * - cpuFrequency = fsbFrequency * multi␊ |
95 | */␊ |
96 | ␊ |
97 | void scan_cpu(PlatformInfo_t *p)␊ |
98 | {␊ |
99 | ␉const char␉*newratio, *newfsb;␊ |
100 | ␉int␉␉␉len, myfsb, i;␊ |
101 | ␉uint64_t␉tscFrequency, fsbFrequency, cpuFrequency, fsbi;␊ |
102 | ␉uint64_t␉msr, flex_ratio = 0;␊ |
103 | ␉uint32_t␉tms, ida, max_ratio, min_ratio;␊ |
104 | ␉uint8_t␉␉bus_ratio_max, maxdiv, bus_ratio_min, currdiv;␊ |
105 | ␉bool␉␉fix_fsb, did, core_i, turbo, isatom, fsbad;␊ |
106 | ␊ |
107 | ␉max_ratio = min_ratio = myfsb = bus_ratio_max = maxdiv = bus_ratio_min = currdiv = i = 0;␊ |
108 | ␊ |
109 | ␉/* get cpuid values */␊ |
110 | ␉for( ; i <= 3; i++)␊ |
111 | ␉{␊ |
112 | ␉␉do_cpuid(i, p->CPU.CPUID[i]);␊ |
113 | ␉}␊ |
114 | ␉␊ |
115 | ␉do_cpuid2(0x00000004, 0, p->CPU.CPUID[CPUID_4]);␊ |
116 | ␉do_cpuid(0x80000000, p->CPU.CPUID[CPUID_80]);␊ |
117 | ␉if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 1) {␊ |
118 | ␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊ |
119 | ␉}␊ |
120 | #if DEBUG_CPU␊ |
121 | ␉{␊ |
122 | ␉␉int␉␉i;␊ |
123 | ␉␉printf("CPUID Raw Values:\n");␊ |
124 | ␉␉for (i=0; i<CPUID_MAX; i++) {␊ |
125 | ␉␉␉printf("%02d: %08x-%08x-%08x-%08x\n", i,␊ |
126 | ␉␉␉␉p->CPU.CPUID[i][0], p->CPU.CPUID[i][1],␊ |
127 | ␉␉␉␉p->CPU.CPUID[i][2], p->CPU.CPUID[i][3]);␊ |
128 | ␉␉}␊ |
129 | ␉}␊ |
130 | #endif␊ |
131 | ␉p->CPU.Vendor␉␉= p->CPU.CPUID[CPUID_0][1];␊ |
132 | ␉p->CPU.Signature␉= p->CPU.CPUID[CPUID_1][0];␊ |
133 | ␉p->CPU.Stepping␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 3, 0);␊ |
134 | ␉p->CPU.Model␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 7, 4);␊ |
135 | ␉p->CPU.Type␉␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 13, 12);␊ |
136 | ␉p->CPU.Family␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 11, 8);␊ |
137 | ␉p->CPU.ExtModel␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 19, 16);␊ |
138 | ␉p->CPU.ExtFamily␉= bitfield(p->CPU.CPUID[CPUID_1][0], 27, 20);␊ |
139 | ␉p->CPU.NoThreads␉= bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␊ |
140 | ␉p->CPU.NoCores␉␉= bitfield(p->CPU.CPUID[CPUID_4][0], 31, 26) + 1;␊ |
141 | ␊ |
142 | ␉p->CPU.Model += (p->CPU.ExtModel << 4);␊ |
143 | ␊ |
144 | ␉/* get brand string (if supported) */␊ |
145 | ␉/* Copyright: from Apple's XNU cpuid.c */␊ |
146 | ␉if (p->CPU.CPUID[CPUID_80][0] > 0x80000004) {␊ |
147 | ␉␉uint32_t␉reg[4];␊ |
148 | char str[128], *s;␊ |
149 | ␉␉/*␊ |
150 | ␉␉ * The brand string 48 bytes (max), guaranteed to␊ |
151 | ␉␉ * be NUL terminated.␊ |
152 | ␉␉ */␊ |
153 | ␉␉do_cpuid(0x80000002, reg);␊ |
154 | ␉␉bcopy((char *)reg, &str[0], 16);␊ |
155 | ␉␉do_cpuid(0x80000003, reg);␊ |
156 | ␉␉bcopy((char *)reg, &str[16], 16);␊ |
157 | ␉␉do_cpuid(0x80000004, reg);␊ |
158 | ␉␉bcopy((char *)reg, &str[32], 16);␊ |
159 | ␉␉for (s = str; *s != '\0'; s++) {␊ |
160 | ␉␉␉if (*s != ' ') break;␊ |
161 | ␉␉}␊ |
162 | ␉␉␊ |
163 | ␉␉strlcpy(p->CPU.BrandString,␉s, sizeof(p->CPU.BrandString));␊ |
164 | ␉␉␊ |
165 | ␉␉if (!strncmp(p->CPU.BrandString, CPU_STRING_UNKNOWN, min(sizeof(p->CPU.BrandString), strlen(CPU_STRING_UNKNOWN) + 1))) {␊ |
166 | ␉␉␉ /*␊ |
167 | ␉␉␉ * This string means we have a firmware-programmable brand string,␊ |
168 | ␉␉␉ * and the firmware couldn't figure out what sort of CPU we have.␊ |
169 | ␉␉␉ */␊ |
170 | ␉␉␉ p->CPU.BrandString[0] = '\0';␊ |
171 | ␉␉ }␊ |
172 | ␉}␊ |
173 | ␉␊ |
174 | ␉/* setup features */␊ |
175 | ␉p->CPU.Features |= (CPU_FEATURE_MMX | CPU_FEATURE_SSE | CPU_FEATURE_SSE2 | CPU_FEATURE_MSR | CPU_FEATURE_APIC | CPU_FEATURE_TM1 | CPU_FEATURE_ACPI) & p->CPU.CPUID[CPUID_1][3];␊ |
176 | ␉p->CPU.Features |= (CPU_FEATURE_SSE3 | CPU_FEATURE_SSE41 | CPU_FEATURE_SSE42 | CPU_FEATURE_EST | CPU_FEATURE_TM2 | CPU_FEATURE_SSSE3 | CPU_FEATURE_xAPIC) & p->CPU.CPUID[CPUID_1][2];␊ |
177 | ␉p->CPU.Features |= (CPU_FEATURE_EM64T | CPU_FEATURE_XD) & p->CPU.CPUID[CPUID_81][3];␊ |
178 | ␉p->CPU.Features |= (CPU_FEATURE_LAHF) & p->CPU.CPUID[CPUID_81][2];␊ |
179 | ␊ |
180 | ␊ |
181 | ␉//if ((CPU_FEATURE_HTT & p->CPU.CPUID[CPUID_1][3]) != 0) {␊ |
182 | ␉if (p->CPU.NoThreads > p->CPU.NoCores) {␊ |
183 | ␉␉p->CPU.Features |= CPU_FEATURE_HTT;␊ |
184 | ␉}␊ |
185 | ␉ ␊ |
186 | ␊ |
187 | ␉tscFrequency = measure_tsc_frequency();␊ |
188 | ␉fsbFrequency = 0;␊ |
189 | ␉cpuFrequency = 0;␊ |
190 | ␉fsbi = 0;␊ |
191 | ␉fix_fsb = false;␊ |
192 | ␉did = false;␊ |
193 | ␉core_i = false;␊ |
194 | ␉turbo = false;␊ |
195 | ␉isatom = false;␊ |
196 | ␉fsbad = false;␊ |
197 | ␊ |
198 | ␉if ((p->CPU.Vendor == 0x756E6547 /* Intel */) && ((p->CPU.Family == 0x06) || (p->CPU.Family == 0x0f)))␊ |
199 | ␉{␊ |
200 | ␉␉verbose("CPU: ");␊ |
201 | ␉␉int tjmax = 0;␊ |
202 | ␉␉msr = rdmsr64(MSR_IA32_PLATFORM_ID);␊ |
203 | ␉␉if((((msr >> 50) & 0x01) == 1) || (rdmsr64(0x17) & (1<<28)))␊ |
204 | ␉␉{␊ |
205 | ␉␉␉p->CPU.Features |= CPU_FEATURE_MOBILE;␊ |
206 | ␉␉␉verbose("Mobile ");␊ |
207 | ␉␉}␊ |
208 | ␉␉verbose("%s\n", p->CPU.BrandString);␊ |
209 | ␉␉␊ |
210 | ␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) || (p->CPU.Family == 0x0f && p->CPU.Model >= 0x03))␊ |
211 | ␉␉{␊ |
212 | ␉␉␉if (p->CPU.Family == 0x06)␊ |
213 | ␉␉␉{␊ |
214 | ␉␉␉␉int intelCPU = p->CPU.Model;␊ |
215 | ␉␉␉␉int Stepp = p->CPU.Stepping;␊ |
216 | ␉␉␉␉int bus;␊ |
217 | ␊ |
218 | ␉␉␉␉switch (intelCPU)␊ |
219 | ␉␉␉␉{␊ |
220 | ␉␉␉␉␉case 0xc:␉␉// Core i7 & Atom␊ |
221 | ␉␉␉␉␉␉if (strstr(p->CPU.BrandString, "Atom")) goto teleport1;␊ |
222 | ␉␉␉␉␉case 0x1a:␉␉// Core i7 LGA1366, Xeon 5500, "Bloomfield", "Gainstown", 45nm␊ |
223 | ␉␉␉␉␉case 0x1e:␉␉// Core i7, i5 LGA1156, "Clarksfield", "Lynnfield", "Jasper", 45nm␊ |
224 | ␉␉␉␉␉case 0x1f:␉␉// Core i7, i5, Nehalem␊ |
225 | ␉␉␉␉␉case 0x25:␉␉// Core i7, i5, i3 LGA1156, "Westmere", "Clarkdale", "Arrandale", 32nm␊ |
226 | ␉␉␉␉␉case 0x2a:␉␉// Sandy Bridge, 32nm␊ |
227 | ␉␉␉␉␉case 0x2c:␉␉// Core i7 LGA1366, Six-core, "Westmere", "Gulftown", 32nm␊ |
228 | ␉␉␉␉␉case 0x2e:␉␉// Core i7, Nehalem-Ex Xeon, "Beckton"␊ |
229 | ␉␉␉␉␉case 0x2f:␉␉// Core i7, Nehalem-Ex Xeon, "Eagleton"␊ |
230 | ␉␉␉␉␉␉core_i = true;␊ |
231 | ␉␉␉␉␉␉tjmax = (rdmsr64(MSR_THERMAL_TARGET) >> 16) & 0xff;␊ |
232 | ␉␉␉␉␉␉msr = rdmsr64(MSR_PLATFORM_INFO);␊ |
233 | ␉␉␉␉␉␉bus_ratio_max = (msr >> 8) & 0xff;␊ |
234 | ␉␉␉␉␉␉bus_ratio_min = (msr >> 40) & 0xff; //valv: not sure about this one (Remarq.1)␊ |
235 | ␉␉␉␉␉␉verbose("CPU: Flex-Ratio = %d ", bus_ratio_max);␊ |
236 | ␉␉␉␉␉␉min_ratio = bus_ratio_min * 10;␊ |
237 | ␉␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊ |
238 | ␉␉␉␉␉␉if ((msr >> 16) & 0x01)␊ |
239 | ␉␉␉␉␉␉{␊ |
240 | ␉␉␉␉␉␉␉flex_ratio = (msr >> 8) & 0xff;␊ |
241 | ␉␉␉␉␉␉␉verbose(">> %d", flex_ratio);␊ |
242 | ␉␉␉␉␉␉␉if(bus_ratio_max > flex_ratio) bus_ratio_max = flex_ratio;␊ |
243 | ␉␉␉␉␉␉}␊ |
244 | ␉␉␉␉␉␉verbose("\n");␊ |
245 | ␉␉␉␉␉␉if(bus_ratio_max) fsbFrequency = (tscFrequency / bus_ratio_max);␊ |
246 | ␊ |
247 | ␉␉␉␉␉␉//valv: Turbo Ratio Limit␊ |
248 | ␉␉␉␉␉␉if ((intelCPU != 0x2e) && (intelCPU != 0x2f))␊ |
249 | ␉␉␉␉␉␉{␊ |
250 | ␉␉␉␉␉␉␉turbo = true;␊ |
251 | ␉␉␉␉␉␉␉msr = rdmsr64(MSR_TURBO_RATIO_LIMIT);␊ |
252 | ␉␉␉␉␉␉␉␊ |
253 | ␉␉␉␉␉␉␉p->CPU.Tone = (msr >> 0) & 0xff;␊ |
254 | ␉␉␉␉␉␉␉p->CPU.Ttwo = (msr >> 8) & 0xff;␊ |
255 | ␉␉␉␉␉␉␉p->CPU.Tthr = (msr >> 16) & 0xff;␊ |
256 | ␉␉␉␉␉␉␉p->CPU.Tfor = (msr >> 24) & 0xff;␊ |
257 | ␊ |
258 | ␉␉␉␉␉␉␉cpuFrequency = bus_ratio_max * fsbFrequency;␊ |
259 | ␉␉␉␉␉␉␉max_ratio = bus_ratio_max * 10;␊ |
260 | ␉␉␉␉␉␉}␊ |
261 | ␉␉␉␉␉␉else cpuFrequency = tscFrequency;␊ |
262 | ␊ |
263 | ␉␉␉␉␉␉if ((getValueForKey(kbusratio, &newratio, &len, &bootInfo->bootConfig)) && (len <= 4))␊ |
264 | ␉␉␉␉␉␉{␊ |
265 | ␉␉␉␉␉␉␉max_ratio = atoi(newratio);␊ |
266 | ␉␉␉␉␉␉␉max_ratio = (max_ratio * 10);␊ |
267 | ␉␉␉␉␉␉␉if (len >= 3) max_ratio = (max_ratio + 5);␊ |
268 | ␊ |
269 | ␉␉␉␉␉␉␉verbose("Bus-Ratio: min=%d, max=%s\n", bus_ratio_min, newratio);␊ |
270 | ␊ |
271 | ␉␉␉␉␉␉␉// extreme overclockers may love 320 ;)␊ |
272 | ␉␉␉␉␉␉␉if ((max_ratio >= min_ratio) && (max_ratio <= 320))␊ |
273 | ␉␉␉␉␉␉␉{␊ |
274 | ␉␉␉␉␉␉␉␉cpuFrequency = (fsbFrequency * max_ratio) / 10;␊ |
275 | ␉␉␉␉␉␉␉␉if (len >= 3) maxdiv = 1;␊ |
276 | ␉␉␉␉␉␉␉␉else maxdiv = 0;␊ |
277 | ␉␉␉␉␉␉␉}␊ |
278 | ␉␉␉␉␉␉␉else max_ratio = (bus_ratio_max * 10);␊ |
279 | ␉␉␉␉␉␉}␊ |
280 | ␉␉␉␉␉␉//valv: to be uncommented if Remarq.1 didn't stick␊ |
281 | ␉␉␉␉␉␉/*if(bus_ratio_max > 0) bus_ratio = flex_ratio;*/␊ |
282 | ␉␉␉␉␉␉p->CPU.MaxRatio = max_ratio;␊ |
283 | ␉␉␉␉␉␉p->CPU.MinRatio = min_ratio;␊ |
284 | ␉␉␉␉␉␉␊ |
285 | ␉␉␉␉␉␉//fsbi = fsbFrequency;␊ |
286 | ␉␉␉␉␉␉if(getIntForKey(kForceFSB, &myfsb, &bootInfo->bootConfig)) goto forcefsb;␊ |
287 | ␉␉␉␉␉␉else myfsb = fsbFrequency / 1000000;␊ |
288 | ␉␉␉␉␉␉verbose("Sticking with [BCLK: %dMhz, Bus-Ratio: %s]\n", myfsb, newratio);␊ |
289 | ␉␉␉␉␉␉break;␊ |
290 | ␉␉␉␉␉case 0xd:␉␉// Pentium M, Dothan, 90nm␊ |
291 | ␉␉␉␉␉case 0xe:␉␉// Core Duo/Solo, Pentium M DC␊ |
292 | ␉␉␉␉␉␉␉teleport1:␊ |
293 | ␉␉␉␉␉␉␉msr = rdmsr64(MSR_IA32_EXT_CONFIG);␊ |
294 | ␉␉␉␉␉␉␉if(msr & (1 << 30)) tjmax = 85;␊ |
295 | ␉␉␉␉␉␉␉goto teleport2;␊ |
296 | ␉␉␉␉␉case 0xf:␉␉// Core Xeon, Core 2 DC, 65nm␊ |
297 | ␉␉␉␉␉␉switch (Stepp)␊ |
298 | ␉␉␉␉␉␉{␊ |
299 | ␉␉␉␉␉␉␉case 0x2:␊ |
300 | ␉␉␉␉␉␉␉␉tjmax = 95;␊ |
301 | ␉␉␉␉␉␉␉␉break;␊ |
302 | ␉␉␉␉␉␉␉case 0x6:␊ |
303 | ␉␉␉␉␉␉␉␉if (p->CPU.NoCores = 2) tjmax = 80;␊ |
304 | ␉␉␉␉␉␉␉␉if (p->CPU.NoCores = 4) tjmax = 90;␊ |
305 | ␉␉␉␉␉␉␉␉else tjmax = 85;␊ |
306 | ␉␉␉␉␉␉␉␉break;␊ |
307 | ␉␉␉␉␉␉␉case 0xb:␊ |
308 | ␉␉␉␉␉␉␉␉tjmax = 90;␊ |
309 | ␉␉␉␉␉␉␉␉break;␊ |
310 | ␉␉␉␉␉␉␉case 0xd:␊ |
311 | ␉␉␉␉␉␉␉default:␊ |
312 | ␉␉␉␉␉␉␉␉msr = rdmsr64(MSR_IA32_EXT_CONFIG);␊ |
313 | ␉␉␉␉␉␉␉␉if(msr & (1 << 30)) tjmax = 85;␊ |
314 | ␉␉␉␉␉␉␉␉break;␊ |
315 | ␉␉␉␉␉␉}␊ |
316 | ␉␉␉␉␉case 0x1c:␉␉// Atom :)␊ |
317 | ␉␉␉␉␉␉switch (Stepp)␊ |
318 | ␉␉␉␉␉␉{␊ |
319 | ␉␉␉␉␉␉␉case 0xa:␊ |
320 | ␉␉␉␉␉␉␉␉tjmax = 100;␊ |
321 | ␉␉␉␉␉␉␉␉break;␊ |
322 | ␉␉␉␉␉␉␉case 0x2:␊ |
323 | ␉␉␉␉␉␉␉default:␊ |
324 | ␉␉␉␉␉␉␉␉tjmax = 90;␊ |
325 | ␉␉␉␉␉␉␉␉break;␊ |
326 | ␉␉␉␉␉␉}␊ |
327 | ␉␉␉␉␉case 0x17:␉␉// Core 2 Duo/Extreme, Xeon, 45nm␊ |
328 | ␉␉␉␉␉␉switch (Stepp)␊ |
329 | ␉␉␉␉␉␉{␊ |
330 | ␉␉␉␉␉␉␉case 0x6:␉␉// Mobile Core2 Duo␊ |
331 | ␉␉␉␉␉␉␉␉tjmax = 104;␊ |
332 | ␉␉␉␉␉␉␉␉break;␊ |
333 | ␉␉␉␉␉␉␉case 0xa:␉␉// Mobile Centrino 2␊ |
334 | ␉␉␉␉␉␉␉␉tjmax = 105;␊ |
335 | ␉␉␉␉␉␉␉␉break;␊ |
336 | ␉␉␉␉␉␉␉default:␊ |
337 | ␉␉␉␉␉␉␉␉if (platformCPUFeature(CPU_FEATURE_MOBILE)) tjmax = 105;␊ |
338 | ␉␉␉␉␉␉␉␉break;␊ |
339 | ␉␉␉␉␉␉}␊ |
340 | ␉␉␉␉␉case 0x16:␉␉// Celeron, Core 2 SC, 65nm␊ |
341 | ␉␉␉␉␉case 0x27:␉␉// Atom Lincroft, 45nm␊ |
342 | ␉␉␉␉␉␉teleport2:␊ |
343 | ␉␉␉␉␉␉core_i = false;␊ |
344 | ␉␉␉␉␉␉//valv: todo: msr_therm2_ctl (0x19d) bit 16 (mode of automatic thermal monitor): 0=tm1, 1=tm2␊ |
345 | ␉␉␉␉␉␉//also, if bit 3 of misc_enable is cleared the above would have no effect␊ |
346 | ␉␉␉␉␉␉if (strstr(p->CPU.BrandString, "Atom"))␊ |
347 | ␉␉␉␉␉␉␉isatom = true;␊ |
348 | ␉␉␉␉␉␉if(!isatom && (platformCPUFeature(CPU_FEATURE_TM1)))␊ |
349 | ␉␉␉␉␉␉{␊ |
350 | ␉␉␉␉␉␉␉msr_t msr32;␊ |
351 | ␉␉␉␉␉␉␉msr32 = rdmsr(MSR_IA32_MISC_ENABLE);␊ |
352 | ␉␉␉␉␉␉␉bool tmfix = false;␊ |
353 | ␉␉␉␉␉␉␉getBoolForKey(kFixTM, &tmfix, &bootInfo->bootConfig);␊ |
354 | ␉␉␉␉␉␉␉if(tmfix)␊ |
355 | ␉␉␉␉␉␉␉{␉␊ |
356 | ␉␉␉␉␉␉␉␉//thermally-initiated on-die modulation of the stop-clock duty cycle␊ |
357 | ␉␉␉␉␉␉␉␉if(!(rdmsr64(MSR_IA32_MISC_ENABLE) & (1 << 3))) msr32.lo |= (1 << 3);␊ |
358 | ␉␉␉␉␉␉␉␉verbose("CPU: Thermal Monitor: TM, ");␊ |
359 | ␉␉␉␉␉␉␉␉␊ |
360 | ␉␉␉␉␉␉␉␉//BIOS must enable this feature if the TM2 feature flag (CPUID.1:ECX[8]) is set␊ |
361 | ␉␉␉␉␉␉␉␉if(platformCPUFeature(CPU_FEATURE_TM2))␊ |
362 | ␉␉␉␉␉␉␉␉{␊ |
363 | ␉␉␉␉␉␉␉␉␉//thermally-initiated frequency transitions␊ |
364 | ␉␉␉␉␉␉␉␉␉msr32.lo |= (1 << 13);␊ |
365 | ␉␉␉␉␉␉␉␉␉verbose("TM2, ");␊ |
366 | ␉␉␉␉␉␉␉␉}␊ |
367 | ␉␉␉␉␉␉␉␉msr32.lo |= (1 << 17);␊ |
368 | ␉␉␉␉␉␉␉␉verbose("PROCHOT, ");␊ |
369 | ␉␉␉␉␉␉␉␉msr32.lo |= (1 << 10);␊ |
370 | ␉␉␉␉␉␉␉␉verbose("FERR\n");␊ |
371 | ␉␉␉␉␉␉␉}␊ |
372 | ␉␉␉␉␉␉␉bool oem_ssdt, tmpval;␊ |
373 | ␉␉␉␉␉␉␉oem_ssdt = false;␊ |
374 | ␉␉␉␉␉␉␉␊ |
375 | ␉␉␉␉␉␉␉oem_ssdt = getBoolForKey(kOEMSSDT, &tmpval, &bootInfo->bootConfig)&&tmpval;␊ |
376 | ␉␉␉␉␉␉␉if(oem_ssdt)␊ |
377 | ␉␉␉␉␉␉␉{␊ |
378 | ␉␉␉␉␉␉␉␉bool c2e, c4e, hc4e;␊ |
379 | ␉␉␉␉␉␉␉␉c2e = c4e = hc4e = false;␊ |
380 | ␊ |
381 | ␉␉␉␉␉␉␉␉getBoolForKey(kC2EEnable, &c2e, &bootInfo->bootConfig);␊ |
382 | ␉␉␉␉␉␉␉␉if(c2e) msr32.lo |= (1 << 26);␊ |
383 | ␉␉␉␉␉␉␉␉␊ |
384 | ␉␉␉␉␉␉␉␉getBoolForKey(kC4EEnable, &c4e, &bootInfo->bootConfig);␊ |
385 | ␉␉␉␉␉␉␉␉if((c4e) && platformCPUFeature(CPU_FEATURE_MOBILE)) msr32.hi |= (1 << (32 - 32));␊ |
386 | ␉␉␉␉␉␉␉␉getBoolForKey(kHardC4EEnable, &hc4e, &bootInfo->bootConfig);␊ |
387 | ␉␉␉␉␉␉␉␉if((hc4e) && platformCPUFeature(CPU_FEATURE_MOBILE)) msr32.hi |= (1 << (33 - 32));␊ |
388 | ␉␉␉␉␉␉␉␉if(c2e || c4e || hc4e) tmfix = true;␊ |
389 | ␉␉␉␉␉␉␉}␊ |
390 | ␉␉␉␉␉␉␉␊ |
391 | ␉␉␉␉␉␉␉if(tmfix)␊ |
392 | ␉␉␉␉␉␉␉{␊ |
393 | ␉␉␉␉␉␉␉␉msr32.hi |= (1 << (36 - 32)); // EMTTM␊ |
394 | ␉␉␉␉␉␉␉␉wrmsr(MSR_IA32_MISC_ENABLE, msr32);␊ |
395 | ␉␉␉␉␉␉␉}␊ |
396 | ␉␉␉␉␉␉␉if(tmfix)␊ |
397 | ␉␉␉␉␉␉␉{␊ |
398 | ␉␉␉␉␉␉␉␉msr32 = rdmsr(PIC_SENS_CFG);␊ |
399 | ␉␉␉␉␉␉␉␉msr32.lo |= (1 << 21);␊ |
400 | ␉␉␉␉␉␉␉␉wrmsr(PIC_SENS_CFG, msr32);␊ |
401 | ␉␉␉␉␉␉␉}␊ |
402 | ␉␉␉␉␉␉}␊ |
403 | ␉␉␉␉␉␉␊ |
404 | ␉␉␉␉␉␉if (rdmsr64(MSR_IA32_EXT_CONFIG) & (1 << 27))␊ |
405 | ␉␉␉␉␉␉{␊ |
406 | ␉␉␉␉␉␉␉wrmsr64(MSR_IA32_EXT_CONFIG, (rdmsr64(MSR_IA32_EXT_CONFIG) | (1 << 28)));␊ |
407 | ␉␉␉␉␉␉␉delay(1);␊ |
408 | ␉␉␉␉␉␉␉did = rdmsr64(MSR_IA32_EXT_CONFIG) & (1 << 28);␊ |
409 | ␉␉␉␉␉␉}␊ |
410 | ␉␉␉␉␉␉getBoolForKey(kFixFSB, &fix_fsb, &bootInfo->bootConfig);␊ |
411 | ␉␉␉␉␉␉if(fix_fsb)␊ |
412 | ␉␉␉␉␉␉{␊ |
413 | ␉␉␉␉␉␉␉msr = rdmsr64(MSR_FSB_FREQ);␊ |
414 | ␉␉␉␉␉␉␉bus = (msr >> 0) & 0x7;␊ |
415 | ␉␉␉␉␉␉␉if(p->CPU.Model == 0xd && bus == 0)␊ |
416 | ␉␉␉␉␉␉␉{␊ |
417 | ␉␉␉␉␉␉␉␉fsbFrequency = 100000000;␊ |
418 | ␉␉␉␉␉␉␉␉myfsb = 100;␊ |
419 | ␉␉␉␉␉␉␉}␊ |
420 | ␉␉␉␉␉␉␉else if(p->CPU.Model == 0xe && p->CPU.ExtModel == 1) goto ratio;␊ |
421 | ␉␉␉␉␉␉␉else␊ |
422 | ␉␉␉␉␉␉␉{␊ |
423 | ␉␉␉␉␉␉␉␉switch (bus)␊ |
424 | ␉␉␉␉␉␉␉␉{␊ |
425 | ␉␉␉␉␉␉␉␉␉case 0:␊ |
426 | ␉␉␉␉␉␉␉␉␉␉fsbFrequency = 266666667;␊ |
427 | ␉␉␉␉␉␉␉␉␉␉myfsb = 266;␊ |
428 | ␉␉␉␉␉␉␉␉␉␉break;␊ |
429 | ␉␉␉␉␉␉␉␉␉case 1:␊ |
430 | ␉␉␉␉␉␉␉␉␉␉fsbFrequency = 133333333;␊ |
431 | ␉␉␉␉␉␉␉␉␉␉myfsb = 133;␊ |
432 | ␉␉␉␉␉␉␉␉␉␉break;␊ |
433 | ␉␉␉␉␉␉␉␉␉case 3:␊ |
434 | ␉␉␉␉␉␉␉␉␉␉fsbFrequency = 166666667;␊ |
435 | ␉␉␉␉␉␉␉␉␉␉myfsb = 166;␊ |
436 | ␉␉␉␉␉␉␉␉␉␉break;␊ |
437 | ␉␉␉␉␉␉␉␉␉case 4:␊ |
438 | ␉␉␉␉␉␉␉␉␉␉fsbFrequency = 333333333;␊ |
439 | ␉␉␉␉␉␉␉␉␉␉myfsb = 333;␊ |
440 | ␉␉␉␉␉␉␉␉␉␉break;␊ |
441 | ␉␉␉␉␉␉␉␉␉case 5:␊ |
442 | ␉␉␉␉␉␉␉␉␉␉fsbFrequency = 100000000;␊ |
443 | ␉␉␉␉␉␉␉␉␉␉myfsb = 100;␊ |
444 | ␉␉␉␉␉␉␉␉␉␉break;␊ |
445 | ␉␉␉␉␉␉␉␉␉case 6:␊ |
446 | ␉␉␉␉␉␉␉␉␉␉fsbFrequency = 400000000;␊ |
447 | ␉␉␉␉␉␉␉␉␉␉myfsb = 400;␊ |
448 | ␉␉␉␉␉␉␉␉␉␉break;␊ |
449 | ␉␉␉␉␉␉␉␉␉case 2:␊ |
450 | ␉␉␉␉␉␉␉␉␉default:␊ |
451 | ␉␉␉␉␉␉␉␉␉␉fsbFrequency = 200000000;␊ |
452 | ␉␉␉␉␉␉␉␉␉␉myfsb = 200;␊ |
453 | ␉␉␉␉␉␉␉␉␉␉break;␊ |
454 | ␉␉␉␉␉␉␉␉}␊ |
455 | ␉␉␉␉␉␉␉}␊ |
456 | ␉␉␉␉␉␉␉uint64_t minfsb = 182000000, maxfsb = 185000000;␊ |
457 | ␉␉␉␉␉␉␉if(((fsbFrequency > minfsb) && (fsbFrequency < maxfsb)) || !fsbFrequency)␊ |
458 | ␉␉␉␉␉␉␉{␊ |
459 | ␉␉␉␉␉␉␉␉fsbFrequency = 200000000;␊ |
460 | ␉␉␉␉␉␉␉␉fsbad = true;␊ |
461 | ␉␉␉␉␉␉␉}␊ |
462 | ␉␉␉␉␉␉␉goto ratio;␊ |
463 | ␉␉␉␉␉␉}␊ |
464 | ␉␉␉␉␉case 0x1d:␉␉// Xeon MP MP 7400␊ |
465 | ␉␉␉␉␉// for 0x2a & 0x2b turbo is true;␊ |
466 | ␉␉␉␉␉//case 0x2a:␉␉// SNB␊ |
467 | ␉␉␉␉␉//case 0x2b:␉␉// SNB Xeon␊ |
468 | ␉␉␉␉␉default:␊ |
469 | ␉␉␉␉␉␉if(getIntForKey(kForceFSB, &myfsb, &bootInfo->bootConfig))␊ |
470 | ␉␉␉␉␉␉{␊ |
471 | ␉␉␉␉␉␉␉forcefsb:␊ |
472 | ␉␉␉␉␉␉␉switch(myfsb)␊ |
473 | ␉␉␉␉␉␉␉{␊ |
474 | ␉␉␉␉␉␉␉␉case 133:␊ |
475 | ␉␉␉␉␉␉␉␉␉fsbFrequency = 133333333;␊ |
476 | ␉␉␉␉␉␉␉␉␉break;␊ |
477 | ␉␉␉␉␉␉␉␉case 166:␊ |
478 | ␉␉␉␉␉␉␉␉␉fsbFrequency = 166666667;␊ |
479 | ␉␉␉␉␉␉␉␉␉break;␊ |
480 | ␉␉␉␉␉␉␉␉case 233:␊ |
481 | ␉␉␉␉␉␉␉␉␉fsbFrequency = 233333333;␊ |
482 | ␉␉␉␉␉␉␉␉␉break;␊ |
483 | ␉␉␉␉␉␉␉␉case 266:␊ |
484 | ␉␉␉␉␉␉␉␉␉fsbFrequency = 266666667;␊ |
485 | ␉␉␉␉␉␉␉␉␉break;␊ |
486 | ␉␉␉␉␉␉␉␉case 333:␊ |
487 | ␉␉␉␉␉␉␉␉␉fsbFrequency = 333333333;␊ |
488 | ␉␉␉␉␉␉␉␉␉break;␊ |
489 | ␉␉␉␉␉␉␉␉case 100:␊ |
490 | ␉␉␉␉␉␉␉␉case 200:␊ |
491 | ␉␉␉␉␉␉␉␉case 400:␊ |
492 | ␉␉␉␉␉␉␉␉␉fsbFrequency = (myfsb * 1000000);␊ |
493 | ␉␉␉␉␉␉␉␉␉break;␊ |
494 | ␉␉␉␉␉␉␉␉default:␊ |
495 | ␉␉␉␉␉␉␉␉␉getValueForKey(kForceFSB, &newfsb, &len, &bootInfo->bootConfig);␊ |
496 | ␉␉␉␉␉␉␉␉␉if((len <= 3) && (myfsb < 400))␊ |
497 | ␉␉␉␉␉␉␉␉␉{␊ |
498 | ␉␉␉␉␉␉␉␉␉␉fsbFrequency = (myfsb * 1000000);␊ |
499 | ␉␉␉␉␉␉␉␉␉␉verbose("Specified FSB: %dMhz. Assuming you know what you 're doing !\n", myfsb);␊ |
500 | ␉␉␉␉␉␉␉␉␉}␊ |
501 | ␉␉␉␉␉␉␉␉␉else if(core_i) fsbFrequency = 133333333;␊ |
502 | ␉␉␉␉␉␉␉␉␉else fsbFrequency = 200000000;␊ |
503 | ␉␉␉␉␉␉␉␉␉break;␊ |
504 | ␉␉␉␉␉␉␉}␊ |
505 | ␉␉␉␉␉␉␉if(core_i)␊ |
506 | ␉␉␉␉␉␉␉{␊ |
507 | ␉␉␉␉␉␉␉␉cpuFrequency = (fsbFrequency * max_ratio) / 10;␊ |
508 | ␉␉␉␉␉␉␉␉verbose("Sticking with [BCLK: %dMhz, Bus-Ratio: %s]\n", myfsb, newratio);␊ |
509 | ␉␉␉␉␉␉␉␉break;␊ |
510 | ␉␉␉␉␉␉␉}␊ |
511 | ␉␉␉␉␉␉␉fix_fsb = true;␊ |
512 | ␉␉␉␉␉␉}␊ |
513 | ␉␉␉␉␉␉goto ratio;␊ |
514 | ␉␉␉␉␉␉break;␊ |
515 | ␉␉␉␉}␊ |
516 | ␉␉␉}␊ |
517 | ␉␉␉else␊ |
518 | ␉␉␉{␊ |
519 | ␉␉␉␉ratio:␊ |
520 | ␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_STATUS);␊ |
521 | ␉␉␉␉maxdiv = (msr >> 46) & 0x01;␊ |
522 | ␉␉␉␉//valv: this seems to be bit 15 instead of 14.␊ |
523 | ␉␉␉␉currdiv = (msr >> 15) & 0x01;␊ |
524 | ␉␉␉␉uint8_t XE = (msr >> 31) & 0x01;␊ |
525 | ␊ |
526 | ␉␉␉␉msr_t msr32;␊ |
527 | ␉␉␉␉msr32 = rdmsr(MSR_IA32_PERF_STATUS);␊ |
528 | ␉␉␉␉bus_ratio_min = (msr32.lo >> 24) & 0x1f;␊ |
529 | ␉␉␉␉min_ratio = bus_ratio_min * 10;␊ |
530 | ␉␉␉␉if(currdiv) min_ratio = min_ratio + 5;␊ |
531 | ␉␉␉␉␊ |
532 | ␉␉␉␉if(XE || (p->CPU.Family == 0x0f)) bus_ratio_max = (msr32.hi >> (40-32)) & 0x1f;␊ |
533 | ␉␉␉␉else bus_ratio_max = ((rdmsr64(MSR_IA32_PLATFORM_ID) >> 8) & 0x1f);␊ |
534 | ␉␉␉␉/* On lower models, currcoef defines TSC freq */␊ |
535 | ␉␉␉␉if (((p->CPU.Family == 0x06) && (p->CPU.Model < 0x0e)) && (p->CPU.Family != 0x0f)) bus_ratio_max = bus_ratio_min;␊ |
536 | ␉␉␉␉// bad hack! Could force a value relying on kpstates, but I fail to see its benefits.␊ |
537 | ␉␉␉␉if(bus_ratio_min == 0) bus_ratio_min = bus_ratio_max;␊ |
538 | ␉␉␉␉␊ |
539 | ␉␉␉␉if(p->CPU.Family == 0x0f)␊ |
540 | ␉␉␉␉{␊ |
541 | ␉␉␉␉␉getBoolForKey(kFixFSB, &fix_fsb, &bootInfo->bootConfig);␊ |
542 | ␉␉␉␉␉if(fix_fsb)␊ |
543 | ␉␉␉␉␉{␊ |
544 | ␉␉␉␉␉␉msr = rdmsr64(MSR_EBC_FREQUENCY_ID);␊ |
545 | ␉␉␉␉␉␉int bus = (msr >> 16) & 0x7;␊ |
546 | ␉␉␉␉␉␉switch (bus)␊ |
547 | ␉␉␉␉␉␉{␊ |
548 | ␉␉␉␉␉␉␉case 0:␊ |
549 | ␉␉␉␉␉␉␉␉fsbFrequency = 266666667;␊ |
550 | ␉␉␉␉␉␉␉␉myfsb = 266;␊ |
551 | ␉␉␉␉␉␉␉␉break;␊ |
552 | ␉␉␉␉␉␉␉case 1:␊ |
553 | ␉␉␉␉␉␉␉␉fsbFrequency = 133333333;␊ |
554 | ␉␉␉␉␉␉␉␉myfsb = 133;␊ |
555 | ␉␉␉␉␉␉␉␉break;␊ |
556 | ␉␉␉␉␉␉␉case 3:␊ |
557 | ␉␉␉␉␉␉␉␉fsbFrequency = 166666667;␊ |
558 | ␉␉␉␉␉␉␉␉myfsb = 166;␊ |
559 | ␉␉␉␉␉␉␉␉break;␊ |
560 | ␉␉␉␉␉␉␉case 2:␊ |
561 | ␉␉␉␉␉␉␉default:␊ |
562 | ␉␉␉␉␉␉␉␉fsbFrequency = 200000000;␊ |
563 | ␉␉␉␉␉␉␉␉myfsb = 200;␊ |
564 | ␉␉␉␉␉␉␉␉break;␊ |
565 | ␉␉␉␉␉␉}␊ |
566 | ␉␉␉␉␉␉uint64_t minfsb = 183000000, maxfsb = 185000000;␊ |
567 | ␉␉␉␉␉␉if (((fsbFrequency > minfsb) && (fsbFrequency < maxfsb)) || (!fsbFrequency))␊ |
568 | ␉␉␉␉␉␉{␊ |
569 | ␉␉␉␉␉␉␉fsbFrequency = 200000000;␊ |
570 | ␉␉␉␉␉␉␉fsbad = true;␊ |
571 | ␉␉␉␉␉␉}␊ |
572 | ␉␉␉␉␉}␊ |
573 | ␉␉␉␉}␊ |
574 | ␊ |
575 | ␉␉␉␉if(fix_fsb)␊ |
576 | ␉␉␉␉{␊ |
577 | ␉␉␉␉␉if (bus_ratio_max)␊ |
578 | ␉␉␉␉␉{␊ |
579 | ␉␉␉␉␉␉if (maxdiv) fsbi = ((tscFrequency * 2) / ((bus_ratio_max * 2) + 1));␊ |
580 | ␉␉␉␉␉␉else fsbi = (tscFrequency / bus_ratio_max);␊ |
581 | ␉␉␉␉␉}␊ |
582 | ␉␉␉␉␉ratio_gn:␊ |
583 | ␉␉␉␉␉if ((getValueForKey(kbusratio, &newratio, &len, &bootInfo->bootConfig)) && (len <= 4))␊ |
584 | ␉␉␉␉␉{␊ |
585 | ␉␉␉␉␉␉max_ratio = atoi(newratio);␊ |
586 | ␉␉␉␉␉␉max_ratio = (max_ratio * 10);␊ |
587 | ␉␉␉␉␉␉if (len >= 3) max_ratio = (max_ratio + 5);␊ |
588 | ␊ |
589 | ␉␉␉␉␉␉verbose("Bus-Ratio defaults: min=%d%s, max=%d%s\n", bus_ratio_min, currdiv ? ".5" : "", bus_ratio_max, maxdiv ? ".5" : "");␊ |
590 | ␉␉␉␉␉␉if ((max_ratio >= min_ratio) && (max_ratio < 200))␊ |
591 | ␉␉␉␉␉␉{␊ |
592 | ␉␉␉␉␉␉␉cpuFrequency = (fsbFrequency * max_ratio) / 10;␊ |
593 | ␉␉␉␉␉␉␉if (len >= 3) maxdiv = 1;␊ |
594 | ␉␉␉␉␉␉␉else maxdiv = 0;␊ |
595 | ␉␉␉␉␉␉␉verbose("Sticking with [FSB: %dMhz, Bus-Ratio: %s]\n", myfsb, newratio);␊ |
596 | ␉␉␉␉␉␉}␊ |
597 | ␉␉␉␉␉␉else␊ |
598 | ␉␉␉␉␉␉{␊ |
599 | ␉␉␉␉␉␉␉printf("Bus-Ratio: Lowest allowed = %d%s. ", bus_ratio_min, currdiv ? ".5" : "");␊ |
600 | ␉␉␉␉␉␉␉goto ratio_vldt;␊ |
601 | ␉␉␉␉␉␉}␊ |
602 | ␉␉␉␉␉}␊ |
603 | ␉␉␉␉␉else␊ |
604 | ␉␉␉␉␉{␊ |
605 | ␉␉␉␉␉␉ratio_vldt:␊ |
606 | ␉␉␉␉␉␉if (maxdiv)␊ |
607 | ␉␉␉␉␉␉{␊ |
608 | ␉␉␉␉␉␉␉cpuFrequency = ((fsbFrequency * ((bus_ratio_max * 2) + 1)) / 2);␊ |
609 | ␉␉␉␉␉␉␉max_ratio = (bus_ratio_max * 10) + 5;␊ |
610 | ␉␉␉␉␉␉}␊ |
611 | ␉␉␉␉␉␉else␊ |
612 | ␉␉␉␉␉␉{␊ |
613 | ␉␉␉␉␉␉␉cpuFrequency = (fsbFrequency * bus_ratio_max);␊ |
614 | ␉␉␉␉␉␉␉max_ratio = bus_ratio_max * 10;␊ |
615 | ␉␉␉␉␉␉}␊ |
616 | ␉␉␉␉␉␉verbose("CPU: Sticking with: [FSB: %dMhz, Bus-Ratio: %d%s] %s\n", myfsb, bus_ratio_max, maxdiv ? ".5" : "", newratio ? "instead" : "");␊ |
617 | ␉␉␉␉␉}␊ |
618 | ␉␉␉␉}␊ |
619 | ␉␉␉␉else␊ |
620 | ␉␉␉␉{␊ |
621 | ␉␉␉␉␉if (bus_ratio_max)␊ |
622 | ␉␉␉␉␉{␊ |
623 | ␉␉␉␉␉␉if (maxdiv)␊ |
624 | ␉␉␉␉␉␉{␊ |
625 | ␉␉␉␉␉␉␉fsbFrequency = ((tscFrequency * 2) / ((bus_ratio_max * 2) + 1));␊ |
626 | ␉␉␉␉␉␉␉max_ratio = ((bus_ratio_max * 10) + 5);␊ |
627 | ␉␉␉␉␉␉}␊ |
628 | ␉␉␉␉␉␉else␊ |
629 | ␉␉␉␉␉␉{␊ |
630 | ␉␉␉␉␉␉␉fsbFrequency = (tscFrequency / bus_ratio_max);␊ |
631 | ␉␉␉␉␉␉␉max_ratio = (bus_ratio_max * 10);␊ |
632 | ␉␉␉␉␉␉}␊ |
633 | ␊ |
634 | ␉␉␉␉␉␉myfsb = (fsbFrequency / 1000000);␊ |
635 | ␉␉␉␉␉␉if (getValueForKey(kbusratio, &newratio, &len, &bootInfo->bootConfig)) goto ratio_gn;␊ |
636 | ␉␉␉␉␉␉else cpuFrequency = ((fsbFrequency * max_ratio) / 10);␊ |
637 | ␊ |
638 | ␉␉␉␉␉␉DBG("max: %d%s current: %d%s\n", bus_ratio_max, maxdiv ? ".5" : "", bus_ratio_min, currdiv ? ".5" : "");␊ |
639 | ␉␉␉␉␉}␊ |
640 | ␉␉␉␉}␊ |
641 | ␉␉␉␉p->CPU.MaxRatio = max_ratio;␊ |
642 | ␉␉␉␉p->CPU.MinRatio = min_ratio;␊ |
643 | ␉␉␉}␊ |
644 | ␉␉}␊ |
645 | ␊ |
646 | ␉␉// on-die sensor␊ |
647 | ␉␉if (p->CPU.CPUID[CPUID_0][0] >= 0x6)␊ |
648 | ␉␉{␊ |
649 | ␉␉␉// Highest Basic Functions Number␊ |
650 | ␉␉␉do_cpuid(6, p->CPU.CPUID[CPUID_81]);␊ |
651 | ␉␉␉tms = bitfield(p->CPU.CPUID[CPUID_81][0], 0, 0);␊ |
652 | ␉␉␉ida = bitfield(p->CPU.CPUID[CPUID_81][0], 1, 1);␊ |
653 | ␉␉␉if(tms != 0)␊ |
654 | ␉␉␉{␊ |
655 | ␉␉␉␉int temp, utjmax;␊ |
656 | ␉␉␉␉if (tjmax == 0) tjmax = 100;␊ |
657 | ␉␉␉␉if((getIntForKey(kTjmax, &utjmax, &bootInfo->bootConfig)) && ((70 <= utjmax) && (utjmax <= 110))) tjmax = utjmax;␊ |
658 | ␉␉␉␉msr = rdmsr64(MSR_THERMAL_STATUS);␊ |
659 | ␉␉␉␉//if ((msr & 0x3) == 0x3)␊ |
660 | ␉␉␉␉if (((msr >> 31) & 0x1) == 1)␊ |
661 | ␉␉␉␉{␊ |
662 | ␉␉␉␉␉temp = tjmax - ((msr >> 16) & 0x7F);␊ |
663 | ␉␉␉␉␉verbose("CPU: Tjmax ~ %d°C ␉ Temperature= ~ %d°C\n", tjmax, temp);␊ |
664 | ␉␉␉␉}␊ |
665 | ␉␉␉␉else temp = -1;␊ |
666 | ␉␉␉}␊ |
667 | ␉␉␉if(ida == 0)␊ |
668 | ␉␉␉{␊ |
669 | ␉␉␉␉verbose("CPU: Attempting to enable IDA ");␊ |
670 | ␉␉␉␉msr_t msr;␊ |
671 | ␉␉␉␉msr = rdmsr(MSR_IA32_MISC_ENABLE);␊ |
672 | ␉␉␉␉msr.hi |= (0 << (38-32));␊ |
673 | ␉␉␉␉wrmsr(MSR_IA32_MISC_ENABLE, msr);␊ |
674 | ␉␉␉␉delay(1);␊ |
675 | ␉␉␉␉if(bitfield(p->CPU.CPUID[CPUID_81][0], 1, 1) == 0) verbose("Failed!\n");␊ |
676 | ␉␉␉␉else verbose("Succeded!\n");␊ |
677 | ␉␉␉}␊ |
678 | ␉␉␉else verbose("CPU: IDA: Enabled!\n");␊ |
679 | ␉␉}␊ |
680 | ␉}␊ |
681 | //#if 0␊ |
682 | ␉// valv: work in progress. Most of this code is going to be moved when ready␊ |
683 | ␉else if(p->CPU.Vendor == 0x68747541 /* AMD */ && p->CPU.Family == 0x0f)␊ |
684 | ␉{␊ |
685 | ␉␉verbose("CPU: ");␊ |
686 | ␉␉// valv: very experimental mobility check␊ |
687 | ␉␉if (p->CPU.CPUID[0x80000000][0] >= 0x80000007)␊ |
688 | ␉␉{␊ |
689 | ␉␉␉uint32_t amo, const_tsc;␊ |
690 | ␉␉␉do_cpuid(0x80000007, p->CPU.CPUID[CPUID_MAX]);␊ |
691 | ␉␉␉amo = bitfield(p->CPU.CPUID[CPUID_MAX][0], 6, 6);␊ |
692 | ␉␉␉const_tsc = bitfield(p->CPU.CPUID[CPUID_MAX][3], 8, 8);␊ |
693 | ␉␉␉// valv: p-state support verification␊ |
694 | ␉␉␉//uint32_t pstate_support = bitfield(p->CPU.CPUID[CPUID_MAX][3], 2, 1);␊ |
695 | ␉␉␉//if(pstate_support != 0) verbose("supproted p-state transition\n")␊ |
696 | ␉␉␉␊ |
697 | ␉␉␉if (const_tsc != 0) verbose("Constant TSC!\n");␊ |
698 | ␉␉␉if (amo == 1)␊ |
699 | ␉␉␉{␊ |
700 | ␉␉␉␉p->CPU.Features |= CPU_FEATURE_MOBILE;␊ |
701 | ␉␉␉␉if (!strstr(p->CPU.BrandString, "obile")) verbose("Mobile ");␊ |
702 | ␉␉␉}␊ |
703 | ␉␉}␊ |
704 | ␉␉//valv: 2nd attemp; just in case␊ |
705 | ␉␉if (!platformCPUFeature(CPU_FEATURE_MOBILE))␊ |
706 | ␉␉{␊ |
707 | ␉␉␉if (strstr(p->CPU.BrandString, "obile"))␊ |
708 | ␉␉␉{␊ |
709 | ␉␉␉␉p->CPU.Features |= CPU_FEATURE_MOBILE;␊ |
710 | ␉␉␉}␊ |
711 | ␉␉}␊ |
712 | ␉␉verbose("%s\n", p->CPU.BrandString);␊ |
713 | ␊ |
714 | ␉␉if(p->CPU.ExtFamily == 0x00 /* K8 */)␊ |
715 | ␉␉{␊ |
716 | ␉␉␉// valv: this section needs some work␊ |
717 | ␉␉␉msr = rdmsr64(K8_FIDVID_STATUS);␊ |
718 | ␉␉␉bus_ratio_max = bitfield(msr, 21, 16);␊ |
719 | ␉␉␉//bus_ratio_max = (msr & 0x3f) / 2 + 4;␊ |
720 | ␉␉␉bus_ratio_min = bitfield(msr, 13, 8);␊ |
721 | ␉␉␉currdiv = (msr & 0x01) * 2;␊ |
722 | ␉␉␉if (bus_ratio_max)␊ |
723 | ␉␉␉{␊ |
724 | ␉␉␉␉if (currdiv)␊ |
725 | ␉␉␉␉{␊ |
726 | ␉␉␉␉␉fsbFrequency = ((tscFrequency * currdiv) / bus_ratio_max); // ?␊ |
727 | ␉␉␉␉␉DBG("%d.%d\n", bus_ratio_max / currdiv, ((bus_ratio_max % currdiv) * 100) / currdiv);␊ |
728 | ␉␉␉␉}␊ |
729 | ␉␉␉␉else␊ |
730 | ␉␉␉␉{␊ |
731 | ␉␉␉␉␉fsbFrequency = (tscFrequency / bus_ratio_max);␊ |
732 | ␉␉␉␉␉DBG("%d\n", bus_ratio_max);␊ |
733 | ␉␉␉␉}␊ |
734 | ␉␉␉␉//fsbFrequency = (tscFrequency / bus_ratio_max); // ?␊ |
735 | ␉␉␉␉cpuFrequency = tscFrequency; // ?␊ |
736 | ␉␉␉}␊ |
737 | ␉␉}␊ |
738 | ␊ |
739 | ␉␉else if(p->CPU.ExtFamily >= 0x01 /* K10+ */)␊ |
740 | ␉␉{␊ |
741 | ␉␉␉msr = rdmsr64(K10_COFVID_STATUS);␊ |
742 | ␉␉␉currdiv = (2 << ((msr >> 6) & 0x07));␊ |
743 | ␉␉␉msr = rdmsr64(AMD_10H_11H_CONFIG);␊ |
744 | ␉␉␉bus_ratio_max = ((msr) & 0x3F);␊ |
745 | ␉␉␉//verbose("max_multi: %d\n", bus_ratio_max);␊ |
746 | ␊ |
747 | ␉␉␉/*msr_t divmsr;␊ |
748 | ␉␉␉divmsr = rdmsr(AMD_10H_11H_CONFIG);␊ |
749 | ␉␉␉maxdiv = (divmsr.hi >> 0x08) & 0x01;␊ |
750 | ␉␉␉verbose("maxdiv: %d, currdiv: %d\n", maxdiv, currdiv);*/␊ |
751 | ␊ |
752 | ␉␉␉if(p->CPU.ExtFamily == 0x01) ␊ |
753 | ␉␉␉␉cpuFrequency = 100 * (bus_ratio_max + 0x10);␊ |
754 | ␉␉␉else ␊ |
755 | ␉␉␉␉cpuFrequency = 100 * (bus_ratio_max + 0x08);␊ |
756 | ␉␉␉␊ |
757 | ␉␉␉uint32_t minFreq = cpuFrequency / (1 << currdiv);␊ |
758 | ␊ |
759 | ␉␉␉uint8_t maxrtio = (cpuFrequency / 20);␊ |
760 | ␉␉␉p->CPU.MaxRatio = maxrtio;␊ |
761 | ␉␉␉␊ |
762 | ␉␉␉fsbFrequency = ((tscFrequency / 100000) / maxrtio);␊ |
763 | ␉␉␉verbose("fsb: %d\n", fsbFrequency);␊ |
764 | ␉␉␉␊ |
765 | ␉␉␉if(maxrtio == ((bus_ratio_max * 10) - 5))␊ |
766 | ␉␉␉{␊ |
767 | ␉␉␉␉verbose("multi: max:%d.5, min:", (bus_ratio_max - 1));␊ |
768 | ␉␉␉␉maxdiv = 1;␊ |
769 | ␉␉␉}␊ |
770 | ␉␉␉else if(maxrtio == ((bus_ratio_max - 1) * 10))␊ |
771 | ␉␉␉{␊ |
772 | ␉␉␉␉verbose("multi: max:%d, min:", (bus_ratio_max - 1));␊ |
773 | ␉␉␉␉maxdiv = 0;␊ |
774 | ␉␉␉}␊ |
775 | ␊ |
776 | ␉␉␉bus_ratio_min = (minFreq / fsbFrequency);␊ |
777 | ␉␉␉verbose("%d", bus_ratio_min);␊ |
778 | ␉␉␉while(minFreq < 800)␊ |
779 | ␉␉␉{␊ |
780 | ␉␉␉␉bus_ratio_min = bus_ratio_min + 1; // bus_ratio_min++; ???␊ |
781 | ␉␉␉␉verbose(" >> %d", bus_ratio_min);␊ |
782 | ␉␉␉}␊ |
783 | ␉␉␉verbose("\n");␊ |
784 | ␊ |
785 | ␉␉␉struct hwpstate ␊ |
786 | ␉␉␉{␊ |
787 | ␉␉␉␉uint32_t␉freq;␉␉/* CPU clock in Mhz. */␊ |
788 | ␉␉␉␉uint32_t␉volts;␉␉/* Voltage in mV. */␊ |
789 | ␉␉␉␉uint32_t␉power;␉␉/* Power consumed in mW. */␊ |
790 | ␉␉␉␉uint8_t␉lat;␉␉␉/* Transition latency in us. */␊ |
791 | ␉␉␉␉uint8_t␉pstate_id;␉␉/* P-State id */␊ |
792 | ␉␉␉};␊ |
793 | ␉␉␉␊ |
794 | ␉␉␉struct hwpstate state[32];␊ |
795 | ␉␉␉int max_state, i,/* did,*/ vid;␊ |
796 | ␉␉␉uint8_t fid;␊ |
797 | ␉␉␉msr = rdmsr64(MSR_AMD_10H_11H_LIMIT);␊ |
798 | ␉␉␉max_state = 1 + (((msr) >> 4) & 0x7);␊ |
799 | ␊ |
800 | ␉␉␉for(i=0; i<max_state; i++)␊ |
801 | ␉␉␉{␊ |
802 | ␉␉␉␉msr = rdmsr64(AMD_10H_11H_CONFIG + i);␊ |
803 | ␉␉␉␉//msr_t didmsr;␊ |
804 | ␉␉␉␉//didmsr = rdmsr(AMD_10H_11H_CONFIG + i);␊ |
805 | ␉␉␉␉if ((msr & ((uint64_t)1 << 63)) != ((uint64_t)1 << 63)) verbose("Invalid MSR!\n");␊ |
806 | ␉␉␉␉else␊ |
807 | ␉␉␉␉{␊ |
808 | ␉␉␉␉␉//did = (didmsr.hi >> 0x08) & 0x01;␊ |
809 | ␉␉␉␉␉if(i == 0) ␊ |
810 | ␉␉␉␉␉{␊ |
811 | ␉␉␉␉␉␉//maxdiv = did;␊ |
812 | ␉␉␉␉␉␉fid = p->CPU.MaxRatio;␊ |
813 | ␉␉␉␉␉␉state[i].freq = ((fid * fsbFrequency) / 10);␊ |
814 | ␉␉␉␉␉␉fid = (fid / 10);␊ |
815 | ␉␉␉␉␉}␊ |
816 | ␉␉␉␉␉else␊ |
817 | ␉␉␉␉␉{␊ |
818 | ␉␉␉␉␉␉fid = bitfield(msr, 5, 0);␊ |
819 | ␉␉␉␉␉␉state[i].freq = (fid * fsbFrequency);␊ |
820 | ␉␉␉␉␉}␊ |
821 | ␉␉␉␉␉␊ |
822 | ␉␉␉␉␉if(i == (max_state -1))␊ |
823 | ␉␉␉␉␉{␊ |
824 | ␉␉␉␉␉␉fid = bus_ratio_min;␊ |
825 | ␉␉␉␉␉␉state[i].freq = (fid * fsbFrequency);␊ |
826 | ␉␉␉␉␉}␊ |
827 | ␉␉␉␉␉␊ |
828 | ␉␉␉␉␉vid = bitfield(msr, 15, 9);␊ |
829 | ␉␉␉␉␉␊ |
830 | ␉␉␉␉␉if(i == 0) verbose("P-State %d: Frequency: %d, Multiplier: %d%s, vid: %d\n", i, state[i].freq, fid, maxdiv ? ".5" : "", vid);␊ |
831 | ␉␉␉␉␉else if((state[i].freq > state[i-1].freq) || (state[i].freq < 800)) verbose("P-State %d: Removed!\n", i);␊ |
832 | ␉␉␉␉␉else verbose("P-State %d: Frequency: %d, Multiplier: %d, vid: %d\n", i, state[i].freq, fid, vid);␊ |
833 | ␉␉␉␉␉state[i].pstate_id = i;␊ |
834 | ␉␉␉␉␉// valv: zeroed for now␊ |
835 | ␉␉␉␉␉state[i].volts = 0;␊ |
836 | ␉␉␉␉␉state[i].power = 0;␊ |
837 | ␉␉␉␉␉state[i].lat = 0;␊ |
838 | ␉␉␉␉}␊ |
839 | ␉␉␉}␊ |
840 | ␉␉␉fsbFrequency = (fsbFrequency * 1000000);␊ |
841 | ␉␉␉cpuFrequency = (state[0].freq * 1000000);␊ |
842 | ␉␉}␊ |
843 | ␉␉␊ |
844 | ␉␉p->CPU.MinRatio = bus_ratio_min * 10;␊ |
845 | ␉}␊ |
846 | ␉else if(p->CPU.Vendor == 0x746e6543 /* CENTAUR */ && p->CPU.Family == 6) //valv: partial!␊ |
847 | ␉{␊ |
848 | ␉␉msr = rdmsr64(MSR_EBL_CR_POWERON);␊ |
849 | ␉␉int bus = (msr >> 18) & 0x3;␊ |
850 | ␉␉switch (bus)␊ |
851 | ␉␉{␊ |
852 | ␉␉␉case 1:␊ |
853 | ␉␉␉␉fsbFrequency = 133333333;␊ |
854 | ␉␉␉␉break;␊ |
855 | ␉␉␉case 2:␊ |
856 | ␉␉␉␉fsbFrequency = 200000000;␊ |
857 | ␉␉␉␉break;␊ |
858 | ␉␉␉case 3:␊ |
859 | ␉␉␉␉fsbFrequency = 166666667;␊ |
860 | ␉␉␉␉break;␊ |
861 | ␉␉␉case 0:␊ |
862 | ␉␉␉default:␉␉␉␉␊ |
863 | ␉␉␉␉fsbFrequency = 100000000;␊ |
864 | ␉␉␉␉break;␊ |
865 | ␉␉}␊ |
866 | ␉␉msr_t msr;␊ |
867 | ␉␉msr = rdmsr(MSR_IA32_PERF_STATUS);␊ |
868 | ␉␉bus_ratio_min = (msr.lo >> 24) & 0x1f;␊ |
869 | ␉␉min_ratio = bus_ratio_min * 10;␊ |
870 | ␉␉bus_ratio_max = (msr.hi >> (40-32)) & 0x1f;␊ |
871 | ␉␉max_ratio = bus_ratio_max * 10;␊ |
872 | ␉␉cpuFrequency = ((fsbFrequency * max_ratio) / 10);␊ |
873 | ␉}␊ |
874 | ␊ |
875 | ␉if (!fsbFrequency)␊ |
876 | ␉{␊ |
877 | ␉␉fsbFrequency = (DEFAULT_FSB * 1000);␊ |
878 | ␉␉cpuFrequency = tscFrequency;␊ |
879 | ␉␉DBG("0 ! using the default value for FSB !\n");␊ |
880 | ␉}␊ |
881 | ␊ |
882 | //#endif␊ |
883 | ␊ |
884 | ␉p->CPU.MaxDiv = maxdiv;␊ |
885 | ␉p->CPU.CurrDiv = currdiv;␊ |
886 | ␉p->CPU.TSCFrequency = tscFrequency;␊ |
887 | ␉p->CPU.FSBFrequency = fsbFrequency;␊ |
888 | ␉p->CPU.CPUFrequency = cpuFrequency;␊ |
889 | ␉p->CPU.ISerie = false;␊ |
890 | ␉p->CPU.Turbo = false;␊ |
891 | ␊ |
892 | ␉if(!fsbad) p->CPU.FSBIFrequency = fsbFrequency;␊ |
893 | ␉else p->CPU.FSBIFrequency = fsbi;␊ |
894 | ␊ |
895 | ␉if (platformCPUFeature(CPU_FEATURE_EST))␊ |
896 | ␉{␊ |
897 | ␉␉msr_t msr32;␊ |
898 | ␉␉msr32 = rdmsr(MSR_IA32_MISC_ENABLE);␊ |
899 | ␉␉if (!(rdmsr64(MSR_IA32_MISC_ENABLE) & (1 << 16)))␊ |
900 | ␉␉{␉//valv: we can also attempt to enable␊ |
901 | ␉␉␉msr32.lo |= (1 << 16);␊ |
902 | ␉␉␉// Lock till next reset!␊ |
903 | ␉␉␉msr32.lo |= (1 << 20);␊ |
904 | ␉␉␉wrmsr(MSR_IA32_MISC_ENABLE, msr32);␊ |
905 | ␉␉␉delay(1);␊ |
906 | ␉␉␉if(rdmsr64(MSR_IA32_MISC_ENABLE) & (1 << 16))␊ |
907 | ␉␉␉{␊ |
908 | ␉␉␉␉p->CPU.EST = 1;␊ |
909 | ␉␉␉␉verbose("CPU: EIST Successfully Enabled!\n");␊ |
910 | ␉␉␉}␊ |
911 | ␉␉␉else␊ |
912 | ␉␉␉{␊ |
913 | ␉␉␉␉p->CPU.EST = 0;␊ |
914 | ␉␉␉␉verbose("CPU: EIST couldn't be enabled!\n");␊ |
915 | ␉␉␉}␊ |
916 | ␉␉}␊ |
917 | ␊ |
918 | ␉␉else p->CPU.EST = 1;␊ |
919 | ␉}␊ |
920 | ␉␊ |
921 | ␉if(core_i) p->CPU.ISerie = true;␊ |
922 | ␉␉DBG("CPU: Vendor/Family/ExtFamily: 0x%x/0x%x/0x%x\n", p->CPU.Vendor, p->CPU.Family, p->CPU.ExtFamily);␊ |
923 | ␉␉DBG("CPU: Model/ExtModel/Stepping: 0x%x/0x%x/0x%x\n", p->CPU.Model, p->CPU.ExtModel, p->CPU.Stepping);␊ |
924 | ␉␉DBG("CPU: Multipliers x10: max=%d, min=%d\n", p->CPU.MaxRatio, p->CPU.MinRatio);␊ |
925 | ␉if(turbo)␊ |
926 | ␉{␊ |
927 | ␉␉DBG("Turbo Ratio: %d/%d/%d/%d\n", p->CPU.Tone, p->CPU.Ttwo, p->CPU.Tthr, p->CPU.Tfor);␊ |
928 | ␉␉p->CPU.Turbo = true;␊ |
929 | ␉}␊ |
930 | ␉␉DBG("CPU: MaxDiv/CurrDiv: 0x%x/0x%x\n", p->CPU.MaxDiv, p->CPU.CurrDiv);␊ |
931 | ␉␉DBG("CPU: TSCFreq: %dMHz\n", p->CPU.TSCFrequency / 1000000);␊ |
932 | ␉␉DBG("CPU: CPUFreq: %dMHz\n", p->CPU.CPUFrequency / 1000000);␊ |
933 | ␉␉DBG("CPU: FSBFreq: %dMHz\n", p->CPU.FSBFrequency / 1000000);␊ |
934 | ␉if(did)␊ |
935 | ␉{␊ |
936 | ␉␉p->CPU.SLFM = did;␊ |
937 | ␉␉DBG("CPU: SLFM: %d\n", p->CPU.SLFM);␊ |
938 | ␉}␊ |
939 | ␉␉if(platformCPUFeature(CPU_FEATURE_EST))␊ |
940 | ␉␉DBG("CPU: Enhanced SpeedStep: %d\n", p->CPU.EST);␊ |
941 | ␉␉DBG("CPU: NoCores/NoThreads: %d/%d\n", p->CPU.NoCores, p->CPU.NoThreads);␊ |
942 | ␉␉DBG("CPU: Features: 0x%08x\n", p->CPU.Features);␊ |
943 | }␊ |
944 | |