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1/*␊
2 * Copyright 2008 Islam Ahmed Zaid. All rights reserved. <azismed@gmail.com>␊
3 * AsereBLN: 2009: cleanup and bugfix␊
4 */␊
5␊
6#include "libsaio.h"␊
7#include "platform.h"␊
8//#include "mem.h"␊
9#include "smbios_patcher.h"␊
10#include "cpu.h"␊
11␊
12#ifndef DEBUG_CPU␊
13#define DEBUG_CPU 0␊
14#endif␊
15␊
16#if DEBUG_CPU␊
17#define DBG(x...)␉␉printf(x)␊
18#else␊
19#define DBG(x...)␉␉msglog(x)␊
20#endif␊
21␊
22␊
23/*␊
24 * DFE: Measures the TSC frequency in Hz (64-bit) using the ACPI PM timer␊
25 */␊
26static uint64_t measure_tsc_frequency(void)␊
27{␊
28 uint64_t tscStart;␊
29 uint64_t tscEnd;␊
30 uint64_t tscDelta = 0xffffffffffffffffULL;␊
31 unsigned long pollCount;␊
32 uint64_t retval = 0;␊
33 int i;␊
34␊
35 /* Time how many TSC ticks elapse in 30 msec using the 8254 PIT␊
36 * counter 2. We run this loop 3 times to make sure the cache␊
37 * is hot and we take the minimum delta from all of the runs.␊
38 * That is to say that we're biased towards measuring the minimum␊
39 * number of TSC ticks that occur while waiting for the timer to␊
40 * expire. That theoretically helps avoid inconsistencies when␊
41 * running under a VM if the TSC is not virtualized and the host␊
42 * steals time. The TSC is normally virtualized for VMware.␊
43 */␊
44 for(i = 0; i < 10; ++i)␊
45 {␊
46 enable_PIT2();␊
47 set_PIT2_mode0(CALIBRATE_LATCH);␊
48 tscStart = rdtsc64();␊
49 pollCount = poll_PIT2_gate();␊
50 tscEnd = rdtsc64();␊
51 /* The poll loop must have run at least a few times for accuracy */␊
52 if(pollCount <= 1)␊
53 continue;␊
54 /* The TSC must increment at LEAST once every millisecond. We␊
55 * should have waited exactly 30 msec so the TSC delta should␊
56 * be >= 30. Anything less and the processor is way too slow.␊
57 */␊
58 if((tscEnd - tscStart) <= CALIBRATE_TIME_MSEC)␊
59 continue;␊
60 // tscDelta = min(tscDelta, (tscEnd - tscStart))␊
61 if( (tscEnd - tscStart) < tscDelta )␊
62 tscDelta = tscEnd - tscStart;␊
63 }␊
64 /* tscDelta is now the least number of TSC ticks the processor made in␊
65 * a timespan of 0.03 s (e.g. 30 milliseconds)␊
66 * Linux thus divides by 30 which gives the answer in kiloHertz because␊
67 * 1 / ms = kHz. But we're xnu and most of the rest of the code uses␊
68 * Hz so we need to convert our milliseconds to seconds. Since we're␊
69 * dividing by the milliseconds, we simply multiply by 1000.␊
70 */␊
71␊
72 /* Unlike linux, we're not limited to 32-bit, but we do need to take care␊
73 * that we're going to multiply by 1000 first so we do need at least some␊
74 * arithmetic headroom. For now, 32-bit should be enough.␊
75 * Also unlike Linux, our compiler can do 64-bit integer arithmetic.␊
76 */␊
77 if(tscDelta > (1ULL<<32))␊
78 retval = 0;␊
79 else␊
80 {␊
81 retval = tscDelta * 1000 / 30;␊
82 }␊
83 disable_PIT2();␊
84 return retval;␊
85}␊
86␊
87/*␊
88 * Calculates the FSB and CPU frequencies using specific MSRs for each CPU␊
89 * - multi. is read from a specific MSR. In the case of Intel, there is:␊
90 * a max multi. (used to calculate the FSB freq.),␊
91 * and a current multi. (used to calculate the CPU freq.)␊
92 * - fsbFrequency = tscFrequency / multi␊
93 * - cpuFrequency = fsbFrequency * multi␊
94 */␊
95␊
96void scan_cpu() //PlatformInfo_t *p)␊
97{␊
98␉PlatformInfo_t *p = Platform;␊
99␉int i = 0;␊
100␉uint8_t turbo;␊
101␉uint64_t␉tscFrequency, fsbFrequency, cpuFrequency;␊
102␉uint64_t␉msr; //, flex_ratio;␊
103␉uint8_t␉␉maxcoef, maxdiv, currcoef, currdiv, mindiv;␊
104␊
105␉maxcoef = maxdiv = currcoef = currdiv = mindiv = 0;␊
106␉␊
107#if DEBUG_CPU␊
108␉printf("Enter cpuid_info\n");␊
109␉pause();␊
110#endif␊
111␉cpuid_update_generic_info();␊
112␉␊
113#if DEBUG_CPU␊
114␉printf("...OK\n");␊
115␉pause();␊
116#endif␊
117␉␊
118#if OLDMETHOD␉␊
119␉/* get cpuid values */␊
120␉for( ; i <= 3; i++)␊
121␉{␊
122␉␉do_cpuid(i, p->CPU.CPUID[i]);␊
123␉}␊
124␉␊
125␉do_cpuid2(0x00000004, 0, p->CPU.CPUID[CPUID_4]);␊
126␉do_cpuid(0x80000000, p->CPU.CPUID[CPUID_80]);␊
127␉if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 1) {␊
128␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊
129␉}␊
130#if DEBUG_CPU␊
131␉{␊
132␉␉int␉␉i;␊
133␉␉DBG("CPUID Raw Values:\n");␊
134␉␉for (i=0; i<CPUID_MAX; i++) {␊
135␉␉␉DBG("%02d: %08x-%08x-%08x-%08x\n", i,␊
136␉␉␉␉p->CPU.CPUID[i][0], p->CPU.CPUID[i][1],␊
137␉␉␉␉p->CPU.CPUID[i][2], p->CPU.CPUID[i][3]);␊
138␉␉}␊
139␉}␊
140#endif␊
141␉p->CPU.Vendor␉␉= p->CPU.CPUID[CPUID_0][1];␊
142␉p->CPU.Signature␉= p->CPU.CPUID[CPUID_1][0];␊
143␉p->CPU.Stepping␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 3, 0);␊
144␉p->CPU.Model␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 7, 4);␊
145␉p->CPU.Family␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 11, 8);␊
146␉p->CPU.ExtModel␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 19, 16);␊
147␉p->CPU.ExtFamily␉= bitfield(p->CPU.CPUID[CPUID_1][0], 27, 20);␊
148␉p->CPU.NoThreads␉= bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␊
149␉p->CPU.NoCores␉␉= bitfield(p->CPU.CPUID[CPUID_4][0], 31, 26) + 1;␊
150␊
151␉p->CPU.Model += (p->CPU.ExtModel << 4);␊
152␉␊
153␉/* get brand string (if supported) */␊
154␉/* Copyright: from Apple's XNU cpuid.c */␊
155␉if (p->CPU.CPUID[CPUID_80][0] > 0x80000004) {␊
156␉␉uint32_t␉reg[4];␊
157 char str[128], *s;␊
158␉␉/*␊
159␉␉ * The brand string 48 bytes (max), guaranteed to␊
160␉␉ * be NUL terminated.␊
161␉␉ */␊
162␉␉do_cpuid(0x80000002, reg);␊
163␉␉bcopy((char *)reg, &str[0], 16);␊
164␉␉do_cpuid(0x80000003, reg);␊
165␉␉bcopy((char *)reg, &str[16], 16);␊
166␉␉do_cpuid(0x80000004, reg);␊
167␉␉bcopy((char *)reg, &str[32], 16);␊
168␉␉for (s = str; *s != '\0'; s++) {␊
169␉␉␉if (*s != ' ') break;␊
170␉␉}␊
171␉␉␊
172␉␉strlcpy(p->CPU.BrandString,␉s, sizeof(p->CPU.BrandString));␊
173␉␉␊
174␉␉if (!strncmp(p->CPU.BrandString, CPU_STRING_UNKNOWN, min(sizeof(p->CPU.BrandString), strlen(CPU_STRING_UNKNOWN) + 1))) {␊
175␉␉␉ /*␊
176␉␉␉ * This string means we have a firmware-programmable brand string,␊
177␉␉␉ * and the firmware couldn't figure out what sort of CPU we have.␊
178␉␉␉ */␊
179␉␉␉ p->CPU.BrandString[0] = '\0';␊
180␉␉ }␊
181␉}␊
182␉␊
183␉/* setup features */␊
184␉p->CPU.Features |= (CPU_FEATURE_MMX | CPU_FEATURE_SSE | CPU_FEATURE_SSE2 | CPU_FEATURE_MSR) & p->CPU.CPUID[CPUID_1][3];␊
185␉p->CPU.Features |= (CPU_FEATURE_SSE3 | CPU_FEATURE_SSE41 | CPU_FEATURE_SSE42) & p->CPU.CPUID[CPUID_1][2];␉␊
186␉p->CPU.Features |= (CPU_FEATURE_EM64T) & p->CPU.CPUID[CPUID_81][3];␊
187␊
188␊
189␉//if ((CPU_FEATURE_HTT & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
190␉if (p->CPU.NoThreads > p->CPU.NoCores) {␊
191␉␉p->CPU.Features |= CPU_FEATURE_HTT;␊
192␉}␊
193#else //Slice␊
194␉p->CPU.Vendor␉␉= *(UInt32*)&cpuid_info()->cpuid_vendor;␊
195␉p->CPU.Signature␉= cpuid_info()->cpuid_signature;␊
196␉p->CPU.Stepping␉␉= cpuid_info()->cpuid_stepping;␊
197␉p->CPU.Model␉␉= cpuid_info()->cpuid_model;␊
198␉p->CPU.Family␉␉= cpuid_info()->cpuid_family;␊
199␉p->CPU.ExtModel␉␉= cpuid_info()->cpuid_extmodel;␊
200␉p->CPU.ExtFamily␉= cpuid_info()->cpuid_extfamily;␊
201//␉DBG("CPU: Vendor/Model/ExtModel: 0x%x/0x%x/0x%x\n", p->CPU.Vendor, p->CPU.Model, p->CPU.ExtModel);␊
202//␉DBG("CPU: Family/ExtFamily: 0x%x/0x%x\n", p->CPU.Family, p->CPU.ExtFamily);␊
203␉␊
204␉strlcpy(p->CPU.BrandString, cpuid_info()->cpuid_brand_string, sizeof(p->CPU.BrandString));␊
205␉DBG("CPU: BrandString %s\n", p->CPU.BrandString);␊
206␉p->CPU.Features = cpuid_info()->cpuid_features;␊
207␉p->CPU.NoCores = cpuid_info()->core_count;␊
208␉p->CPU.NoThreads = cpuid_info()->thread_count;␊
209//␉DBG("CPU: MaxCoef/CurrCoef: 0x%x/0x%x\n", p->CPU.MaxCoef, p->CPU.CurrCoef);␊
210//␉DBG("CPU: MaxDiv/CurrDiv: 0x%x/0x%x\n", p->CPU.MaxDiv?2:1, p->CPU.CurrDiv?2:1);␊
211//␉DBG("CPU: TSCFreq: %dMHz\n", p->CPU.TSCFrequency / 1000000);␊
212//␉DBG("CPU: FSBFreq: %dMHz\n", p->CPU.FSBFrequency / 1000000);␊
213//␉DBG("CPU: CPUFreq: %dMHz\n", p->CPU.CPUFrequency / 1000000);␊
214//␉DBG("CPU: NoCores/NoThreads: %d/%d\n", p->CPU.NoCores, p->CPU.NoThreads);␊
215//␉DBG("CPU: Features: 0x%08x\n", p->CPU.Features);␊
216#if DEBUG_CPU␊
217␉pause();␊
218#endif␊
219␉␊
220#endif␊
221␊
222␉tscFrequency = measure_tsc_frequency();␊
223␉DBG("measure_tsc_frequency = %dMHz\n", tscFrequency / MEGA);␊
224␉fsbFrequency = 0;␊
225␉cpuFrequency = 0;␊
226␊
227␉if ((p->CPU.Vendor == 0x756E6547 /* Intel */) && ␊
228␉␉((p->CPU.Family == 0x06) || ␊
229␉␉ (p->CPU.Family == 0x0f)))␊
230␉{␊
231␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) || ␊
232␉␉␉(p->CPU.Family == 0x0f && p->CPU.Model >= 0x03))␊
233␉␉{␊
234␉␉␉/* Nehalem CPU model */␊
235␉␉␉if (p->CPU.Family == 0x06 && (p->CPU.Model == 0x1a || p->CPU.Model == 0x1e ||␊
236␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == 0x1f || p->CPU.Model == 0x25 ||␊
237␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == 0x19 || p->CPU.Model == 0x2c)) ␊
238␉␉␉{␊
239␉␉␉␉msr = rdmsr64(MSR_PLATFORM_INFO);␊
240␉␉␉␉DBG("msr(0x%04x): platform_info %08x-%08x\n", MSR_PLATFORM_INFO,␊
241␉␉␉␉(msr >> 32) & 0xffffffff, msr & 0xffffffff);␊
242␉␉␉␉mindiv = (msr >> 40) & 0xff;␊
243␉␉␉␉maxcoef = (msr >> 8) & 0xff; ␊
244␉␉␉␉␊
245␉␉␉␉msr = rdmsr64(MSR_TURBO_RATIO);␊
246␉␉␉␉turbo = msr & 0x7f;␊
247␉␉␉␉//Slice - doesn't work␊
248␉␉␉␉/*␊
249␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊
250␉␉␉␉DBG("msr(0x%04x): flex_ratio %08x\n", MSR_FLEX_RATIO, msr & 0xffffffff);␊
251␉␉␉␉if ((msr >> 16) & 0x01) {␊
252␉␉␉␉␉flex_ratio = (msr >> 8) & 0xff;␊
253␉␉␉␉␉if (currcoef > flex_ratio) {␊
254␉␉␉␉␉␉currcoef = flex_ratio;␊
255␉␉␉␉␉}␊
256␉␉␉␉}*/␊
257␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_STATUS);␊
258␉␉␉␉if (msr) {␊
259␉␉␉␉␉currcoef = msr & 0x1f;␊
260␉␉␉␉}␊
261␉␉␉␉␊
262␉␉␉␉if (!currcoef) {␊
263␉␉␉␉␉currcoef = maxcoef;␊
264␉␉␉␉}␊
265␉␉␉␉␊
266␉␉␉␉if (currcoef < mindiv) {␊
267␉␉␉␉␉currcoef = mindiv;␊
268␉␉␉␉}␊
269␉␉␉␉␊
270␉␉␉␉if (currcoef) {␊
271␉␉␉␉␉fsbFrequency = (tscFrequency / currcoef);␊
272␉␉␉␉}␊
273␉␉␉␉cpuFrequency = tscFrequency;␊
274␉␉␉} ␊
275␉␉␉else //not nehalem␊
276␉␉␉{␊
277␉␉␉␉//Slice - it is not FSB frequency. It is System Bus Speed: FSB = SBS * 4;␉␊
278␉␉␉␉if (p->CPU.Family != 0x0d){␊
279␉␉␉␉␉msr = rdmsr64(MSR_FSB_FREQ);␊
280␉␉␉␉␉switch (msr & 7) {␊
281␉␉␉␉␉␉case 0:␊
282␉␉␉␉␉␉␉fsbFrequency = 266670 * 1000;␊
283␉␉␉␉␉␉␉break;␊
284␉␉␉␉␉␉case 1:␊
285␉␉␉␉␉␉␉fsbFrequency = 133330 * 1000;␊
286␉␉␉␉␉␉␉break;␊
287␉␉␉␉␉␉case 2:␊
288␉␉␉␉␉␉␉fsbFrequency = 200000 * 1000;␊
289␉␉␉␉␉␉␉break;␊
290␉␉␉␉␉␉case 3:␊
291␉␉␉␉␉␉␉fsbFrequency = 166670 * 1000;␊
292␉␉␉␉␉␉␉break;␊
293␉␉␉␉␉␉case 4:␊
294␉␉␉␉␉␉␉fsbFrequency = 333330 * 1000;␊
295␉␉␉␉␉␉␉break;␊
296␉␉␉␉␉␉case 5:␊
297␉␉␉␉␉␉␉fsbFrequency = 200000 * 1000;␊
298␉␉␉␉␉␉␉break;␊
299␉␉␉␉␉␉case 6:␊
300␉␉␉␉␉␉␉fsbFrequency = 400000 * 1000;␊
301␉␉␉␉␉␉␉break;␊
302␉␉␉␉␉␉default:␊
303␉␉␉␉␉␉␉fsbFrequency = 0;␊
304␉␉␉␉␉␉␉break;␊
305␉␉␉␉␉}␊
306␉␉␉␉␉DBG("msr(0x%04x): MSR_FSB_FREQ %d.%dMHz\n", MSR_FSB_FREQ,␊
307␉␉␉␉␉␉fsbFrequency/MEGA, (fsbFrequency%MEGA)/1000);␊
308␉␉␉␉}␊
309␉␉␉␉␊
310␉␉␉␉msr = rdmsr64(MSR_PLATFORM_INFO); //info only?␊
311␉␉␉␉uint32_t m2 = msr >> 32;␊
312␉␉␉␉DBG("msr(0x%04x): platform_info %08x-%08x\n", MSR_PLATFORM_INFO,␊
313␉␉␉␉␉m2 & 0xffffffff, msr & 0xffffffff);␊
314␉␉␉␉turbo = (m2 >> 8) & 0x1f;␊
315␉␉␉␉␊
316␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_STATUS);␊
317␉␉␉␉m2 = msr >> 32;␊
318␉␉␉␉DBG("msr(0x%04x): MSR_IA32_PERF_STATUS %08x-%08x\n", MSR_IA32_PERF_STATUS,␊
319␉␉␉␉␉m2 & 0xffffffff, msr & 0xffffffff);␊
320␉␉␉␉␊
321␉␉␉␉currcoef = (msr >> 8) & 0x1f;␊
322␉␉␉␉mindiv = (msr >> 24) & 0xf;␊
323␉␉␉␉if (currcoef < mindiv) {␊
324␉␉␉␉␉currcoef = mindiv;␊
325␉␉␉␉}␊
326␉␉␉␉␊
327␉␉␉␉/* Non-integer bus ratio for the max-multi*/␊
328␉␉␉␉maxdiv = (msr >> 46) & 0x01;␊
329␉␉␉␉/* Non-integer bus ratio for the current-multi (undocumented)*/␊
330␉␉␉␉currdiv = (msr >> 14) & 0x01;␊
331␊
332␉␉␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0e) || ␊
333␉␉␉␉␉(p->CPU.Family == 0x0f)) // This will always be model >= 3␊
334␉␉␉␉{␊
335␉␉␉␉␉/* On these models, maxcoef defines TSC freq */␊
336␉␉␉␉␉maxcoef = (msr >> 40) & 0x1f;␊
337␉␉␉␉} ␊
338␉␉␉␉else ␊
339␉␉␉␉{␊
340␉␉␉␉␉/* On lower models, currcoef defines TSC freq */␊
341␉␉␉␉␉/* XXX */␊
342␉␉␉␉␉maxcoef = currcoef;␊
343␉␉␉␉}␊
344␊
345␉␉␉␉if (maxcoef) ␊
346␉␉␉␉{␊
347␉␉␉␉␉if (!fsbFrequency) {␊
348␉␉␉␉␉␉if (maxdiv)␊
349␉␉␉␉␉␉{␊
350␉␉␉␉␉␉␉fsbFrequency = ((tscFrequency * 2) / ((maxcoef * 2) + 1));␊
351␉␉␉␉␉␉}␊
352␉␉␉␉␉␉else ␊
353␉␉␉␉␉␉{␊
354␉␉␉␉␉␉␉fsbFrequency = (tscFrequency / maxcoef);␊
355␉␉␉␉␉␉}␊
356␉␉␉␉␉␉␊
357␉␉␉␉␉}␊
358␉␉␉␉␉␊
359␉␉␉␉␉if (currdiv) ␊
360␉␉␉␉␉{␊
361␉␉␉␉␉␉cpuFrequency = (fsbFrequency * ((currcoef * 2) + 1) / 2);␊
362␉␉␉␉␉}␊
363␉␉␉␉␉else ␊
364␉␉␉␉␉{␊
365␉␉␉␉␉␉cpuFrequency = (fsbFrequency * currcoef);␊
366␉␉␉␉␉}␊
367␉␉␉␉␉DBG("max: %d%s current: %d%s\n", maxcoef, maxdiv ? ".5" : "",currcoef, currdiv ? ".5" : "");␊
368␉␉␉␉}␊
369␉␉␉}␊
370␉␉}␊
371␉␉/* Mobile CPU ? */␊
372//Slice ␊
373␉␉msr = rdmsr64(MSR_IA32_PLATFORM_ID);␊
374␉␉DBG("msr(0x%04x): MSR_IA32_PLATFORM_ID 0x%08x\n", MSR_IA32_PLATFORM_ID, msr & 0xffffffff); //__LINE__ - source line number :)␊
375␉␉if (!scanDMI() && msr) {␊
376␉␉␉p->CPU.Mobile = FALSE;␊
377␉␉␉switch (p->CPU.Model) {␊
378␉␉␉␉case 0x0D:␊
379␉␉␉␉␉p->CPU.Mobile = TRUE; // CPU_FEATURE_MOBILE;␊
380␉␉␉␉␉break;␊
381␉␉␉␉case 0x0F:␊
382␉␉␉␉␉p->CPU.Mobile = FALSE; // CPU_FEATURE_MOBILE;␊
383␉␉␉␉␉break;␊
384␉␉␉␉case 0x02:␊
385␉␉␉␉case 0x03:␊
386␉␉␉␉case 0x04:␊
387␉␉␉␉case 0x06:␉␊
388␉␉␉␉␉p->CPU.Mobile = (rdmsr64(MSR_P4_EBC_FREQUENCY_ID) && (1 << 21));␊
389␉␉␉␉␉break;␊
390␉␉␉␉default:␊
391␉␉␉␉␉p->CPU.Mobile = (rdmsr64(MSR_IA32_PLATFORM_ID) && (1<<28));␊
392␉␉␉␉␉break;␊
393␉␉␉}␊
394␉␉␉if (p->CPU.Mobile) {␊
395␉␉␉␉p->CPU.Features |= CPU_FEATURE_MOBILE;␊
396␉␉␉}␊
397␉␉}␊
398␉␉DBG("CPU is %s\n", p->CPU.Mobile?"Mobile":"Desktop");␊
399␉␉␉␊
400␉}␊
401#if 0␊
402␉else if((p->CPU.Vendor == 0x68747541 /* AMD */) && (p->CPU.Family == 0x0f))␊
403␉{␊
404␉␉if(p->CPU.ExtFamily == 0x00 /* K8 */)␊
405␉␉{␊
406␉␉␉msr = rdmsr64(K8_FIDVID_STATUS);␊
407␉␉␉currcoef = (msr & 0x3f) / 2 + 4;␊
408␉␉␉currdiv = (msr & 0x01) * 2;␊
409␉␉} ␊
410␉␉else if(p->CPU.ExtFamily >= 0x01 /* K10+ */)␊
411␉␉{␊
412␉␉␉msr = rdmsr64(K10_COFVID_STATUS);␊
413␉␉␉if(p->CPU.ExtFamily == 0x01 /* K10 */)␊
414␉␉␉␉currcoef = (msr & 0x3f) + 0x10;␊
415␉␉␉else /* K11+ */␊
416␉␉␉␉currcoef = (msr & 0x3f) + 0x08;␊
417␉␉␉currdiv = (2 << ((msr >> 6) & 0x07));␊
418␉␉}␊
419␊
420␉␉if (currcoef) ␊
421␉␉{␊
422␉␉␉if (currdiv) ␊
423␉␉␉{␊
424␉␉␉␉fsbFrequency = ((tscFrequency * currdiv) / currcoef);␊
425␉␉␉␉DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);␊
426␉␉␉}␊
427␉␉␉else␊
428␉␉␉{␊
429␉␉␉␉fsbFrequency = (tscFrequency / currcoef);␊
430␉␉␉␉DBG("%d\n", currcoef);␊
431␉␉␉}␊
432␉␉␉fsbFrequency = (tscFrequency / currcoef);␊
433␉␉␉cpuFrequency = tscFrequency;␊
434␉␉}␊
435␉}␊
436#endif␊
437␉else if(p->CPU.Vendor == 0x746e6543 && p->CPU.Family == 6)␊
438␉{␊
439␉␉switch (p->CPU.Model) {␊
440␉␉␉case CPU_VIA_NANO:␊
441␉␉␉␉// NOTE: TSC is constant, irrelevent of speed steping ␊
442␉␉␉␉break;␊
443␉␉␉default:␊
444␉␉␉␉break;␊
445␉␉}␊
446␉␉␊
447␉␉msr = rdmsr64(MSR_NANO_FCR2);␊
448␉␉verbose("MSR_IA32_EBL_CR_POWERON Returns 0x%X 0x%X\n", msr >> 32, msr & 0xffffffff);␊
449␉␉␊
450␉␉//msr = msr >> 32;␊
451␉␉msr |= VIA_ALTERNATIVE_VENDOR_BIT;␊
452␉␉//msr = msr << 32;␊
453␉␉␊
454␉␉verbose("MSR_IA32_EBL_CR_POWERON Returns 0x%X 0x%X\n", msr >> 32, msr & 0xffffffff);␊
455␉␉wrmsr64(MSR_NANO_FCR2, msr);␊
456␉␉msr = rdmsr64(MSR_NANO_FCR2);␊
457␉␉verbose("MSR_IA32_EBL_CR_POWERON Returns 0x%X 0x%X\n", msr >> 32, msr & 0xffffffff);␊
458␉␉␊
459␉␉␊
460␉␉/* get cpuid values */␊
461␉␉for( ; i <= 3; i++)␊
462␉␉{␊
463␉␉␉do_cpuid(i, p->CPU.CPUID[i]);␊
464␉␉}␊
465␉␉//int numcpuid_supported = p->CPU.CPUID[CPUID_0][0];␉// max number cpuid call␊
466␉␉//int numextcpuid = p->CPU.CPUID[CPUID_80][0];␊
467␉␉␉␉␉␉␉␉␉␉␉␉␉␉␉//p->CPU.Features = 0;␊
468␉␉␉␉␉␉␉␉␉␉␉␉␉␉␉//␉␉bitfield(p->CPU.CPUID[CPUID_1][1], 0, 0) FEATURE_C␊
469␉␉␊
470␉␉// CPUID_0 -> largest cpuid val in EAX␊
471␉␉// CPUID_0 -> rem = vendor string␊
472␉␉/*␊
473␉␉CPUID_1 EDX:␊
474␉␉ 0 -> FPU␊
475␉␉ 1 -> VME␊
476␉␉ 2 -> DE␊
477␉␉ 3 -> PSE␊
478␉␉ 4 -> TSC␊
479␉␉ 5 -> MSR␊
480␉␉ 6 -> PAE␊
481␉␉ 7 -> MCE␊
482␉␉ 8 -> CX8␊
483␉␉ 9 -> APIC␊
484␉␉ 10 -> Reserved␊
485␉␉ 11 -> Fast Call␊
486␉␉ 12 -> MTTR␊
487␉␉ 13 -> PGE␊
488␉␉ 14 -> MCA␊
489␉␉ 15 -> CMOV␊
490␉␉ 16 -> PAT␊
491␉␉ 17 -> PSE36␊
492␉␉ 18 -> Serial Number ␊
493␉␉ 23 -> MMX␊
494␉␉ 24 -> FXSR␊
495␉␉ 25 -> SSE␊
496␉␉ */␊
497␉␉␊
498␉␉//CPUID_80 -> largest excpuid value in EAX␊
499␉␉//CPUID_81,EAX -> Signature␊
500␉␉//CPUID_80,EDX -> Ext Features␊
501␉␉//CPUID_82 -> CPU String␊
502␉␉//CPUID_83 -> CPU String␊
503␉␉//CPUID_84 -> CPU String␊
504␉␉p->CPU.NoThreads = p->CPU.NoCores;␊
505␉␉␊
506␉}␊
507␉␊
508␉if (!fsbFrequency) {␊
509␉␉fsbFrequency = (DEFAULT_FSB * 1000);␊
510␉␉cpuFrequency = tscFrequency;␊
511␉␉msglog("CPU: fsb=0 ! using the default value 100MHz !\n");␊
512␉}␊
513␉␊
514/*␉␊
515␉p->CPU.Vendor␉␉= p->CPU.CPUID[CPUID_0][1];␊
516␉p->CPU.Signature␉= p->CPU.CPUID[CPUID_1][0];␊
517␉p->CPU.Stepping␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 3, 0);␊
518␉p->CPU.Model␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 7, 4);␊
519␉p->CPU.Family␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 11, 8);␊
520␉p->CPU.ExtModel␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 19, 16);␊
521␉p->CPU.ExtFamily␉= bitfield(p->CPU.CPUID[CPUID_1][0], 27, 20);␊
522␉p->CPU.NoThreads␉= bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␊
523*/␉␊
524␊
525␊
526␉p->CPU.MaxCoef = turbo;␊
527␉p->CPU.MaxDiv = maxdiv;␊
528␉p->CPU.MinCoef = mindiv;␊
529␉p->CPU.CurrCoef = currcoef;␊
530␉p->CPU.CurrDiv = currdiv;␊
531␉p->CPU.TSCFrequency = tscFrequency;␊
532␉p->CPU.FSBFrequency = fsbFrequency;␊
533␉p->CPU.CPUFrequency = cpuFrequency;␊
534␊
535␉DBG("CPU: Vendor/Model/ExtModel: 0x%x/0x%x/0x%x\n", p->CPU.Vendor, p->CPU.Model, p->CPU.ExtModel);␊
536␉DBG("CPU: Family/ExtFamily: 0x%x/0x%x\n", p->CPU.Family, p->CPU.ExtFamily);␊
537␉DBG("CPU: MaxCoef/CurrCoef/Turbo: 0x%x/0x%x\n", p->CPU.MaxCoef, p->CPU.CurrCoef, turbo);␊
538␉DBG("CPU: MaxDiv/CurrDiv: 0x%x/0x%x\n", p->CPU.MaxDiv?2:1, p->CPU.CurrDiv?2:1);␊
539␉DBG("CPU: TSCFreq: %dMHz\n", p->CPU.TSCFrequency / 1000000);␊
540␉DBG("CPU: FSBFreq: %dMHz\n", p->CPU.FSBFrequency / 1000000);␊
541␉DBG("CPU: CPUFreq: %dMHz\n", p->CPU.CPUFrequency / 1000000);␊
542␉DBG("CPU: NoCores/NoThreads: %d/%d\n", p->CPU.NoCores, p->CPU.NoThreads);␊
543␉DBG("CPU: Features: 0x%08x\n", p->CPU.Features);␊
544#if DEBUG_CPU␊
545␉pause();␊
546#endif␊
547}␊
548

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