| 1 | /*␊ |
| 2 | * Copyright (c) 2009 Evan Lojewski. All rights reserved.␊ |
| 3 | */␊ |
| 4 | ␊ |
| 5 | #include "libsaio.h"␊ |
| 6 | #include "boot.h"␊ |
| 7 | #include "bootstruct.h"␊ |
| 8 | #include "pci.h"␊ |
| 9 | #include "hpet.h"␊ |
| 10 | ␊ |
| 11 | #ifndef DEBUG_HPET␊ |
| 12 | #define DEBUG_HPET 0␊ |
| 13 | #endif␊ |
| 14 | ␊ |
| 15 | #if DEBUG_HPET␊ |
| 16 | #define DBG(x...) printf(x)␊ |
| 17 | #else␊ |
| 18 | #define DBG(x...)␊ |
| 19 | #endif␊ |
| 20 | ␊ |
| 21 | void force_enable_hpet_intel(pci_dt_t *lpc_dev);␊ |
| 22 | void force_enable_hpet_via(pci_dt_t *lpc_dev);␊ |
| 23 | ␊ |
| 24 | /*␊ |
| 25 | * Force HPET enabled␊ |
| 26 | *␊ |
| 27 | * VIA fix from http://forum.voodooprojects.org/index.php/topic,1596.0.html␊ |
| 28 | */␊ |
| 29 | ␊ |
| 30 | static struct lpc_controller_t lpc_controllers_intel[] = {␊ |
| 31 | ␉␊ |
| 32 | ␉// Default unknown chipset␊ |
| 33 | ␉{ 0, 0, "" },␊ |
| 34 | ␉␊ |
| 35 | ␉// Intel␊ |
| 36 | ␉{ 0x8086, 0x24dc, "ICH5" },␊ |
| 37 | ␉{ 0x8086, 0x2640, "ICH6" },␊ |
| 38 | ␉{ 0x8086, 0x2641, "ICH6M" },␊ |
| 39 | ␉␊ |
| 40 | ␉{ 0x8086, 0x27b0, "ICH7 DH" },␊ |
| 41 | ␉{ 0x8086, 0x27b8, "ICH7" },␊ |
| 42 | ␉{ 0x8086, 0x27b9, "ICH7M" },␊ |
| 43 | ␉{ 0x8086, 0x27bd, "ICH7M DH" },␊ |
| 44 | ␊ |
| 45 | ␉{ 0x8086, 0x27bc, "NM10" },␊ |
| 46 | ␊ |
| 47 | ␉{ 0x8086, 0x2810, "ICH8R" },␊ |
| 48 | ␉{ 0x8086, 0x2811, "ICH8M-E" },␊ |
| 49 | ␉{ 0x8086, 0x2812, "ICH8DH" },␊ |
| 50 | ␉{ 0x8086, 0x2814, "ICH8DO" },␊ |
| 51 | ␉{ 0x8086, 0x2815, "ICH8M" },␊ |
| 52 | ␉␊ |
| 53 | ␉{ 0x8086, 0x2912, "ICH9DH" },␊ |
| 54 | ␉{ 0x8086, 0x2914, "ICH9DO" },␊ |
| 55 | ␉{ 0x8086, 0x2916, "ICH9R" },␊ |
| 56 | ␉{ 0x8086, 0x2917, "ICH9M-E" },␊ |
| 57 | ␉{ 0x8086, 0x2918, "ICH9" },␊ |
| 58 | ␉{ 0x8086, 0x2919, "ICH9M" },␊ |
| 59 | ␉␊ |
| 60 | ␉{ 0x8086, 0x3a14, "ICH10DO" },␊ |
| 61 | ␉{ 0x8086, 0x3a16, "ICH10R" },␊ |
| 62 | ␉{ 0x8086, 0x3a18, "ICH10" },␊ |
| 63 | ␉{ 0x8086, 0x3a1a, "ICH10D" },␊ |
| 64 | };␊ |
| 65 | ␊ |
| 66 | static struct lpc_controller_t lpc_controllers_via[] = {␊ |
| 67 | ␉// Default unknown chipset␊ |
| 68 | ␉{ 0, 0, "" },␊ |
| 69 | ␉␊ |
| 70 | ␉{ 0x1106, 0x3372, "VT8237S" },␊ |
| 71 | };␊ |
| 72 | ␊ |
| 73 | ␊ |
| 74 | void force_enable_hpet(pci_dt_t *lpc_dev)␊ |
| 75 | {␊ |
| 76 | ␉switch(lpc_dev->vendor_id)␊ |
| 77 | ␉{␊ |
| 78 | ␉␉case 0x8086:␊ |
| 79 | ␉␉␉force_enable_hpet_intel(lpc_dev);␊ |
| 80 | ␉␉␉break;␊ |
| 81 | ␉␉␉␊ |
| 82 | ␉␉case 0x1106:␊ |
| 83 | ␉␉␉force_enable_hpet_via(lpc_dev);␊ |
| 84 | ␉␉␉break;␊ |
| 85 | ␉}␊ |
| 86 | ␉␊ |
| 87 | ␉␊ |
| 88 | #if DEBUG_HPET␊ |
| 89 | ␉printf("Press [Enter] to continue...\n");␊ |
| 90 | ␉getc();␊ |
| 91 | #endif␊ |
| 92 | }␊ |
| 93 | ␊ |
| 94 | void force_enable_hpet_via(pci_dt_t *lpc_dev)␊ |
| 95 | {␊ |
| 96 | ␉uint32_t␉val, hpet_address = 0xFED00000;␊ |
| 97 | ␉int i;␊ |
| 98 | ␉␊ |
| 99 | ␉for(i = 1; i < sizeof(lpc_controllers_via) / sizeof(lpc_controllers_via[0]); i++)␊ |
| 100 | ␉{␊ |
| 101 | ␉␉if (␉(lpc_controllers_via[i].vendor == lpc_dev->vendor_id) ␊ |
| 102 | ␉␉␉&& (lpc_controllers_via[i].device == lpc_dev->device_id))␊ |
| 103 | ␉␉{␉␊ |
| 104 | ␉␉␉val = pci_config_read32(lpc_dev->dev.addr, 0x68);␊ |
| 105 | ␉␉␉␊ |
| 106 | ␉␉␉DBG("VIA %s LPC Interface [%04x:%04x], MMIO\n", ␊ |
| 107 | ␉␉␉␉lpc_controllers_via[i].name, lpc_dev->vendor_id, lpc_dev->device_id);␊ |
| 108 | ␉␉␉␊ |
| 109 | ␉␉␉if (val & 0x80) {␊ |
| 110 | ␉␉␉␉hpet_address = (val & ~0x3ff);␊ |
| 111 | ␉␉␉␉DBG("HPET at 0x%lx\n", hpet_address);␊ |
| 112 | ␉␉␉}␊ |
| 113 | ␉␉␉else ␊ |
| 114 | ␉␉␉{␊ |
| 115 | ␉␉␉␉val = 0xfed00000 | 0x80;␊ |
| 116 | ␉␉␉␉pci_config_write32(lpc_dev->dev.addr, 0x68, val);␊ |
| 117 | ␉␉␉␉val = pci_config_read32(lpc_dev->dev.addr, 0x68);␊ |
| 118 | ␉␉␉␉if (val & 0x80) {␊ |
| 119 | ␉␉␉␉␉hpet_address = (val & ~0x3ff);␊ |
| 120 | ␉␉␉␉␉DBG("Force enabled HPET at 0x%lx\n", hpet_address);␊ |
| 121 | ␉␉␉␉}␊ |
| 122 | ␉␉␉␉else {␊ |
| 123 | ␉␉␉␉␉DBG("Unable to enable HPET");␊ |
| 124 | ␉␉␉␉}␊ |
| 125 | ␉␉␉}␊ |
| 126 | ␉␉}␊ |
| 127 | ␉}␊ |
| 128 | }␊ |
| 129 | ␊ |
| 130 | ␊ |
| 131 | ␊ |
| 132 | void force_enable_hpet_intel(pci_dt_t *lpc_dev)␊ |
| 133 | {␊ |
| 134 | ␉uint32_t␉val, hpet_address = 0xFED00000;␊ |
| 135 | ␉int i;␊ |
| 136 | ␉void␉␉*rcba;␊ |
| 137 | ␉␊ |
| 138 | ␉/* LPC on Intel ICH is always (?) at 00:1f.0 */␊ |
| 139 | ␉for(i = 1; i < sizeof(lpc_controllers_intel) / sizeof(lpc_controllers_intel[0]); i++)␊ |
| 140 | ␉{␊ |
| 141 | ␉␉if (␉(lpc_controllers_intel[i].vendor == lpc_dev->vendor_id) ␊ |
| 142 | ␉␉␉&& (lpc_controllers_intel[i].device == lpc_dev->device_id))␊ |
| 143 | ␉␉{␉␊ |
| 144 | ␉␉␉␊ |
| 145 | ␉␉␉rcba = (void *)(pci_config_read32(lpc_dev->dev.addr, 0xF0) & 0xFFFFC000);␊ |
| 146 | ␉␉␉␊ |
| 147 | ␉␉␉DBG("Intel(R) %s LPC Interface [%04x:%04x], MMIO @ 0x%lx\n", ␊ |
| 148 | ␉␉␉␉lpc_controllers_intel[i].name, lpc_dev->vendor_id, lpc_dev->device_id, rcba);␊ |
| 149 | ␉␉␉␊ |
| 150 | ␉␉␉if (rcba == 0)␊ |
| 151 | ␉␉␉␉printf(" RCBA disabled; cannot force enable HPET\n");␊ |
| 152 | ␉␉␉else␊ |
| 153 | ␉␉␉{␊ |
| 154 | ␉␉␉␉val = REG32(rcba, 0x3404);␊ |
| 155 | ␉␉␉␉if (val & 0x80)␊ |
| 156 | ␉␉␉␉{␊ |
| 157 | ␉␉␉␉␉// HPET is enabled in HPTC. Just not reported by BIOS␊ |
| 158 | ␉␉␉␉␉DBG(" HPET is enabled in HPTC, just not reported by BIOS\n");␊ |
| 159 | ␉␉␉␉␉hpet_address |= (val & 3) << 12 ;␊ |
| 160 | ␉␉␉␉␉DBG(" HPET MMIO @ 0x%lx\n", hpet_address);␊ |
| 161 | ␉␉␉␉}␊ |
| 162 | ␉␉␉␉else␊ |
| 163 | ␉␉␉␉{␊ |
| 164 | ␉␉␉␉␉// HPET disabled in HPTC. Trying to enable␊ |
| 165 | ␉␉␉␉␉DBG(" HPET is disabled in HPTC, trying to enable\n");␉␉␉␉␉␉␉␉␉␊ |
| 166 | ␉␉␉␉␉REG32(rcba, 0x3404) = val | 0x80;␊ |
| 167 | ␉␉␉␉␉hpet_address |= (val & 3) << 12 ;␊ |
| 168 | ␉␉␉␉␉DBG(" Force enabled HPET, MMIO @ 0x%lx\n", hpet_address);␊ |
| 169 | ␉␉␉␉}␊ |
| 170 | ␉␉␉␉␊ |
| 171 | ␉␉␉␉// verify if the job is done␊ |
| 172 | ␉␉␉␉val = REG32(rcba, 0x3404);␊ |
| 173 | ␉␉␉␉if (!(val & 0x80))␊ |
| 174 | ␉␉␉␉␉printf(" Failed to force enable HPET\n");␊ |
| 175 | ␉␉␉}␊ |
| 176 | ␉␉␉break;␊ |
| 177 | ␉␉}␊ |
| 178 | ␉}␊ |
| 179 | }␊ |
| 180 | |
