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Root/branches/meklort/i386/modules/Resolution/915resolution.c

Source at commit 734 created 13 years 2 months ago.
By meklort, Typo fixes, gma hack, nvidia dev id, more work needed for nvidia
1/*␊
2 * resolution.h␊
3 * ␊
4 *␉NOTE: I don't beleive this code is production ready / should be in trunk␊
5 * Atleast, not in it's current state. ␊
6 *␊
7 * Created by Evan Lojewski on 3/4/10.␊
8 * Copyright 2009. All rights reserved.␊
9 *␊
10 */␊
11#ifndef _RESOLUTION_H_␊
12#define _RESOLUTION_H_␊
13␊
14#include "libsaio.h"␊
15#include "edid.h"␊
16#include "915resolution.h"␊
17␊
18␊
19void patchVideoBios()␊
20{␉␉␊
21␉UInt32 x = 0, y = 0, bp = 0;␊
22␉␊
23␉getResolution(&x, &y, &bp);␊
24␉␊
25␉␊
26␉if (x != 0 &&␊
27␉␉y != 0 && ␊
28␉␉bp != 0)␊
29␉{␊
30␉␉vbios_map * map;␊
31␉␉␊
32␉␉map = open_vbios(CT_UNKNOWN);␊
33␉␉if(map)␊
34␉␉{␊
35␉␉␉unlock_vbios(map);␊
36␉␉␉␊
37␉␉␉set_mode(map, x, y, bp, 0, 0);␊
38␉␉␉␊
39␉␉␉relock_vbios(map);␊
40␉␉␉␊
41␉␉␉close_vbios(map);␊
42␉␉}␊
43␉}␉␉␊
44␉␊
45}␊
46␊
47␊
48/* Copied from 915 resolution created by steve tomljenovic␊
49 *␊
50 * This code is based on the techniques used in :␊
51 *␊
52 * - 855patch. Many thanks to Christian Zietz (czietz gmx net)␊
53 * for demonstrating how to shadow the VBIOS into system RAM␊
54 * and then modify it.␊
55 *␊
56 * - 1280patch by Andrew Tipton (andrewtipton null li).␊
57 *␊
58 * - 855resolution by Alain Poirier␊
59 *␊
60 * This source code is into the public domain.␊
61 */␊
62␊
63/**␊
64 **␊
65 **/␊
66␊
67#define CONFIG_MECH_ONE_ADDR␉0xCF8␊
68#define CONFIG_MECH_ONE_DATA␉0xCFC␊
69␊
70int freqs[] = { 60, 75, 85 };␊
71␊
72UInt32 get_chipset_id(void)␊
73{␊
74␉outl(CONFIG_MECH_ONE_ADDR, 0x80000000);␊
75␉return inl(CONFIG_MECH_ONE_DATA);␊
76}␊
77␊
78chipset_type get_chipset(UInt32 id)␊
79{␊
80␉chipset_type type;␊
81␉␉␊
82␉switch (id) {␊
83␉␉case 0x35758086:␊
84␉␉␉type = CT_830;␊
85␉␉␉break;␊
86␉␉␉␊
87␉␉case 0x25608086:␊
88␉␉␉type = CT_845G;␊
89␉␉␉break;␊
90␉␉␉␊
91␉␉case 0x35808086:␊
92␉␉␉type = CT_855GM;␊
93␉␉␉break;␊
94␉␉␉␊
95␉␉case 0x25708086:␊
96␉␉␉type = CT_865G;␊
97␉␉␉break;␊
98␉␉␉␊
99␉␉case 0x25808086:␊
100␉␉␉type = CT_915G;␊
101␉␉␉break;␊
102␉␉␉␊
103␉␉case 0x25908086:␊
104␉␉␉type = CT_915GM;␊
105␉␉␉break;␊
106␉␉␉␊
107␉␉case 0x27708086:␊
108␉␉␉type = CT_945G;␊
109␉␉␉break;␊
110␉␉␉␊
111␉␉case 0x27a08086:␊
112␉␉␉type = CT_945GM;␊
113␉␉␉break;␊
114␉␉␉␊
115␉␉case 0x27ac8086:␊
116␉␉␉type = CT_945GME;␊
117␉␉␉break;␊
118␉␉␉␊
119␉␉case 0x29708086:␊
120␉␉␉type = CT_946GZ;␊
121␉␉␉break;␊
122␉␉␉␊
123␉␉case 0x27748086:␊
124␉␉␉type = CT_955X;␊
125␉␉␉break;␊
126␉␉␉␊
127␉␉case 0x277c8086:␊
128␉␉␉type = CT_975X;␊
129␉␉␉break;␊
130␊
131␉␉case 0x29a08086:␊
132␉␉␉type = CT_G965;␊
133␉␉␉break;␊
134␉␉␉␊
135␉␉case 0x29908086:␊
136␉␉␉type = CT_Q965;␊
137␉␉␉break;␊
138␉␉␉␊
139␉␉case 0x81008086:␊
140␉␉␉type = CT_500;␊
141␉␉␉break;␊
142␉␉␉␊
143␉␉case 0x2e108086:␊
144␉␉case 0X2e908086:␊
145␉␉␉type = CT_B43;␊
146␉␉␉break;␊
147␊
148␉␉case 0x2e208086:␊
149␉␉␉type = CT_P45;␊
150␉␉␉break;␊
151␊
152␉␉case 0x2e308086:␊
153␉␉␉type = CT_G41;␊
154␉␉␉break;␊
155␉␉␉␉␉␊
156␉␉case 0x29c08086:␊
157␉␉␉type = CT_G31;␊
158␉␉␉break;␊
159␉␉␉␊
160␉␉case 0x29208086:␊
161␉␉␉type = CT_G45;␊
162␉␉␉break;␊
163␉␉␉␊
164␉␉case 0xA0108086:␉// mobile␊
165␉␉case 0xA0008086:␉// desktop␊
166␉␉␉type = CT_3150;␊
167␉␉␉break;␊
168␉␉␉␊
169␉␉case 0x2a008086:␊
170␉␉␉type = CT_965GM;␊
171␉␉␉break;␊
172␉␉␉␊
173␉␉case 0x29e08086:␊
174␉␉␉type = CT_X48;␊
175␉␉␉break;␉␉␉␊
176␉␉␉␉␊
177␉␉case 0x2a408086:␊
178␉␉␉type = CT_GM45;␊
179␉␉␉break;␊
180␉␉␉␊
181␉␉␉␊
182␉␉default:␊
183␉␉␉if((id & 0x0000FFFF) == 0x00008086) // Intel chipset␊
184␉␉␉{␊
185␉␉␉␉//printf("Unknown chipset 0x%llX, please email id to meklort@gmail.com", id);␊
186␉␉␉␉//getc();␊
187␉␉␉␉type = CT_UNKNOWN_INTEL;␊
188␉␉␉␉//type = CT_UNKNOWN;␊
189␊
190␉␉␉}␊
191␉␉␉else␊
192␉␉␉{␊
193␉␉␉␉type = CT_UNKNOWN;␊
194␉␉␉}␊
195␉␉␉break;␊
196␉}␊
197␉return type;␊
198}␊
199␊
200vbios_resolution_type1 * map_type1_resolution(vbios_map * map, UInt16 res)␊
201{␊
202␉vbios_resolution_type1 * ptr = ((vbios_resolution_type1*)(map->bios_ptr + res)); ␊
203␉return ptr;␊
204}␊
205␊
206vbios_resolution_type2 * map_type2_resolution(vbios_map * map, UInt16 res)␊
207{␊
208␉vbios_resolution_type2 * ptr = ((vbios_resolution_type2*)(map->bios_ptr + res)); ␊
209␉return ptr;␊
210}␊
211␊
212vbios_resolution_type3 * map_type3_resolution(vbios_map * map, UInt16 res)␊
213{␊
214␉vbios_resolution_type3 * ptr = ((vbios_resolution_type3*)(map->bios_ptr + res)); ␊
215␉return ptr;␊
216}␊
217␊
218char detect_bios_type(vbios_map * map, char modeline, int entry_size)␊
219{␊
220␉UInt32 i;␊
221␉UInt16 r1, r2;␊
222␉␊
223␉r1 = r2 = 32000;␊
224␉␊
225␉for (i=0; i < map->mode_table_size; i++)␊
226␉{␊
227␉␉if (map->mode_table[i].resolution <= r1)␊
228␉␉{␊
229␉␉␉r1 = map->mode_table[i].resolution;␊
230␉␉}␊
231␉␉else␊
232␉␉{␊
233␉␉␉if (map->mode_table[i].resolution <= r2)␊
234␉␉␉{␊
235␉␉␉␉r2 = map->mode_table[i].resolution;␊
236␉␉␉}␊
237␉␉}␊
238␉␉␊
239␉␉/*printf("r1 = %d r2 = %d\n", r1, r2);*/␊
240␉}␊
241␉␊
242␉return (r2-r1-6) % entry_size == 0;␊
243}␊
244␊
245void close_vbios(vbios_map * map);␊
246␊
247char detect_ati_bios_type(vbios_map * map)␊
248{␉␊
249␉return map->mode_table_size % sizeof(ATOM_MODE_TIMING) == 0;␊
250}␊
251␊
252␊
253vbios_map * open_vbios(chipset_type forced_chipset)␊
254{␊
255␉UInt32 z;␊
256␉vbios_map * map = malloc(sizeof(vbios_map));␊
257␉for(z=0; z<sizeof(vbios_map); z++) ((char*)map)[z]=0;␊
258␉/*␊
259␉ * Determine chipset␊
260␉ */␊
261␉␊
262␉if (forced_chipset == CT_UNKNOWN)␊
263␉{␊
264␉␉map->chipset_id = get_chipset_id();␊
265␉␉map->chipset = get_chipset(map->chipset_id);␊
266␉}␊
267␉else if (forced_chipset != CT_UNKNOWN)␊
268␉{␊
269␉␉map->chipset = forced_chipset;␊
270␉}␊
271␉␊
272␉␊
273␉if (map->chipset == CT_UNKNOWN)␊
274␉{␊
275␉␉//verbose("Unknown chipset type.\n");␊
276␉␉//verbose("915resolution only works with Intel 800/900 series graphic chipsets.\n");␊
277␉␉//verbose("Chipset Id: %x\n", map->chipset_id);␊
278␉␉close_vbios(map);␊
279␉␉return 0;␊
280␉}␊
281␉␊
282␉␊
283␉/*␊
284␉ * Map the video bios to memory␊
285␉ */␊
286␉map->bios_ptr=(char*)VBIOS_START;␊
287␉␊
288␉/*␊
289␉ * check if we have ATI Radeon␊
290␉ */␊
291␉map->ati_tables.base = map->bios_ptr;␊
292␉map->ati_tables.AtomRomHeader = (ATOM_ROM_HEADER *) (map->bios_ptr + *(unsigned short *) (map->bios_ptr + OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER)); ␊
293␉if (strcmp ((char *) map->ati_tables.AtomRomHeader->uaFirmWareSignature, "ATOM") == 0)␊
294␉{␊
295␉␉// ATI Radeon Card␊
296␉␉map->bios = BT_ATI_1;␊
297␉␉␊
298␉␉map->ati_tables.MasterDataTables = (unsigned short *) &((ATOM_MASTER_DATA_TABLE *) (map->bios_ptr + map->ati_tables.AtomRomHeader->usMasterDataTableOffset))->ListOfDataTables;␊
299␉␉unsigned short std_vesa_offset = (unsigned short) ((ATOM_MASTER_LIST_OF_DATA_TABLES *)map->ati_tables.MasterDataTables)->StandardVESA_Timing;␊
300␉␉ATOM_STANDARD_VESA_TIMING * std_vesa = (ATOM_STANDARD_VESA_TIMING *) (map->bios_ptr + std_vesa_offset);␊
301␉␉␊
302␉␉map->ati_mode_table = (char *) &std_vesa->aModeTimings;␊
303␉␉if (map->ati_mode_table == 0)␊
304␉␉{␊
305␉␉␉printf("Unable to locate the mode table.\n");␊
306␉␉␉printf("Please run the program 'dump_bios' as root and\n");␊
307␉␉␉printf("email the file 'vbios.dmp' to stomljen@yahoo.com.\n");␊
308␉␉␉printf("Chipset: %d\n", map->chipset);␊
309␉␉␉close_vbios(map);␊
310␉␉␉return 0;␊
311␉␉}␊
312␉␉map->mode_table_size = std_vesa->sHeader.usStructureSize - sizeof(ATOM_COMMON_TABLE_HEADER);␊
313␉␉␊
314␉␉if (!detect_ati_bios_type(map)) map->bios = BT_ATI_2;␊
315␉␉␊
316␉}␊
317␉else {␊
318␉␉␊
319␉␉/*␊
320␉␉ * check if we have NVIDIA␊
321␉␉ */␊
322␊
323␉␉int i = 0;␊
324␉␉while (i < 512)␊
325␉␉{ // we don't need to look through the whole bios, just the firs 512 bytes␊
326␉␉␉if ((␉map->bios_ptr[i] == 'N') ␊
327␉␉␉␉&& (map->bios_ptr[i+1] == 'V') ␊
328␉␉␉␉&& (map->bios_ptr[i+2] == 'I') ␊
329␉␉␉␉&& (map->bios_ptr[i+3] == 'D')) ␊
330␉␉␉{␊
331␉␉␉␉map->bios = BT_NVDA;␊
332␉␉␉␉unsigned short nv_data_table_offset = 0;␊
333␉␉␉␉unsigned short * nv_data_table;␊
334␉␉␉␉NV_VESA_TABLE * std_vesa;␊
335␉␉␉␉␊
336␉␉␉␉int i = 0;␊
337␉␉␉␉␊
338␉␉␉␉while (i < 0x300)␊
339␉␉␉␉{ //We don't need to look for the table in the whole bios, the 768 first bytes only␊
340␉␉␉␉␉if ((␉map->bios_ptr[i] == 0x44) ␊
341␉␉␉␉␉␉&& (map->bios_ptr[i+1] == 0x01) ␊
342␉␉␉␉␉␉&& (map->bios_ptr[i+2] == 0x04) ␊
343␉␉␉␉␉␉&& (map->bios_ptr[i+3] == 0x00))␊
344␉␉␉␉␉{␊
345␉␉␉␉␉␉nv_data_table_offset = (unsigned short) (map->bios_ptr[i+4] | (map->bios_ptr[i+5] << 8));␊
346␉␉␉␉␉␉break;␊
347␉␉␉␉␉}␊
348␉␉␉␉␉i++;␊
349␉␉␉␉}␊
350␉␉␉␉␊
351␉␉␉␉nv_data_table = (unsigned short *) (map->bios_ptr + (nv_data_table_offset + OFFSET_TO_VESA_TABLE_INDEX));␊
352␉␉␉␉std_vesa = (NV_VESA_TABLE *) (map->bios_ptr + *nv_data_table);␊
353␉␉␉␉␊
354␉␉␉␉map->nv_mode_table = (char *) std_vesa->sModelines;␊
355␉␉␉␉if (map->nv_mode_table == 0)␊
356␉␉␉␉{␊
357␉␉␉␉␉printf("Unable to locate the mode table.\n");␊
358␉␉␉␉␉printf("Please run the program 'dump_bios' as root and\n");␊
359␉␉␉␉␉printf("email the file 'vbios.dmp' to stomljen@yahoo.com.\n");␊
360␉␉␉␉␉printf("Chipset: %s\n", map->chipset);␊
361␉␉␉␉␉close_vbios(map);␊
362␉␉␉␉␉return 0;␊
363␉␉␉␉}␊
364␉␉␉␉map->mode_table_size = std_vesa->sHeader.usTable_Size;␊
365␉␉␉␉␊
366␉␉␉␉break;␊
367␉␉␉}␊
368␉␉␉i++;␊
369␉␉}␊
370␉}␊
371␉␊
372␉␊
373␉/*␊
374␉ * check if we have Intel␊
375␉ */␊
376␉␊
377␉/*if (map->chipset == CT_UNKNOWN && memmem(map->bios_ptr, VBIOS_SIZE, INTEL_SIGNATURE, strlen(INTEL_SIGNATURE))) {␊
378␉ printf( "Intel chipset detected. However, 915resolution was unable to determine the chipset type.\n");␊
379␉ ␊
380␉ printf("Chipset Id: %x\n", map->chipset_id);␊
381␉ ␊
382␉ printf("Please report this problem to stomljen@yahoo.com\n");␊
383␉ ␊
384␉ close_vbios(map);␊
385␉ return 0;␊
386␉ }*/␊
387␉␊
388␉/*␊
389␉ * check for others␊
390␉ */␊
391␉␊
392␊
393␉␊
394␉/*␊
395␉ * Figure out where the mode table is ␊
396␉ */␊
397␉if ((map->bios != BT_ATI_1) && (map->bios != BT_NVDA)) ␊
398␉{␊
399␉␉char* p = map->bios_ptr + 16;␊
400␉␉char* limit = map->bios_ptr + VBIOS_SIZE - (3 * sizeof(vbios_mode));␊
401␉␉␊
402␉␉while (p < limit && map->mode_table == 0)␊
403␉␉{␊
404␉␉␉vbios_mode * mode_ptr = (vbios_mode *) p;␊
405␉␉␉␊
406␉␉␉if (((mode_ptr[0].mode & 0xf0) == 0x30) && ((mode_ptr[1].mode & 0xf0) == 0x30) &&␊
407␉␉␉␉((mode_ptr[2].mode & 0xf0) == 0x30) && ((mode_ptr[3].mode & 0xf0) == 0x30))␊
408␉␉␉{␊
409␉␉␉␉map->mode_table = mode_ptr;␊
410␉␉␉}␊
411␉␉␉␊
412␉␉␉p++;␊
413␉␉}␊
414␉␉␊
415␉␉if (map->mode_table == 0) ␊
416␉␉{␊
417␉␉␉close_vbios(map);␊
418␉␉␉return 0;␊
419␉␉}␊
420␉}␊
421␉␊
422␉␊
423␉/*␊
424␉ * Determine size of mode table␊
425␉ */␊
426␉if ((map->bios != BT_ATI_1) && (map->bios != BT_ATI_2) && (map->bios != BT_NVDA))␊
427␉{␊
428␉␉vbios_mode * mode_ptr = map->mode_table;␊
429␉␉␊
430␉␉while (mode_ptr->mode != 0xff)␊
431␉␉{␊
432␉␉␉map->mode_table_size++;␊
433␉␉␉mode_ptr++;␊
434␉␉}␊
435␉}␊
436␉␊
437␉/*␊
438␉ * Figure out what type of bios we have␊
439␉ * order of detection is important␊
440␉ */␊
441␉if ((map->bios != BT_ATI_1) && (map->bios != BT_ATI_2) && (map->bios != BT_NVDA))␊
442␉{␊
443␉␉if (detect_bios_type(map, TRUE, sizeof(vbios_modeline_type3)))␊
444␉␉{␊
445␉␉␉map->bios = BT_3;␊
446␉␉}␊
447␉␉else if (detect_bios_type(map, TRUE, sizeof(vbios_modeline_type2)))␊
448␉␉{␊
449␉␉␉map->bios = BT_2;␊
450␉␉}␊
451␉␉else if (detect_bios_type(map, FALSE, sizeof(vbios_resolution_type1)))␊
452␉␉{␊
453␉␉␉map->bios = BT_1;␊
454␉␉}␊
455␉␉else {␊
456␉␉␉return 0;␊
457␉␉}␊
458␉}␊
459␉␊
460␉return map;␊
461}␊
462␊
463void close_vbios(vbios_map * map)␊
464{␊
465␉free(map);␊
466}␊
467␊
468void unlock_vbios(vbios_map * map)␊
469{␊
470␉␊
471␉map->unlocked = TRUE;␊
472␊
473␉switch (map->chipset) {␊
474␉␉case CT_UNKNOWN:␊
475␉␉␉break;␊
476␉␉case CT_830:␊
477␉␉case CT_855GM:␊
478␉␉␉outl(CONFIG_MECH_ONE_ADDR, 0x8000005a);␊
479␉␉␉map->b1 = inb(CONFIG_MECH_ONE_DATA + 2);␊
480␉␉␉␊
481␉␉␉outl(CONFIG_MECH_ONE_ADDR, 0x8000005a);␊
482␉␉␉outb(CONFIG_MECH_ONE_DATA + 2, 0x33);␊
483␉␉␉break;␊
484␉␉case CT_845G:␊
485␉␉case CT_865G:␊
486␉␉case CT_915G:␊
487␉␉case CT_915GM:␊
488␉␉case CT_945G:␊
489␉␉case CT_945GM:␊
490␉␉case CT_945GME:␊
491␉␉case CT_946GZ:␊
492␉␉case CT_G965:␊
493␉␉case CT_Q965:␊
494␉␉case CT_965GM:␊
495␉␉case CT_975X:␊
496␉␉case CT_P35:␊
497␉␉case CT_955X:␊
498␉␉case CT_X48:␊
499␉␉case CT_B43:␊
500␉␉case CT_Q45:␊
501␉␉case CT_P45:␊
502␉␉case CT_GM45:␊
503␉␉case CT_G45:␊
504␉␉case CT_G41:␊
505␉␉case CT_G31:␊
506␉␉case CT_500:␊
507␉␉case CT_3150:␊
508␉␉case CT_UNKNOWN_INTEL:␉// Assume newer intel chipset is the same as before␊
509␉␉␉outl(CONFIG_MECH_ONE_ADDR, 0x80000090);␊
510␉␉␉map->b1 = inb(CONFIG_MECH_ONE_DATA + 1);␊
511␉␉␉map->b2 = inb(CONFIG_MECH_ONE_DATA + 2);␊
512␉␉␉outl(CONFIG_MECH_ONE_ADDR, 0x80000090);␊
513␉␉␉outb(CONFIG_MECH_ONE_DATA + 1, 0x33);␊
514␉␉␉outb(CONFIG_MECH_ONE_DATA + 2, 0x33);␊
515␉␉␉break;␊
516␉}␊
517␉␊
518#if DEBUG␊
519␉{␊
520␉␉UInt32 t = inl(CONFIG_MECH_ONE_DATA);␊
521␉␉verbose("unlock PAM: (0x%08x)\n", t);␊
522␉}␊
523#endif␊
524}␊
525␊
526void relock_vbios(vbios_map * map)␊
527{␊
528␉␊
529␉map->unlocked = FALSE;␊
530␉␊
531␉switch (map->chipset)␊
532␉{␊
533␉␉case CT_UNKNOWN:␊
534␉␉␉break;␊
535␉␉case CT_830:␊
536␉␉case CT_855GM:␊
537␉␉␉outl(CONFIG_MECH_ONE_ADDR, 0x8000005a);␊
538␉␉␉outb(CONFIG_MECH_ONE_DATA + 2, map->b1);␊
539␉␉␉break;␊
540␉␉case CT_845G:␊
541␉␉case CT_865G:␊
542␉␉case CT_915G:␊
543␉␉case CT_915GM:␊
544␉␉case CT_945G:␊
545␉␉case CT_945GM:␊
546␉␉case CT_945GME:␊
547␉␉case CT_946GZ:␊
548␉␉case CT_G965:␊
549␉␉case CT_955X:␊
550␉␉case CT_G45:␊
551␉␉case CT_Q965:␊
552␉␉case CT_965GM:␊
553␉␉case CT_975X:␊
554␉␉case CT_P35:␊
555␉␉case CT_X48:␊
556␉␉case CT_B43:␊
557␉␉case CT_Q45:␊
558␉␉case CT_P45:␊
559␉␉case CT_GM45:␊
560␉␉case CT_G41:␊
561␉␉case CT_G31:␊
562␉␉case CT_500:␊
563␉␉case CT_3150:␊
564␉␉case CT_UNKNOWN_INTEL:␊
565␉␉␉outl(CONFIG_MECH_ONE_ADDR, 0x80000090);␊
566␉␉␉outb(CONFIG_MECH_ONE_DATA + 1, map->b1);␊
567␉␉␉outb(CONFIG_MECH_ONE_DATA + 2, map->b2);␊
568␉␉␉break;␊
569␉}␊
570␉␊
571#if DEBUG␊
572␉{␊
573 UInt32 t = inl(CONFIG_MECH_ONE_DATA);␊
574␉␉verbose("relock PAM: (0x%08x)\n", t);␊
575␉}␊
576#endif␊
577}␊
578␊
579␊
580int getMode(edid_mode *mode)␊
581{␊
582␉char* edidInfo = readEDID();␊
583␉␉␉␊
584␉if(!edidInfo) return 1;␊
585␉␉␊
586␉mode->pixel_clock = (edidInfo[55] << 8) | edidInfo[54];␊
587␉mode->h_active = edidInfo[56] | ((edidInfo[58] & 0xF0) << 4);␊
588␉mode->h_blanking = ((edidInfo[58] & 0x0F) << 8) | edidInfo[57];␊
589␉mode->v_active = edidInfo[59] | ((edidInfo[61] & 0xF0) << 4);␊
590␉mode->v_blanking = ((edidInfo[61] & 0x0F) << 8) | edidInfo[60];␊
591␉mode->h_sync_offset = ((edidInfo[65] & 0xC0) >> 2) | edidInfo[62];␊
592␉mode->h_sync_width = (edidInfo[65] & 0x30) | edidInfo[63];␊
593␉mode->v_sync_offset = (edidInfo[65] & 0x0C) | ((edidInfo[64] & 0x0C) >> 2);␊
594␉mode->v_sync_width = ((edidInfo[65] & 0x3) << 2) | (edidInfo[64] & 0x03);␊
595␉␉␊
596␉␉␊
597␉free( edidInfo );␊
598␉␉␊
599␉if(!mode->h_active) return 1;␊
600␉␊
601␉return 0;␊
602␉␉␊
603}␊
604␊
605␊
606static void gtf_timings(UInt32 x, UInt32 y, UInt32 freq,␊
607␉␉␉␉␉␉unsigned long *clock,␊
608␉␉␉␉␉␉UInt16 *hsyncstart, UInt16 *hsyncend, UInt16 *hblank,␊
609␉␉␉␉␉␉UInt16 *vsyncstart, UInt16 *vsyncend, UInt16 *vblank)␊
610{␊
611␉UInt32 hbl, vbl, vfreq;␊
612␉␊
613␉vbl = y + (y+1)/(20000.0/(11*freq) - 1) + 1.5;␊
614␉vfreq = vbl * freq;␊
615␉hbl = 16 * (int)(x * (30.0 - 300000.0 / vfreq) /␊
616␉␉␉␉␉ + (70.0 + 300000.0 / vfreq) / 16.0 + 0.5);␊
617␉␊
618␉*vsyncstart = y;␊
619␉*vsyncend = y + 3;␊
620␉*vblank = vbl - 1;␊
621␉*hsyncstart = x + hbl / 2 - (x + hbl + 50) / 100 * 8 - 1;␊
622␉*hsyncend = x + hbl / 2 - 1;␊
623␉*hblank = x + hbl - 1;␊
624␉*clock = (x + hbl) * vfreq / 1000;␊
625}␊
626␊
627void set_mode(vbios_map * map, /*UInt32 mode,*/ UInt32 x, UInt32 y, UInt32 bp, UInt32 htotal, UInt32 vtotal) {␊
628␉UInt32 xprev, yprev;␊
629␉UInt32 i = 0, j;␊
630␉// patch first available mode␊
631␉␊
632␉//␉for (i=0; i < map->mode_table_size; i++) {␊
633␉//␉␉if (map->mode_table[0].mode == mode) {␊
634␉switch(map->bios) {␊
635␉␉case BT_1:␊
636␉␉{␊
637␉␉␉vbios_resolution_type1 * res = map_type1_resolution(map, map->mode_table[i].resolution);␊
638␉␉␉␊
639␉␉␉if (bp) {␊
640␉␉␉␉map->mode_table[i].bits_per_pixel = bp;␊
641␉␉␉}␊
642␉␉␉␊
643␉␉␉res->x2 = (htotal?(((htotal-x) >> 8) & 0x0f) : (res->x2 & 0x0f)) | ((x >> 4) & 0xf0);␊
644␉␉␉res->x1 = (x & 0xff);␊
645␉␉␉␊
646␉␉␉res->y2 = (vtotal?(((vtotal-y) >> 8) & 0x0f) : (res->y2 & 0x0f)) | ((y >> 4) & 0xf0);␊
647␉␉␉res->y1 = (y & 0xff);␊
648␉␉␉if (htotal)␊
649␉␉␉␉res->x_total = ((htotal-x) & 0xff);␊
650␉␉␉␊
651␉␉␉if (vtotal)␊
652␉␉␉␉res->y_total = ((vtotal-y) & 0xff);␊
653␉␉␉␊
654␉␉␉break;␊
655␉␉}␊
656␉␉case BT_2:␊
657␉␉{␊
658␉␉␉vbios_resolution_type2 * res = map_type2_resolution(map, map->mode_table[i].resolution);␊
659␉␉␉␊
660␉␉␉res->xchars = x / 8;␊
661␉␉␉res->ychars = y / 16 - 1;␊
662␉␉␉xprev = res->modelines[0].x1;␊
663␉␉␉yprev = res->modelines[0].y1;␊
664␉␉␉␊
665␉␉␉for(j=0; j < 3; j++) {␊
666␉␉␉␉vbios_modeline_type2 * modeline = &res->modelines[j];␊
667␉␉␉␉␊
668␉␉␉␉if (modeline->x1 == xprev && modeline->y1 == yprev) {␊
669␉␉␉␉␉modeline->x1 = modeline->x2 = x-1;␊
670␉␉␉␉␉modeline->y1 = modeline->y2 = y-1;␊
671␉␉␉␉␉␊
672␉␉␉␉␉gtf_timings(x, y, freqs[j], &modeline->clock,␊
673␉␉␉␉␉␉␉␉&modeline->hsyncstart, &modeline->hsyncend,␊
674␉␉␉␉␉␉␉␉&modeline->hblank, &modeline->vsyncstart,␊
675␉␉␉␉␉␉␉␉&modeline->vsyncend, &modeline->vblank);␊
676␉␉␉␉␉␊
677␉␉␉␉␉if (htotal)␊
678␉␉␉␉␉␉modeline->htotal = htotal;␊
679␉␉␉␉␉else␊
680␉␉␉␉␉␉modeline->htotal = modeline->hblank;␊
681␉␉␉␉␉␊
682␉␉␉␉␉if (vtotal)␊
683␉␉␉␉␉␉modeline->vtotal = vtotal;␊
684␉␉␉␉␉else␊
685␉␉␉␉␉␉modeline->vtotal = modeline->vblank;␊
686␉␉␉␉}␊
687␉␉␉}␊
688␉␉␉break;␊
689␉␉}␊
690␉␉case BT_3:␊
691␉␉{␊
692␉␉␉vbios_resolution_type3 * res = map_type3_resolution(map, map->mode_table[i].resolution);␊
693␉␉␉␊
694␉␉␉xprev = res->modelines[0].x1;␊
695␉␉␉yprev = res->modelines[0].y1;␊
696␉␉␉␊
697␉␉␉for (j=0; j < 3; j++) {␊
698␉␉␉␉vbios_modeline_type3 * modeline = &res->modelines[j];␊
699␉␉␉␉␊
700␉␉␉␉if (modeline->x1 == xprev && modeline->y1 == yprev) {␊
701␉␉␉␉␉modeline->x1 = modeline->x2 = x-1;␊
702␉␉␉␉␉modeline->y1 = modeline->y2 = y-1;␊
703␉␉␉␉␉␊
704␉␉␉␉␉gtf_timings(x, y, freqs[j], &modeline->clock,␊
705␉␉␉␉␉␉␉␉&modeline->hsyncstart, &modeline->hsyncend,␊
706␉␉␉␉␉␉␉␉&modeline->hblank, &modeline->vsyncstart,␊
707␉␉␉␉␉␉␉␉&modeline->vsyncend, &modeline->vblank);␊
708␉␉␉␉␉if (htotal)␊
709␉␉␉␉␉␉modeline->htotal = htotal;␊
710␉␉␉␉␉else␊
711␉␉␉␉␉␉modeline->htotal = modeline->hblank;␊
712␉␉␉␉␉if (vtotal)␊
713␉␉␉␉␉␉modeline->vtotal = vtotal;␊
714␉␉␉␉␉else␊
715␉␉␉␉␉␉modeline->vtotal = modeline->vblank;␊
716␉␉␉␉␉␊
717␉␉␉␉␉modeline->timing_h = y-1;␊
718␉␉␉␉␉modeline->timing_v = x-1;␊
719␉␉␉␉}␊
720␉␉␉}␊
721␉␉␉break;␊
722␉␉}␊
723␉␉case BT_ATI_1:␊
724␉␉{␊
725␉␉␉edid_mode mode;␊
726␉␉␉␉␊
727␉␉␉ATOM_MODE_TIMING *mode_timing = (ATOM_MODE_TIMING *) map->ati_mode_table;␊
728␊
729␉␉␉//if (mode.pixel_clock && (mode.h_active == x) && (mode.v_active == y) && !force) {␊
730␉␉␉if (!getMode(&mode)) {␊
731␉␉␉␉mode_timing->usCRTC_H_Total = mode.h_active + mode.h_blanking;␊
732␉␉␉␉mode_timing->usCRTC_H_Disp = mode.h_active;␊
733␉␉␉␉mode_timing->usCRTC_H_SyncStart = mode.h_active + mode.h_sync_offset;␊
734␉␉␉␉mode_timing->usCRTC_H_SyncWidth = mode.h_sync_width;␊
735␉␉␉␉␉␊
736␉␉␉␉mode_timing->usCRTC_V_Total = mode.v_active + mode.v_blanking;␊
737␉␉␉␉mode_timing->usCRTC_V_Disp = mode.v_active;␊
738␉␉␉␉mode_timing->usCRTC_V_SyncStart = mode.v_active + mode.v_sync_offset;␊
739␉␉␉␉mode_timing->usCRTC_V_SyncWidth = mode.v_sync_width;␊
740␊
741␉␉␉␉mode_timing->usPixelClock = mode.pixel_clock;␊
742␉␉␉}␊
743␉␉␉/*else␊
744␉␉␉{␊
745␉␉␉␉vbios_modeline_type2 modeline;␊
746␊
747␉␉␉␉cvt_timings(x, y, freqs[0], &modeline.clock,␊
748␉␉␉␉␉␉␉&modeline.hsyncstart, &modeline.hsyncend,␊
749␉␉␉␉␉␉␉&modeline.hblank, &modeline.vsyncstart,␊
750␉␉␉␉␉␉␉&modeline.vsyncend, &modeline.vblank, 0);␊
751␊
752␉␉␉␉mode_timing->usCRTC_H_Total = x + modeline.hblank;␊
753␉␉␉␉mode_timing->usCRTC_H_Disp = x;␊
754␉␉␉␉mode_timing->usCRTC_H_SyncStart = modeline.hsyncstart;␊
755␉␉␉␉mode_timing->usCRTC_H_SyncWidth = modeline.hsyncend - modeline.hsyncstart;␊
756␊
757␉␉␉␉mode_timing->usCRTC_V_Total = y + modeline.vblank;␊
758␉␉␉␉mode_timing->usCRTC_V_Disp = y;␊
759␉␉␉␉mode_timing->usCRTC_V_SyncStart = modeline.vsyncstart;␊
760␉␉␉␉mode_timing->usCRTC_V_SyncWidth = modeline.vsyncend - modeline.vsyncstart;␊
761␉␉␉␉␉␉␉␉␉␉␉␉␊
762␉␉␉␉mode_timing->usPixelClock = modeline.clock;␊
763␉␉␉ }*/␊
764␉␊
765␉␉␉break;␊
766␉␉}␊
767␉␉case BT_ATI_2:␊
768␉␉{␊
769␉␉␉edid_mode mode;␊
770␉␉␉␉␉␉␊
771␉␉␉ATOM_DTD_FORMAT *mode_timing = (ATOM_DTD_FORMAT *) map->ati_mode_table;␊
772␉␉␉␊
773␉␉␉/*if (mode.pixel_clock && (mode.h_active == x) && (mode.v_active == y) && !force) {*/␊
774␉␉␉if (!getMode(&mode)) {␊
775␉␉␉␉mode_timing->usHBlanking_Time = mode.h_blanking;␊
776␉␉␉␉mode_timing->usHActive = mode.h_active;␊
777␉␉␉␉mode_timing->usHSyncOffset = mode.h_sync_offset;␊
778␉␉␉␉mode_timing->usHSyncWidth = mode.h_sync_width;␊
779␉␉␉␉␉␉␉␉␉␉␊
780␉␉␉␉mode_timing->usVBlanking_Time = mode.v_blanking;␊
781␉␉␉␉mode_timing->usVActive = mode.v_active;␊
782␉␉␉␉mode_timing->usVSyncOffset = mode.v_sync_offset;␊
783␉␉␉␉mode_timing->usVSyncWidth = mode.v_sync_width;␊
784␉␉␉␉␉␉␉␉␉␉␊
785␉␉␉␉mode_timing->usPixClk = mode.pixel_clock;␊
786␉␉␉}␊
787␉␉␉/*else␊
788␉␉␉{␊
789␉␉␉␉vbios_modeline_type2 modeline;␊
790␉␉␉␊
791␉␉␉␉cvt_timings(x, y, freqs[0], &modeline.clock,␊
792␉␉␉␉␉␉␉&modeline.hsyncstart, &modeline.hsyncend,␊
793␉␉␉␉␉␉␉&modeline.hblank, &modeline.vsyncstart,␊
794␉␉␉␉␉␉␉&modeline.vsyncend, &modeline.vblank, 0);␊
795␉␉␉␉␉␉␉␉␉␉␉␊
796␉␉␉␉mode_timing->usHBlanking_Time = modeline.hblank;␊
797␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉mode_timing->usHActive = x;␊
798␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉mode_timing->usHSyncOffset = modeline.hsyncstart - x;␊
799␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉mode_timing->usHSyncWidth = modeline.hsyncend - modeline.hsyncstart;␊
800␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉␊
801␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉mode_timing->usVBlanking_Time = modeline.vblank;␊
802␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉mode_timing->usVActive = y;␊
803␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉mode_timing->usVSyncOffset = modeline.vsyncstart - y;␊
804␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉mode_timing->usVSyncWidth = modeline.hsyncend - modeline.hsyncstart;␊
805␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉␊
806␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉mode_timing->usPixClk = modeline.clock;␊
807␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉}*/␊
808␉␉␉␉␊
809␉␉␉␊
810␉␉␉break;␊
811␉␉}␊
812␉␉case BT_NVDA:␊
813␉␉{␊
814␉␉␉edid_mode mode;␊
815␉␉␉␊
816␉␉␉NV_MODELINE *mode_timing = (NV_MODELINE *) map->nv_mode_table;␊
817␉␉␉␊
818␉␉␉/*if (mode.pixel_clock && (mode.h_active == x) && (mode.v_active == y) && !force) {*/␊
819␉␉␉if (!getMode(&mode)) {␊
820␉␉␉␉mode_timing[i].usH_Total = mode.h_active + mode.h_blanking;␊
821␉␉␉␉mode_timing[i].usH_Active = mode.h_active;␊
822␉␉␉␉mode_timing[i].usH_SyncStart = mode.h_active + mode.h_sync_offset;␊
823␉␉␉␉mode_timing[i].usH_SyncEnd = mode.h_active + mode.h_sync_offset + mode.h_sync_width;␊
824␉␉␉␉␊
825␉␉␉␉mode_timing[i].usV_Total = mode.v_active + mode.v_blanking;␊
826␉␉␉␉mode_timing[i].usV_Active = mode.v_active;␊
827␉␉␉␉mode_timing[i].usV_SyncStart = mode.v_active + mode.v_sync_offset;␊
828␉␉␉␉mode_timing[i].usV_SyncEnd = mode.v_active + mode.v_sync_offset + mode.v_sync_width;␊
829␉␉␉␉␊
830␉␉␉␉mode_timing[i].usPixel_Clock = mode.pixel_clock;␊
831␉␉␉}␊
832␉␉␉/*else␊
833␉␉␉ {␊
834␉␉␉ vbios_modeline_type2 modeline;␊
835␉␉␉ ␊
836␉␉␉ cvt_timings(x, y, freqs[0], &modeline.clock,␊
837␉␉␉ &modeline.hsyncstart, &modeline.hsyncend,␊
838␉␉␉ &modeline.hblank, &modeline.vsyncstart,␊
839␉␉␉ &modeline.vsyncend, &modeline.vblank, 0);␊
840␉␉␉ ␊
841␉␉␉ mode_timing[i].usH_Total = x + modeline.hblank - 1;␊
842␉␉␉ mode_timing[i].usH_Active = x;␊
843␉␉␉ mode_timing[i].usH_SyncStart = modeline.hsyncstart - 1;␊
844␉␉␉ mode_timing[i].usH_SyncEnd = modeline.hsyncend - 1;␊
845␉␉␉ ␊
846␉␉␉ mode_timing[i].usV_Total = y + modeline.vblank - 1;␊
847␉␉␉ mode_timing[i].usV_Active = y;␊
848␉␉␉ mode_timing[i].usV_SyncStart = modeline.vsyncstart - 1;␊
849␉␉␉ mode_timing[i].usV_SyncEnd = modeline.vsyncend - 1;␊
850␉␉␉ ␊
851␉␉␉ mode_timing[i].usPixel_Clock = modeline.clock;␊
852␉␉␉ }*/␊
853␉␉␉break;␊
854␉␉}␊
855␉␉case BT_UNKNOWN:␊
856␉␉{␊
857␉␉␉break;␊
858␉␉}␊
859␉}␊
860␉//␉␉}␊
861␉//␉}␊
862}␊
863␊
864#endif // _RESOLUTION_H_

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