Chameleon

Chameleon Svn Source Tree

Root/branches/meklort/i386/modules/Resolution/915resolution.c

Source at commit 735 created 9 years 5 months ago.
By meklort, GUI module bugfixes. Kext Patcher additions.
1/*
2 * resolution.h
3 *
4 *NOTE: I don't beleive this code is production ready / should be in trunk
5 * Atleast, not in it's current state.
6 *
7 * Created by Evan Lojewski on 3/4/10.
8 * Copyright 2009. All rights reserved.
9 *
10 */
11#ifndef _RESOLUTION_H_
12#define _RESOLUTION_H_
13
14#include "libsaio.h"
15#include "edid.h"
16#include "915resolution.h"
17
18
19void patchVideoBios()
20{
21UInt32 x = 0, y = 0, bp = 0;
22
23getResolution(&x, &y, &bp);
24
25
26if (x != 0 &&
27y != 0 &&
28bp != 0)
29{
30vbios_map * map;
31
32map = open_vbios(CT_UNKNOWN);
33if(map)
34{
35unlock_vbios(map);
36
37set_mode(map, x, y, bp, 0, 0);
38
39relock_vbios(map);
40
41close_vbios(map);
42}
43}
44}
45
46
47/* Copied from 915 resolution created by steve tomljenovic
48 *
49 * This code is based on the techniques used in :
50 *
51 * - 855patch. Many thanks to Christian Zietz (czietz gmx net)
52 * for demonstrating how to shadow the VBIOS into system RAM
53 * and then modify it.
54 *
55 * - 1280patch by Andrew Tipton (andrewtipton null li).
56 *
57 * - 855resolution by Alain Poirier
58 *
59 * This source code is into the public domain.
60 */
61
62/**
63 **
64 **/
65
66#define CONFIG_MECH_ONE_ADDR0xCF8
67#define CONFIG_MECH_ONE_DATA0xCFC
68
69int freqs[] = { 60, 75, 85 };
70
71UInt32 get_chipset_id(void)
72{
73outl(CONFIG_MECH_ONE_ADDR, 0x80000000);
74return inl(CONFIG_MECH_ONE_DATA);
75}
76
77chipset_type get_chipset(UInt32 id)
78{
79chipset_type type;
80
81switch (id) {
82case 0x35758086:
83type = CT_830;
84break;
85
86case 0x25608086:
87type = CT_845G;
88break;
89
90case 0x35808086:
91type = CT_855GM;
92break;
93
94case 0x25708086:
95type = CT_865G;
96break;
97
98case 0x25808086:
99type = CT_915G;
100break;
101
102case 0x25908086:
103type = CT_915GM;
104break;
105
106case 0x27708086:
107type = CT_945G;
108break;
109
110case 0x27a08086:
111type = CT_945GM;
112break;
113
114case 0x27ac8086:
115type = CT_945GME;
116break;
117
118case 0x29708086:
119type = CT_946GZ;
120break;
121
122case 0x27748086:
123type = CT_955X;
124break;
125
126case 0x277c8086:
127type = CT_975X;
128break;
129
130case 0x29a08086:
131type = CT_G965;
132break;
133
134case 0x29908086:
135type = CT_Q965;
136break;
137
138case 0x81008086:
139type = CT_500;
140break;
141
142case 0x2e108086:
143case 0X2e908086:
144type = CT_B43;
145break;
146
147case 0x2e208086:
148type = CT_P45;
149break;
150
151case 0x2e308086:
152type = CT_G41;
153break;
154
155case 0x29c08086:
156type = CT_G31;
157break;
158
159case 0x29208086:
160type = CT_G45;
161break;
162
163case 0xA0108086:// mobile
164case 0xA0008086:// desktop
165type = CT_3150;
166break;
167
168case 0x2a008086:
169type = CT_965GM;
170break;
171
172case 0x29e08086:
173type = CT_X48;
174break;
175
176case 0x2a408086:
177type = CT_GM45;
178break;
179
180
181default:
182if((id & 0x0000FFFF) == 0x00008086) // Intel chipset
183{
184//printf("Unknown chipset 0x%llX, please email id to meklort@gmail.com", id);
185//getc();
186type = CT_UNKNOWN_INTEL;
187//type = CT_UNKNOWN;
188
189}
190else
191{
192type = CT_UNKNOWN;
193}
194break;
195}
196return type;
197}
198
199vbios_resolution_type1 * map_type1_resolution(vbios_map * map, UInt16 res)
200{
201vbios_resolution_type1 * ptr = ((vbios_resolution_type1*)(map->bios_ptr + res));
202return ptr;
203}
204
205vbios_resolution_type2 * map_type2_resolution(vbios_map * map, UInt16 res)
206{
207vbios_resolution_type2 * ptr = ((vbios_resolution_type2*)(map->bios_ptr + res));
208return ptr;
209}
210
211vbios_resolution_type3 * map_type3_resolution(vbios_map * map, UInt16 res)
212{
213vbios_resolution_type3 * ptr = ((vbios_resolution_type3*)(map->bios_ptr + res));
214return ptr;
215}
216
217char detect_bios_type(vbios_map * map, char modeline, int entry_size)
218{
219UInt32 i;
220UInt16 r1, r2;
221
222r1 = r2 = 32000;
223
224for (i=0; i < map->mode_table_size; i++)
225{
226if (map->mode_table[i].resolution <= r1)
227{
228r1 = map->mode_table[i].resolution;
229}
230else
231{
232if (map->mode_table[i].resolution <= r2)
233{
234r2 = map->mode_table[i].resolution;
235}
236}
237
238/*printf("r1 = %d r2 = %d\n", r1, r2);*/
239}
240
241return (r2-r1-6) % entry_size == 0;
242}
243
244void close_vbios(vbios_map * map);
245
246char detect_ati_bios_type(vbios_map * map)
247{
248return map->mode_table_size % sizeof(ATOM_MODE_TIMING) == 0;
249}
250
251
252vbios_map * open_vbios(chipset_type forced_chipset)
253{
254UInt32 z;
255vbios_map * map = malloc(sizeof(vbios_map));
256for(z=0; z<sizeof(vbios_map); z++) ((char*)map)[z]=0;
257/*
258 * Determine chipset
259 */
260
261if (forced_chipset == CT_UNKNOWN)
262{
263map->chipset_id = get_chipset_id();
264map->chipset = get_chipset(map->chipset_id);
265}
266else if (forced_chipset != CT_UNKNOWN)
267{
268map->chipset = forced_chipset;
269}
270
271
272if (map->chipset == CT_UNKNOWN)
273{
274//verbose("Unknown chipset type.\n");
275//verbose("915resolution only works with Intel 800/900 series graphic chipsets.\n");
276//verbose("Chipset Id: %x\n", map->chipset_id);
277close_vbios(map);
278return 0;
279}
280
281
282/*
283 * Map the video bios to memory
284 */
285map->bios_ptr=(char*)VBIOS_START;
286
287/*
288 * check if we have ATI Radeon
289 */
290map->ati_tables.base = map->bios_ptr;
291map->ati_tables.AtomRomHeader = (ATOM_ROM_HEADER *) (map->bios_ptr + *(unsigned short *) (map->bios_ptr + OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER));
292if (strcmp ((char *) map->ati_tables.AtomRomHeader->uaFirmWareSignature, "ATOM") == 0)
293{
294// ATI Radeon Card
295map->bios = BT_ATI_1;
296
297map->ati_tables.MasterDataTables = (unsigned short *) &((ATOM_MASTER_DATA_TABLE *) (map->bios_ptr + map->ati_tables.AtomRomHeader->usMasterDataTableOffset))->ListOfDataTables;
298unsigned short std_vesa_offset = (unsigned short) ((ATOM_MASTER_LIST_OF_DATA_TABLES *)map->ati_tables.MasterDataTables)->StandardVESA_Timing;
299ATOM_STANDARD_VESA_TIMING * std_vesa = (ATOM_STANDARD_VESA_TIMING *) (map->bios_ptr + std_vesa_offset);
300
301map->ati_mode_table = (char *) &std_vesa->aModeTimings;
302if (map->ati_mode_table == 0)
303{
304printf("Unable to locate the mode table.\n");
305printf("Please run the program 'dump_bios' as root and\n");
306printf("email the file 'vbios.dmp' to stomljen@yahoo.com.\n");
307printf("Chipset: %d\n", map->chipset);
308close_vbios(map);
309return 0;
310}
311map->mode_table_size = std_vesa->sHeader.usStructureSize - sizeof(ATOM_COMMON_TABLE_HEADER);
312
313if (!detect_ati_bios_type(map)) map->bios = BT_ATI_2;
314
315}
316else {
317
318/*
319 * check if we have NVIDIA
320 */
321
322int i = 0;
323while (i < 512)
324{ // we don't need to look through the whole bios, just the firs 512 bytes
325if ((map->bios_ptr[i] == 'N')
326&& (map->bios_ptr[i+1] == 'V')
327&& (map->bios_ptr[i+2] == 'I')
328&& (map->bios_ptr[i+3] == 'D'))
329{
330map->bios = BT_NVDA;
331unsigned short nv_data_table_offset = 0;
332unsigned short * nv_data_table;
333NV_VESA_TABLE * std_vesa;
334
335int i = 0;
336
337while (i < 0x300)
338{ //We don't need to look for the table in the whole bios, the 768 first bytes only
339if ((map->bios_ptr[i] == 0x44)
340&& (map->bios_ptr[i+1] == 0x01)
341&& (map->bios_ptr[i+2] == 0x04)
342&& (map->bios_ptr[i+3] == 0x00))
343{
344nv_data_table_offset = (unsigned short) (map->bios_ptr[i+4] | (map->bios_ptr[i+5] << 8));
345break;
346}
347i++;
348}
349
350nv_data_table = (unsigned short *) (map->bios_ptr + (nv_data_table_offset + OFFSET_TO_VESA_TABLE_INDEX));
351std_vesa = (NV_VESA_TABLE *) (map->bios_ptr + *nv_data_table);
352
353map->nv_mode_table = (char *) std_vesa->sModelines;
354if (map->nv_mode_table == 0)
355{
356printf("Unable to locate the mode table.\n");
357printf("Please run the program 'dump_bios' as root and\n");
358printf("email the file 'vbios.dmp' to stomljen@yahoo.com.\n");
359printf("Chipset: %s\n", map->chipset);
360close_vbios(map);
361return 0;
362}
363map->mode_table_size = std_vesa->sHeader.usTable_Size;
364
365break;
366}
367i++;
368}
369}
370
371
372/*
373 * check if we have Intel
374 */
375
376/*if (map->chipset == CT_UNKNOWN && memmem(map->bios_ptr, VBIOS_SIZE, INTEL_SIGNATURE, strlen(INTEL_SIGNATURE))) {
377 printf( "Intel chipset detected. However, 915resolution was unable to determine the chipset type.\n");
378
379 printf("Chipset Id: %x\n", map->chipset_id);
380
381 printf("Please report this problem to stomljen@yahoo.com\n");
382
383 close_vbios(map);
384 return 0;
385 }*/
386
387/*
388 * check for others
389 */
390
391
392
393/*
394 * Figure out where the mode table is
395 */
396if ((map->bios != BT_ATI_1) && (map->bios != BT_NVDA))
397{
398char* p = map->bios_ptr + 16;
399char* limit = map->bios_ptr + VBIOS_SIZE - (3 * sizeof(vbios_mode));
400
401while (p < limit && map->mode_table == 0)
402{
403vbios_mode * mode_ptr = (vbios_mode *) p;
404
405if (((mode_ptr[0].mode & 0xf0) == 0x30) && ((mode_ptr[1].mode & 0xf0) == 0x30) &&
406((mode_ptr[2].mode & 0xf0) == 0x30) && ((mode_ptr[3].mode & 0xf0) == 0x30))
407{
408map->mode_table = mode_ptr;
409}
410
411p++;
412}
413
414if (map->mode_table == 0)
415{
416close_vbios(map);
417return 0;
418}
419}
420
421
422/*
423 * Determine size of mode table
424 */
425if ((map->bios != BT_ATI_1) && (map->bios != BT_ATI_2) && (map->bios != BT_NVDA))
426{
427vbios_mode * mode_ptr = map->mode_table;
428
429while (mode_ptr->mode != 0xff)
430{
431map->mode_table_size++;
432mode_ptr++;
433}
434}
435
436/*
437 * Figure out what type of bios we have
438 * order of detection is important
439 */
440if ((map->bios != BT_ATI_1) && (map->bios != BT_ATI_2) && (map->bios != BT_NVDA))
441{
442if (detect_bios_type(map, TRUE, sizeof(vbios_modeline_type3)))
443{
444map->bios = BT_3;
445}
446else if (detect_bios_type(map, TRUE, sizeof(vbios_modeline_type2)))
447{
448map->bios = BT_2;
449}
450else if (detect_bios_type(map, FALSE, sizeof(vbios_resolution_type1)))
451{
452map->bios = BT_1;
453}
454else {
455return 0;
456}
457}
458
459return map;
460}
461
462void close_vbios(vbios_map * map)
463{
464free(map);
465}
466
467void unlock_vbios(vbios_map * map)
468{
469
470map->unlocked = TRUE;
471
472switch (map->chipset) {
473case CT_UNKNOWN:
474break;
475case CT_830:
476case CT_855GM:
477outl(CONFIG_MECH_ONE_ADDR, 0x8000005a);
478map->b1 = inb(CONFIG_MECH_ONE_DATA + 2);
479
480outl(CONFIG_MECH_ONE_ADDR, 0x8000005a);
481outb(CONFIG_MECH_ONE_DATA + 2, 0x33);
482break;
483case CT_845G:
484case CT_865G:
485case CT_915G:
486case CT_915GM:
487case CT_945G:
488case CT_945GM:
489case CT_945GME:
490case CT_946GZ:
491case CT_G965:
492case CT_Q965:
493case CT_965GM:
494case CT_975X:
495case CT_P35:
496case CT_955X:
497case CT_X48:
498case CT_B43:
499case CT_Q45:
500case CT_P45:
501case CT_GM45:
502case CT_G45:
503case CT_G41:
504case CT_G31:
505case CT_500:
506case CT_3150:
507case CT_UNKNOWN_INTEL:// Assume newer intel chipset is the same as before
508outl(CONFIG_MECH_ONE_ADDR, 0x80000090);
509map->b1 = inb(CONFIG_MECH_ONE_DATA + 1);
510map->b2 = inb(CONFIG_MECH_ONE_DATA + 2);
511outl(CONFIG_MECH_ONE_ADDR, 0x80000090);
512outb(CONFIG_MECH_ONE_DATA + 1, 0x33);
513outb(CONFIG_MECH_ONE_DATA + 2, 0x33);
514break;
515}
516
517#if DEBUG
518{
519UInt32 t = inl(CONFIG_MECH_ONE_DATA);
520verbose("unlock PAM: (0x%08x)\n", t);
521}
522#endif
523}
524
525void relock_vbios(vbios_map * map)
526{
527
528map->unlocked = FALSE;
529
530switch (map->chipset)
531{
532case CT_UNKNOWN:
533break;
534case CT_830:
535case CT_855GM:
536outl(CONFIG_MECH_ONE_ADDR, 0x8000005a);
537outb(CONFIG_MECH_ONE_DATA + 2, map->b1);
538break;
539case CT_845G:
540case CT_865G:
541case CT_915G:
542case CT_915GM:
543case CT_945G:
544case CT_945GM:
545case CT_945GME:
546case CT_946GZ:
547case CT_G965:
548case CT_955X:
549case CT_G45:
550case CT_Q965:
551case CT_965GM:
552case CT_975X:
553case CT_P35:
554case CT_X48:
555case CT_B43:
556case CT_Q45:
557case CT_P45:
558case CT_GM45:
559case CT_G41:
560case CT_G31:
561case CT_500:
562case CT_3150:
563case CT_UNKNOWN_INTEL:
564outl(CONFIG_MECH_ONE_ADDR, 0x80000090);
565outb(CONFIG_MECH_ONE_DATA + 1, map->b1);
566outb(CONFIG_MECH_ONE_DATA + 2, map->b2);
567break;
568}
569
570#if DEBUG
571{
572 UInt32 t = inl(CONFIG_MECH_ONE_DATA);
573verbose("relock PAM: (0x%08x)\n", t);
574}
575#endif
576}
577
578
579int getMode(edid_mode *mode)
580{
581char* edidInfo = readEDID();
582
583if(!edidInfo) return 1;
584
585mode->pixel_clock = (edidInfo[55] << 8) | edidInfo[54];
586mode->h_active = edidInfo[56] | ((edidInfo[58] & 0xF0) << 4);
587mode->h_blanking = ((edidInfo[58] & 0x0F) << 8) | edidInfo[57];
588mode->v_active = edidInfo[59] | ((edidInfo[61] & 0xF0) << 4);
589mode->v_blanking = ((edidInfo[61] & 0x0F) << 8) | edidInfo[60];
590mode->h_sync_offset = ((edidInfo[65] & 0xC0) >> 2) | edidInfo[62];
591mode->h_sync_width = (edidInfo[65] & 0x30) | edidInfo[63];
592mode->v_sync_offset = (edidInfo[65] & 0x0C) | ((edidInfo[64] & 0x0C) >> 2);
593mode->v_sync_width = ((edidInfo[65] & 0x3) << 2) | (edidInfo[64] & 0x03);
594
595
596free( edidInfo );
597
598if(!mode->h_active) return 1;
599
600return 0;
601
602}
603
604
605static void gtf_timings(UInt32 x, UInt32 y, UInt32 freq,
606unsigned long *clock,
607UInt16 *hsyncstart, UInt16 *hsyncend, UInt16 *hblank,
608UInt16 *vsyncstart, UInt16 *vsyncend, UInt16 *vblank)
609{
610UInt32 hbl, vbl, vfreq;
611
612vbl = y + (y+1)/(20000.0/(11*freq) - 1) + 1.5;
613vfreq = vbl * freq;
614hbl = 16 * (int)(x * (30.0 - 300000.0 / vfreq) /
615 + (70.0 + 300000.0 / vfreq) / 16.0 + 0.5);
616
617*vsyncstart = y;
618*vsyncend = y + 3;
619*vblank = vbl - 1;
620*hsyncstart = x + hbl / 2 - (x + hbl + 50) / 100 * 8 - 1;
621*hsyncend = x + hbl / 2 - 1;
622*hblank = x + hbl - 1;
623*clock = (x + hbl) * vfreq / 1000;
624}
625
626void set_mode(vbios_map * map, /*UInt32 mode,*/ UInt32 x, UInt32 y, UInt32 bp, UInt32 htotal, UInt32 vtotal) {
627UInt32 xprev, yprev;
628UInt32 i = 0, j;
629// patch first available mode
630
631//for (i=0; i < map->mode_table_size; i++) {
632//if (map->mode_table[0].mode == mode) {
633switch(map->bios) {
634case BT_1:
635{
636vbios_resolution_type1 * res = map_type1_resolution(map, map->mode_table[i].resolution);
637
638if (bp) {
639map->mode_table[i].bits_per_pixel = bp;
640}
641
642res->x2 = (htotal?(((htotal-x) >> 8) & 0x0f) : (res->x2 & 0x0f)) | ((x >> 4) & 0xf0);
643res->x1 = (x & 0xff);
644
645res->y2 = (vtotal?(((vtotal-y) >> 8) & 0x0f) : (res->y2 & 0x0f)) | ((y >> 4) & 0xf0);
646res->y1 = (y & 0xff);
647if (htotal)
648res->x_total = ((htotal-x) & 0xff);
649
650if (vtotal)
651res->y_total = ((vtotal-y) & 0xff);
652
653break;
654}
655case BT_2:
656{
657vbios_resolution_type2 * res = map_type2_resolution(map, map->mode_table[i].resolution);
658
659res->xchars = x / 8;
660res->ychars = y / 16 - 1;
661xprev = res->modelines[0].x1;
662yprev = res->modelines[0].y1;
663
664for(j=0; j < 3; j++) {
665vbios_modeline_type2 * modeline = &res->modelines[j];
666
667if (modeline->x1 == xprev && modeline->y1 == yprev) {
668modeline->x1 = modeline->x2 = x-1;
669modeline->y1 = modeline->y2 = y-1;
670
671gtf_timings(x, y, freqs[j], &modeline->clock,
672&modeline->hsyncstart, &modeline->hsyncend,
673&modeline->hblank, &modeline->vsyncstart,
674&modeline->vsyncend, &modeline->vblank);
675
676if (htotal)
677modeline->htotal = htotal;
678else
679modeline->htotal = modeline->hblank;
680
681if (vtotal)
682modeline->vtotal = vtotal;
683else
684modeline->vtotal = modeline->vblank;
685}
686}
687break;
688}
689case BT_3:
690{
691vbios_resolution_type3 * res = map_type3_resolution(map, map->mode_table[i].resolution);
692
693xprev = res->modelines[0].x1;
694yprev = res->modelines[0].y1;
695
696for (j=0; j < 3; j++) {
697vbios_modeline_type3 * modeline = &res->modelines[j];
698
699if (modeline->x1 == xprev && modeline->y1 == yprev) {
700modeline->x1 = modeline->x2 = x-1;
701modeline->y1 = modeline->y2 = y-1;
702
703gtf_timings(x, y, freqs[j], &modeline->clock,
704&modeline->hsyncstart, &modeline->hsyncend,
705&modeline->hblank, &modeline->vsyncstart,
706&modeline->vsyncend, &modeline->vblank);
707if (htotal)
708modeline->htotal = htotal;
709else
710modeline->htotal = modeline->hblank;
711if (vtotal)
712modeline->vtotal = vtotal;
713else
714modeline->vtotal = modeline->vblank;
715
716modeline->timing_h = y-1;
717modeline->timing_v = x-1;
718}
719}
720break;
721}
722case BT_ATI_1:
723{
724edid_mode mode;
725
726ATOM_MODE_TIMING *mode_timing = (ATOM_MODE_TIMING *) map->ati_mode_table;
727
728//if (mode.pixel_clock && (mode.h_active == x) && (mode.v_active == y) && !force) {
729if (!getMode(&mode)) {
730mode_timing->usCRTC_H_Total = mode.h_active + mode.h_blanking;
731mode_timing->usCRTC_H_Disp = mode.h_active;
732mode_timing->usCRTC_H_SyncStart = mode.h_active + mode.h_sync_offset;
733mode_timing->usCRTC_H_SyncWidth = mode.h_sync_width;
734
735mode_timing->usCRTC_V_Total = mode.v_active + mode.v_blanking;
736mode_timing->usCRTC_V_Disp = mode.v_active;
737mode_timing->usCRTC_V_SyncStart = mode.v_active + mode.v_sync_offset;
738mode_timing->usCRTC_V_SyncWidth = mode.v_sync_width;
739
740mode_timing->usPixelClock = mode.pixel_clock;
741}
742/*else
743{
744vbios_modeline_type2 modeline;
745
746cvt_timings(x, y, freqs[0], &modeline.clock,
747&modeline.hsyncstart, &modeline.hsyncend,
748&modeline.hblank, &modeline.vsyncstart,
749&modeline.vsyncend, &modeline.vblank, 0);
750
751mode_timing->usCRTC_H_Total = x + modeline.hblank;
752mode_timing->usCRTC_H_Disp = x;
753mode_timing->usCRTC_H_SyncStart = modeline.hsyncstart;
754mode_timing->usCRTC_H_SyncWidth = modeline.hsyncend - modeline.hsyncstart;
755
756mode_timing->usCRTC_V_Total = y + modeline.vblank;
757mode_timing->usCRTC_V_Disp = y;
758mode_timing->usCRTC_V_SyncStart = modeline.vsyncstart;
759mode_timing->usCRTC_V_SyncWidth = modeline.vsyncend - modeline.vsyncstart;
760
761mode_timing->usPixelClock = modeline.clock;
762 }*/
763
764break;
765}
766case BT_ATI_2:
767{
768edid_mode mode;
769
770ATOM_DTD_FORMAT *mode_timing = (ATOM_DTD_FORMAT *) map->ati_mode_table;
771
772/*if (mode.pixel_clock && (mode.h_active == x) && (mode.v_active == y) && !force) {*/
773if (!getMode(&mode)) {
774mode_timing->usHBlanking_Time = mode.h_blanking;
775mode_timing->usHActive = mode.h_active;
776mode_timing->usHSyncOffset = mode.h_sync_offset;
777mode_timing->usHSyncWidth = mode.h_sync_width;
778
779mode_timing->usVBlanking_Time = mode.v_blanking;
780mode_timing->usVActive = mode.v_active;
781mode_timing->usVSyncOffset = mode.v_sync_offset;
782mode_timing->usVSyncWidth = mode.v_sync_width;
783
784mode_timing->usPixClk = mode.pixel_clock;
785}
786/*else
787{
788vbios_modeline_type2 modeline;
789
790cvt_timings(x, y, freqs[0], &modeline.clock,
791&modeline.hsyncstart, &modeline.hsyncend,
792&modeline.hblank, &modeline.vsyncstart,
793&modeline.vsyncend, &modeline.vblank, 0);
794
795mode_timing->usHBlanking_Time = modeline.hblank;
796 +mode_timing->usHActive = x;
797 +mode_timing->usHSyncOffset = modeline.hsyncstart - x;
798 +mode_timing->usHSyncWidth = modeline.hsyncend - modeline.hsyncstart;
799 +
800 +mode_timing->usVBlanking_Time = modeline.vblank;
801 +mode_timing->usVActive = y;
802 +mode_timing->usVSyncOffset = modeline.vsyncstart - y;
803 +mode_timing->usVSyncWidth = modeline.hsyncend - modeline.hsyncstart;
804 +
805 +mode_timing->usPixClk = modeline.clock;
806 +}*/
807
808
809break;
810}
811case BT_NVDA:
812{
813edid_mode mode;
814
815NV_MODELINE *mode_timing = (NV_MODELINE *) map->nv_mode_table;
816
817/*if (mode.pixel_clock && (mode.h_active == x) && (mode.v_active == y) && !force) {*/
818if (!getMode(&mode)) {
819mode_timing[i].usH_Total = mode.h_active + mode.h_blanking;
820mode_timing[i].usH_Active = mode.h_active;
821mode_timing[i].usH_SyncStart = mode.h_active + mode.h_sync_offset;
822mode_timing[i].usH_SyncEnd = mode.h_active + mode.h_sync_offset + mode.h_sync_width;
823
824mode_timing[i].usV_Total = mode.v_active + mode.v_blanking;
825mode_timing[i].usV_Active = mode.v_active;
826mode_timing[i].usV_SyncStart = mode.v_active + mode.v_sync_offset;
827mode_timing[i].usV_SyncEnd = mode.v_active + mode.v_sync_offset + mode.v_sync_width;
828
829mode_timing[i].usPixel_Clock = mode.pixel_clock;
830}
831/*else
832 {
833 vbios_modeline_type2 modeline;
834
835 cvt_timings(x, y, freqs[0], &modeline.clock,
836 &modeline.hsyncstart, &modeline.hsyncend,
837 &modeline.hblank, &modeline.vsyncstart,
838 &modeline.vsyncend, &modeline.vblank, 0);
839
840 mode_timing[i].usH_Total = x + modeline.hblank - 1;
841 mode_timing[i].usH_Active = x;
842 mode_timing[i].usH_SyncStart = modeline.hsyncstart - 1;
843 mode_timing[i].usH_SyncEnd = modeline.hsyncend - 1;
844
845 mode_timing[i].usV_Total = y + modeline.vblank - 1;
846 mode_timing[i].usV_Active = y;
847 mode_timing[i].usV_SyncStart = modeline.vsyncstart - 1;
848 mode_timing[i].usV_SyncEnd = modeline.vsyncend - 1;
849
850 mode_timing[i].usPixel_Clock = modeline.clock;
851 }*/
852break;
853}
854case BT_UNKNOWN:
855{
856break;
857}
858}
859//}
860//}
861}
862
863#endif // _RESOLUTION_H_

Archive Download this file

Revision: 735