| 1 | /*␊ |
| 2 | * platform.h␊ |
| 3 | * AsereBLN: reworked and extended␊ |
| 4 | *␊ |
| 5 | */␊ |
| 6 | ␊ |
| 7 | #ifndef __LIBSAIO_PLATFORM_H␊ |
| 8 | #define __LIBSAIO_PLATFORM_H␊ |
| 9 | ␊ |
| 10 | #include "libsaio.h"␊ |
| 11 | ␊ |
| 12 | extern bool platformCPUFeature(uint32_t);␊ |
| 13 | extern void scan_platform(void);␊ |
| 14 | extern void dumpPhysAddr(const char * title, void * a, int len);␊ |
| 15 | ␊ |
| 16 | #define bit(n)␉␉␉␉(1UL << (n))␊ |
| 17 | #define bitmask(h,l)␉␉((bit(h)|(bit(h)-1)) & ~(bit(l)-1))␊ |
| 18 | #define bitfield(x,h,l)␉␉(((x) & bitmask(h,l)) >> l)␊ |
| 19 | ␊ |
| 20 | /* CPUID index into cpuid_raw */␊ |
| 21 | #define CPUID_0␉␉␉␉0␊ |
| 22 | #define CPUID_1␉␉␉␉1␊ |
| 23 | #define CPUID_2␉␉␉␉2␊ |
| 24 | #define CPUID_3␉␉␉␉3␊ |
| 25 | #define CPUID_4␉␉␉␉4␊ |
| 26 | #define CPUID_80␉␉␉5␊ |
| 27 | #define CPUID_81␉␉␉6␊ |
| 28 | #define CPUID_MAX␉␉␉7␊ |
| 29 | ␊ |
| 30 | #define CPU_MODEL_YONAH␉␉␉0x0E␉␉␉// Sossaman, Yonah␊ |
| 31 | #define CPU_MODEL_MEROM␉␉␉0x0F␉␉␉// Allendale, Conroe, Kentsfield, Woodcrest, Clovertown, Tigerton, Merom␊ |
| 32 | #define CPU_MODEL_PENRYN␉␉0x17␉␉␉// Wolfdale, Yorkfield, Harpertown, Penryn␊ |
| 33 | #define CPU_MODEL_NEHALEM␉␉0x1A␉␉␉// Bloomfield. Nehalem-EP, Nehalem-WS, Gainestown ␊ |
| 34 | #define CPU_MODEL_ATOM␉␉␉0x1C␉␉␉// Atom␊ |
| 35 | #define CPU_MODEL_DUNNINGTON␉0x1D␉␉␉// Dunnington␊ |
| 36 | #define CPU_MODEL_FIELDS␉␉0x1E␉␉␉// Lynnfield, Clarksfield, Jasper Forest␊ |
| 37 | #define CPU_MODEL_DALES␉␉␉0x1F␉␉␉// Havendale, Auburndale␊ |
| 38 | #define CPU_MODEL_DALES_32NM␉0x25␉␉␉// Clarkdale, Arrandale: Dual core␊ |
| 39 | #define CPU_MODEL_SANDY_BRIDGE␉0x2A␉␉␉// Sandy Bridge␊ |
| 40 | #define CPU_MODEL_WESTMERE␉␉0x2C␉␉␉// Gulftown, Westmere-EP, Westmere-WS␊ |
| 41 | #define CPU_MODEL_NEHALEM_EX␉0x2E␉␉␉// Beckton␊ |
| 42 | #define CPU_MODEL_WESTMERE_EX␉0x2F␊ |
| 43 | ␊ |
| 44 | /* CPU Features */␊ |
| 45 | // NOTE: These are currently mapped to the actual bit in the cpuid value␊ |
| 46 | #define CPU_FEATURE_MMX␉␉␉bit(23)␉␉␉// MMX Instruction Set␊ |
| 47 | #define CPU_FEATURE_SSE␉␉␉bit(25)␉␉␉// SSE Instruction Set␊ |
| 48 | #define CPU_FEATURE_SSE2␉␉bit(26)␉␉␉// SSE2 Instruction Set␊ |
| 49 | #define CPU_FEATURE_SSE3␉␉bit(0)␉␉␉// SSE3 Instruction Set␊ |
| 50 | #define CPU_FEATURE_SSE41␉␉bit(19)␉␉␉// SSE41 Instruction Set␊ |
| 51 | #define CPU_FEATURE_SSE42␉␉bit(20)␉␉␉// SSE42 Instruction Set␊ |
| 52 | #define CPU_FEATURE_EM64T␉␉bit(29)␉␉␉// 64Bit Support␊ |
| 53 | #define CPU_FEATURE_HTT␉␉␉bit(28)␉␉␉// HyperThreading␊ |
| 54 | #define CPU_FEATURE_MSR␉␉␉bit(5)␉␉␉// MSR Support␊ |
| 55 | #define CPU_FEATURE_APIC␉␉bit(9)␉␉␉// On-chip APIC Hardware␊ |
| 56 | #define CPU_FEATURE_EST␉␉␉bit(7)␉␉␉// Enhanced Intel SpeedStep␊ |
| 57 | #define CPU_FEATURE_TM2␉␉␉bit(8)␉␉␉// Thermal Monitor 2␊ |
| 58 | #define CPU_FEATURE_TM1␉␉␉bit(29)␉␉␉// Thermal Monitor 1␊ |
| 59 | #define CPU_FEATURE_SSSE3␉␉bit(9)␉␉␉// Supplemental SSE3 Instruction Set␊ |
| 60 | #define CPU_FEATURE_xAPIC␉␉bit(21)␉␉␉// Extended APIC Mode␊ |
| 61 | #define CPU_FEATURE_ACPI␉␉bit(22)␉␉␉// Thermal Monitor and Software Controlled Clock␊ |
| 62 | #define CPU_FEATURE_LAHF␉␉bit(20)␉␉␉// LAHF/SAHF Instructions␊ |
| 63 | #define CPU_FEATURE_XD␉␉␉bit(20)␉␉␉// Execute Disable␊ |
| 64 | ␊ |
| 65 | // NOTE: Determine correct bit for below (28 is already in use)␊ |
| 66 | #define CPU_FEATURE_MOBILE␉␉bit(1)␉␉␉// Mobile CPU␊ |
| 67 | ␊ |
| 68 | /* SMBIOS Memory Types */ ␊ |
| 69 | #define SMB_MEM_TYPE_UNDEFINED␉0␊ |
| 70 | #define SMB_MEM_TYPE_OTHER␉␉1␊ |
| 71 | #define SMB_MEM_TYPE_UNKNOWN␉2␊ |
| 72 | #define SMB_MEM_TYPE_DRAM␉␉3␊ |
| 73 | #define SMB_MEM_TYPE_EDRAM␉␉4␊ |
| 74 | #define SMB_MEM_TYPE_VRAM␉␉5␊ |
| 75 | #define SMB_MEM_TYPE_SRAM␉␉6␊ |
| 76 | #define SMB_MEM_TYPE_RAM␉␉7␊ |
| 77 | #define SMB_MEM_TYPE_ROM␉␉8␊ |
| 78 | #define SMB_MEM_TYPE_FLASH␉␉9␊ |
| 79 | #define SMB_MEM_TYPE_EEPROM␉␉10␊ |
| 80 | #define SMB_MEM_TYPE_FEPROM␉␉11␊ |
| 81 | #define SMB_MEM_TYPE_EPROM␉␉12␊ |
| 82 | #define SMB_MEM_TYPE_CDRAM␉␉13␊ |
| 83 | #define SMB_MEM_TYPE_3DRAM␉␉14␊ |
| 84 | #define SMB_MEM_TYPE_SDRAM␉␉15␊ |
| 85 | #define SMB_MEM_TYPE_SGRAM␉␉16␊ |
| 86 | #define SMB_MEM_TYPE_RDRAM␉␉17␊ |
| 87 | #define SMB_MEM_TYPE_DDR␉␉18␊ |
| 88 | #define SMB_MEM_TYPE_DDR2␉␉19␊ |
| 89 | #define SMB_MEM_TYPE_FBDIMM␉␉20␊ |
| 90 | #define SMB_MEM_TYPE_DDR3␉␉24␉␉␉␉// Supported in 10.5.6+ AppleSMBIOS␊ |
| 91 | ␊ |
| 92 | /* Memory Configuration Types */ ␊ |
| 93 | #define SMB_MEM_CHANNEL_UNKNOWN␉␉0␊ |
| 94 | #define SMB_MEM_CHANNEL_SINGLE␉␉1␊ |
| 95 | #define SMB_MEM_CHANNEL_DUAL␉␉2␊ |
| 96 | #define SMB_MEM_CHANNEL_TRIPLE␉␉3␊ |
| 97 | ␊ |
| 98 | /* Maximum number of ram slots */␊ |
| 99 | #define MAX_RAM_SLOTS␉␉␉8␊ |
| 100 | #define RAM_SLOT_ENUMERATOR␉␉{0, 2, 4, 1, 3, 5, 6, 8, 10, 7, 9, 11}␊ |
| 101 | ␊ |
| 102 | /* Maximum number of SPD bytes */␊ |
| 103 | #define MAX_SPD_SIZE␉␉␉256␊ |
| 104 | ␊ |
| 105 | /* Size of SMBIOS UUID in bytes */␊ |
| 106 | #define UUID_LEN␉␉␉16␊ |
| 107 | ␊ |
| 108 | typedef struct _RamSlotInfo_t {␊ |
| 109 | uint32_t␉␉ModuleSize;␉␉␉␉␉// Size of Module in MB␊ |
| 110 | uint32_t␉␉Frequency;␉␉␉␉␉// in Mhz␊ |
| 111 | const char*␉␉Vendor;␊ |
| 112 | const char*␉␉PartNo;␊ |
| 113 | const char*␉␉SerialNo;␊ |
| 114 | char*␉␉␉spd;␉␉␉␉␉␉// SPD Dump␊ |
| 115 | bool␉␉␉InUse;␊ |
| 116 | uint8_t␉␉␉Type;␊ |
| 117 | uint8_t␉␉␉BankConnections;␉␉␉// table type 6, see (3.3.7)␊ |
| 118 | uint8_t␉␉␉BankConnCnt;␊ |
| 119 | ␊ |
| 120 | } RamSlotInfo_t;␊ |
| 121 | ␊ |
| 122 | typedef struct _PlatformInfo_t {␊ |
| 123 | ␉struct CPU {␊ |
| 124 | ␉␉uint32_t␉␉Features;␉␉␉␉// CPU Features like MMX, SSE2, VT, MobileCPU␊ |
| 125 | ␉␉uint32_t␉␉Vendor;␉␉␉␉␉// Vendor␊ |
| 126 | ␉␉uint32_t␉␉Signature;␉␉␉␉// Signature␊ |
| 127 | ␉␉uint32_t␉␉Stepping;␉␉␉␉// Stepping␊ |
| 128 | ␉␉uint32_t␉␉Model;␉␉␉␉␉// Model␊ |
| 129 | ␉␉uint32_t␉␉ExtModel;␉␉␉␉// Extended Model␊ |
| 130 | ␉␉uint32_t␉␉Family;␉␉␉␉␉// Family␊ |
| 131 | ␉␉uint32_t␉␉ExtFamily;␉␉␉␉// Extended Family␊ |
| 132 | ␉␉uint32_t␉␉NoCores;␉␉␉␉// No Cores per Package␊ |
| 133 | ␉␉uint32_t␉␉NoThreads;␉␉␉␉// Threads per Package␊ |
| 134 | ␉␉uint8_t␉␉␉MaxCoef;␉␉␉␉// Max Multiplier␊ |
| 135 | ␉␉uint8_t␉␉␉MaxDiv;␊ |
| 136 | ␉␉uint8_t␉␉␉CurrCoef;␉␉␉␉// Current Multiplier␊ |
| 137 | ␉␉uint8_t␉␉␉CurrDiv;␊ |
| 138 | ␉␉uint64_t␉␉TSCFrequency;␉␉␉// TSC Frequency Hz␊ |
| 139 | ␉␉uint64_t␉␉FSBFrequency;␉␉␉// FSB Frequency Hz␊ |
| 140 | ␉␉uint64_t␉␉CPUFrequency;␉␉␉// CPU Frequency Hz␊ |
| 141 | ␉␉char␉␉␉BrandString[48];␉␉// 48 Byte Branding String␊ |
| 142 | ␉␉uint32_t␉␉CPUID[CPUID_MAX][4];␉// CPUID 0..4, 80..81 Raw Values␊ |
| 143 | ␉} CPU;␊ |
| 144 | ␊ |
| 145 | ␉struct RAM {␊ |
| 146 | ␉␉uint64_t␉␉Frequency;␉␉␉␉// Ram Frequency␊ |
| 147 | ␉␉uint32_t␉␉Divider;␉␉␉␉// Memory divider␊ |
| 148 | ␉␉uint8_t␉␉␉CAS;␉␉␉␉␉// CAS 1/2/2.5/3/4/5/6/7␊ |
| 149 | ␉␉uint8_t␉␉␉TRC;␉␉␉␉␉␊ |
| 150 | ␉␉uint8_t␉␉␉TRP;␊ |
| 151 | ␉␉uint8_t␉␉␉RAS;␊ |
| 152 | ␉␉uint8_t␉␉␉Channels;␉␉␉␉// Channel Configuration Single,Dual or Triple␊ |
| 153 | ␉␉uint8_t␉␉␉NoSlots;␉␉␉␉// Maximum no of slots available␊ |
| 154 | ␉␉uint8_t␉␉␉Type;␉␉␉␉␉// Standard SMBIOS v2.5 Memory Type␊ |
| 155 | ␉␉RamSlotInfo_t␉DIMM[MAX_RAM_SLOTS];␉// Information about each slot␊ |
| 156 | ␉} RAM;␊ |
| 157 | ␊ |
| 158 | ␉struct DMI {␊ |
| 159 | ␉␉int␉␉␉MaxMemorySlots;␉␉␉␉// number of memory slots polulated by SMBIOS␊ |
| 160 | ␉␉int␉␉␉CntMemorySlots;␉␉␉␉// number of memory slots counted␊ |
| 161 | ␉␉int␉␉␉MemoryModules;␉␉␉␉// number of memory modules installed␊ |
| 162 | ␉␉int␉␉␉DIMM[MAX_RAM_SLOTS];␉␉// Information and SPD mapping for each slot␊ |
| 163 | ␉} DMI;␊ |
| 164 | ␉uint8_t␉␉␉␉Type;␉␉␉␉␉// System Type: 1=Desktop, 2=Portable... according ACPI2.0 (FACP: PM_Profile)␊ |
| 165 | } PlatformInfo_t;␊ |
| 166 | ␊ |
| 167 | extern PlatformInfo_t Platform;␊ |
| 168 | ␊ |
| 169 | #endif /* !__LIBSAIO_PLATFORM_H */␊ |
| 170 | |
