Chameleon

Chameleon Svn Source Tree

Root/branches/cparm/i386/libsaio/platform.h

1/*␊
2 * platform.h␊
3 * AsereBLN: reworked and extended␊
4 *␊
5 */␊
6␊
7#ifndef __LIBSAIO_PLATFORM_H␊
8#define __LIBSAIO_PLATFORM_H␊
9␊
10#include "libsaio.h"␊
11␊
12extern bool platformCPUFeature(uint32_t);␊
13extern void scan_platform(void);␊
14␊
15#define bit(n)␉␉␉(1UL << (n))␊
16#define bitmask(h,l)␉␉((bit(h)|(bit(h)-1)) & ~(bit(l)-1))␊
17#define bitfield(x,h,l)␉␉(((x) & bitmask(h,l)) >> l)␊
18␊
19␊
20/* CPUID index into cpuid_raw */␊
21#define CPUID_0␉␉␉␉0␊
22#define CPUID_1␉␉␉␉1␊
23#define CPUID_2␉␉␉␉2␊
24#define CPUID_3␉␉␉␉3␊
25#define CPUID_4␉␉␉␉4␊
26#define CPUID_80␉␉␉5␊
27#define CPUID_81␉␉␉6␊
28#define CPUID_MAX␉␉␉7␊
29␊
30#define CPU_MODEL_YONAH␉␉␉0x0E␊
31#define CPU_MODEL_MEROM␉␉␉0x0F␊
32#define CPU_MODEL_PENRYN␉␉0x17␊
33#define CPU_MODEL_NEHALEM␉␉0x1A␊
34#define CPU_MODEL_ATOM␉␉␉0x1C␊
35#define CPU_MODEL_FIELDS␉␉0x1E␉/* Lynnfield, Clarksfield, Jasper */␊
36#define CPU_MODEL_DALES␉␉␉0x1F␉/* Havendale, Auburndale */␊
37#define CPU_MODEL_DALES_32NM␉0x25␉/* Clarkdale, Arrandale */␊
38#define CPU_MODEL_WESTMERE␉␉0x2C␉/* Gulftown, Westmere-EP, Westmere-WS */␊
39#define CPU_MODEL_NEHALEM_EX␉0x2E␊
40#define CPU_MODEL_WESTMERE_EX␉0x2F␊
41␊
42/* CPU Features */␊
43// NOTE: Theses are currently mapped to the actual bit in the cpuid value␊
44#define CPU_FEATURE_MMX␉␉␉bit(23)␉␉// MMX Instruction Set␊
45#define CPU_FEATURE_SSE␉␉␉bit(25)␉␉// SSE Instruction Set␊
46#define CPU_FEATURE_SSE2␉␉bit(26)␉␉// SSE2 Instruction Set␊
47#define CPU_FEATURE_SSE3␉␉bit(0)␉␉// SSE3 Instruction Set␊
48#define CPU_FEATURE_SSE41␉␉bit(19)␉␉// SSE41 Instruction Set␊
49#define CPU_FEATURE_SSE42␉␉bit(20)␉␉// SSE42 Instruction Set␊
50#define CPU_FEATURE_EM64T␉␉bit(29)␉␉// 64Bit Support␊
51#define CPU_FEATURE_HTT␉␉␉bit(28)␉␉// HyperThreading␊
52#define CPU_FEATURE_MSR␉␉␉bit(5)␉␉// MSR Support␊
53␊
54// NOTE: Determine correct bit for bellow (28 is already in use)␊
55#define CPU_FEATURE_MOBILE␉␉bit(1)␉␉// Mobile CPU␊
56␊
57␊
58/* SMBIOS Memory Types */ ␊
59#define SMB_MEM_TYPE_UNDEFINED␉0␊
60#define SMB_MEM_TYPE_OTHER␉␉1␊
61#define SMB_MEM_TYPE_UNKNOWN␉2␊
62#define SMB_MEM_TYPE_DRAM␉␉3␊
63#define SMB_MEM_TYPE_EDRAM␉␉4␊
64#define SMB_MEM_TYPE_VRAM␉␉5␊
65#define SMB_MEM_TYPE_SRAM␉␉6␊
66#define SMB_MEM_TYPE_RAM␉␉7␊
67#define SMB_MEM_TYPE_ROM␉␉8␊
68#define SMB_MEM_TYPE_FLASH␉␉9␊
69#define SMB_MEM_TYPE_EEPROM␉␉10␊
70#define SMB_MEM_TYPE_FEPROM␉␉11␊
71#define SMB_MEM_TYPE_EPROM␉␉12␊
72#define SMB_MEM_TYPE_CDRAM␉␉13␊
73#define SMB_MEM_TYPE_3DRAM␉␉14␊
74#define SMB_MEM_TYPE_SDRAM␉␉15␊
75#define SMB_MEM_TYPE_SGRAM␉␉16␊
76#define SMB_MEM_TYPE_RDRAM␉␉17␊
77#define SMB_MEM_TYPE_DDR␉␉18␊
78#define SMB_MEM_TYPE_DDR2␉␉19␊
79#define SMB_MEM_TYPE_FBDIMM␉␉20␊
80#define SMB_MEM_TYPE_DDR3␉␉24␉␉␉// Supported in 10.5.6+ AppleSMBIOS␊
81␊
82/* Memory Configuration Types */ ␊
83#define SMB_MEM_CHANNEL_UNKNOWN␉␉0␊
84#define SMB_MEM_CHANNEL_SINGLE␉␉1␊
85#define SMB_MEM_CHANNEL_DUAL␉␉2␊
86#define SMB_MEM_CHANNEL_TRIPLE␉␉3␊
87␊
88/* Maximum number of ram slots */␊
89#define MAX_RAM_SLOTS␉␉␉8␊
90#define RAM_SLOT_ENUMERATOR␉␉{0, 2, 4, 1, 3, 5, 6, 8, 10, 7, 9, 11}␊
91␊
92/* Maximum number of SPD bytes */␊
93#define MAX_SPD_SIZE␉␉␉256␊
94␊
95/* Size of SMBIOS UUID in bytes */␊
96#define UUID_LEN␉␉␉16␊
97␊
98typedef struct _RamSlotInfo_t {␊
99 uint32_t␉␉ModuleSize;␉␉␉␉␉␉// Size of Module in MB␊
100 uint32_t␉␉Frequency; // in Mhz␊
101 const char*␉␉Vendor;␊
102 const char*␉␉PartNo;␊
103 const char*␉␉SerialNo;␊
104 char*␉␉␉spd;␉␉␉␉␉␉␉// SPD Dump␊
105 bool␉␉␉InUse;␊
106 uint8_t␉␉␉Type;␊
107 uint8_t␉␉␉BankConnections; // table type 6, see (3.3.7)␊
108 uint8_t␉␉␉BankConnCnt;␊
109␊
110} RamSlotInfo_t;␊
111␊
112typedef struct _PlatformInfo_t {␊
113␉struct CPU {␊
114␉␉uint32_t␉␉Features;␉␉// CPU Features like MMX, SSE2, VT, MobileCPU␊
115␉␉uint32_t␉␉Vendor;␉␉␉// Vendor␊
116␉␉uint32_t␉␉Signature;␉␉// Signature␊
117␉␉uint32_t␉␉Stepping;␉␉// Stepping␊
118␉␉uint32_t␉␉Model;␉␉␉// Model␊
119␉␉uint32_t␉␉ExtModel;␉␉// Extended Model␊
120␉␉uint32_t␉␉Family;␉␉␉// Family␊
121␉␉uint32_t␉␉ExtFamily;␉␉// Extended Family␊
122␉␉uint32_t␉␉NoCores;␉␉// No Cores per Package␊
123␉␉uint32_t␉␉NoThreads;␉␉// Threads per Package␊
124␉␉uint8_t␉␉␉MaxCoef;␉␉// Max Multiplier␊
125␉␉uint8_t␉␉␉MaxDiv;␊
126␉␉uint8_t␉␉␉CurrCoef;␉␉// Current Multiplier␊
127␉␉uint8_t␉␉␉CurrDiv;␊
128␉␉uint64_t␉␉TSCFrequency;␉␉// TSC Frequency Hz␊
129␉␉uint64_t␉␉FSBFrequency;␉␉// FSB Frequency Hz␊
130␉␉uint64_t␉␉CPUFrequency;␉␉// CPU Frequency Hz␊
131␉␉char␉␉␉BrandString[48];␉// 48 Byte Branding String␊
132␉␉uint32_t␉␉CPUID[CPUID_MAX][4];␉// CPUID 0..4, 80..81 Raw Values␊
133␉} CPU;␊
134␊
135␉struct RAM {␊
136␉␉uint64_t␉␉Frequency;␉␉␉␉// Ram Frequency␊
137␉␉uint32_t␉␉Divider;␉␉␉␉// Memory divider␊
138␉␉uint8_t␉␉␉CAS;␉␉␉␉␉// CAS 1/2/2.5/3/4/5/6/7␊
139␉␉uint8_t␉␉␉TRC;␉␉␉␉␉␊
140␉␉uint8_t␉␉␉TRP;␊
141␉␉uint8_t␉␉␉RAS;␊
142␉␉uint8_t␉␉␉Channels;␉␉␉␉// Channel Configuration Single,Dual or Triple␊
143␉␉uint8_t␉␉␉NoSlots;␉␉␉␉// Maximum no of slots available␊
144␉␉uint8_t␉␉␉Type;␉␉␉␉␉// Standard SMBIOS v2.5 Memory Type␊
145␉␉RamSlotInfo_t␉DIMM[MAX_RAM_SLOTS];␉// Information about each slot␊
146␉} RAM;␊
147␊
148␉struct DMI {␊
149␉␉int␉␉␉MaxMemorySlots;␉␉// number of memory slots polulated by SMBIOS␊
150␉␉int␉␉␉CntMemorySlots;␉␉// number of memory slots counted␊
151␉␉int␉␉␉MemoryModules;␉␉// number of memory modules installed␊
152␉␉int␉␉␉DIMM[MAX_RAM_SLOTS];␉// Information and SPD mapping for each slot␊
153␉} DMI;␊
154␉uint8_t␉␉␉␉Type;␉␉␉// System Type: 1=Desktop, 2=Portable... according ACPI2.0 (FACP: PM_Profile)␊
155␉uint8_t␉␉␉␉*UUID; // SMBios UUID␊
156␉//char␉␉␉␉*Name;␉␉␉// the Platorm/Product name ␊
157␉uint32_t␉␉␉hardware_signature;␊
158} PlatformInfo_t;␊
159␊
160extern PlatformInfo_t *Platform;␊
161#endif /* !__LIBSAIO_PLATFORM_H */␊
162

Archive Download this file

Revision: 789