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1/*␊
2 * spd.c - serial presence detect memory information␊
3 *␊
4 * Originally restored from pcefi10.5␊
5 * Dynamic mem detection original impl. by Rekursor␊
6 * System profiler fix and other fixes by Mozodojo.␊
7 */␊
8␊
9#include "libsaio.h"␊
10#include "pci.h"␊
11#include "platform.h"␊
12#include "spd.h"␊
13#include "saio_internal.h"␊
14#include "bootstruct.h"␊
15#include "memvendors.h"␊
16␊
17#ifndef DEBUG_SPD␊
18#define DEBUG_SPD 0␊
19#endif␊
20␊
21#if DEBUG_SPD␊
22#define DBG(x...)␉printf(x)␊
23#include "mem.h"␊
24#else␊
25#define DBG(x...)␊
26#endif␊
27␊
28const char *spd_memory_types[] =␊
29{␊
30␉"RAM", /* 00h Undefined */␊
31␉"FPM", /* 01h FPM */␊
32␉"EDO", /* 02h EDO */␊
33␉"",␉␉␉␉/* 03h PIPELINE NIBBLE */␊
34␉"SDRAM", /* 04h SDRAM */␊
35␉"",␉␉␉␉/* 05h MULTIPLEXED ROM */␊
36␉"DDR SGRAM",␉/* 06h SGRAM DDR */␊
37␉"DDR SDRAM",␉/* 07h SDRAM DDR */␊
38␉"DDR2 SDRAM", /* 08h SDRAM DDR 2 */␊
39␉"",␉␉␉␉/* 09h Undefined */␊
40␉"",␉␉␉␉/* 0Ah Undefined */␊
41␉"DDR3 SDRAM" /* 0Bh SDRAM DDR 3 */␊
42};␊
43␊
44#define UNKNOWN_MEM_TYPE 2␊
45uint8_t spd_mem_to_smbios[] =␊
46{␊
47␉UNKNOWN_MEM_TYPE, /* 00h Undefined */␊
48␉UNKNOWN_MEM_TYPE, /* 01h FPM */␊
49␉UNKNOWN_MEM_TYPE, /* 02h EDO */␊
50␉UNKNOWN_MEM_TYPE,␉ /* 03h PIPELINE NIBBLE */␊
51␉SMB_MEM_TYPE_SDRAM, /* 04h SDRAM */␊
52␉SMB_MEM_TYPE_ROM,␉ /* 05h MULTIPLEXED ROM */␊
53␉SMB_MEM_TYPE_SGRAM, /* 06h SGRAM DDR */␊
54␉SMB_MEM_TYPE_DDR, /* 07h SDRAM DDR */␊
55␉SMB_MEM_TYPE_DDR2, /* 08h SDRAM DDR 2 */␊
56␉UNKNOWN_MEM_TYPE, ␉ /* 09h Undefined */␊
57␉UNKNOWN_MEM_TYPE,␉ /* 0Ah Undefined */␊
58␉SMB_MEM_TYPE_DDR3 /* 0Bh SDRAM DDR 3 */␊
59};␊
60#define SPD_TO_SMBIOS_SIZE (sizeof(spd_mem_to_smbios)/sizeof(uint8_t))␊
61␊
62#define rdtsc(low,high) \␊
63__asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high))␊
64␊
65#define SMBHSTSTS 0␊
66#define SMBHSTCNT 2␊
67#define SMBHSTCMD 3␊
68#define SMBHSTADD 4␊
69#define SMBHSTDAT 5␊
70#define SBMBLKDAT 7␊
71␊
72/** Read one byte from the intel i2c, used for reading SPD on intel chipsets only. */␊
73unsigned char smb_read_byte_intel(uint32_t base, uint8_t adr, uint8_t cmd)␊
74{␊
75 int l1 = 0;␊
76␉int l2 = 0;␊
77␉int h1 = 0;␊
78␉int h2 = 0;␊
79 unsigned long long t;␊
80␉␊
81 outb(base + SMBHSTSTS, 0x1f);␉␉␉␉␉// reset SMBus Controller␊
82 outb(base + SMBHSTDAT, 0xff);␊
83␉␊
84 while( inb(base + SMBHSTSTS) & 0x01)␊
85␉{␊
86␉␉rdtsc(l2, h2);␊
87␉␉t = ((h2 - h1) * 0xffffffff + (l2 - l1)) / (Platform->CPU.TSCFrequency / 100);␊
88␉␉if(t > 50) return 0xFF;␉// hack, exit if unresponsive.␊
89␉}␊
90␉␊
91 outb(base + SMBHSTCMD, cmd);␊
92 outb(base + SMBHSTADD, (adr << 1) | 0x01 );␊
93 outb(base + SMBHSTCNT, 0x48 );␊
94␉␊
95 rdtsc(l1, h1);␊
96␉␊
97 ␉while (!( inb(base + SMBHSTSTS) & 0x02))␉␉// wait til command finished␊
98␉{␉␊
99␉␉rdtsc(l2, h2);␊
100␉␉t = ((h2 - h1) * 0xffffffff + (l2 - l1)) / (Platform->CPU.TSCFrequency / 100);␊
101␉␉if (t > 5)␊
102␉␉␉break;␉␉␉␉␉␉␉␉␉// break after 5ms␊
103 }␊
104 return inb(base + SMBHSTDAT);␊
105}␊
106␊
107/* SPD i2c read optimization: prefetch only what we need, read non prefetcheable bytes on the fly */␊
108#define READ_SPD(spd, base, slot, x) spd[x] = smb_read_byte_intel(base, 0x50 + slot, x)␊
109␊
110int spd_indexes[] = {␊
111␉SPD_MEMORY_TYPE,␊
112␉SPD_DDR3_MEMORY_BANK,␊
113␉SPD_DDR3_MEMORY_CODE,␊
114␉SPD_NUM_ROWS,␊
115␉SPD_NUM_COLUMNS,␊
116␉SPD_NUM_DIMM_BANKS,␊
117␉SPD_NUM_BANKS_PER_SDRAM,␊
118␉4,7,8,9,12,64, /* TODO: give names to these values */␊
119␉95,96,97,98, 122,123,124,125 /* UIS */␊
120};␊
121#define SPD_INDEXES_SIZE (sizeof(spd_indexes) / sizeof(int))␊
122␊
123/** Read from spd *used* values only*/␊
124static void init_spd(char * spd, uint32_t base, int slot)␊
125{␊
126␉int i;␊
127␉for (i=0; i< SPD_INDEXES_SIZE; i++) {␊
128␉␉READ_SPD(spd, base, slot, spd_indexes[i]);␊
129␉}␊
130}␊
131␊
132/** Get Vendor Name from spd, 2 cases handled DDR3 and DDR2, ␊
133 have different formats, always return a valid ptr.*/␊
134const char * getVendorName(RamSlotInfo_t* slot, uint32_t base, int slot_num)␊
135{␊
136 uint8_t bank = 0;␊
137 uint8_t code = 0;␊
138 int i = 0;␊
139 uint8_t * spd = (uint8_t *) slot->spd;␊
140␉␊
141 if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR3) { // DDR3␊
142 bank = (spd[SPD_DDR3_MEMORY_BANK] & 0x07f); // constructors like Patriot use b7=1␊
143 code = spd[SPD_DDR3_MEMORY_CODE];␊
144 for (i=0; i < VEN_MAP_SIZE; i++)␊
145 if (bank==vendorMap[i].bank && code==vendorMap[i].code)␊
146 return vendorMap[i].name;␊
147 }␊
148 else if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR2) {␊
149 if(spd[64]==0x7f) {␊
150 for (i=64; i<72 && spd[i]==0x7f;i++) {␊
151␉␉␉␉bank++;␊
152␉␉␉␉READ_SPD(spd, base, slot_num,i+1); // prefetch next spd byte to read for next loop␊
153␉␉␉}␊
154␉␉␉READ_SPD(spd, base, slot_num,i);␊
155 code = spd[i];␊
156 } else {␊
157 code = spd[64]; ␊
158 bank = 0;␊
159 }␊
160 for (i=0; i < VEN_MAP_SIZE; i++)␊
161 if (bank==vendorMap[i].bank && code==vendorMap[i].code)␊
162 return vendorMap[i].name;␊
163 }␊
164 /* OK there is no vendor id here lets try to match the partnum if it exists */␊
165 if (strstr(slot->PartNo,"GU332") == slot->PartNo) // Unifosa fingerprint␊
166 return "Unifosa";␊
167 return "NoName";␊
168}␊
169␊
170/** Get Default Memory Module Speed (no overclocking handled) */␊
171int getDDRspeedMhz(const char * spd)␊
172{␊
173 if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR3) { ␊
174 switch(spd[12]) {␊
175␉␉␉case 0x0f:␊
176␉␉␉␉return 1066;␊
177␉␉␉case 0x0c:␊
178␉␉␉␉return 1333;␊
179␉␉␉case 0x0a:␊
180␉␉␉␉return 1600;␊
181␉␉␉case 0x14:␊
182␉␉␉default:␊
183␉␉␉␉return 800;␊
184 }␊
185 } ␊
186 else if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR2) {␊
187 switch(spd[9]) {␊
188␉␉␉case 0x50:␊
189␉␉␉␉return 400;␊
190␉␉␉case 0x3d:␊
191␉␉␉␉return 533;␊
192␉␉␉case 0x30:␊
193␉␉␉␉return 667;␊
194␉␉␉case 0x25:␊
195␉␉␉default:␊
196␉␉␉␉return 800;␊
197 }␊
198 }␊
199 return 800; // default freq for unknown types␊
200}␊
201␊
202#define SMST(a) ((uint8_t)((spd[a] & 0xf0) >> 4))␊
203#define SLST(a) ((uint8_t)(spd[a] & 0x0f))␊
204␊
205/** Get DDR3 or DDR2 serial number, 0 most of the times, always return a valid ptr */␊
206char asciiSerial[16];␊
207const char *getDDRSerial(const char* spd)␊
208{␊
209 ␊
210 if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR3) // DDR3␊
211 {␊
212␉␉sprintf(asciiSerial, "%X%X%X%X%X%X%X%X", SMST(122) /*& 0x7*/, SLST(122), SMST(123), SLST(123), SMST(124), SLST(124), SMST(125), SLST(125));␊
213 }␊
214 else if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR2) // DDR2 or DDR␊
215 { ␊
216␉␉sprintf(asciiSerial, "%X%X%X%X%X%X%X%X", SMST(95) /*& 0x7*/, SLST(95), SMST(96), SLST(96), SMST(97), SLST(97), SMST(98), SLST(98));␊
217 }␊
218␉␊
219 return strdup(asciiSerial);␊
220}␊
221␊
222/** Get DDR3 or DDR2 Part Number, always return a valid ptr */␊
223char asciiPartNo[32];␊
224const char * getDDRPartNum(char* spd, uint32_t base, int slot)␊
225{␊
226␉int i, start=0, index = 0;␊
227␉␊
228 if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR3) {␊
229␉␉start = 128;␊
230␉}␊
231 else if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR2) {␊
232␉␉start = 73;␊
233␉}␊
234␉␊
235 // Check that the spd part name is zero terminated and that it is ascii:␊
236 bzero(asciiPartNo, sizeof(asciiPartNo));␊
237␉char c;␊
238␉for (i=start; i < start + sizeof(asciiPartNo); i++) {␊
239␉␉READ_SPD(spd, base, slot, i); // only read once the corresponding model part (ddr3 or ddr2)␊
240␉␉c = spd[i];␊
241␉␉if (isalpha(c) || isdigit(c) || ispunct(c)) // It seems that System Profiler likes only letters and digits...␊
242␉␉␉asciiPartNo[index++] = c;␊
243␉␉else if (!isascii(c))␊
244␉␉␉break;␊
245␉}␊
246␉␊
247␉return strdup(asciiPartNo);␊
248 return NULL;␊
249}␊
250␊
251int mapping []= {0,2,1,3,4,6,5,7,8,10,9,11};␊
252␊
253␊
254/** Read from smbus the SPD content and interpret it for detecting memory attributes */␊
255static void read_smb_intel(pci_dt_t *smbus_dev)␊
256{ ␊
257 int i, speed;␊
258 uint8_t spd_size, spd_type;␊
259 uint32_t base;␊
260 bool dump = false;␊
261 RamSlotInfo_t* slot;␊
262␉␊
263 base = pci_config_read16(smbus_dev->dev.addr, 0x20) & 0xFFFE;␊
264 DBG("Scanning smbus_dev <%04x, %04x> ...\n",smbus_dev->vendor_id, smbus_dev->device_id);␊
265␉␊
266 getBoolForKey("DumpSPD", &dump, &bootInfo->bootConfig);␊
267 bool fullBanks = // needed at least for laptops␊
268␉Platform->DMI.MemoryModules == Platform->DMI.MaxMemorySlots;␊
269␉// Search MAX_RAM_SLOTS slots␊
270␉char spdbuf[256];␊
271␉␊
272 for (i = 0; i < MAX_RAM_SLOTS; i++){␊
273␉␉DBG("Scanning slot %d\n", i);␊
274 slot = &Platform->RAM.DIMM[i];␊
275 spd_size = smb_read_byte_intel(base, 0x50 + i, 0);␊
276 // Check spd is present␊
277 if (spd_size && (spd_size != 0xff) ) {␊
278␉␉␉slot->spd = spdbuf;␊
279 slot->InUse = true;␊
280␉␉␉␊
281 bzero(slot->spd, spd_size);␊
282 ␊
283 // Copy spd data into buffer␊
284 ␊
285␉␉␉//for (x = 0; x < spd_size; x++) slot->spd[x] = smb_read_byte_intel(base, 0x50 + i, x);␊
286 init_spd(slot->spd, base, i);␊
287␉␉␉␊
288 switch (slot->spd[SPD_MEMORY_TYPE]) {␊
289␉␉␉␉case SPD_MEMORY_TYPE_SDRAM_DDR2:␊
290␉␉␉␉␉␊
291␉␉␉␉␉slot->ModuleSize = ((1 << (slot->spd[SPD_NUM_ROWS] & 0x0f) + (slot->spd[SPD_NUM_COLUMNS] & 0x0f) - 17) * ␊
292␉␉␉␉␉␉␉␉␉␉((slot->spd[SPD_NUM_DIMM_BANKS] & 0x7) + 1) * slot->spd[SPD_NUM_BANKS_PER_SDRAM]);␊
293␉␉␉␉␉break;␊
294␉␉␉␉␉␊
295␉␉␉␉case SPD_MEMORY_TYPE_SDRAM_DDR3:␊
296␉␉␉␉␉␊
297␉␉␉␉␉slot->ModuleSize = ((slot->spd[4] & 0x0f) + 28 ) + ((slot->spd[8] & 0x7) + 3 );␊
298␉␉␉␉␉slot->ModuleSize -= (slot->spd[7] & 0x7) + 25;␊
299␉␉␉␉␉slot->ModuleSize = ((1 << slot->ModuleSize) * (((slot->spd[7] >> 3) & 0x1f) + 1));␊
300␉␉␉␉␉␊
301␉␉␉␉␉break;␊
302 }␊
303 ␊
304 spd_type = (slot->spd[SPD_MEMORY_TYPE] < ((char) 12) ? slot->spd[SPD_MEMORY_TYPE] : 0);␊
305 slot->Type = spd_mem_to_smbios[spd_type];␊
306 slot->PartNo = getDDRPartNum(slot->spd, base, i);␊
307 slot->Vendor = getVendorName(slot, base, i);␊
308 slot->SerialNo = getDDRSerial(slot->spd);␊
309␉␉␉␊
310 // determine spd speed␊
311 speed = getDDRspeedMhz(slot->spd);␊
312 if (slot->Frequency<speed) slot->Frequency = speed;␊
313␉␉␉␊
314␉␉␉// pci memory controller if available, is more reliable␊
315␉␉␉if (Platform->RAM.Frequency > 0) {␊
316␉␉␉␉uint32_t freq = (uint32_t)Platform->RAM.Frequency / 500000;␊
317␉␉␉␉// now round off special cases␊
318␉␉␉␉uint32_t fmod100 = freq %100;␊
319␉␉␉␉switch(fmod100) {␊
320␉␉␉␉␉case 1:␉freq--;␉break;␊
321␉␉␉␉␉case 32:␉freq++;␉break;␊
322␉␉␉␉␉case 65:␉freq++; break;␊
323␉␉␉␉␉case 98:␉freq+=2;break;␊
324␉␉␉␉␉case 99:␉freq++; break;␊
325␉␉␉␉}␊
326␉␉␉␉slot->Frequency = freq;␊
327␉␉␉}␊
328␉␉␉␊
329␉␉␉verbose("Slot: %d Type %d %dMB (%s) %dMHz Vendor=%s\n PartNo=%s SerialNo=%s\n", ␊
330␉␉␉␉␉i, ␊
331␉␉␉␉␉(int)slot->Type,␊
332␉␉␉␉␉slot->ModuleSize, ␊
333␉␉␉␉␉spd_memory_types[spd_type],␊
334␉␉␉␉␉slot->Frequency,␊
335␉␉␉␉␉slot->Vendor,␊
336␉␉␉␉␉slot->PartNo,␊
337␉␉␉␉␉slot->SerialNo); ␊
338#if DEBUG_SPD␉␉␉␊
339␉␉␉␉dumpPhysAddr("spd content: ",slot->spd, spd_size);␊
340␉␉␉␉getc();␊
341#endif ␊
342 }␊
343 // laptops sometimes show slot 0 and 2 with slot 1 empty when only 2 slots are presents so:␊
344 Platform->DMI.DIMM[i]= ␊
345␉␉i>0 && Platform->RAM.DIMM[1].InUse==false && fullBanks && Platform->DMI.MaxMemorySlots==2 ? ␊
346␉␉mapping[i] : i; // for laptops case, mapping setup would need to be more generic than this␊
347 ␊
348␉␉slot->spd = NULL;␊
349␉␉␊
350 } // for␊
351}␊
352␊
353struct smbus_controllers_t smbus_controllers[] = {␊
354␉␊
355␉{0x8086, 0x269B, "ESB2", read_smb_intel },␊
356␉{0x8086, 0x25A4, "6300ESB", read_smb_intel },␊
357␉{0x8086, 0x24C3, "ICH4", read_smb_intel },␊
358␉{0x8086, 0x24D3, "ICH5", read_smb_intel },␊
359␉{0x8086, 0x266A, "ICH6", read_smb_intel },␊
360␉{0x8086, 0x27DA, "ICH7", read_smb_intel },␊
361␉{0x8086, 0x283E, "ICH8", read_smb_intel },␊
362␉{0x8086, 0x2930, "ICH9", read_smb_intel },␉␊
363␉{0x8086, 0x3A30, "ICH10R", read_smb_intel },␊
364␉{0x8086, 0x3A60, "ICH10B", read_smb_intel },␊
365␉{0x8086, 0x3B30, "P55", read_smb_intel },␊
366␉{0x8086, 0x5032, "EP80579", read_smb_intel }␊
367␉␊
368};␊
369␊
370␊
371bool is_smbus_controller(pci_dt_t* pci_dt)␊
372{␊
373␉int i = 0;␊
374␉for ( ; i < sizeof(smbus_controllers) / sizeof(smbus_controllers[0]); i++ )␊
375␉{␊
376␉␉if (pci_dt->vendor_id == smbus_controllers[i].vendor &&␊
377␉␉␉pci_dt->device_id == smbus_controllers[i].device)␊
378␉␉{␊
379␉␉␉return true;␊
380␉␉} ␊
381␉}␊
382␉return false;␊
383}␉␊
384␊
385void scan_spd(PlatformInfo_t *p, pci_dt_t* smbus_controller_dev)␊
386{␊
387␉int i = 0;␊
388␉for ( ; i < sizeof(smbus_controllers) / sizeof(smbus_controllers[0]); i++ )␊
389␉{␊
390␉␉if (smbus_controller_dev->vendor_id == smbus_controllers[i].vendor &&␊
391␉␉␉smbus_controller_dev->device_id == smbus_controllers[i].device)␊
392␉␉{␊
393␉␉␉smbus_controllers[i].read_smb(smbus_controller_dev); // read smb␊
394␉␉} ␊
395␉}␊
396}␊
397

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