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Root/trunk/i386/libsaio/nvidia.c

1/*␊
2 * NVidia injector␊
3 *␊
4 * Copyright (C) 2009 Jasmin Fazlic, iNDi␊
5 *␊
6 * NVidia injector is free software: you can redistribute it and/or modify␊
7 * it under the terms of the GNU General Public License as published by␊
8 * the Free Software Foundation, either version 3 of the License, or␊
9 * (at your option) any later version.␊
10 *␊
11 * NVidia driver and injector is distributed in the hope that it will be useful,␊
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of␊
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the␊
14 * GNU General Public License for more details.␊
15 *␊
16 * You should have received a copy of the GNU General Public License␊
17 * along with NVidia injector. If not, see <http://www.gnu.org/licenses/>.␊
18 */ ␊
19/*␊
20 * Alternatively you can choose to comply with APSL␊
21 */␊
22 ␊
23 ␊
24/*␊
25 * DCB-Table parsing is based on software (nouveau driver) originally distributed under following license:␊
26 *␊
27 *␊
28 * Copyright 2005-2006 Erik Waling␊
29 * Copyright 2006 Stephane Marchesin␊
30 * Copyright 2007-2009 Stuart Bennett␊
31 *␊
32 * Permission is hereby granted, free of charge, to any person obtaining a␊
33 * copy of this software and associated documentation files (the "Software"),␊
34 * to deal in the Software without restriction, including without limitation␊
35 * the rights to use, copy, modify, merge, publish, distribute, sublicense,␊
36 * and/or sell copies of the Software, and to permit persons to whom the␊
37 * Software is furnished to do so, subject to the following conditions:␊
38 *␊
39 * The above copyright notice and this permission notice shall be included in␊
40 * all copies or substantial portions of the Software.␊
41 *␊
42 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR␊
43 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,␊
44 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL␊
45 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,␊
46 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF␊
47 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE␊
48 * SOFTWARE.␊
49 */␊
50␊
51#include "libsaio.h"␊
52#include "bootstruct.h"␊
53#include "pci.h"␊
54#include "platform.h"␊
55#include "device_inject.h"␊
56#include "nvidia.h"␊
57␊
58#ifndef DEBUG_NVIDIA␊
59#define DEBUG_NVIDIA 0␊
60#endif␊
61␊
62#if DEBUG_NVIDIA␊
63#define DBG(x...)␉printf(x)␊
64#else␊
65#define DBG(x...)␊
66#endif␊
67␊
68#define PATCH_ROM_SUCCESS 1␊
69#define PATCH_ROM_SUCCESS_HAS_LVDS 2␊
70#define PATCH_ROM_FAILED 0␊
71#define MAX_NUM_DCB_ENTRIES 16␊
72␊
73#define TYPE_GROUPED 0xff␊
74␊
75extern uint32_t devices_number;␊
76␊
77const char *nvidia_compatible_0[]␉=␉{ "@0,compatible",␉"NVDA,NVMac"␉␉};␊
78const char *nvidia_compatible_1[]␉=␉{ "@1,compatible",␉"NVDA,NVMac"␉␉};␊
79const char *nvidia_device_type_0[]␉=␉{ "@0,device_type",␉"display"␉␉␉};␊
80const char *nvidia_device_type_1[]␉=␉{ "@1,device_type",␉"display"␉␉␉};␊
81const char *nvidia_device_type[]␉=␉{ "device_type",␉"NVDA,Parent"␉␉};␊
82const char *nvidia_name_0[]␉␉␉=␉{ "@0,name",␉␉"NVDA,Display-A"␉};␊
83const char *nvidia_name_1[]␉␉␉=␉{ "@1,name",␉␉"NVDA,Display-B"␉};␊
84const char *nvidia_slot_name[]␉␉=␉{ "AAPL,slot-name",␉␉"Slot-1"};␊
85␊
86uint8_t default_NVCAP[]= {␉␊
870x04, 0x00, 0x00, 0x00,␊
880x00, 0x00, 0x0d, 0x00,␊
890x00, 0x00, 0x00, 0x00,␊
900x00, 0x00, 0x00, 0x0a,␊
910x00, 0x00, 0x00, 0x00␊
92};␊
93␊
94uint16_t swap16(uint16_t toswap) {␊
95␉return (((toswap & 0x00FF) << 8) | ((toswap & 0xFF00) >> 8));␊
96}␊
97␊
98// Known cards as of 2008/08/26␊
99static struct nv_chipsets_t NVKnownChipsets[] = {␊
100␉{ 0x00000000, "Unknown" },␊
101␉{ 0x10DE0301, "GeForce FX 5800 Ultra" },␊
102␉{ 0x10DE0302, "GeForce FX 5800" },␊
103␉{ 0x10DE0308, "Quadro FX 2000" },␊
104␉{ 0x10DE0309, "Quadro FX 1000" },␊
105␉{ 0x10DE0311, "GeForce FX 5600 Ultra" },␊
106␉{ 0x10DE0312, "GeForce FX 5600" },␊
107␉{ 0x10DE0314, "GeForce FX 5600XT" },␊
108␉{ 0x10DE031A, "GeForce FX Go5600" },␊
109␉{ 0x10DE031B, "GeForce FX Go5650" },␊
110␉{ 0x10DE031C, "Quadro FX Go700" },␊
111␉{ 0x10DE0324, "GeForce FX Go5200" },␊
112␉{ 0x10DE0325, "GeForce FX Go5250" },␊
113␉{ 0x10DE0326, "GeForce FX 5500" },␊
114␉{ 0x10DE0328, "GeForce FX Go5200 32M/64M" },␊
115␉{ 0x10DE032A, "Quadro NVS 55/280 PCI" },␊
116␉{ 0x10DE032B, "Quadro FX 500/600 PCI" },␊
117␉{ 0x10DE032C, "GeForce FX Go53xx Series" },␊
118␉{ 0x10DE032D, "GeForce FX Go5100" },␊
119␉{ 0x10DE0330, "GeForce FX 5900 Ultra" },␊
120␉{ 0x10DE0331, "GeForce FX 5900" },␊
121␉{ 0x10DE0332, "GeForce FX 5900XT" },␊
122␉{ 0x10DE0333, "GeForce FX 5950 Ultra" },␊
123␉{ 0x10DE0334, "GeForce FX 5900ZT" },␊
124␉{ 0x10DE0338, "Quadro FX 3000" },␊
125␉{ 0x10DE033F, "Quadro FX 700" },␊
126␉{ 0x10DE0341, "GeForce FX 5700 Ultra" },␊
127␉{ 0x10DE0342, "GeForce FX 5700" },␊
128␉{ 0x10DE0343, "GeForce FX 5700LE" },␊
129␉{ 0x10DE0344, "GeForce FX 5700VE" },␊
130␉{ 0x10DE0347, "GeForce FX Go5700" },␊
131␉{ 0x10DE0348, "GeForce FX Go5700" },␊
132␉{ 0x10DE034C, "Quadro FX Go1000" },␊
133␉{ 0x10DE034E, "Quadro FX 1100" },␊
134␉{ 0x10DE0040, "GeForce 6800 Ultra" },␊
135␉{ 0x10DE0041, "GeForce 6800" },␊
136␉{ 0x10DE0042, "GeForce 6800 LE" },␊
137␉{ 0x10DE0043, "GeForce 6800 XE" },␊
138␉{ 0x10DE0044, "GeForce 6800 XT" },␊
139␉{ 0x10DE0045, "GeForce 6800 GT" },␊
140␉{ 0x10DE0046, "GeForce 6800 GT" },␊
141␉{ 0x10DE0047, "GeForce 6800 GS" },␊
142␉{ 0x10DE0048, "GeForce 6800 XT" },␊
143␉{ 0x10DE004E, "Quadro FX 4000" },␊
144␉{ 0x10DE00C0, "GeForce 6800 GS" },␊
145␉{ 0x10DE00C1, "GeForce 6800" },␊
146␉{ 0x10DE00C2, "GeForce 6800 LE" },␊
147␉{ 0x10DE00C3, "GeForce 6800 XT" },␊
148␉{ 0x10DE00C8, "GeForce Go 6800" },␊
149␉{ 0x10DE00C9, "GeForce Go 6800 Ultra" },␊
150␉{ 0x10DE00CC, "Quadro FX Go1400" },␊
151␉{ 0x10DE00CD, "Quadro FX 3450/4000 SDI" },␊
152␉{ 0x10DE00CE, "Quadro FX 1400" },␊
153␉{ 0x10DE0140, "GeForce 6600 GT" },␊
154␉{ 0x10DE0141, "GeForce 6600" },␊
155␉{ 0x10DE0142, "GeForce 6600 LE" },␊
156␉{ 0x10DE0143, "GeForce 6600 VE" },␊
157␉{ 0x10DE0144, "GeForce Go 6600" },␊
158␉{ 0x10DE0145, "GeForce 6610 XL" },␊
159␉{ 0x10DE0146, "GeForce Go 6600 TE/6200 TE" },␊
160␉{ 0x10DE0147, "GeForce 6700 XL" },␊
161␉{ 0x10DE0148, "GeForce Go 6600" },␊
162␉{ 0x10DE0149, "GeForce Go 6600 GT" },␊
163␉{ 0x10DE014C, "Quadro FX 550" },␊
164␉{ 0x10DE014D, "Quadro FX 550" },␊
165␉{ 0x10DE014E, "Quadro FX 540" },␊
166␉{ 0x10DE014F, "GeForce 6200" },␊
167␉{ 0x10DE0160, "GeForce 6500" },␊
168␉{ 0x10DE0161, "GeForce 6200 TurboCache(TM)" },␊
169␉{ 0x10DE0162, "GeForce 6200SE TurboCache(TM)" },␊
170␉{ 0x10DE0163, "GeForce 6200 LE" },␊
171␉{ 0x10DE0164, "GeForce Go 6200" },␊
172␉{ 0x10DE0165, "Quadro NVS 285" },␊
173␉{ 0x10DE0166, "GeForce Go 6400" },␊
174␉{ 0x10DE0167, "GeForce Go 6200" },␊
175␉{ 0x10DE0168, "GeForce Go 6400" },␊
176␉{ 0x10DE0169, "GeForce 6250" },␊
177␉{ 0x10DE016A, "GeForce 7100 GS" },␊
178␉{ 0x10DE0211, "GeForce 6800" },␊
179␉{ 0x10DE0212, "GeForce 6800 LE" },␊
180␉{ 0x10DE0215, "GeForce 6800 GT" },␊
181␉{ 0x10DE0218, "GeForce 6800 XT" },␊
182␉{ 0x10DE0221, "GeForce 6200" },␊
183␉{ 0x10DE0222, "GeForce 6200 A-LE" },␊
184␉{ 0x10DE0090, "GeForce 7800 GTX" },␊
185␉{ 0x10DE0091, "GeForce 7800 GTX" },␊
186␉{ 0x10DE0092, "GeForce 7800 GT" },␊
187␉{ 0x10DE0093, "GeForce 7800 GS" },␊
188␉{ 0x10DE0095, "GeForce 7800 SLI" },␊
189␉{ 0x10DE0098, "GeForce Go 7800" },␊
190␉{ 0x10DE0099, "GeForce Go 7800 GTX" },␊
191␉{ 0x10DE009D, "Quadro FX 4500" },␊
192␉{ 0x10DE01D1, "GeForce 7300 LE" },␊
193␉{ 0x10DE01D3, "GeForce 7300 SE" },␊
194␉{ 0x10DE01D6, "GeForce Go 7200" },␊
195␉{ 0x10DE01D7, "GeForce Go 7300" },␊
196␉{ 0x10DE01D8, "GeForce Go 7400" },␊
197␉{ 0x10DE01D9, "GeForce Go 7400 GS" },␊
198␉{ 0x10DE01DA, "Quadro NVS 110M" },␊
199␉{ 0x10DE01DB, "Quadro NVS 120M" },␊
200␉{ 0x10DE01DC, "Quadro FX 350M" },␊
201␉{ 0x10DE01DD, "GeForce 7500 LE" },␊
202␉{ 0x10DE01DE, "Quadro FX 350" },␊
203␉{ 0x10DE01DF, "GeForce 7300 GS" },␊
204␉{ 0x10DE0391, "GeForce 7600 GT" },␊
205␉{ 0x10DE0392, "GeForce 7600 GS" },␊
206␉{ 0x10DE0393, "GeForce 7300 GT" },␊
207␉{ 0x10DE0394, "GeForce 7600 LE" },␊
208␉{ 0x10DE0395, "GeForce 7300 GT" },␊
209␉{ 0x10DE0397, "GeForce Go 7700" },␊
210␉{ 0x10DE0398, "GeForce Go 7600" },␊
211␉{ 0x10DE0399, "GeForce Go 7600 GT"},␊
212␉{ 0x10DE039A, "Quadro NVS 300M" },␊
213␉{ 0x10DE039B, "GeForce Go 7900 SE" },␊
214␉{ 0x10DE039C, "Quadro FX 550M" },␊
215␉{ 0x10DE039E, "Quadro FX 560" },␊
216␉{ 0x10DE0290, "GeForce 7900 GTX" },␊
217␉{ 0x10DE0291, "GeForce 7900 GT" },␊
218␉{ 0x10DE0292, "GeForce 7900 GS" },␊
219␉{ 0x10DE0298, "GeForce Go 7900 GS" },␊
220␉{ 0x10DE0299, "GeForce Go 7900 GTX" },␊
221␉{ 0x10DE029A, "Quadro FX 2500M" },␊
222␉{ 0x10DE029B, "Quadro FX 1500M" },␊
223␉{ 0x10DE029C, "Quadro FX 5500" },␊
224␉{ 0x10DE029D, "Quadro FX 3500" },␊
225␉{ 0x10DE029E, "Quadro FX 1500" },␊
226␉{ 0x10DE029F, "Quadro FX 4500 X2" },␊
227␉{ 0x10DE0240, "GeForce 6150" },␊
228␉{ 0x10DE0241, "GeForce 6150 LE" },␊
229␉{ 0x10DE0242, "GeForce 6100" },␊
230␉{ 0x10DE0244, "GeForce Go 6150" },␊
231␉{ 0x10DE0247, "GeForce Go 6100" },␊
232␊
233␉/*************** G8x ***************/␊
234␉{ 0x10DE0191, "GeForce 8800 GTX" },␊
235␉{ 0x10DE0193, "GeForce 8800 GTS" },␊
236␉{ 0x10DE0194, "GeForce 8800 Ultra" },␊
237␉{ 0x10DE019D, "Quadro FX 5600" },␊
238␉{ 0x10DE019E, "Quadro FX 4600" },␊
239␉{ 0x10DE0400, "GeForce 8600 GTS" },␊
240␉{ 0x10DE0401, "GeForce 8600 GT" },␊
241␉{ 0x10DE0402, "GeForce 8600 GT" },␊
242␉{ 0x10DE0403, "GeForce 8600 GS" },␊
243␉{ 0x10DE0404, "GeForce 8400 GS" },␊
244␉{ 0x10DE0405, "GeForce 9500M GS" },␊
245␉{ 0x10DE0407, "GeForce 8600M GT" },␊
246␉{ 0x10DE0408, "GeForce 9650M GS" },␊
247␉{ 0x10DE0409, "GeForce 8700M GT" },␊
248␉{ 0x10DE040A, "Quadro FX 370" },␊
249␉{ 0x10DE040B, "Quadro NVS 320M" },␊
250␉{ 0x10DE040C, "Quadro FX 570M" },␊
251␉{ 0x10DE040D, "Quadro FX 1600M" },␊
252␉{ 0x10DE040E, "Quadro FX 570" },␊
253␉{ 0x10DE040F, "Quadro FX 1700" },␊
254␉{ 0x10DE0420, "GeForce 8400 SE" },␊
255␉{ 0x10DE0421, "GeForce 8500 GT" },␊
256␉{ 0x10DE0422, "GeForce 8400 GS" },␊
257␉{ 0x10DE0423, "GeForce 8300 GS" },␊
258␉{ 0x10DE0424, "GeForce 8400 GS" },␊
259␉{ 0x10DE0425, "GeForce 8600M GS" },␊
260␉{ 0x10DE0426, "GeForce 8400M GT" },␊
261␉{ 0x10DE0427, "GeForce 8400M GS" },␊
262␉{ 0x10DE0428, "GeForce 8400M G" },␊
263␉{ 0x10DE0429, "Quadro NVS 140M" },␊
264␉{ 0x10DE042A, "Quadro NVS 130M" },␊
265␉{ 0x10DE042B, "Quadro NVS 135M" },␊
266␉{ 0x10DE042C, "GeForce 9400 GT" },␊
267␉{ 0x10DE042D, "Quadro FX 360M" },␊
268␉{ 0x10DE042E, "GeForce 9300M G" },␊
269␉{ 0x10DE042F, "Quadro NVS 290" },␊
270␉{ 0x10DE05E1, "GeForce GTX 280" },␊
271␉{ 0x10DE05E2, "GeForce GTX 260" },␊
272␉{ 0x10DE0600, "GeForce 8800 GTS 512" },␊
273␉{ 0x10DE0602, "GeForce 8800 GT" },␊
274␉{ 0x10DE0604, "GeForce 9800 GX2" },␊
275␉{ 0x10DE0605, "GeForce 9800 GT" },␊
276␉{ 0x10DE0606, "GeForce 8800 GS" },␊
277␉{ 0x10DE0609, "GeForce 8800M GTS" },␊
278␉{ 0x10DE060C, "GeForce 8800M GTX" },␊
279␉{ 0x10DE060D, "GeForce 8800 GS" },␊
280␉{ 0x10DE0610, "GeForce 9600 GSO" },␊
281␉{ 0x10DE0611, "GeForce 8800 GT" },␊
282␉{ 0x10DE0612, "GeForce 9800 GTX" },␊
283␉{ 0x10DE0613, "GeForce 9800 GTX+" },␊
284␉{ 0x10DE0614, "GeForce 9800 GT" },␊
285␉{ 0x10DE0615, "GeForce 250 GTS" },␊
286␉{ 0x10DE061A, "Quadro FX 3700" },␊
287␉{ 0x10DE061C, "Quadro FX 3600M" },␊
288␉{ 0x10DE0622, "GeForce 9600 GT" },␊
289␉{ 0x10DE0623, "GeForce 9600 GS" },␊
290␉{ 0x10DE0628, "GeForce 9800M GTS" },␊
291␉{ 0x10DE062A, "GeForce 9700M GTS" },␊
292␉{ 0x10DE062C, "GeForce 9800M GTS" },␊
293␉{ 0x10DE0640, "GeForce 9500 GT" },␊
294␉{ 0x10DE0647, "GeForce 9600M GT" },␊
295␉{ 0x10DE0648, "GeForce 9600M GS" },␊
296␉{ 0x10DE0649, "GeForce 9600M GT" },␊
297␉{ 0x10DE064B, "GeForce 9500M G" },␊
298␉{ 0x10DE065B, "GeForce 9400 GT" },␊
299␉{ 0x10DE06E1, "GeForce 9300 GS" },␊
300␉{ 0x10DE06E4, "GeForce 8400 GS" },␊
301␉{ 0x10DE06E5, "GeForce 9300M GS" },␊
302␉{ 0x10DE06E8, "GeForce 9200M GS" },␊
303␉{ 0x10DE06E9, "GeForce 9300M GS" },␊
304␉{ 0x10DE06EA, "Quadro NVS 150M" },␊
305␉{ 0x10DE06EB, "Quadro NVS 160M" },␊
306␊
307␉/*************** GT2xx *************/␊
308␉{ 0x10DE05E0, "GeForce GTX 295" },␊
309␉{ 0x10DE05E1, "GeForce GTX 280" },␊
310␉{ 0x10DE05E2, "GeForce GTX 260" },␊
311␉{ 0x10DE05E3, "GeForce GTX 285" },␊
312␉{ 0x10DE05E6, "GeForce GTX 275" },␊
313};␊
314␊
315uint32_t swap32(uint32_t toswap) {␊
316␉return ((toswap & 0x000000FF) << 24) |␊
317␉((toswap & 0x0000FF00) << 8 ) |␊
318␉((toswap & 0x00FF0000) >> 8 ) |␊
319␉((toswap & 0xFF000000) >> 24);␊
320}␉␊
321␊
322uint8_t read8(uint8_t *ptr, uint16_t offset) { ␊
323␉return ptr[offset];␊
324}␊
325␊
326uint16_t read16(uint8_t *ptr, uint16_t offset) {␊
327␉uint8_t ret[2];␊
328␉ret[0] = ptr[offset+1];␊
329␉ret[1] = ptr[offset];␊
330␉return *((uint16_t*)&ret);␊
331}␊
332␊
333uint32_t read32(uint8_t *ptr, uint16_t offset) {␊
334␉uint8_t ret[4];␊
335␉ret[0] = ptr[offset+3];␊
336␉ret[1] = ptr[offset+2];␊
337␉ret[2] = ptr[offset+1];␊
338␉ret[3] = ptr[offset];␊
339␉return *((uint32_t*)&ret);␊
340}␊
341 ␊
342int patch_nvidia_rom(uint8_t *rom) {␊
343␉if(!rom || (rom[0] != 0x55 && rom[1] != 0xaa)) {␊
344␉␉printf("False ROM signature: 0x%02x%02x\n", rom[0], rom[1]);␊
345␉␉return PATCH_ROM_FAILED;␊
346␉}␊
347␉␊
348␉uint16_t dcbptr = swap16(read16(rom, 0x36));␊
349␉if(!dcbptr) {␊
350␉␉printf("no dcb table found\n");␊
351␉␉return PATCH_ROM_FAILED;␊
352␉}/* else␊
353␉ printf("dcb table at offset 0x%04x\n", dcbptr);␊
354␉ */␊
355␉uint8_t *dcbtable = &rom[dcbptr];␊
356␉uint8_t dcbtable_version = dcbtable[0];␊
357␉uint8_t headerlength = 0;␊
358␉uint8_t recordlength = 0;␊
359␉uint8_t numentries = 0;␊
360␉␊
361␉if(dcbtable_version >= 0x20) {␊
362␉␉uint32_t sig;␊
363␉␉␊
364␉␉if(dcbtable_version >= 0x30) {␊
365␉␉␉headerlength = dcbtable[1];␊
366␉␉␉numentries = dcbtable[2];␊
367␉␉␉recordlength = dcbtable[3];␊
368␉␉␉sig = *(uint32_t *)&dcbtable[6];␊
369␉␉} else {␊
370␉␉␉sig = *(uint32_t *)&dcbtable[4];␊
371␉␉␉headerlength = 8;␊
372␉␉}␊
373␉␉if (sig != 0x4edcbdcb) {␊
374␉␉␉printf("bad display config block signature (0x%8x)\n", sig);␊
375␉␉␉return PATCH_ROM_FAILED;␊
376␉␉}␊
377␉} else if (dcbtable_version >= 0x14) { /* some NV15/16, and NV11+ */␊
378␉␉char sig[8] = { 0 };␊
379␉␉␊
380␉␉strncpy(sig, (char *)&dcbtable[-7], 7);␊
381␉␉recordlength = 10;␊
382␉␉if (strcmp(sig, "DEV_REC")) {␊
383␉␉␉printf("Bad Display Configuration Block signature (%s)\n", sig);␊
384␉␉␉return PATCH_ROM_FAILED;␊
385␉␉}␊
386␉} else {␊
387␉␉return PATCH_ROM_FAILED;␊
388␉}␊
389␉␊
390␉if(numentries >= MAX_NUM_DCB_ENTRIES)␊
391␉␉numentries = MAX_NUM_DCB_ENTRIES;␊
392␉␊
393␉uint8_t num_outputs = 0, i=0;␊
394␉struct dcbentry {␊
395␉␉uint8_t type;␊
396␉␉uint8_t index;␊
397␉␉uint8_t *heads;␊
398␉} entries[numentries];␊
399␉␊
400␉for (i = 0; i < numentries; i++) {␊
401␉␉uint32_t connection;␊
402␉␉connection = *(uint32_t *)&dcbtable[headerlength + recordlength * i];␊
403␉␉/* Should we allow discontinuous DCBs? Certainly DCB I2C tables can be discontinuous */␊
404␉␉if ((connection & 0x0000000f) == 0x0000000f) /* end of records */ ␊
405␉␉␉continue;␊
406␉␉if (connection == 0x00000000) /* seen on an NV11 with DCB v1.5 */ ␊
407␉␉␉continue;␊
408␉␉if ((connection & 0xf) == 0x6) /* we skip type 6 as it doesnt appear on macbook nvcaps */␊
409␉␉␉continue;␊
410␉␉␊
411␉␉entries[num_outputs].type = connection & 0xf;␊
412␉␉entries[num_outputs].index = num_outputs;␊
413␉␉entries[num_outputs++].heads = (uint8_t*)&(dcbtable[(headerlength + recordlength * i) + 1]);␊
414␊
415␉}␊
416␉␊
417␉int has_lvds = false;␊
418␉uint8_t channel1 = 0, channel2 = 0;␊
419␉␊
420␉for(i=0; i<num_outputs; i++) {␊
421␉␉if(entries[i].type == 3) {␊
422␉␉␉has_lvds = true;␊
423␉␉␉//printf("found LVDS\n");␊
424␉␉␉channel1 |= ( 0x1 << entries[i].index);␊
425␉␉␉entries[i].type = TYPE_GROUPED;␊
426␉␉}␊
427␉}␊
428␉// if we have a LVDS output, we group the rest to the second channel␊
429␉if(has_lvds) {␊
430␉␉for(i=0; i<num_outputs; i++) {␊
431␉␉␉if(entries[i].type == TYPE_GROUPED)␊
432␉␉␉␉continue;␊
433␉␉␉channel2 |= ( 0x1 << entries[i].index);␊
434␉␉␉entries[i].type = TYPE_GROUPED;␊
435␉␉}␊
436␉} else {␊
437␉␉//␊
438␉␉int x;␊
439␉␉// we loop twice as we need to generate two channels␊
440␉␉for(x=0; x<=1; x++) {␊
441␉␉␉for(i=0; i<num_outputs; i++) {␊
442␉␉␉␉if(entries[i].type == TYPE_GROUPED)␊
443␉␉␉␉␉continue;␊
444␉␉␉␉// if type is TMDS, the prior output is ANALOG␊
445␉␉␉␉// we always group ANALOG and TMDS␊
446␉␉␉␉// if there is a TV output after TMDS, we group it to that channel as well␊
447␉␉␉␉if(i && entries[i].type == 0x2) {␊
448␉␉␉␉␉switch (x) {␊
449␉␉␉␉␉␉case 0:␊
450␉␉␉␉␉␉␉//printf("group channel 1\n");␊
451␉␉␉␉␉␉␉channel1 |= ( 0x1 << entries[i].index);␊
452␉␉␉␉␉␉␉entries[i].type = TYPE_GROUPED;␊
453␉␉␉␉␉␉␉if((entries[i-1].type == 0x0)) {␊
454␉␉␉␉␉␉␉␉channel1 |= ( 0x1 << entries[i-1].index);␊
455␉␉␉␉␉␉␉␉entries[i-1].type = TYPE_GROUPED;␊
456␉␉␉␉␉␉␉}␊
457␉␉␉␉␉␉␉// group TV as well if there is one␊
458␉␉␉␉␉␉␉if( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) ) {␊
459␉␉␉␉␉␉␉␉//␉printf("group tv1\n");␊
460␉␉␉␉␉␉␉␉channel1 |= ( 0x1 << entries[i+1].index);␊
461␉␉␉␉␉␉␉␉entries[i+1].type = TYPE_GROUPED;␊
462␉␉␉␉␉␉␉}␊
463␉␉␉␉␉␉␉break;␊
464␉␉␉␉␉␉case 1:␊
465␉␉␉␉␉␉␉//printf("group channel 2 : %d\n", i);␊
466␉␉␉␉␉␉␉channel2 |= ( 0x1 << entries[i].index);␊
467␉␉␉␉␉␉␉entries[i].type = TYPE_GROUPED;␊
468␉␉␉␉␉␉␉if((entries[i-1].type == 0x0)) {␊
469␉␉␉␉␉␉␉␉channel2 |= ( 0x1 << entries[i-1].index);␊
470␉␉␉␉␉␉␉␉entries[i-1].type = TYPE_GROUPED;␊
471␉␉␉␉␉␉␉}␊
472␉␉␉␉␉␉␉// group TV as well if there is one␊
473␉␉␉␉␉␉␉if( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) ) {␊
474␉␉␉␉␉␉␉␉//␉printf("group tv2\n");␊
475␉␉␉␉␉␉␉␉channel2 |= ( 0x1 << entries[i+1].index);␊
476␉␉␉␉␉␉␉␉entries[i+1].type = TYPE_GROUPED;␊
477␉␉␉␉␉␉␉}␊
478␉␉␉␉␉␉␉break;␊
479␉␉␉␉␉␉␉␊
480␉␉␉␉␉}␊
481␉␉␉␉␉break;␊
482␉␉␉␉}␊
483␉␉␉}␊
484␉␉}␊
485␉}␊
486␉␊
487␉// if we have left ungrouped outputs merge them to the empty channel␊
488␉uint8_t *togroup;// = (channel1 ? (channel2 ? NULL : &channel2) : &channel1);␊
489␉togroup = &channel2;␊
490␉for(i=0; i<num_outputs;i++)␊
491␉␉if(entries[i].type != TYPE_GROUPED) {␊
492␉␉␉//printf("%d not grouped\n", i);␊
493␉␉␉if(togroup)␊
494␉␉␉␉*togroup |= ( 0x1 << entries[i].index);␊
495␉␉␉entries[i].type = TYPE_GROUPED;␊
496␉␉}␊
497␉␊
498␉if(channel1 > channel2) {␊
499␉␉uint8_t buff = channel1;␊
500␉␉channel1 = channel2;␊
501␉␉channel2 = buff;␊
502␉}␊
503␉␊
504␉default_NVCAP[6] = channel1;␊
505␉default_NVCAP[8] = channel2;␊
506␉␊
507␉// patching HEADS␊
508␉for(i=0; i<num_outputs;i++) {␊
509␉␉if(channel1 & (1 << i))␊
510␉␉␉*entries[i].heads = 1;␊
511␉␉else if(channel2 & (1 << i))␊
512␉␉␉*entries[i].heads = 2;␊
513␉}␊
514␉␊
515␉return (has_lvds ? PATCH_ROM_SUCCESS_HAS_LVDS : PATCH_ROM_SUCCESS);␊
516}␊
517␊
518char *get_nvidia_model(uint32_t id) {␊
519␉int i=0;␊
520␉for(i = 0; i < (sizeof(NVKnownChipsets) / sizeof(NVKnownChipsets[0])); i++) {␊
521␉␉if(NVKnownChipsets[i].device == id)␊
522␉␉␉return NVKnownChipsets[i].name;␊
523␉}␊
524␉return NVKnownChipsets[0].name;␊
525}␊
526␊
527uint32_t load_nvidia_bios_file(char *filename, char *buffer)␊
528{␊
529␉int␉␉fd, size;␊
530␉char␉dirspec[128];␊
531␊
532␉// Check booting partition␊
533␉sprintf(dirspec, "%s", filename);␊
534␉fd = open(dirspec, 0);␊
535␉if (fd < 0)␊
536␉{␉␊
537␉␉// Check Extra on booting partition␊
538␉␉sprintf(dirspec, "/Extra/%s", filename);␊
539␉␉fd = open(dirspec, 0);␊
540␉␉if (fd < 0)␊
541␉␉{␉␊
542␉␉␉// Fall back to booter partition␊
543␉␉␉sprintf(dirspec, "bt(0,0)/Extra/%s", filename);␊
544␉␉␉fd=open (dirspec, 0);␊
545␉␉␉if (fd < 0)␊
546␉␉␉␉return 0;␊
547␉␉}␊
548␉}␊
549␊
550␉size = read(fd, buffer, file_size (fd));␊
551␉close (fd);␊
552␉return size;␊
553}␊
554␊
555int devprop_add_nvidia_template(struct DevPropDevice *device)␊
556{␊
557␉if(!device)␊
558␉␉return 0;␊
559␉␊
560␉if(!DP_ADD_TEMP_VAL(device, nvidia_compatible_0))␊
561␉␉return 0;␊
562␉if(!DP_ADD_TEMP_VAL(device, nvidia_device_type_0))␊
563␉␉return 0;␊
564␉if(!DP_ADD_TEMP_VAL(device, nvidia_name_0))␊
565␉␉return 0;␊
566␉if(!DP_ADD_TEMP_VAL(device, nvidia_compatible_1))␊
567␉␉return 0;␊
568␉if(!DP_ADD_TEMP_VAL(device, nvidia_device_type_1))␊
569␉␉return 0;␊
570␉if(!DP_ADD_TEMP_VAL(device, nvidia_name_1))␊
571␉␉return 0;␊
572␉if(!DP_ADD_TEMP_VAL(device, nvidia_device_type))␊
573␉␉return 0;␊
574␊
575␉char tmp[10];␊
576␉sprintf(tmp, "Slot-%x",devices_number);␊
577␉devprop_add_value(device, "AAPL,slot-name", tmp, strlen(tmp));␊
578␉devices_number++;␊
579␉␊
580␉return 1;␊
581}␊
582␊
583␊
584bool setup_nvidia_devprop(pci_dt_t *nvda_dev)␊
585{␊
586␉int␉␉␉len;␊
587␉char␉␉*devicepath;␊
588␉uint8_t␉␉*nvRom, *rom;␊
589␉volatile uint8_t *regs;␊
590␉uint32_t␉videoRam, nvBiosOveride, nvBiosSize;␊
591␉uint32_t␉bar[7];␊
592␉uint8_t␉␉nvPatch = 0;␊
593␉␊
594␉char␉␉biosVersion[32];␊
595␉char␉␉*model;␊
596␉const char␉*nvFilename;␊
597␊
598␉devicepath = get_pci_dev_path(nvda_dev);␊
599␊
600␉bar[0] = pci_config_read32(nvda_dev->dev.addr, 0x10 );␊
601␉regs = (uint8_t *) (bar[0] & ~0x0f);␊
602␉␊
603␉// Amount of VRAM in kilobytes␊
604␉videoRam = (REG32(0x10020c) & 0xfff00000) >> 10;␊
605␊
606␉model = get_nvidia_model((nvda_dev->vendor_id << 16) | nvda_dev->device_id);␊
607␊
608␉verbose("nVidia %s %dMB NV%02x [%04x:%04x] :: %s\n", ␊
609␉␉␉model, (videoRam / 1024),␊
610␉␉␉(REG32(0) >> 20) & 0x1ff, nvda_dev->vendor_id, nvda_dev->device_id,␊
611␉␉␉devicepath);␊
612␊
613␉rom = malloc(0x10000);␊
614␊
615␉if(!rom)␊
616␉{␊
617␉␉verbose(" ROM malloc failed.\n");␊
618␉␉return 0;␊
619␉}␊
620␊
621␉if (!getValueForKey("VideoROM", &nvFilename, &len, &bootInfo->bootConfig))␊
622␉␉nvFilename="NVIDIA.ROM";␊
623␉␊
624␉// Load video bios overide␊
625␉nvBiosOveride = nvBiosSize = load_nvidia_bios_file((char *)nvFilename, (char *)rom);␊
626␉ ␊
627␉// Otherwise read bios from card␊
628␉if (nvBiosOveride == 0)␊
629␉{␉␊
630␉␉// TODO: we should really check for the signature␊
631␉␉//␉␉ before copying the rom, i think.␊
632␉␉␊
633␉␉// PRAMIN first␊
634␉␉nvRom = (uint8_t*)&regs[NV_PRAMIN_OFFSET];␊
635␉␉bcopy((uint32_t *)nvRom, rom, 0x10000);␊
636␉␉␊
637␉␉// Valid Signature ?␊
638␉␉if(rom[0] != 0x55 && rom[1] != 0xaa)␊
639␉␉{␊
640␉␉␉// PROM next␊
641␉␉␉// Enable PROM access␊
642␉␉␉(REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED;␊
643␊
644␉␉␉nvRom = (uint8_t*)&regs[NV_PROM_OFFSET];␊
645␉␉␉bcopy((uint8_t *)nvRom, rom, 0x10000);␊
646␉␉␉␊
647␉␉␉// disable PROM access␊
648␉␉␉(REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED;␉␊
649␊
650␉␉␉// Valid Signature ?␊
651␉␉␉if(rom[0] != 0x55 && rom[1] != 0xaa)␊
652␉␉␉{␊
653␉␉␉␉// 0xC0000 last␊
654␉␉␉␉bcopy((char *)0xc0000, rom, 0x10000);␊
655␉␉␉␉␊
656␉␉␉␉// Valid Signature ?␊
657␉␉␉␉if(rom[0] != 0x55 && rom[1] != 0xaa)␊
658␉␉␉␉{␊
659␉␉␉␉␉verbose(" Unable to locate video bios.\n");␊
660␉␉␉␉␉return 0;␊
661␉␉␉␉} ␊
662␉␉␉␉else␊
663␉␉␉␉␉DBG(" ROM Address 0x%x Signature 0x%02x%02x\n", ␊
664␉␉␉␉␉␉nvRom, (uint8_t)rom[0], (uint8_t)rom[1]);␊
665␉␉␉}␊
666␉␉␉else␊
667␉␉␉␉DBG(" PROM Address 0x%x Signature 0x%02x%02x\n", ␊
668␉␉␉␉␉nvRom, (uint8_t)rom[0], (uint8_t)rom[1]);␊
669␉␉}␊
670␉␉else␊
671␉␉␉DBG(" PRAM Address 0x%x Signature 0x%02x%02x\n", ␊
672␉␉␉␉nvRom, (uint8_t)rom[0], (uint8_t)rom[1]);␊
673␉}␊
674␉else␊
675␉␉DBG(" %s Signature 0x%02x%02x %d bytes\n", ␊
676␉␉␉nvFilename, (uint8_t)rom[0], (uint8_t)rom[1], nvBiosOveride);␊
677␊
678␉nvPatch = patch_nvidia_rom(rom);␊
679␊
680␉if(nvPatch == PATCH_ROM_FAILED)␊
681␉{␊
682␉␉printf(" ROM Patching Failed.\n");␊
683␉␉return false;␊
684␉}␊
685␊
686␉struct␉pci_rom_pci_header_t *rom_pci_header;␉␊
687␉rom_pci_header = (struct pci_rom_pci_header_t*)(rom + *(uint16_t *)&rom[24]);␊
688␊
689␉// check for 'PCIR' sig␊
690␉if (rom_pci_header->signature == 0x50434952)␊
691␉␉if (rom_pci_header->device != nvda_dev->device_id)␊
692␉␉␉// Get Model from the OpROM␊
693␉␉␉model = get_nvidia_model((rom_pci_header->vendor << 16) | rom_pci_header->device);␊
694␉else␊
695␉␉printf("incorrect PCI ROM sig: 0x%x\n", rom_pci_header->signature);␊
696␊
697␉if (!string)␊
698␉␉string = devprop_create_string();␊
699␊
700␉struct DevPropDevice *device = malloc(sizeof(struct DevPropDevice));␊
701␉device = devprop_add_device(string, devicepath);␊
702␉␊
703␉if(!device)␊
704␉{␊
705␉␉printf("Failed initializing dev-prop string dev-entry, press any key...\n");␊
706␉␉free(rom);␊
707␉␉getc();␊
708␉␉return false;␊
709␉}␊
710␊
711␉/* FIXME: for primary graphics card only */␊
712␉uint32_t boot_display = 0x00000001;␊
713␉devprop_add_value(device, "@0,AAPL,boot-display", (uint8_t*)&boot_display, 4);␊
714␊
715␉if(nvPatch == PATCH_ROM_SUCCESS_HAS_LVDS)␊
716␉{␊
717␉␉uint8_t built_in = 0x01;␊
718␉␉devprop_add_value(device, "@0,built-in", (uint8_t*)&built_in, 1);␊
719␉}␊
720␊
721␉videoRam *= 1024;␊
722␊
723␉sprintf(biosVersion, "xx.xx.xx - %s", (nvBiosOveride > 0) ? nvFilename : "internal");␊
724␉␊
725␉devprop_add_nvidia_template(device);␊
726␉devprop_add_value(device, "NVCAP", default_NVCAP, 20);␊
727␉devprop_add_value(device, "VRAM,totalsize", (uint8_t*)&videoRam, 4);␊
728␉devprop_add_value(device, "model", (uint8_t*)model, (strlen(model) + 1));␊
729␉devprop_add_value(device, "rom-revision", (uint8_t*)biosVersion, (strlen(biosVersion) + 1));␊
730␊
731␉BOOL set_vbios_prop = false;␊
732␉getBoolForKey("VBIOS", &set_vbios_prop, &bootInfo->bootConfig);␊
733␉if (set_vbios_prop)␊
734␉␉devprop_add_value(device, "vbios", rom, (nvBiosOveride > 0) ? nvBiosOveride : (rom[2] * 512));␊
735␊
736␉stringdata = malloc(sizeof(uint8_t) * string->length);␊
737␉if(!stringdata)␊
738␉{␊
739␉␉printf("no stringdata press a key...\n");␊
740␉␉getc();␊
741␉␉return false;␊
742␉}␊
743␉␊
744␉memcpy(stringdata, (uint8_t*)devprop_generate_string(string), string->length);␊
745␉stringlength = string->length;␊
746␊
747␉return true;␊
748}␊
749

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