Chameleon

Chameleon Svn Source Tree

Root/branches/azimutz/Chazi/i386/libsaio/smbios_getters.c

1/*␊
2 * Add (c) here␊
3 *␊
4 * Copyright .... All rights reserved.␊
5 *␊
6 */␊
7␊
8#include "smbios_getters.h"␊
9␊
10#ifndef DEBUG_SMBIOS␊
11#define DEBUG_SMBIOS 0␊
12#endif␊
13␊
14#if DEBUG_SMBIOS␊
15#define DBG(x...)␉printf(x)␊
16#else␊
17#define DBG(x...)␊
18#endif␊
19␊
20␊
21bool getProcessorInformationExternalClock(returnType *value)␊
22{␊
23␉value->word = Platform.CPU.FSBFrequency/1000000;␊
24␉return true;␊
25}␊
26␊
27bool getProcessorInformationMaximumClock(returnType *value)␊
28{␊
29␉value->word = Platform.CPU.CPUFrequency/1000000;␊
30␉return true;␊
31}␊
32␊
33bool getSMBOemProcessorBusSpeed(returnType *value)␊
34{␊
35␉if (Platform.CPU.Vendor == 0x756E6547) // Intel␊
36␉{␉␉␊
37␉␉switch (Platform.CPU.Family) ␊
38␉␉{␊
39␉␉␉case 0x06:␊
40␉␉␉{␊
41␉␉␉␉switch (Platform.CPU.Model)␊
42␉␉␉␉{␊
43␉␉␉␉␉case 0x0D:␉␉␉␉␉// ?␊
44␉␉␉␉␉case CPU_MODEL_YONAH:␉␉// Yonah␉␉0x0E␊
45␉␉␉␉␉case CPU_MODEL_MEROM:␉␉// Merom␉␉0x0F␊
46␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉// Penryn␉␉0x17␊
47␉␉␉␉␉case CPU_MODEL_ATOM:␉␉// Atom 45nm␉0x1C␊
48␉␉␉␉␉␉return false;␊
49␊
50␉␉␉␉␉case 0x19:␉␉␉␉␉// Intel Core i5 650 @3.20 Ghz␊
51␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉// Intel Core i7 LGA1366 (45nm)␊
52␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉// Intel Core i5, i7 LGA1156 (45nm)␊
53␉␉␉␉␉case CPU_MODEL_DALES:␉␉// Intel Core i5, i7 LGA1156 (45nm) ???␊
54␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉// Intel Core i3, i5, i7 LGA1156 (32nm)␊
55␉␉␉␉␉case CPU_MODEL_WESTMERE:␉// Intel Core i7 LGA1366 (32nm) 6 Core␊
56␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␉// Intel Core i7 LGA1366 (45nm) 6 Core ???␊
57␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉// Intel Core i7 LGA1366 (45nm) 6 Core ???␊
58␉␉␉␉␉{␊
59␉␉␉␉␉␉// thanks to dgobe for i3/i5/i7 bus speed detection␊
60␉␉␉␉␉␉int nhm_bus = 0x3F;␊
61␉␉␉␉␉␉static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};␊
62␉␉␉␉␉␉unsigned long did, vid;␊
63␉␉␉␉␉␉int i;␊
64␉␉␉␉␉␉␊
65␉␉␉␉␉␉// Nehalem supports Scrubbing␊
66␉␉␉␉␉␉// First, locate the PCI bus where the MCH is located␊
67␉␉␉␉␉␉for(i = 0; i < sizeof(possible_nhm_bus); i++)␊
68␉␉␉␉␉␉{␊
69␉␉␉␉␉␉␉vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x00);␊
70␉␉␉␉␉␉␉did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x02);␊
71␉␉␉␉␉␉␉vid &= 0xFFFF;␊
72␉␉␉␉␉␉␉did &= 0xFF00;␊
73␉␉␉␉␉␉␉␊
74␉␉␉␉␉␉␉if(vid == 0x8086 && did >= 0x2C00)␊
75␉␉␉␉␉␉␉␉nhm_bus = possible_nhm_bus[i]; ␊
76␉␉␉␉␉␉}␊
77␉␉␉␉␉␉␊
78␉␉␉␉␉␉unsigned long qpimult, qpibusspeed;␊
79␉␉␉␉␉␉qpimult = pci_config_read32(PCIADDR(nhm_bus, 2, 1), 0x50);␊
80␉␉␉␉␉␉qpimult &= 0x7F;␊
81␉␉␉␉␉␉DBG("qpimult %d\n", qpimult);␊
82␉␉␉␉␉␉qpibusspeed = (qpimult * 2 * (Platform.CPU.FSBFrequency/1000000));␊
83␉␉␉␉␉␉// Rek: rounding decimals to match original mac profile info␊
84␉␉␉␉␉␉if (qpibusspeed%100 != 0)qpibusspeed = ((qpibusspeed+50)/100)*100;␊
85␉␉␉␉␉␉DBG("qpibusspeed %d\n", qpibusspeed);␊
86␉␉␉␉␉␉value->word = qpibusspeed;␊
87␉␉␉␉␉␉return true;␊
88␉␉␉␉␉}␊
89␉␉␉␉}␊
90␉␉␉}␊
91␉␉}␊
92␉}␊
93␉return false;␊
94}␊
95␊
96uint16_t simpleGetSMBOemProcessorType(void)␊
97{␊
98␉if (Platform.CPU.NoCores >= 4) ␊
99␉{␊
100␉␉return 0x0501;␉// Quad-Core Xeon␊
101␉}␊
102␉else if (Platform.CPU.NoCores == 1) ␊
103␉{␊
104␉␉return 0x0201;␉// Core Solo␊
105␉};␊
106␉␊
107␉return 0x0301;␉␉// Core 2 Duo␊
108}␊
109␊
110bool getSMBOemProcessorType(returnType *value)␊
111{␊
112␉static bool done = false;␉␉␊
113␉␉␊
114␉value->word = simpleGetSMBOemProcessorType();␊
115␊
116␉if (Platform.CPU.Vendor == 0x756E6547) // Intel␊
117␉{␊
118␉␉if (!done)␊
119␉␉{␊
120␉␉␉verbose("CPU is %s, family 0x%x, model 0x%x\n", Platform.CPU.BrandString, Platform.CPU.Family, Platform.CPU.Model);␊
121␉␉␉done = true;␊
122␉␉}␊
123␉␉␊
124␉␉switch (Platform.CPU.Family) ␊
125␉␉{␊
126␉␉␉case 0x06:␊
127␉␉␉{␊
128␉␉␉␉switch (Platform.CPU.Model)␊
129␉␉␉␉{␊
130␉␉␉␉␉case 0x0D:␉␉␉␉␉␉␉// ?␊
131␉␉␉␉␉case CPU_MODEL_YONAH:␉␉␉␉// Yonah␊
132␉␉␉␉␉case CPU_MODEL_MEROM:␉␉␉␉// Merom␊
133␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉␉␉// Penryn␊
134␉␉␉␉␉case CPU_MODEL_ATOM:␉␉␉␉// Intel Atom (45nm)␊
135␉␉␉␉␉␉return true;␊
136␊
137␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉␉␉// Intel Core i7 LGA1366 (45nm)␊
138␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)"))␊
139␉␉␉␉␉␉␉value->word = 0x0501;␉␉␉// Xeon ␊
140␉␉␉␉␉␉else␊
141␉␉␉␉␉␉␉value->word = 0x0701;␉␉␉// Core i7␊
142␉␉␉␉␉␉return true;␊
143␊
144␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉␉␉// Lynnfield, Clarksfield, Jasper␊
145␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊
146␉␉␉␉␉␉␉value->word = 0x601;␉␉// Core i5␊
147␉␉␉␉␉␉else␊
148␉␉␉␉␉␉␉value->word = 0x0701;␉␉// Core i7␊
149␉␉␉␉␉␉return true;␊
150␊
151␉␉␉␉␉case CPU_MODEL_DALES:␉␉␉␉// Intel Core i5, i7 LGA1156 (45nm) (Havendale, Auburndale)␊
152␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊
153␉␉␉␉␉␉␉value->word = 0x601;␉␉// Core i5␊
154␉␉␉␉␉␉else␊
155␉␉␉␉␉␉␉value->word = 0x0701;␉␉// Core i7␊
156␉␉␉␉␉␉return true;␊
157␊
158␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉␉␉// Intel Core i3, i5, i7 LGA1156 (32nm) (Clarkdale, Arrandale)␊
159␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3"))␊
160␉␉␉␉␉␉␉value->word = 0x901;␉␉// Core i3␊
161␉␉␉␉␉␉else␊
162␉␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊
163␉␉␉␉␉␉␉␉value->word = 0x601;␉// Core i5␊
164␉␉␉␉␉␉␉else␊
165␉␉␉␉␉␉␉␉value->word = 0x0701;␉// Core i7␊
166␉␉␉␉␉␉return true;␊
167␊
168␉␉␉␉␉case CPU_MODEL_WESTMERE:␉␉␉// Intel Core i7 LGA1366 (32nm) 6 Core (Gulftown, Westmere-EP, Westmere-WS)␊
169␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉␉␉// Intel Core i7 LGA1366 (45nm) 6 Core ???␊
170␉␉␉␉␉␉value->word = 0x0501;␉␉␉// Core i7␊
171␉␉␉␉␉␉return true;␊
172␊
173␉␉␉␉␉case 0x19:␉␉␉␉␉␉␉// Intel Core i5 650 @3.20 Ghz␊
174␉␉␉␉␉␉value->word = 0x601;␉␉␉// Core i5␊
175␉␉␉␉␉␉return true;␊
176␉␉␉␉}␊
177␉␉␉}␊
178␉␉}␊
179␉}␊
180␉␊
181␉return false;␊
182}␊
183␊
184bool getSMBMemoryDeviceMemoryType(returnType *value)␊
185{␊
186␉static int idx = -1;␊
187␉int␉map;␊
188␊
189␉idx++;␊
190␉if (idx < MAX_RAM_SLOTS)␊
191␉{␊
192␉␉map = Platform.DMI.DIMM[idx];␊
193␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Type != 0)␊
194␉␉{␊
195␉␉␉DBG("RAM Detected Type = %d\n", Platform.RAM.DIMM[map].Type);␊
196␉␉␉value->byte = Platform.RAM.DIMM[map].Type;␊
197␉␉␉return true;␊
198␉␉}␊
199␉}␊
200␉␊
201␉return false;␊
202//␉value->byte = SMB_MEM_TYPE_DDR2;␊
203//␉return true;␊
204}␊
205␊
206bool getSMBMemoryDeviceMemorySpeed(returnType *value)␊
207{␊
208␉static int idx = -1;␊
209␉int␉map;␊
210␊
211␉idx++;␊
212␉if (idx < MAX_RAM_SLOTS)␊
213␉{␊
214␉␉map = Platform.DMI.DIMM[idx];␊
215␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Frequency != 0)␊
216␉␉{␊
217␉␉␉DBG("RAM Detected Freq = %d Mhz\n", Platform.RAM.DIMM[map].Frequency);␊
218␉␉␉value->dword = Platform.RAM.DIMM[map].Frequency;␊
219␉␉␉return true;␊
220␉␉}␊
221␉}␊
222␊
223␉return false;␊
224//␉value->dword = 800;␊
225//␉return true;␊
226}␊
227␊
228bool getSMBMemoryDeviceManufacturer(returnType *value)␊
229{␊
230␉static int idx = -1;␊
231␉int␉map;␊
232␊
233␉idx++;␊
234␉if (idx < MAX_RAM_SLOTS)␊
235␉{␊
236␉␉map = Platform.DMI.DIMM[idx];␊
237␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].Vendor) > 0)␊
238␉␉{␊
239␉␉␉DBG("RAM Detected Vendor[%d]='%s'\n", idx, Platform.RAM.DIMM[map].Vendor);␊
240␉␉␉value->string = Platform.RAM.DIMM[map].Vendor;␊
241␉␉␉return true;␊
242␉␉}␊
243␉}␊
244␊
245␉return false;␊
246//␉value->string = "N/A";␊
247//␉return true;␊
248}␊
249␉␊
250bool getSMBMemoryDeviceSerialNumber(returnType *value)␊
251{␊
252␉static int idx = -1;␊
253␉int␉map;␊
254␊
255␉idx++;␊
256␉if (idx < MAX_RAM_SLOTS)␊
257␉{␊
258␉␉map = Platform.DMI.DIMM[idx];␊
259␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].SerialNo) > 0)␊
260␉␉{␊
261␉␉␉DBG("name = %s, map=%d, RAM Detected SerialNo[%d]='%s'\n", name ? name : "", ␊
262␉␉␉␉map, idx, Platform.RAM.DIMM[map].SerialNo);␊
263␉␉␉value->string = Platform.RAM.DIMM[map].SerialNo;␊
264␉␉␉return true;␊
265␉␉}␊
266␉}␊
267␊
268␉return false;␊
269//␉value->string = "N/A";␊
270//␉return true;␊
271}␊
272␊
273bool getSMBMemoryDevicePartNumber(returnType *value)␊
274{␊
275␉static int idx = -1;␊
276␉int␉map;␊
277␊
278␉idx++;␊
279␉if (idx < MAX_RAM_SLOTS)␊
280␉{␊
281␉␉map = Platform.DMI.DIMM[idx];␊
282␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].PartNo) > 0)␊
283␉␉{␊
284␉␉␉DBG("Ram Detected PartNo[%d]='%s'\n", idx, Platform.RAM.DIMM[map].PartNo);␊
285␉␉␉value->string = Platform.RAM.DIMM[map].PartNo;␊
286␉␉␉return true;␊
287␉␉}␊
288␉}␊
289␊
290␉return false;␊
291//␉value->string = "N/A";␊
292//␉return true;␊
293}␊
294␊
295␊
296// getting smbios addr with fast compare ops, late checksum testing ...␊
297#define COMPARE_DWORD(a,b) ( *((uint32_t *) a) == *((uint32_t *) b) )␊
298static const char * const SMTAG = "_SM_";␊
299static const char* const DMITAG = "_DMI_";␊
300␊
301SMBEntryPoint *getAddressOfSmbiosTable(void)␊
302{␊
303␉SMBEntryPoint␉*smbios;␊
304␉/* ␊
305␉ * The logic is to start at 0xf0000 and end at 0xfffff iterating 16 bytes at a time looking␊
306␉ * for the SMBIOS entry-point structure anchor (literal ASCII "_SM_").␊
307␉ */␊
308␉smbios = (SMBEntryPoint*)SMBIOS_RANGE_START;␊
309␉while (smbios <= (SMBEntryPoint *)SMBIOS_RANGE_END) {␊
310␉␉if (COMPARE_DWORD(smbios->anchor, SMTAG) && ␊
311␉␉␉COMPARE_DWORD(smbios->dmi.anchor, DMITAG) &&␊
312␉␉␉smbios->dmi.anchor[4] == DMITAG[4] &&␊
313␉␉␉checksum8(smbios, sizeof(SMBEntryPoint)) == 0)␊
314␉ {␊
315␉␉␉return smbios;␊
316␉ }␊
317␉␉smbios = (SMBEntryPoint*)(((char*)smbios) + 16);␊
318␉}␊
319␉printf("ERROR: Unable to find SMBIOS!\n");␊
320␉pause();␊
321␉return NULL;␊
322}␊
323␊
324

Archive Download this file

Revision: 824