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Root/trunk/i386/libsaio/smbios_getters.c

1/*␊
2 * Add (c) here␊
3 *␊
4 * Copyright .... All rights reserved.␊
5 *␊
6 */␊
7␊
8#include "smbios_getters.h"␊
9␊
10#ifndef DEBUG_SMBIOS␊
11#define DEBUG_SMBIOS 0␊
12#endif␊
13␊
14#if DEBUG_SMBIOS␊
15#define DBG(x...)␉printf(x)␊
16#else␊
17#define DBG(x...)␊
18#endif␊
19␊
20␊
21bool getProcessorInformationExternalClock(returnType *value)␊
22{␊
23␉value->word = Platform.CPU.FSBFrequency/1000000;␊
24␉return true;␊
25}␊
26␊
27bool getProcessorInformationMaximumClock(returnType *value)␊
28{␊
29␉value->word = Platform.CPU.CPUFrequency/1000000;␊
30␉return true;␊
31}␊
32␊
33bool getSMBOemProcessorBusSpeed(returnType *value)␊
34{␊
35␉if (Platform.CPU.Vendor == 0x756E6547) // Intel␊
36␉{␉␉␊
37␉␉switch (Platform.CPU.Family) ␊
38␉␉{␊
39␉␉␉case 0x06:␊
40␉␉␉{␊
41␉␉␉␉switch (Platform.CPU.Model)␊
42␉␉␉␉{␊
43␉␉␉␉␉case 0x0D:␉␉␉␉␉// ?␊
44␉␉␉␉␉case CPU_MODEL_YONAH:␉␉// Yonah␉␉0x0E␊
45␉␉␉␉␉case CPU_MODEL_MEROM:␉␉// Merom␉␉0x0F␊
46␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉// Penryn␉␉0x17␊
47␉␉␉␉␉case CPU_MODEL_ATOM:␉␉// Atom 45nm␉0x1C␊
48␉␉␉␉␉␉return false;␊
49␊
50␉␉␉␉␉case 0x19:␉␉␉␉␉// Intel Core i5 650 @3.20 Ghz␊
51␉␉␉␉␉case CPU_MODEL_SANDY:␉␉// Intel Core i5, i7 LGA1155 sandy bridge␊
52␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉// Intel Core i7 LGA1366 (45nm)␊
53␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉// Intel Core i5, i7 LGA1156 (45nm)␊
54␉␉␉␉␉case CPU_MODEL_DALES:␉␉// Intel Core i5, i7 LGA1156 (45nm) ???␊
55␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉// Intel Core i3, i5, i7 LGA1156 (32nm)␊
56␉␉␉␉␉case CPU_MODEL_WESTMERE:␉// Intel Core i7 LGA1366 (32nm) 6 Core␊
57␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␉// Intel Core i7 LGA1366 (45nm) 6 Core ???␊
58␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉// Intel Core i7 LGA1366 (45nm) 6 Core ???␊
59␉␉␉␉␉{␊
60␉␉␉␉␉␉// thanks to dgobe for i3/i5/i7 bus speed detection␊
61␉␉␉␉␉␉int nhm_bus = 0x3F;␊
62␉␉␉␉␉␉static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};␊
63␉␉␉␉␉␉unsigned long did, vid;␊
64␉␉␉␉␉␉int i;␊
65␉␉␉␉␉␉␊
66␉␉␉␉␉␉// Nehalem supports Scrubbing␊
67␉␉␉␉␉␉// First, locate the PCI bus where the MCH is located␊
68␉␉␉␉␉␉for(i = 0; i < sizeof(possible_nhm_bus); i++)␊
69␉␉␉␉␉␉{␊
70␉␉␉␉␉␉␉vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x00);␊
71␉␉␉␉␉␉␉did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x02);␊
72␉␉␉␉␉␉␉vid &= 0xFFFF;␊
73␉␉␉␉␉␉␉did &= 0xFF00;␊
74␉␉␉␉␉␉␉␊
75␉␉␉␉␉␉␉if(vid == 0x8086 && did >= 0x2C00)␊
76␉␉␉␉␉␉␉␉nhm_bus = possible_nhm_bus[i]; ␊
77␉␉␉␉␉␉}␊
78␉␉␉␉␉␉␊
79␉␉␉␉␉␉unsigned long qpimult, qpibusspeed;␊
80␉␉␉␉␉␉qpimult = pci_config_read32(PCIADDR(nhm_bus, 2, 1), 0x50);␊
81␉␉␉␉␉␉qpimult &= 0x7F;␊
82␉␉␉␉␉␉DBG("qpimult %d\n", qpimult);␊
83␉␉␉␉␉␉qpibusspeed = (qpimult * 2 * (Platform.CPU.FSBFrequency/1000000));␊
84␉␉␉␉␉␉// Rek: rounding decimals to match original mac profile info␊
85␉␉␉␉␉␉if (qpibusspeed%100 != 0)qpibusspeed = ((qpibusspeed+50)/100)*100;␊
86␉␉␉␉␉␉DBG("qpibusspeed %d\n", qpibusspeed);␊
87␉␉␉␉␉␉value->word = qpibusspeed;␊
88␉␉␉␉␉␉return true;␊
89␉␉␉␉␉}␊
90␉␉␉␉}␊
91␉␉␉}␊
92␉␉}␊
93␉}␊
94␉return false;␊
95}␊
96␊
97uint16_t simpleGetSMBOemProcessorType(void)␊
98{␊
99␉if (Platform.CPU.NoCores >= 4) ␊
100␉{␊
101␉␉return 0x0501;␉// Quad-Core Xeon␊
102␉}␊
103␉else if (Platform.CPU.NoCores == 1) ␊
104␉{␊
105␉␉return 0x0201;␉// Core Solo␊
106␉};␊
107␉␊
108␉return 0x0301;␉␉// Core 2 Duo␊
109}␊
110␊
111bool getSMBOemProcessorType(returnType *value)␊
112{␊
113␉static bool done = false;␉␉␊
114␉␉␊
115␉value->word = simpleGetSMBOemProcessorType();␊
116␊
117␉if (Platform.CPU.Vendor == 0x756E6547) // Intel␊
118␉{␊
119␉␉if (!done)␊
120␉␉{␊
121␉␉␉verbose("CPU is %s, family 0x%x, model 0x%x\n", Platform.CPU.BrandString, Platform.CPU.Family, Platform.CPU.Model);␊
122␉␉␉done = true;␊
123␉␉}␊
124␉␉␊
125␉␉switch (Platform.CPU.Family) ␊
126␉␉{␊
127␉␉␉case 0x06:␊
128␉␉␉{␊
129␉␉␉␉switch (Platform.CPU.Model)␊
130␉␉␉␉{␊
131␉␉␉␉␉case 0x0D:␉␉␉␉␉␉␉// ?␊
132␉␉␉␉␉case CPU_MODEL_YONAH:␉␉␉␉// Yonah␊
133␉␉␉␉␉case CPU_MODEL_MEROM:␉␉␉␉// Merom␊
134␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉␉␉// Penryn␊
135␉␉␉␉␉case CPU_MODEL_ATOM:␉␉␉␉// Intel Atom (45nm)␊
136␉␉␉␉␉␉return true;␊
137␊
138␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉␉␉// Intel Core i7 LGA1366 (45nm)␊
139␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)"))␊
140␉␉␉␉␉␉␉value->word = 0x0501;␉␉␉// Xeon ␊
141␉␉␉␉␉␉else␊
142␉␉␉␉␉␉␉value->word = 0x0701;␉␉␉// Core i7␊
143␊
144␉␉␉␉␉␉return true;␊
145␊
146␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉␉␉// Lynnfield, Clarksfield, Jasper␊
147␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊
148␉␉␉␉␉␉␉value->word = 0x601;␉␉// Core i5␊
149␉␉␉␉␉␉else␊
150␉␉␉␉␉␉␉value->word = 0x0701;␉␉// Core i7␊
151␉␉␉␉␉␉return true;␊
152␊
153␉␉␉␉␉case CPU_MODEL_DALES:␉␉␉␉// Intel Core i5, i7 LGA1156 (45nm) (Havendale, Auburndale)␊
154␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊
155␉␉␉␉␉␉␉value->word = 0x601;␉␉// Core i5␊
156␉␉␉␉␉␉else␊
157␉␉␉␉␉␉␉value->word = 0x0701;␉␉// Core i7␊
158␉␉␉␉␉␉return true;␊
159␊
160␉␉␉␉␉case CPU_MODEL_SANDY:␉␉␉␉// Intel Core i3, i5, i7 LGA1155 sandy bridge␊
161␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉␉␉// Intel Core i3, i5, i7 LGA1156 (32nm) (Clarkdale, Arrandale)␊
162␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3"))␊
163␉␉␉␉␉␉␉value->word = 0x901;␉␉// Core i3␊
164␉␉␉␉␉␉else␊
165␉␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊
166␉␉␉␉␉␉␉␉value->word = 0x601;␉// Core i5␊
167␉␉␉␉␉␉␉else␊
168␉␉␉␉␉␉␉␉value->word = 0x0701;␉// Core i7␊
169␉␉␉␉␉␉return true;␊
170␊
171␉␉␉␉␉case CPU_MODEL_WESTMERE:␉␉␉// Intel Core i7 LGA1366 (32nm) 6 Core (Gulftown, Westmere-EP, Westmere-WS)␊
172␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉␉␉// Intel Core i7 LGA1366 (45nm) 6 Core ???␊
173␉␉␉␉␉␉value->word = 0x0501;␉␉␉// Core i7␊
174␉␉␉␉␉␉return true;␊
175␊
176␉␉␉␉␉case 0x19:␉␉␉␉␉␉␉// Intel Core i5 650 @3.20 Ghz␊
177␉␉␉␉␉␉value->word = 0x601;␉␉␉// Core i5␊
178␉␉␉␉␉␉return true;␊
179␉␉␉␉}␊
180␉␉␉}␊
181␉␉}␊
182␉}␊
183␉␊
184␉return false;␊
185}␊
186␊
187bool getSMBMemoryDeviceMemoryType(returnType *value)␊
188{␊
189␉static int idx = -1;␊
190␉int␉map;␊
191␊
192␉idx++;␊
193␉if (idx < MAX_RAM_SLOTS)␊
194␉{␊
195␉␉map = Platform.DMI.DIMM[idx];␊
196␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Type != 0)␊
197␉␉{␊
198␉␉␉DBG("RAM Detected Type = %d\n", Platform.RAM.DIMM[map].Type);␊
199␉␉␉value->byte = Platform.RAM.DIMM[map].Type;␊
200␉␉␉return true;␊
201␉␉}␊
202␉}␊
203␉␊
204␉return false;␊
205//␉value->byte = SMB_MEM_TYPE_DDR2;␊
206//␉return true;␊
207}␊
208␊
209bool getSMBMemoryDeviceMemorySpeed(returnType *value)␊
210{␊
211␉static int idx = -1;␊
212␉int␉map;␊
213␊
214␉idx++;␊
215␉if (idx < MAX_RAM_SLOTS)␊
216␉{␊
217␉␉map = Platform.DMI.DIMM[idx];␊
218␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Frequency != 0)␊
219␉␉{␊
220␉␉␉DBG("RAM Detected Freq = %d Mhz\n", Platform.RAM.DIMM[map].Frequency);␊
221␉␉␉value->dword = Platform.RAM.DIMM[map].Frequency;␊
222␉␉␉return true;␊
223␉␉}␊
224␉}␊
225␊
226␉return false;␊
227//␉value->dword = 800;␊
228//␉return true;␊
229}␊
230␊
231bool getSMBMemoryDeviceManufacturer(returnType *value)␊
232{␊
233␉static int idx = -1;␊
234␉int␉map;␊
235␊
236␉idx++;␊
237␉if (idx < MAX_RAM_SLOTS)␊
238␉{␊
239␉␉map = Platform.DMI.DIMM[idx];␊
240␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].Vendor) > 0)␊
241␉␉{␊
242␉␉␉DBG("RAM Detected Vendor[%d]='%s'\n", idx, Platform.RAM.DIMM[map].Vendor);␊
243␉␉␉value->string = Platform.RAM.DIMM[map].Vendor;␊
244␉␉␉return true;␊
245␉␉}␊
246␉}␊
247␊
248␉return false;␊
249//␉value->string = "N/A";␊
250//␉return true;␊
251}␊
252␉␊
253bool getSMBMemoryDeviceSerialNumber(returnType *value)␊
254{␊
255␉static int idx = -1;␊
256␉int␉map;␊
257␊
258␉idx++;␊
259␉if (idx < MAX_RAM_SLOTS)␊
260␉{␊
261␉␉map = Platform.DMI.DIMM[idx];␊
262␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].SerialNo) > 0)␊
263␉␉{␊
264␉␉␉DBG("name = %s, map=%d, RAM Detected SerialNo[%d]='%s'\n", name ? name : "", ␊
265␉␉␉␉map, idx, Platform.RAM.DIMM[map].SerialNo);␊
266␉␉␉value->string = Platform.RAM.DIMM[map].SerialNo;␊
267␉␉␉return true;␊
268␉␉}␊
269␉}␊
270␊
271␉return false;␊
272//␉value->string = "N/A";␊
273//␉return true;␊
274}␊
275␊
276bool getSMBMemoryDevicePartNumber(returnType *value)␊
277{␊
278␉static int idx = -1;␊
279␉int␉map;␊
280␊
281␉idx++;␊
282␉if (idx < MAX_RAM_SLOTS)␊
283␉{␊
284␉␉map = Platform.DMI.DIMM[idx];␊
285␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].PartNo) > 0)␊
286␉␉{␊
287␉␉␉DBG("Ram Detected PartNo[%d]='%s'\n", idx, Platform.RAM.DIMM[map].PartNo);␊
288␉␉␉value->string = Platform.RAM.DIMM[map].PartNo;␊
289␉␉␉return true;␊
290␉␉}␊
291␉}␊
292␊
293␉return false;␊
294//␉value->string = "N/A";␊
295//␉return true;␊
296}␊
297␊
298␊
299// getting smbios addr with fast compare ops, late checksum testing ...␊
300#define COMPARE_DWORD(a,b) ( *((uint32_t *) a) == *((uint32_t *) b) )␊
301static const char * const SMTAG = "_SM_";␊
302static const char* const DMITAG = "_DMI_";␊
303␊
304SMBEntryPoint *getAddressOfSmbiosTable(void)␊
305{␊
306␉SMBEntryPoint␉*smbios;␊
307␉/* ␊
308␉ * The logic is to start at 0xf0000 and end at 0xfffff iterating 16 bytes at a time looking␊
309␉ * for the SMBIOS entry-point structure anchor (literal ASCII "_SM_").␊
310␉ */␊
311␉smbios = (SMBEntryPoint*)SMBIOS_RANGE_START;␊
312␉while (smbios <= (SMBEntryPoint *)SMBIOS_RANGE_END) {␊
313␉␉if (COMPARE_DWORD(smbios->anchor, SMTAG) && ␊
314␉␉␉COMPARE_DWORD(smbios->dmi.anchor, DMITAG) &&␊
315␉␉␉smbios->dmi.anchor[4] == DMITAG[4] &&␊
316␉␉␉checksum8(smbios, sizeof(SMBEntryPoint)) == 0)␊
317␉ {␊
318␉␉␉return smbios;␊
319␉ }␊
320␉␉smbios = (SMBEntryPoint*)(((char*)smbios) + 16);␊
321␉}␊
322␉printf("ERROR: Unable to find SMBIOS!\n");␊
323␉pause();␊
324␉return NULL;␊
325}␊
326␊
327

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