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1/*␊
2 * usb.c␊
3 * ␊
4 *␊
5 * Created by mackerintel on 12/20/08.␊
6 * Copyright 2008 mackerintel. All rights reserved.␊
7 *␊
8 */␊
9␊
10//#include "libsaio.h"␊
11//#include "bootstruct.h"␊
12#include "boot.h"␊
13#include "io_inline.h"␊
14#include "pci.h"␊
15␊
16#ifndef DEBUG_USB␊
17#define DEBUG_USB 0␊
18#endif␊
19␊
20#if DEBUG_USB␊
21#define DBG(x...)␉printf(x)␊
22#else␊
23#define DBG(x...)␊
24#endif␊
25␊
26␊
27struct pciList␊
28{␊
29␉pci_dt_t* pciDev;␊
30␉struct pciList* next;␊
31};␊
32␊
33struct pciList* usbList = NULL;␊
34␊
35int legacy_off (pci_dt_t *pci_dev);␊
36int ehci_acquire (pci_dt_t *pci_dev);␊
37int uhci_reset (pci_dt_t *pci_dev);␊
38␊
39// Add usb device to the list␊
40void notify_usb_dev(pci_dt_t *pci_dev)␊
41{␊
42␉struct pciList* current = usbList;␊
43␉if(!usbList)␊
44␉{␊
45␉␉usbList = (struct pciList*)malloc(sizeof(struct pciList));␊
46␉␉usbList->next = NULL;␊
47␉␉usbList->pciDev = pci_dev;␊
48␉}␊
49␉else␊
50␉{␊
51␉␉while(current != NULL && current->next != NULL)␊
52␉␉{␊
53␉␉␉current = current->next;␊
54␉␉}␊
55␉␉current->next = (struct pciList*)malloc(sizeof(struct pciList));␊
56␉␉current = current->next;␊
57␉␉␊
58␉␉current->pciDev = pci_dev;␊
59␉␉current->next = NULL;␊
60␉}␊
61}␊
62␊
63// Loop through the list and call the apropriate patch function␊
64int usb_loop()␊
65{␊
66␉int retVal = 1;␊
67␉bool fix_ehci, fix_uhci, fix_usb, fix_legacy;␊
68␉fix_ehci = fix_uhci = fix_usb = fix_legacy = false;␊
69␉␊
70␉if (getBoolForKey(kUSBBusFixKey, &fix_usb, &bootInfo->bootConfig))␊
71␉{␊
72␉␉fix_ehci = fix_uhci = fix_legacy = fix_usb;␉// Disable all if none set␊
73␉}␊
74␉else ␊
75␉{␊
76␉␉getBoolForKey(kEHCIacquireKey, &fix_ehci, &bootInfo->bootConfig);␊
77␉␉getBoolForKey(kUHCIresetKey, &fix_uhci, &bootInfo->bootConfig);␊
78␉␉getBoolForKey(kLegacyOffKey, &fix_legacy, &bootInfo->bootConfig);␊
79␉}␊
80␉␊
81␉struct pciList* current = usbList;␊
82␉␊
83␉while(current)␊
84␉{␊
85␉␉switch (pci_config_read8(current->pciDev->dev.addr, PCI_CLASS_PROG))␊
86␉␉{␊
87␉␉␉// EHCI␊
88␉␉␉case 0x20:␊
89␉␉ ␉if (fix_ehci)␊
90␉␉␉␉␉retVal &= ehci_acquire(current->pciDev);␊
91␉␉␉␉␊
92␉␉ ␉if (fix_legacy)␊
93␉␉␉␉␉retVal &= legacy_off(current->pciDev);␊
94␉␉␉␉␊
95␉␉␉␉break;␊
96␉␉␉␉␊
97␉␉␉// UHCI␊
98␉␉␉case 0x00:␊
99␉␉␉␉if (fix_uhci)␊
100␉␉␉␉␉retVal &= uhci_reset(current->pciDev);␊
101␊
102␉␉␉␉break;␊
103␉␉}␊
104␉␉␊
105␉␉current = current->next;␊
106␉}␊
107␉return retVal;␊
108}␊
109␊
110int legacy_off (pci_dt_t *pci_dev)␊
111{␊
112␉// Set usb legacy off modification by Signal64␊
113␉// NOTE: This *must* be called after the last file is loaded from the drive in the event that we are booting form usb.␊
114␉// NOTE2: This should be called after any getc() call. (aka, after the Wait=y keyword is used)␊
115␉// AKA: Make this run immediatly before the kernel is called␊
116␉uint32_t␉capaddr, opaddr; ␉␉␊
117␉uint8_t␉␉eecp;␉␉␉␊
118␉uint32_t␉usbcmd, usbsts, usbintr;␉␉␉␊
119␉uint32_t␉usblegsup, usblegctlsts;␉␉␊
120␉␊
121␉int isOSowned;␊
122␉int isBIOSowned;␊
123␉␊
124␉verbose("Setting Legacy USB Off on controller [%04x:%04x] at %02x:%2x.%x\n", ␊
125␉␉␉pci_dev->vendor_id, pci_dev->device_id,␊
126␉␉␉pci_dev->dev.bits.bus, pci_dev->dev.bits.dev, pci_dev->dev.bits.func);␊
127␉␊
128␉// capaddr = Capability Registers = dev.addr + offset stored in dev.addr + 0x10 (USBBASE)␊
129␉capaddr = pci_config_read32(pci_dev->dev.addr, 0x10);␉␊
130␉␊
131␉// opaddr = Operational Registers = capaddr + offset (8bit CAPLENGTH in Capability Registers + offset 0)␊
132␉opaddr = capaddr + *((unsigned char*)(capaddr)); ␉␉␊
133␉␊
134␉// eecp = EHCI Extended Capabilities offset = capaddr HCCPARAMS bits 15:8␊
135␉eecp = *((unsigned char*)(capaddr + 9));␊
136␉␊
137␉DBG("capaddr=%x opaddr=%x eecp=%x\n", capaddr, opaddr, eecp);␊
138␉␊
139␉usbcmd = *((unsigned int*)(opaddr));␉␉␉// Command Register␊
140␉usbsts = *((unsigned int*)(opaddr + 4));␉␉// Status Register␊
141␉usbintr = *((unsigned int*)(opaddr + 8));␉␉// Interrupt Enable Register␊
142␉␊
143␉DBG("usbcmd=%08x usbsts=%08x usbintr=%08x\n", usbcmd, usbsts, usbintr);␊
144␉␊
145␉// read PCI Config 32bit USBLEGSUP (eecp+0) ␊
146␉usblegsup = pci_config_read32(pci_dev->dev.addr, eecp);␊
147␉␊
148␉// informational only␊
149␉isBIOSowned = !!((usblegsup) & (1 << (16)));␊
150␉isOSowned = !!((usblegsup) & (1 << (24)));␊
151␉␊
152␉// read PCI Config 32bit USBLEGCTLSTS (eecp+4) ␊
153␉usblegctlsts = pci_config_read32(pci_dev->dev.addr, eecp + 4);␊
154␉␊
155␉DBG("usblegsup=%08x isOSowned=%d isBIOSowned=%d usblegctlsts=%08x\n", usblegsup, isOSowned, isBIOSowned, usblegctlsts);␊
156␉␊
157␉// Reset registers to Legacy OFF␊
158␉DBG("Clearing USBLEGCTLSTS\n");␊
159␉pci_config_write32(pci_dev->dev.addr, eecp + 4, 0);␉//usblegctlsts␊
160␉␊
161␉// if delay value is in milliseconds it doesn't appear to work. ␊
162␉// setting value to anything up to 65535 does not add the expected delay here.␊
163␉delay(100);␊
164␉␊
165␉usbcmd = *((unsigned int*)(opaddr));␊
166␉usbsts = *((unsigned int*)(opaddr + 4));␊
167␉usbintr = *((unsigned int*)(opaddr + 8));␊
168␉␊
169␉DBG("usbcmd=%08x usbsts=%08x usbintr=%08x\n", usbcmd, usbsts, usbintr);␊
170␉␊
171␉DBG("Clearing Registers\n");␊
172␉␊
173␉// clear registers to default␊
174␉usbcmd = (usbcmd & 0xffffff00);␊
175␉*((unsigned int*)(opaddr)) = usbcmd;␊
176␉*((unsigned int*)(opaddr + 8)) = 0;␉␉␉␉␉//usbintr - clear interrupt registers␊
177␉*((unsigned int*)(opaddr + 4)) = 0x1000;␉␉␉//usbsts - clear status registers ␉␊
178␉pci_config_write32(pci_dev->dev.addr, eecp, 1);␉␉//usblegsup␊
179␉␊
180␉// get the results␊
181␉usbcmd = *((unsigned int*)(opaddr));␊
182␉usbsts = *((unsigned int*)(opaddr + 4));␊
183␉usbintr = *((unsigned int*)(opaddr + 8));␊
184␉␊
185␉DBG("usbcmd=%08x usbsts=%08x usbintr=%08x\n", usbcmd, usbsts, usbintr);␊
186␉␊
187␉// read 32bit USBLEGSUP (eecp+0) ␊
188␉usblegsup = pci_config_read32(pci_dev->dev.addr, eecp);␊
189␉␊
190␉// informational only␊
191␉isBIOSowned = !!((usblegsup) & (1 << (16)));␊
192␉isOSowned = !!((usblegsup) & (1 << (24)));␊
193␉␊
194␉// read 32bit USBLEGCTLSTS (eecp+4) ␊
195␉usblegctlsts = pci_config_read32(pci_dev->dev.addr, eecp + 4);␊
196␉␊
197␉DBG("usblegsup=%08x isOSowned=%d isBIOSowned=%d usblegctlsts=%08x\n", usblegsup, isOSowned, isBIOSowned, usblegctlsts);␊
198␉␊
199␉verbose("Legacy USB Off Done\n");␉␊
200␉return 1;␊
201}␊
202␊
203int ehci_acquire (pci_dt_t *pci_dev)␊
204{␊
205␉int␉␉j, k;␊
206␉uint32_t␉base;␊
207␉uint8_t␉␉eecp;␊
208␉uint8_t␉␉legacy[8];␊
209␉bool␉␉isOwnershipConflict;␉␊
210␉bool␉␉alwaysHardBIOSReset;␊
211␊
212␉alwaysHardBIOSReset = false;␉␊
213␉if (!getBoolForKey(kEHCIhardKey, &alwaysHardBIOSReset, &bootInfo->bootConfig)) {␊
214␉␉alwaysHardBIOSReset = true;␊
215␉}␊
216␊
217␉pci_config_write16(pci_dev->dev.addr, 0x04, 0x0002);␊
218␉base = pci_config_read32(pci_dev->dev.addr, 0x10);␊
219␊
220␉verbose("EHCI controller [%04x:%04x] at %02x:%2x.%x DMA @%x\n", ␊
221␉␉pci_dev->vendor_id, pci_dev->device_id,␊
222␉␉pci_dev->dev.bits.bus, pci_dev->dev.bits.dev, pci_dev->dev.bits.func, ␊
223␉␉base);␊
224␊
225␉if (*((unsigned char*)base) < 0xc)␊
226␉{␊
227␉␉DBG("Config space too small: no legacy implementation\n");␊
228␉␉return 1;␊
229␉}␊
230␉eecp = *((unsigned char*)(base + 9));␊
231␉if (!eecp) {␊
232␉␉DBG("No extended capabilities: no legacy implementation\n");␊
233␉␉return 1;␊
234␉}␊
235␊
236␉DBG("eecp=%x\n",eecp);␊
237␊
238␉// bad way to do it␊
239␉// pci_conf_write(pci_dev->dev.addr, eecp, 4, 0x01000001);␊
240␉for (j = 0; j < 8; j++) {␊
241␉␉legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j);␊
242␉␉DBG("%02x ", legacy[j]);␊
243␉}␊
244␉DBG("\n");␊
245␊
246␉//Real Job: based on orByte's AppleUSBEHCI.cpp␊
247␉//We try soft reset first - some systems hang on reboot with hard reset␊
248␉// Definitely needed during reboot on 10.4.6␊
249␊
250␉isOwnershipConflict = ((legacy[3] & 1 != 0) && (legacy[2] & 1 != 0));␊
251␉if (!alwaysHardBIOSReset && isOwnershipConflict) {␊
252␉␉DBG("EHCI - Ownership conflict - attempting soft reset ...\n");␊
253␉␉DBG("EHCI - toggle OS Ownership to 0\n");␊
254␉␉pci_config_write8(pci_dev->dev.addr, eecp + 3, 0);␊
255␉␉for (k = 0; k < 25; k++) {␊
256␉␉␉for (j = 0; j < 8; j++) {␊
257␉␉␉␉legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j);␊
258␉␉␉}␊
259␉␉␉if (legacy[3] == 0) {␊
260␉␉␉␉break;␊
261␉␉␉}␊
262␉␉␉delay(10);␊
263␉␉}␊
264␉}␉␊
265␊
266␉DBG("Found USBLEGSUP_ID - value %x:%x - writing OSOwned\n", legacy[3],legacy[2]);␊
267␉pci_config_write8(pci_dev->dev.addr, eecp + 3, 1);␊
268␊
269␉// wait for kEHCI_USBLEGSUP_BIOSOwned bit to clear␊
270␉for (k = 0; k < 25; k++) {␊
271␉␉for (j = 0;j < 8; j++) {␊
272␉␉␉legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j);␊
273␉␉}␊
274␉␉DBG ("%x:%x,",legacy[3],legacy[2]);␊
275␉␉if (legacy[2] == 0) {␊
276␉␉␉break;␊
277␉␉}␊
278␉␉delay(10);␊
279␉}␊
280␊
281␉for (j = 0;j < 8; j++) {␊
282␉␉legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j);␊
283␉}␊
284␉isOwnershipConflict = ((legacy[2]) != 0);␊
285␉if (isOwnershipConflict) {␊
286␉␉// Soft reset has failed. Assume SMI being ignored␊
287␉␉// Hard reset␊
288␉␉// Force Clear BIOS BIT␊
289␉␉DBG("EHCI - Ownership conflict - attempting hard reset ...\n");␉␉␉␊
290␉␉DBG ("%x:%x\n",legacy[3],legacy[2]);␊
291␉␉DBG("EHCI - Force BIOS Ownership to 0\n");␊
292␊
293␉␉pci_config_write8(pci_dev->dev.addr, eecp + 2, 0);␊
294␉␉for (k = 0; k < 25; k++) {␊
295␉␉␉for (j = 0; j < 8; j++) {␊
296␉␉␉␉legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j);␊
297␉␉␉}␊
298␉␉␉DBG ("%x:%x,",legacy[3],legacy[2]);␊
299␊
300␉␉␉if ((legacy[2]) == 0) {␊
301␉␉␉␉break;␊
302␉␉␉}␊
303␉␉␉delay(10);␉␊
304␉␉}␉␉␊
305␉␉// Disable further SMI events␊
306␉␉for (j = 4; j < 8; j++) {␊
307␉␉␉pci_config_write8(pci_dev->dev.addr, eecp + j, 0);␊
308␉␉}␊
309␉}␊
310␊
311␉for (j = 0; j < 8; j++) {␊
312␉␉legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j);␊
313␉}␊
314␊
315␉DBG ("%x:%x\n",legacy[3],legacy[2]);␊
316␊
317␉// Final Ownership Resolution Check...␊
318␉if (legacy[2] & 1) {␉␉␉␉␉␊
319␉␉DBG("EHCI controller unable to take control from BIOS\n");␊
320␉␉return 0;␊
321␉}␊
322␊
323␉DBG("EHCI Acquire OS Ownership done\n");␉␊
324␉return 1;␊
325}␊
326␊
327int uhci_reset (pci_dt_t *pci_dev)␊
328{␊
329␉uint32_t base, port_base;␊
330␉␊
331␉base = pci_config_read32(pci_dev->dev.addr, 0x20);␊
332␉port_base = (base >> 5) & 0x07ff;␊
333␊
334␉verbose("UHCI controller [%04x:%04x] at %02x:%2x.%x base %x(%x)\n", ␊
335␉␉pci_dev->vendor_id, pci_dev->device_id,␊
336␉␉pci_dev->dev.bits.bus, pci_dev->dev.bits.dev, pci_dev->dev.bits.func, ␊
337␉␉port_base, base);␊
338␉␊
339␉pci_config_write16(pci_dev->dev.addr, 0xc0, 0x8f00);␊
340␊
341␉outw (port_base, 0x0002);␊
342␉delay(10);␊
343␉outw (port_base+4,0);␊
344␉delay(10);␊
345␉outw (port_base,0);␊
346␉return 1;␊
347}␊
348

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