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1/*␊
2 * Add (c) here␊
3 *␊
4 * Copyright .... All rights reserved.␊
5 *␊
6 */␊
7␊
8#include "smbios_getters.h"␊
9␊
10#ifndef DEBUG_SMBIOS␊
11#define DEBUG_SMBIOS 0␊
12#endif␊
13␊
14#if DEBUG_SMBIOS␊
15#define DBG(x...)␉printf(x)␊
16#else␊
17#define DBG(x...)␊
18#endif␊
19␊
20␊
21bool getProcessorInformationExternalClock(returnType *value)␊
22{␊
23␉value->word = Platform.CPU.FSBFrequency/1000000;␊
24␉return true;␊
25}␊
26␊
27bool getProcessorInformationMaximumClock(returnType *value)␊
28{␊
29␉value->word = Platform.CPU.CPUFrequency/1000000;␊
30␉return true;␊
31}␊
32␊
33bool getSMBOemProcessorBusSpeed(returnType *value)␊
34{␊
35␉if (Platform.CPU.Vendor == 0x756E6547) // Intel␊
36␉{␉␉␊
37␉␉switch (Platform.CPU.Family) ␊
38␉␉{␊
39␉␉␉case 0x06:␊
40␉␉␉{␊
41␉␉␉␉switch (Platform.CPU.Model)␊
42␉␉␉␉{␊
43␉␉␉␉␉case 0x0D:␉␉␉␉␉// ?␊
44␉␉␉␉␉case CPU_MODEL_YONAH:␉␉// Yonah␉␉0x0E␊
45␉␉␉␉␉case CPU_MODEL_MEROM:␉␉// Merom␉␉0x0F␊
46␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉// Penryn␉␉0x17␊
47␉␉␉␉␉case CPU_MODEL_ATOM:␉␉// Atom 45nm␉0x1C␊
48␉␉␉␉␉␉return false;␊
49␊
50␉␉␉␉␉case 0x19:␉␉␉␉␉// Intel Core i5 650 @3.20 Ghz␊
51␉␉␉␉␉case CPU_MODEL_SANDY:␉␉// Intel Core i5, i7 LGA1155 sandy bridge␊
52 case CPU_MODEL_SANDY_XEON: ␊
53␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉// Intel Core i7 LGA1366 (45nm)␊
54␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉// Intel Core i5, i7 LGA1156 (45nm)␊
55␉␉␉␉␉case CPU_MODEL_DALES:␉␉// Intel Core i5, i7 LGA1156 (45nm) ???␊
56␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉// Intel Core i3, i5, i7 LGA1156 (32nm)␊
57␉␉␉␉␉case CPU_MODEL_WESTMERE:␉// Intel Core i7 LGA1366 (32nm) 6 Core␊
58␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␉// Intel Core i7 LGA1366 (45nm) 6 Core ???␊
59␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉// Intel Core i7 LGA1366 (45nm) 6 Core ???␊
60␉␉␉␉␉{␊
61␉␉␉␉␉␉// thanks to dgobe for i3/i5/i7 bus speed detection␊
62␉␉␉␉␉␉int nhm_bus = 0x3F;␊
63␉␉␉␉␉␉static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};␊
64␉␉␉␉␉␉unsigned long did, vid;␊
65␉␉␉␉␉␉int i;␊
66␉␉␉␉␉␉␊
67␉␉␉␉␉␉// Nehalem supports Scrubbing␊
68␉␉␉␉␉␉// First, locate the PCI bus where the MCH is located␊
69␉␉␉␉␉␉for(i = 0; i < sizeof(possible_nhm_bus); i++)␊
70␉␉␉␉␉␉{␊
71␉␉␉␉␉␉␉vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x00);␊
72␉␉␉␉␉␉␉did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x02);␊
73␉␉␉␉␉␉␉vid &= 0xFFFF;␊
74␉␉␉␉␉␉␉did &= 0xFF00;␊
75␉␉␉␉␉␉␉␊
76␉␉␉␉␉␉␉if(vid == 0x8086 && did >= 0x2C00)␊
77␉␉␉␉␉␉␉␉nhm_bus = possible_nhm_bus[i]; ␊
78␉␉␉␉␉␉}␊
79␉␉␉␉␉␉␊
80␉␉␉␉␉␉unsigned long qpimult, qpibusspeed;␊
81␉␉␉␉␉␉qpimult = pci_config_read32(PCIADDR(nhm_bus, 2, 1), 0x50);␊
82␉␉␉␉␉␉qpimult &= 0x7F;␊
83␉␉␉␉␉␉DBG("qpimult %d\n", qpimult);␊
84␉␉␉␉␉␉qpibusspeed = (qpimult * 2 * (Platform.CPU.FSBFrequency/1000000));␊
85␉␉␉␉␉␉// Rek: rounding decimals to match original mac profile info␊
86␉␉␉␉␉␉if (qpibusspeed%100 != 0)qpibusspeed = ((qpibusspeed+50)/100)*100;␊
87␉␉␉␉␉␉DBG("qpibusspeed %d\n", qpibusspeed);␊
88␉␉␉␉␉␉value->word = qpibusspeed;␊
89␉␉␉␉␉␉return true;␊
90␉␉␉␉␉}␊
91␉␉␉␉}␊
92␉␉␉}␊
93␉␉}␊
94␉}␊
95␉return false;␊
96}␊
97␊
98uint16_t simpleGetSMBOemProcessorType(void)␊
99{␊
100␉if (Platform.CPU.NoCores >= 4) ␊
101␉{␊
102␉␉return 0x0501;␉// Quad-Core Xeon␊
103␉}␊
104␉else if (Platform.CPU.NoCores == 1) ␊
105␉{␊
106␉␉return 0x0201;␉// Core Solo␊
107␉};␊
108␉␊
109␉return 0x0301;␉␉// Core 2 Duo␊
110}␊
111␊
112bool getSMBOemProcessorType(returnType *value)␊
113{␊
114␉static bool done = false;␉␉␊
115␉␉␊
116␉value->word = simpleGetSMBOemProcessorType();␊
117␊
118␉if (Platform.CPU.Vendor == 0x756E6547) // Intel␊
119␉{␊
120␉␉if (!done)␊
121␉␉{␊
122␉␉␉verbose("CPU is %s, family 0x%x, model 0x%x\n", Platform.CPU.BrandString, Platform.CPU.Family, Platform.CPU.Model);␊
123␉␉␉done = true;␊
124␉␉}␊
125␉␉␊
126␉␉switch (Platform.CPU.Family) ␊
127␉␉{␊
128␉␉␉case 0x06:␊
129␉␉␉{␊
130␉␉␉␉switch (Platform.CPU.Model)␊
131␉␉␉␉{␊
132␉␉␉␉␉case 0x0D:␉␉␉␉␉␉␉// ?␊
133␉␉␉␉␉case CPU_MODEL_YONAH:␉␉␉␉// Yonah␊
134␉␉␉␉␉case CPU_MODEL_MEROM:␉␉␉␉// Merom␊
135␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉␉␉// Penryn␊
136␉␉␉␉␉case CPU_MODEL_ATOM:␉␉␉␉// Intel Atom (45nm)␊
137␉␉␉␉␉␉return true;␊
138␊
139␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉␉␉// Intel Core i7 LGA1366 (45nm)␊
140␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)"))␊
141␉␉␉␉␉␉␉value->word = 0x0501;␉␉␉// Xeon ␊
142␉␉␉␉␉␉else␊
143␉␉␉␉␉␉␉value->word = 0x0701;␉␉␉// Core i7␊
144␊
145␉␉␉␉␉␉return true;␊
146␊
147␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉␉␉// Lynnfield, Clarksfield, Jasper␊
148␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊
149␉␉␉␉␉␉␉value->word = 0x601;␉␉// Core i5␊
150␉␉␉␉␉␉else␊
151␉␉␉␉␉␉␉value->word = 0x0701;␉␉// Core i7␊
152␉␉␉␉␉␉return true;␊
153␊
154␉␉␉␉␉case CPU_MODEL_DALES:␉␉␉␉// Intel Core i5, i7 LGA1156 (45nm) (Havendale, Auburndale)␊
155␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊
156␉␉␉␉␉␉␉value->word = 0x601;␉␉// Core i5␊
157␉␉␉␉␉␉else␊
158␉␉␉␉␉␉␉value->word = 0x0701;␉␉// Core i7␊
159␉␉␉␉␉␉return true;␊
160␊
161␉␉␉␉␉case CPU_MODEL_SANDY:␉␉␉␉// Intel Core i3, i5, i7 LGA1155 sandy bridge␊
162 case CPU_MODEL_SANDY_XEON:␊
163␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉␉␉// Intel Core i3, i5, i7 LGA1156 (32nm) (Clarkdale, Arrandale)␊
164␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3"))␊
165␉␉␉␉␉␉␉value->word = 0x901;␉␉// Core i3␊
166␉␉␉␉␉␉else␊
167␉␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊
168␉␉␉␉␉␉␉␉value->word = 0x601;␉// Core i5␊
169␉␉␉␉␉␉␉else␊
170␉␉␉␉␉␉␉␉value->word = 0x0701;␉// Core i7␊
171␉␉␉␉␉␉return true;␊
172␊
173␉␉␉␉␉case CPU_MODEL_WESTMERE:␉␉␉// Intel Core i7 LGA1366 (32nm) 6 Core (Gulftown, Westmere-EP, Westmere-WS)␊
174␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉␉␉// Intel Core i7 LGA1366 (45nm) 6 Core ???␊
175␉␉␉␉␉␉value->word = 0x0501;␉␉␉// Core i7␊
176␉␉␉␉␉␉return true;␊
177␊
178␉␉␉␉␉case 0x19:␉␉␉␉␉␉␉// Intel Core i5 650 @3.20 Ghz␊
179␉␉␉␉␉␉value->word = 0x601;␉␉␉// Core i5␊
180␉␉␉␉␉␉return true;␊
181␉␉␉␉}␊
182␉␉␉}␊
183␉␉}␊
184␉}␊
185␉␊
186␉return false;␊
187}␊
188␊
189bool getSMBMemoryDeviceMemoryType(returnType *value)␊
190{␊
191␉static int idx = -1;␊
192␉int␉map;␊
193␊
194␉idx++;␊
195␉if (idx < MAX_RAM_SLOTS)␊
196␉{␊
197␉␉map = Platform.DMI.DIMM[idx];␊
198␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Type != 0)␊
199␉␉{␊
200␉␉␉DBG("RAM Detected Type = %d\n", Platform.RAM.DIMM[map].Type);␊
201␉␉␉value->byte = Platform.RAM.DIMM[map].Type;␊
202␉␉␉return true;␊
203␉␉}␊
204␉}␊
205␉␊
206␉return false;␊
207//␉value->byte = SMB_MEM_TYPE_DDR2;␊
208//␉return true;␊
209}␊
210␊
211bool getSMBMemoryDeviceMemorySpeed(returnType *value)␊
212{␊
213␉static int idx = -1;␊
214␉int␉map;␊
215␊
216␉idx++;␊
217␉if (idx < MAX_RAM_SLOTS)␊
218␉{␊
219␉␉map = Platform.DMI.DIMM[idx];␊
220␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Frequency != 0)␊
221␉␉{␊
222␉␉␉DBG("RAM Detected Freq = %d Mhz\n", Platform.RAM.DIMM[map].Frequency);␊
223␉␉␉value->dword = Platform.RAM.DIMM[map].Frequency;␊
224␉␉␉return true;␊
225␉␉}␊
226␉}␊
227␊
228␉return false;␊
229//␉value->dword = 800;␊
230//␉return true;␊
231}␊
232␊
233bool getSMBMemoryDeviceManufacturer(returnType *value)␊
234{␊
235␉static int idx = -1;␊
236␉int␉map;␊
237␊
238␉idx++;␊
239␉if (idx < MAX_RAM_SLOTS)␊
240␉{␊
241␉␉map = Platform.DMI.DIMM[idx];␊
242␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].Vendor) > 0)␊
243␉␉{␊
244␉␉␉DBG("RAM Detected Vendor[%d]='%s'\n", idx, Platform.RAM.DIMM[map].Vendor);␊
245␉␉␉value->string = Platform.RAM.DIMM[map].Vendor;␊
246␉␉␉return true;␊
247␉␉}␊
248␉}␊
249␊
250//␉return false;␊
251␉value->string = NOT_AVAILABLE;␊
252␉return true;␊
253}␊
254␉␊
255bool getSMBMemoryDeviceSerialNumber(returnType *value)␊
256{␊
257␉static int idx = -1;␊
258␉int␉map;␊
259␊
260␉idx++;␊
261␉if (idx < MAX_RAM_SLOTS)␊
262␉{␊
263␉␉map = Platform.DMI.DIMM[idx];␊
264␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].SerialNo) > 0)␊
265␉␉{␊
266␉␉␉DBG("map=%d, RAM Detected SerialNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].SerialNo);␊
267␉␉␉value->string = Platform.RAM.DIMM[map].SerialNo;␊
268␉␉␉return true;␊
269␉␉}␊
270␉}␊
271␊
272//␉return false;␊
273␉value->string = NOT_AVAILABLE;␊
274␉return true;␊
275}␊
276␊
277bool getSMBMemoryDevicePartNumber(returnType *value)␊
278{␊
279␉static int idx = -1;␊
280␉int␉map;␊
281␊
282␉idx++;␊
283␉if (idx < MAX_RAM_SLOTS)␊
284␉{␊
285␉␉map = Platform.DMI.DIMM[idx];␊
286␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].PartNo) > 0)␊
287␉␉{␊
288␉␉␉DBG("map=%d, RAM Detected PartNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].PartNo);␊
289␉␉␉value->string = Platform.RAM.DIMM[map].PartNo;␊
290␉␉␉return true;␊
291␉␉}␊
292␉}␊
293␊
294//␉return false;␊
295␉value->string = NOT_AVAILABLE;␊
296␉return true;␊
297}␊
298␊
299␊
300// getting smbios addr with fast compare ops, late checksum testing ...␊
301#define COMPARE_DWORD(a,b) ( *((uint32_t *) a) == *((uint32_t *) b) )␊
302static const char * const SMTAG = "_SM_";␊
303static const char* const DMITAG = "_DMI_";␊
304␊
305SMBEntryPoint *getAddressOfSmbiosTable(void)␊
306{␊
307␉SMBEntryPoint␉*smbios;␊
308␉/* ␊
309␉ * The logic is to start at 0xf0000 and end at 0xfffff iterating 16 bytes at a time looking␊
310␉ * for the SMBIOS entry-point structure anchor (literal ASCII "_SM_").␊
311␉ */␊
312␉smbios = (SMBEntryPoint*)SMBIOS_RANGE_START;␊
313␉while (smbios <= (SMBEntryPoint *)SMBIOS_RANGE_END) {␊
314␉␉if (COMPARE_DWORD(smbios->anchor, SMTAG) && ␊
315␉␉␉COMPARE_DWORD(smbios->dmi.anchor, DMITAG) &&␊
316␉␉␉smbios->dmi.anchor[4] == DMITAG[4] &&␊
317␉␉␉checksum8(smbios, sizeof(SMBEntryPoint)) == 0)␊
318␉ {␊
319␉␉␉return smbios;␊
320␉ }␊
321␉␉smbios = (SMBEntryPoint*)(((char*)smbios) + 16);␊
322␉}␊
323␉printf("ERROR: Unable to find SMBIOS!\n");␊
324␉pause();␊
325␉return NULL;␊
326}␊
327␊
328

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