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Root/branches/Chimera/i386/libsaio/nvidia.c

1/*␊
2 * NVidia injector␊
3 *␊
4 * Copyright (C) 2009 Jasmin Fazlic, iNDi␊
5 *␊
6 * NVidia injector is free software: you can redistribute it and/or modify␊
7 * it under the terms of the GNU General Public License as published by␊
8 * the Free Software Foundation, either version 3 of the License, or␊
9 * (at your option) any later version.␊
10 *␊
11 * NVidia driver and injector is distributed in the hope that it will be useful,␊
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of␊
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the␊
14 * GNU General Public License for more details.␊
15 *␊
16 * You should have received a copy of the GNU General Public License␊
17 * along with NVidia injector. If not, see <http://www.gnu.org/licenses/>.␊
18 */ ␊
19/*␊
20 * Alternatively you can choose to comply with APSL␊
21 */␊
22 ␊
23 ␊
24/*␊
25 * DCB-Table parsing is based on software (nouveau driver) originally distributed under following license:␊
26 *␊
27 *␊
28 * Copyright 2005-2006 Erik Waling␊
29 * Copyright 2006 Stephane Marchesin␊
30 * Copyright 2007-2009 Stuart Bennett␊
31 *␊
32 * Permission is hereby granted, free of charge, to any person obtaining a␊
33 * copy of this software and associated documentation files (the "Software"),␊
34 * to deal in the Software without restriction, including without limitation␊
35 * the rights to use, copy, modify, merge, publish, distribute, sublicense,␊
36 * and/or sell copies of the Software, and to permit persons to whom the␊
37 * Software is furnished to do so, subject to the following conditions:␊
38 *␊
39 * The above copyright notice and this permission notice shall be included in␊
40 * all copies or substantial portions of the Software.␊
41 *␊
42 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR␊
43 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,␊
44 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL␊
45 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,␊
46 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF␊
47 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE␊
48 * SOFTWARE.␊
49 */␊
50␊
51#include "libsaio.h"␊
52#include "boot.h"␊
53#include "bootstruct.h"␊
54#include "pci.h"␊
55#include "platform.h"␊
56#include "device_inject.h"␊
57#include "nvidia.h"␊
58␊
59#ifndef DEBUG_NVIDIA␊
60#define DEBUG_NVIDIA 0␊
61#endif␊
62␊
63#if DEBUG_NVIDIA␊
64#define DBG(x...)␉printf(x)␊
65#else␊
66#define DBG(x...)␊
67#endif␊
68␊
69#define NVIDIA_ROM_SIZE 0x10000␊
70#define PATCH_ROM_SUCCESS 1␊
71#define PATCH_ROM_SUCCESS_HAS_LVDS 2␊
72#define PATCH_ROM_FAILED 0␊
73#define MAX_NUM_DCB_ENTRIES 16␊
74␊
75#define TYPE_GROUPED 0xff␊
76␊
77extern uint32_t devices_number;␊
78␊
79const char *nvidia_compatible_0[]␉=␉{ "@0,compatible",␉"NVDA,NVMac" };␊
80const char *nvidia_compatible_1[]␉=␉{ "@1,compatible",␉"NVDA,NVMac" };␊
81const char *nvidia_device_type_0[]␉=␉{ "@0,device_type",␉"display" };␊
82const char *nvidia_device_type_1[]␉=␉{ "@1,device_type",␉"display" };␊
83const char *nvidia_device_type[]␉=␉{ "device_type",␉"NVDA,Parent" };␊
84const char *nvidia_name_0[]␉␉=␉{ "@0,name",␉␉"NVDA,Display-A" };␊
85const char *nvidia_name_1[]␉␉=␉{ "@1,name",␉␉"NVDA,Display-B" };␊
86const char *nvidia_slot_name[]␉␉=␉{ "AAPL,slot-name",␉"Slot-1" };␊
87␊
88static uint8_t default_NVCAP[]= {␊
89␉0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0d, 0x00,␊
90␉0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a,␊
91␉0x00, 0x00, 0x00, 0x00␊
92};␊
93␊
94#define NVCAP_LEN ( sizeof(default_NVCAP) / sizeof(uint8_t) )␊
95␊
96static struct nv_chipsets_t NVKnownChipsets[] = {␊
97␉{ 0x00000000, "Unknown" },␊
98␉// 0040 - 004F␉␊
99␉{ 0x10DE0040, "GeForce 6800 Ultra" },␊
100␉{ 0x10DE0041, "GeForce 6800" },␊
101␉{ 0x10DE0042, "GeForce 6800 LE" },␊
102␉{ 0x10DE0043, "GeForce 6800 XE" },␊
103␉{ 0x10DE0044, "GeForce 6800 XT" },␊
104␉{ 0x10DE0045, "GeForce 6800 GT" },␊
105␉{ 0x10DE0046, "GeForce 6800 GT" },␊
106␉{ 0x10DE0047, "GeForce 6800 GS" },␊
107␉{ 0x10DE0048, "GeForce 6800 XT" },␊
108␉{ 0x10DE004D, "Quadro FX 3400" },␊
109␉{ 0x10DE004E, "Quadro FX 4000" },␊
110␉// 0050 - 005F␊
111␉// 0060 - 006F␉␊
112␉// 0070 - 007F␉␊
113␉// 0080 - 008F␉␊
114␉// 0090 - 009F␉␊
115␉{ 0x10DE0090, "GeForce 7800 GTX" },␊
116␉{ 0x10DE0091, "GeForce 7800 GTX" },␊
117␉{ 0x10DE0092, "GeForce 7800 GT" },␊
118␉{ 0x10DE0093, "GeForce 7800 GS" },␊
119␉{ 0x10DE0095, "GeForce 7800 SLI" },␊
120␉{ 0x10DE0098, "GeForce Go 7800" },␊
121␉{ 0x10DE0099, "GeForce Go 7800 GTX" },␊
122␉{ 0x10DE009D, "Quadro FX 4500" },␊
123␉// 00A0 - 00AF␉␊
124␉// 00B0 - 00BF␉␊
125␉// 00C0 - 00CF␉␊
126␉{ 0x10DE00C0, "GeForce 6800 GS" },␊
127␉{ 0x10DE00C1, "GeForce 6800" },␊
128␉{ 0x10DE00C2, "GeForce 6800 LE" },␊
129␉{ 0x10DE00C3, "GeForce 6800 XT" },␊
130␉{ 0x10DE00C8, "GeForce Go 6800" },␊
131␉{ 0x10DE00C9, "GeForce Go 6800 Ultra" },␊
132␉{ 0x10DE00CC, "Quadro FX Go1400" },␊
133␉{ 0x10DE00CD, "Quadro FX 3450/4000 SDI" },␊
134␉{ 0x10DE00CE, "Quadro FX 1400" },␊
135␉// 00D0 - 00DF␉␊
136␉// 00E0 - 00EF␉␊
137␉// 00F0 - 00FF␉␊
138␉{ 0x10DE00F1, "GeForce 6600 GT" },␊
139␉{ 0x10DE00F2, "GeForce 6600" },␊
140␉{ 0x10DE00F3, "GeForce 6200" },␊
141␉{ 0x10DE00F4, "GeForce 6600 LE" },␊
142␉{ 0x10DE00F5, "GeForce 7800 GS" },␊
143␉{ 0x10DE00F6, "GeForce 6800 GS/XT" },␊
144␉{ 0x10DE00F8, "Quadro FX 3400/4400" },␊
145␉{ 0x10DE00F9, "GeForce 6800 Series GPU" },␊
146␉// 0100 - 010F␉␊
147␉// 0110 - 011F␉␊
148␉// 0120 - 012F␉␊
149␉// 0130 - 013F␉␊
150␉// 0140 - 014F␉␊
151␉{ 0x10DE0140, "GeForce 6600 GT" },␊
152␉{ 0x10DE0141, "GeForce 6600" },␊
153␉{ 0x10DE0142, "GeForce 6600 LE" },␊
154␉{ 0x10DE0143, "GeForce 6600 VE" },␊
155␉{ 0x10DE0144, "GeForce Go 6600" },␊
156␉{ 0x10DE0145, "GeForce 6610 XL" },␊
157␉{ 0x10DE0146, "GeForce Go 6600 TE/6200 TE" },␊
158␉{ 0x10DE0147, "GeForce 6700 XL" },␊
159␉{ 0x10DE0148, "GeForce Go 6600" },␊
160␉{ 0x10DE0149, "GeForce Go 6600 GT" },␊
161␉{ 0x10DE014A, "Quadro NVS 440" },␊
162␉{ 0x10DE014C, "Quadro FX 550" },␊
163␉{ 0x10DE014D, "Quadro FX 550" },␊
164␉{ 0x10DE014E, "Quadro FX 540" },␊
165␉{ 0x10DE014F, "GeForce 6200" },␊
166␉// 0150 - 015F␉␊
167␉// 0160 - 016F␉␊
168␉{ 0x10DE0160, "GeForce 6500" },␊
169␉{ 0x10DE0161, "GeForce 6200 TurboCache(TM)" },␊
170␉{ 0x10DE0162, "GeForce 6200SE TurboCache(TM)" },␊
171␉{ 0x10DE0163, "GeForce 6200 LE" },␊
172␉{ 0x10DE0164, "GeForce Go 6200" },␊
173␉{ 0x10DE0165, "Quadro NVS 285" },␊
174␉{ 0x10DE0166, "GeForce Go 6400" },␊
175␉{ 0x10DE0167, "GeForce Go 6200" },␊
176␉{ 0x10DE0168, "GeForce Go 6400" },␊
177␉{ 0x10DE0169, "GeForce 6250" },␊
178␉{ 0x10DE016A, "GeForce 7100 GS" },␊
179␉// 0170 - 017F␉␊
180␉// 0180 - 018F␉␊
181␉// 0190 - 019F␉␉␊
182␉{ 0x10DE0191, "GeForce 8800 GTX" },␊
183␉{ 0x10DE0193, "GeForce 8800 GTS" },␊
184␉{ 0x10DE0194, "GeForce 8800 Ultra" },␊
185␉{ 0x10DE0197, "Tesla C870" },␊
186␉{ 0x10DE019D, "Quadro FX 5600" },␊
187␉{ 0x10DE019E, "Quadro FX 4600" },␊
188␉// 01A0 - 01AF␉␊
189␉// 01B0 - 01BF␉␊
190␉// 01C0 - 01CF␉␊
191␉// 01D0 - 01DF␉␉␊
192␉{ 0x10DE01D0, "GeForce 7350 LE" },␊
193␉{ 0x10DE01D1, "GeForce 7300 LE" },␊
194␉{ 0x10DE01D2, "GeForce 7550 LE" },␊
195␉{ 0x10DE01D3, "GeForce 7300 SE/7200 GS" },␊
196␉{ 0x10DE01D6, "GeForce Go 7200" },␊
197␉{ 0x10DE01D7, "GeForce Go 7300" },␊
198␉{ 0x10DE01D8, "GeForce Go 7400" },␊
199␉{ 0x10DE01D9, "GeForce Go 7400 GS" },␊
200␉{ 0x10DE01DA, "Quadro NVS 110M" },␊
201␉{ 0x10DE01DB, "Quadro NVS 120M" },␊
202␉{ 0x10DE01DC, "Quadro FX 350M" },␊
203␉{ 0x10DE01DD, "GeForce 7500 LE" },␊
204␉{ 0x10DE01DE, "Quadro FX 350" },␊
205␉{ 0x10DE01DF, "GeForce 7300 GS" },␊
206␉// 01E0 - 01EF␉␊
207␉// 01F0 - 01FF␊
208␉// 0200 - 020F␉␊
209␉// 0210 - 021F␉␊
210␉{ 0x10DE0211, "GeForce 6800" },␊
211␉{ 0x10DE0212, "GeForce 6800 LE" },␊
212␉{ 0x10DE0215, "GeForce 6800 GT" },␊
213␉{ 0x10DE0218, "GeForce 6800 XT" },␊
214␉// 0220 - 022F␉␊
215␉{ 0x10DE0221, "GeForce 6200" },␊
216␉{ 0x10DE0222, "GeForce 6200 A-LE" },␊
217␉// 0230 - 023F␉␊
218␉// 0240 - 024F␉␊
219␉{ 0x10DE0240, "GeForce 6150" },␊
220␉{ 0x10DE0241, "GeForce 6150 LE" },␊
221␉{ 0x10DE0242, "GeForce 6100" },␊
222␉{ 0x10DE0244, "GeForce Go 6150" },␊
223␉{ 0x10DE0245, "Quadro NVS 210S / GeForce 6150LE" },␊
224␉{ 0x10DE0247, "GeForce Go 6100" },␊
225␉// 0250 - 025F␉␊
226␉// 0260 - 026F␉␊
227␉// 0270 - 027F␉␊
228␉// 0280 - 028F␉␉␊
229␉// 0290 - 029F␉␊
230␉{ 0x10DE0290, "GeForce 7900 GTX" },␊
231␉{ 0x10DE0291, "GeForce 7900 GT/GTO" },␊
232␉{ 0x10DE0292, "GeForce 7900 GS" },␊
233␉{ 0x10DE0293, "GeForce 7950 GX2" },␊
234␉{ 0x10DE0294, "GeForce 7950 GX2" },␊
235␉{ 0x10DE0295, "GeForce 7950 GT" },␊
236␉{ 0x10DE0298, "GeForce Go 7900 GS" },␊
237␉{ 0x10DE0299, "GeForce Go 7900 GTX" },␊
238␉{ 0x10DE029A, "Quadro FX 2500M" },␊
239␉{ 0x10DE029B, "Quadro FX 1500M" },␊
240␉{ 0x10DE029C, "Quadro FX 5500" },␊
241␉{ 0x10DE029D, "Quadro FX 3500" },␊
242␉{ 0x10DE029E, "Quadro FX 1500" },␊
243␉{ 0x10DE029F, "Quadro FX 4500 X2" },␊
244␉// 02A0 - 02AF␉␊
245␉// 02B0 - 02BF␉␊
246␉// 02C0 - 02CF␉␊
247␉// 02D0 - 02DF␉␉␊
248␉// 02E0 - 02EF␉␉␊
249␉{ 0x10DE02E0, "GeForce 7600 GT" },␊
250␉{ 0x10DE02E1, "GeForce 7600 GS" },␊
251␉{ 0x10DE02E2, "GeForce 7300 GT" },␊
252␉{ 0x10DE02E3, "GeForce 7900 GS" },␊
253␉{ 0x10DE02E4, "GeForce 7950 GT" },␊
254␉// 02F0 - 02FF␉␉␊
255␉// 0300 - 030F␉␉␊
256␉{ 0x10DE0301, "GeForce FX 5800 Ultra" },␊
257␉{ 0x10DE0302, "GeForce FX 5800" },␊
258␉{ 0x10DE0308, "Quadro FX 2000" },␊
259␉{ 0x10DE0309, "Quadro FX 1000" },␊
260␉// 0310 - 031F␉␉␊
261␉{ 0x10DE0311, "GeForce FX 5600 Ultra" },␊
262␉{ 0x10DE0312, "GeForce FX 5600" },␊
263␉{ 0x10DE0314, "GeForce FX 5600XT" },␊
264␉{ 0x10DE031A, "GeForce FX Go5600" },␊
265␉{ 0x10DE031B, "GeForce FX Go5650" },␊
266␉{ 0x10DE031C, "Quadro FX Go700" },␊
267␉// 0320 - 032F␉␉␊
268␉{ 0x10DE0324, "GeForce FX Go5200" },␊
269␉{ 0x10DE0325, "GeForce FX Go5250" },␊
270␉{ 0x10DE0326, "GeForce FX 5500" },␊
271␉{ 0x10DE0328, "GeForce FX Go5200 32M/64M" },␊
272␉{ 0x10DE032A, "Quadro NVS 55/280 PCI" },␊
273␉{ 0x10DE032B, "Quadro FX 500/600 PCI" },␊
274␉{ 0x10DE032C, "GeForce FX Go53xx Series" },␊
275␉{ 0x10DE032D, "GeForce FX Go5100" },␊
276␉// 0330 - 033F␊
277␉{ 0x10DE0330, "GeForce FX 5900 Ultra" },␊
278␉{ 0x10DE0331, "GeForce FX 5900" },␊
279␉{ 0x10DE0332, "GeForce FX 5900XT" },␊
280␉{ 0x10DE0333, "GeForce FX 5950 Ultra" },␊
281␉{ 0x10DE0334, "GeForce FX 5900ZT" },␊
282␉{ 0x10DE0338, "Quadro FX 3000" },␊
283␉{ 0x10DE033F, "Quadro FX 700" },␊
284␉// 0340 - 034F␊
285␉{ 0x10DE0341, "GeForce FX 5700 Ultra" },␊
286␉{ 0x10DE0342, "GeForce FX 5700" },␊
287␉{ 0x10DE0343, "GeForce FX 5700LE" },␊
288␉{ 0x10DE0344, "GeForce FX 5700VE" },␊
289␉{ 0x10DE0347, "GeForce FX Go5700" },␊
290␉{ 0x10DE0348, "GeForce FX Go5700" },␊
291␉{ 0x10DE034C, "Quadro FX Go1000" },␊
292␉{ 0x10DE034E, "Quadro FX 1100" },␊
293␉// 0350 - 035F␉␊
294␉// 0360 - 036F␉␊
295␉// 0370 - 037F␉␊
296␉// 0380 - 038F␉␉␉␊
297␉{ 0x10DE038B, "GeForce 7650 GS" },␊
298␉// 0390 - 039F␊
299␉{ 0x10DE0390, "GeForce 7650 GS" },␊
300␉{ 0x10DE0391, "GeForce 7600 GT" },␊
301␉{ 0x10DE0392, "GeForce 7600 GS" },␊
302␉{ 0x10DE0393, "GeForce 7300 GT" },␊
303␉{ 0x10DE0394, "GeForce 7600 LE" },␊
304␉{ 0x10DE0395, "GeForce 7300 GT" },␊
305␉{ 0x10DE0397, "GeForce Go 7700" },␊
306␉{ 0x10DE0398, "GeForce Go 7600" },␊
307␉{ 0x10DE0399, "GeForce Go 7600 GT"},␊
308␉{ 0x10DE039A, "Quadro NVS 300M" },␊
309␉{ 0x10DE039B, "GeForce Go 7900 SE" },␊
310␉{ 0x10DE039C, "Quadro FX 550M" },␊
311␉{ 0x10DE039E, "Quadro FX 560" },␊
312␉// 03A0 - 03AF␉␊
313␉// 03B0 - 03BF␉␊
314␉// 03C0 - 03CF␉␊
315␉// 03D0 - 03DF␉␉␉␊
316␉{ 0x10DE03D0, "GeForce 6150SE nForce 430" },␊
317␉{ 0x10DE03D1, "GeForce 6100 nForce 405" },␊
318␉{ 0x10DE03D2, "GeForce 6100 nForce 400" },␊
319␉{ 0x10DE03D5, "GeForce 6100 nForce 420" },␊
320␉{ 0x10DE03D6, "GeForce 7025 / nForce 630a" },␊
321␉// 03E0 - 03EF␊
322␉// 03F0 - 03FF␊
323␉// 0400 - 040F␉␉␊
324␉{ 0x10DE0400, "GeForce 8600 GTS" },␊
325␉{ 0x10DE0401, "GeForce 8600 GT" },␊
326␉{ 0x10DE0402, "GeForce 8600 GT" },␊
327␉{ 0x10DE0403, "GeForce 8600 GS" },␊
328␉{ 0x10DE0404, "GeForce 8400 GS" },␊
329␉{ 0x10DE0405, "GeForce 9500M GS" },␊
330␉{ 0x10DE0406, "GeForce 8300 GS" },␊
331␉{ 0x10DE0407, "GeForce 8600M GT" },␊
332␉{ 0x10DE0408, "GeForce 9650M GS" },␊
333␉{ 0x10DE0409, "GeForce 8700M GT" },␊
334␉{ 0x10DE040A, "Quadro FX 370" },␊
335␉{ 0x10DE040B, "Quadro NVS 320M" },␊
336␉{ 0x10DE040C, "Quadro FX 570M" },␊
337␉{ 0x10DE040D, "Quadro FX 1600M" },␊
338␉{ 0x10DE040E, "Quadro FX 570" },␊
339␉{ 0x10DE040F, "Quadro FX 1700" },␊
340␉// 0410 - 041F␉␊
341␉{ 0x10DE0410, "GeForce GT 330" },␊
342␉// 0420 - 042F␉␊
343␉{ 0x10DE0420, "GeForce 8400 SE" },␊
344␉{ 0x10DE0421, "GeForce 8500 GT" },␊
345␉{ 0x10DE0422, "GeForce 8400 GS" },␊
346␉{ 0x10DE0423, "GeForce 8300 GS" },␊
347␉{ 0x10DE0424, "GeForce 8400 GS" },␊
348␉{ 0x10DE0425, "GeForce 8600M GS" },␊
349␉{ 0x10DE0426, "GeForce 8400M GT" },␊
350␉{ 0x10DE0427, "GeForce 8400M GS" },␊
351␉{ 0x10DE0428, "GeForce 8400M G" },␊
352␉{ 0x10DE0429, "Quadro NVS 140M" },␊
353␉{ 0x10DE042A, "Quadro NVS 130M" },␊
354␉{ 0x10DE042B, "Quadro NVS 135M" },␊
355␉{ 0x10DE042C, "GeForce 9400 GT" },␊
356␉{ 0x10DE042D, "Quadro FX 360M" },␊
357␉{ 0x10DE042E, "GeForce 9300M G" },␊
358␉{ 0x10DE042F, "Quadro NVS 290" },␊
359␉// 0430 - 043F␊
360␉// 0440 - 044F␊
361␉// 0450 - 045F␊
362␉// 0460 - 046F␊
363␉// 0470 - 047F␊
364␉// 0480 - 048F␊
365␉// 0490 - 049F␊
366␉// 04A0 - 04AF␊
367␉// 04B0 - 04BF␊
368␉// 04C0 - 04CF␊
369␉// 04D0 - 04DF␊
370␉// 04E0 - 04EF␊
371␉// 04F0 - 04FF␊
372␉// 0500 - 050F␉␊
373␉// 0510 - 051F␉␊
374␉// 0520 - 052F␉␊
375␉// 0530 - 053F␉␊
376␉{ 0x10DE053A, "GeForce 7050 PV / nForce 630a" },␊
377␉{ 0x10DE053B, "GeForce 7050 PV / nForce 630a" },␊
378␉{ 0x10DE053E, "GeForce 7025 / nForce 630a" },␊
379␉// 0540 - 054F␊
380␉// 0550 - 055F␊
381␉// 0560 - 056F␊
382␉// 0570 - 057F␊
383␉// 0580 - 058F␊
384␉// 0590 - 059F␊
385␉// 05A0 - 05AF␊
386␉// 05B0 - 05BF␊
387␉// 05C0 - 05CF␊
388␉// 05D0 - 05DF␊
389␉// 05E0 - 05EF␉␊
390␉{ 0x10DE05E0, "GeForce GTX 295" },␊
391␉{ 0x10DE05E1, "GeForce GTX 280" },␊
392␉{ 0x10DE05E2, "GeForce GTX 260" },␊
393␉{ 0x10DE05E3, "GeForce GTX 285" },␊
394␉{ 0x10DE05E6, "GeForce GTX 275" },␊
395␉{ 0x10DE05EA, "GeForce GTX 260" },␊
396␉{ 0x10DE05EB, "GeForce GTX 295" },␊
397␉{ 0x10DE05ED, "Quadroplex 2200 D2" },␊
398␉// 05F0 - 05FF␉␉␊
399␉{ 0x10DE05F8, "Quadroplex 2200 S4" },␊
400␉{ 0x10DE05F9, "Quadro CX" },␊
401␉{ 0x10DE05FD, "Quadro FX 5800" },␊
402␉{ 0x10DE05FE, "Quadro FX 4800" },␊
403␉{ 0x10DE05FF, "Quadro FX 3800" },␊
404␉// 0600 - 060F␉␊
405␉{ 0x10DE0600, "GeForce 8800 GTS 512" },␊
406␉{ 0x10DE0601, "GeForce 9800 GT" },␊
407␉{ 0x10DE0602, "GeForce 8800 GT" },␊
408␉{ 0x10DE0603, "GeForce GT 230" },␊
409␉{ 0x10DE0604, "GeForce 9800 GX2" },␊
410␉{ 0x10DE0605, "GeForce 9800 GT" },␊
411␉{ 0x10DE0606, "GeForce 8800 GS" },␊
412␉{ 0x10DE0607, "GeForce GTS 240" },␊
413␉{ 0x10DE0608, "GeForce 9800M GTX" },␊
414␉{ 0x10DE0609, "GeForce 8800M GTS" },␊
415␉{ 0x10DE060A, "GeForce GTX 280M" },␊
416␉{ 0x10DE060B, "GeForce 9800M GT" },␊
417␉{ 0x10DE060C, "GeForce 8800M GTX" },␊
418␉{ 0x10DE060D, "GeForce 8800 GS" },␊
419␉{ 0x10DE060F, "GeForce GTX 285M" },␊
420␉// 0610 - 061F␉␊
421␉{ 0x10DE0610, "GeForce 9600 GSO" },␊
422␉{ 0x10DE0611, "GeForce 8800 GT" },␊
423␉{ 0x10DE0612, "GeForce 9800 GTX" },␊
424␉{ 0x10DE0613, "GeForce 9800 GTX+" },␊
425␉{ 0x10DE0614, "GeForce 9800 GT" },␊
426␉{ 0x10DE0615, "GeForce GTS 250" },␊
427␉{ 0x10DE0617, "GeForce 9800M GTX" },␊
428␉{ 0x10DE0618, "GeForce GTX 260M" },␊
429␉{ 0x10DE0619, "Quadro FX 4700 X2" },␊
430␉{ 0x10DE061A, "Quadro FX 3700" },␊
431␉{ 0x10DE061B, "Quadro VX 200" },␊
432␉{ 0x10DE061C, "Quadro FX 3600M" },␊
433␉{ 0x10DE061D, "Quadro FX 2800M" },␊
434␉{ 0x10DE061F, "Quadro FX 3800M" },␊
435␉// 0620 - 062F␉␊
436␉{ 0x10DE0622, "GeForce 9600 GT" },␊
437␉{ 0x10DE0623, "GeForce 9600 GS" },␊
438␉{ 0x10DE0625, "GeForce 9600 GSO 512"},␊
439␉{ 0x10DE0626, "GeForce GT 130" },␊
440␉{ 0x10DE0627, "GeForce GT 140" },␊
441␉{ 0x10DE0628, "GeForce 9800M GTS" },␊
442␉{ 0x10DE062A, "GeForce 9700M GTS" },␊
443␉{ 0x10DE062C, "GeForce 9800M GTS" },␊
444␉{ 0x10DE062D, "GeForce 9600 GT" },␊
445␉{ 0x10DE062E, "GeForce 9600 GT" },␊
446␉// 0630 - 063F␉␊
447␉{ 0x10DE0631, "GeForce GTS 160M" },␊
448␉{ 0x10DE0632, "GeForce GTS 150M" },␊
449␉{ 0x10DE0635, "GeForce 9600 GSO" },␊
450␉{ 0x10DE0637, "GeForce 9600 GT" },␊
451␉{ 0x10DE0638, "Quadro FX 1800" },␊
452␉{ 0x10DE063A, "Quadro FX 2700M" },␊
453␉// 0640 - 064F␉␊
454␉{ 0x10DE0640, "GeForce 9500 GT" },␊
455␉{ 0x10DE0641, "GeForce 9400 GT" },␊
456␉{ 0x10DE0642, "GeForce 8400 GS" },␊
457␉{ 0x10DE0643, "GeForce 9500 GT" },␊
458␉{ 0x10DE0644, "GeForce 9500 GS" },␊
459␉{ 0x10DE0645, "GeForce 9500 GS" },␊
460␉{ 0x10DE0646, "GeForce GT 120" },␊
461␉{ 0x10DE0647, "GeForce 9600M GT" },␊
462␉{ 0x10DE0648, "GeForce 9600M GS" },␊
463␉{ 0x10DE0649, "GeForce 9600M GT" },␊
464␉{ 0x10DE064A, "GeForce 9700M GT" },␊
465␉{ 0x10DE064B, "GeForce 9500M G" },␊
466␉{ 0x10DE064C, "GeForce 9650M GT" },␊
467␉// 0650 - 065F␉␉␊
468␉{ 0x10DE0651, "GeForce G 110M" },␊
469␉{ 0x10DE0652, "GeForce GT 130M" },␊
470␉{ 0x10DE0653, "GeForce GT 120M" },␊
471␉{ 0x10DE0654, "GeForce GT 220M" },␊
472␉{ 0x10DE0656, "GeForce 9650 S" },␊
473␉{ 0x10DE0658, "Quadro FX 380" },␊
474␉{ 0x10DE0659, "Quadro FX 580" },␊
475␉{ 0x10DE065A, "Quadro FX 1700M" },␊
476␉{ 0x10DE065B, "GeForce 9400 GT" },␊
477␉{ 0x10DE065C, "Quadro FX 770M" },␊
478␉{ 0x10DE065F, "GeForce G210" },␊
479␉// 0660 - 066F␊
480␉// 0670 - 067F␊
481␉// 0680 - 068F␊
482␉// 0690 - 069F␊
483␉// 06A0 - 06AF␊
484␉// 06B0 - 06BF␊
485␉// 06C0 - 06CF␊
486␉{ 0x10DE06C0, "GeForce GTX 480" },␊
487␉{ 0x10DE06C3, "GeForce GTX D12U" },␊
488␉{ 0x10DE06C4, "GeForce GTX 465" },␊
489␉{ 0x10DE06CA, "GeForce GTX 480M" },␊
490␉{ 0x10DE06CD, "GeForce GTX 470" },␊
491␉// 06D0 - 06DF␊
492␉{ 0x10DE06D1, "Tesla C2050" },␉// TODO: sub-device id: 0x0771␊
493␉{ 0x10DE06D1, "Tesla C2070" },␉// TODO: sub-device id: 0x0772␊
494␉{ 0x10DE06D2, "Tesla M2070" },␊
495␉{ 0x10DE06D8, "Quadro 6000" },␊
496␉{ 0x10DE06D9, "Quadro 5000" },␊
497␉{ 0x10DE06DA, "Quadro 5000M" },␊
498␉{ 0x10DE06DC, "Quadro 6000" },␊
499␉{ 0x10DE06DD, "Quadro 4000" },␊
500␉{ 0x10DE06DE, "Tesla M2050" },␉// TODO: sub-device id: 0x0846␊
501␉{ 0x10DE06DE, "Tesla M2070" },␉// TODO: sub-device id: ?␉␊
502␉// 0x10DE06DE also applies to misc S2050, X2070, M2050, M2070␊
503␉// 06E0 - 06EF␉␊
504␉{ 0x10DE06E0, "GeForce 9300 GE" },␊
505␉{ 0x10DE06E1, "GeForce 9300 GS" },␊
506␉{ 0x10DE06E2, "GeForce 8400" },␊
507␉{ 0x10DE06E3, "GeForce 8400 SE" },␊
508␉{ 0x10DE06E4, "GeForce 8400 GS" },␊
509␉{ 0x10DE06E5, "GeForce 9300M GS" },␊
510␉{ 0x10DE06E6, "GeForce G100" },␊
511␉{ 0x10DE06E7, "GeForce 9300 SE" },␊
512␉{ 0x10DE06E8, "GeForce 9200M GS" },␊
513␉{ 0x10DE06E9, "GeForce 9300M GS" },␊
514␉{ 0x10DE06EA, "Quadro NVS 150M" },␊
515␉{ 0x10DE06EB, "Quadro NVS 160M" },␊
516␉{ 0x10DE06EC, "GeForce G 105M" },␊
517␉{ 0x10DE06EF, "GeForce G 103M" },␊
518␉// 06F0 - 06FF␉␊
519␉{ 0x10DE06F8, "Quadro NVS 420" },␊
520␉{ 0x10DE06F9, "Quadro FX 370 LP" },␊
521␉{ 0x10DE06FA, "Quadro NVS 450" },␊
522␉{ 0x10DE06FB, "Quadro FX 370M" },␊
523␉{ 0x10DE06FD, "Quadro NVS 295" },␊
524␉// 0700 - 070F␊
525␉// 0710 - 071F␊
526␉// 0720 - 072F␊
527␉// 0730 - 073F␊
528␉// 0740 - 074F␊
529␉// 0750 - 075F␊
530␉// 0760 - 076F␊
531␉// 0770 - 077F␊
532␉// 0780 - 078F␊
533␉// 0790 - 079F␊
534␉// 07A0 - 07AF␊
535␉// 07B0 - 07BF␊
536␉// 07C0 - 07CF␊
537␉// 07D0 - 07DF␉␊
538␉// 07E0 - 07EF␉␉␊
539␉{ 0x10DE07E0, "GeForce 7150 / nForce 630i" },␊
540␉{ 0x10DE07E1, "GeForce 7100 / nForce 630i" },␊
541␉{ 0x10DE07E2, "GeForce 7050 / nForce 630i" },␊
542␉{ 0x10DE07E3, "GeForce 7050 / nForce 610i" },␊
543␉{ 0x10DE07E5, "GeForce 7050 / nForce 620i" },␊
544␉// 07F0 - 07FF␉␊
545␉// 0800 - 080F␊
546␉// 0810 - 081F␊
547␉// 0820 - 082F␊
548␉// 0830 - 083F␊
549␉// 0840 - 084F␊
550␉{ 0x10DE0844, "GeForce 9100M G" },␊
551␉{ 0x10DE0845, "GeForce 8200M G" },␊
552␉{ 0x10DE0846, "GeForce 9200" },␊
553␉{ 0x10DE0847, "GeForce 9100" },␊
554␉{ 0x10DE0848, "GeForce 8300" },␊
555␉{ 0x10DE0849, "GeForce 8200" },␊
556␉{ 0x10DE084A, "nForce 730a" },␊
557␉{ 0x10DE084B, "GeForce 9200" },␊
558␉{ 0x10DE084C, "nForce 980a/780a SLI" },␊
559␉{ 0x10DE084D, "nForce 750a SLI" },␊
560␉{ 0x10DE084F, "GeForce 8100 / nForce 720a" },␊
561␉// 0850 - 085F␊
562␉// 0860 - 086F␉␊
563␉{ 0x10DE0860, "GeForce 9400" },␊
564␉{ 0x10DE0861, "GeForce 9400" },␊
565␉{ 0x10DE0862, "GeForce 9400M G" },␊
566␉{ 0x10DE0863, "GeForce 9400M" },␊
567␉{ 0x10DE0864, "GeForce 9300" },␊
568␉{ 0x10DE0865, "ION" },␊
569␉{ 0x10DE0866, "GeForce 9400M G" },␊
570␉{ 0x10DE0867, "GeForce 9400" },␊
571␉{ 0x10DE0868, "nForce 760i SLI" },␊
572␉{ 0x10DE086A, "GeForce 9400" },␊
573␉{ 0x10DE086C, "GeForce 9300 / nForce 730i" },␊
574␉{ 0x10DE086D, "GeForce 9200" },␊
575␉{ 0x10DE086E, "GeForce 9100M G" },␊
576␉{ 0x10DE086F, "GeForce 8200M G" },␊
577␉// 0870 - 087F␉␊
578␉{ 0x10DE0870, "GeForce 9400M" },␊
579␉{ 0x10DE0871, "GeForce 9200" },␊
580␉{ 0x10DE0872, "GeForce G102M" },␊
581␉{ 0x10DE0873, "GeForce G102M" },␊
582␉{ 0x10DE0874, "ION 9300M" },␉␊
583␉{ 0x10DE0876, "ION" },␊
584␉{ 0x10DE087A, "GeForce 9400" },␊
585␉{ 0x10DE087D, "ION 9400M" },␊
586␉{ 0x10DE087E, "ION LE" },␊
587␉{ 0x10DE087F, "ION LE" },␊
588␉// 0880 - 088F␊
589␉// 0890 - 089F␊
590␉// 08A0 - 08AF␊
591␉// 08B0 - 08BF␊
592␉// 08C0 - 08CF␊
593␉// 08D0 - 08DF␉␊
594␉// 08E0 - 08EF␉␉␉␊
595␉// 08F0 - 08FF␊
596␉// 0900 - 090F␊
597␉// 0910 - 091F␊
598␉// 0920 - 092F␊
599␉// 0930 - 093F␊
600␉// 0940 - 094F␊
601␉// 0950 - 095F␊
602␉// 0960 - 096F␊
603␉// 0970 - 097F␊
604␉// 0980 - 098F␊
605␉// 0990 - 099F␊
606␉// 09A0 - 09AF␊
607␉// 09B0 - 09BF␊
608␉// 09C0 - 09CF␊
609␉// 09D0 - 09DF␉␊
610␉// 09E0 - 09EF␊
611␉// 09F0 - 09FF␊
612␉// 0A00 - 0A0F␊
613␉// 0A10 - 0A1F␊
614␉// 0A20 - 0A2F␊
615␉{ 0x10DE0A20, "GeForce GT220" },␊
616␉{ 0x10DE0A22, "GeForce 315" },␊
617␉{ 0x10DE0A23, "GeForce 210" },␊
618␉{ 0x10DE0A28, "GeForce GT 230M" },␊
619␉{ 0x10DE0A29, "GeForce GT 330M" },␊
620␉{ 0x10DE0A2A, "GeForce GT 230M" },␊
621␉{ 0x10DE0A2B, "GeForce GT 330M" },␊
622␉{ 0x10DE0A2C, "NVS 5100M" },␊
623␉{ 0x10DE0A2D, "GeForce GT 320M" },␉␊
624␉// 0A30 - 0A3F␉␊
625␉{ 0x10DE0A34, "GeForce GT 240M" },␊
626␉{ 0x10DE0A35, "GeForce GT 325M" },␊
627␉{ 0x10DE0A3C, "Quadro FX 880M" },␊
628␉// 0A40 - 0A4F␊
629␉// 0A50 - 0A5F␊
630␉// 0A60 - 0A6F␊
631␉{ 0x10DE0A60, "GeForce G210" },␊
632␉{ 0x10DE0A62, "GeForce 205" },␊
633␉{ 0x10DE0A63, "GeForce 310" },␊
634␉{ 0x10DE0A64, "ION" },␊
635␉{ 0x10DE0A65, "GeForce 210" },␊
636␉{ 0x10DE0A66, "GeForce 310" },␊
637␉{ 0x10DE0A67, "GeForce 315" },␊
638␉{ 0x10DE0A68, "GeForce G105M" },␊
639␉{ 0x10DE0A69, "GeForce G105M" },␊
640␉{ 0x10DE0A6A, "NVS 2100M" },␊
641␉{ 0x10DE0A6C, "NVS 3100M" },␊
642␉{ 0x10DE0A6E, "GeForce 305M" },␊
643␉{ 0x10DE0A6F, "ION" },␉␊
644␉// 0A70 - 0A7F␊
645␉{ 0x10DE0A70, "GeForce 310M" },␊
646␉{ 0x10DE0A71, "GeForce 305M" },␊
647␉{ 0x10DE0A72, "GeForce 310M" },␊
648␉{ 0x10DE0A73, "GeForce 305M" },␊
649␉{ 0x10DE0A74, "GeForce G210M" },␊
650␉{ 0x10DE0A75, "GeForce G310M" },␊
651␉{ 0x10DE0A78, "Quadro FX 380 LP" },␊
652␉{ 0x10DE0A7C, "Quadro FX 380M" },␊
653␉// 0A80 - 0A8F␊
654␉// 0A90 - 0A9F␊
655␉// 0AA0 - 0AAF␊
656␉// 0AB0 - 0ABF␊
657␉// 0AC0 - 0ACF␊
658␉// 0AD0 - 0ADF␉␊
659␉// 0AE0 - 0AEF␊
660␉// 0AF0 - 0AFF␊
661␉// 0B00 - 0B0F␊
662␉// 0B10 - 0B1F␊
663␉// 0B20 - 0B2F␊
664␉// 0B30 - 0B3F␊
665␉// 0B40 - 0B4F␊
666␉// 0B50 - 0B5F␊
667␉// 0B60 - 0B6F␊
668␉// 0B70 - 0B7F␊
669␉// 0B80 - 0B8F␊
670␉// 0B90 - 0B9F␊
671␉// 0BA0 - 0BAF␊
672␉// 0BB0 - 0BBF␊
673␉// 0BC0 - 0BCF␊
674␉// 0BD0 - 0BDF␉␊
675␉// 0BE0 - 0BEF␊
676␉// 0BF0 - 0BFF␊
677␉// 0C00 - 0C0F␊
678␉// 0C10 - 0C1F␊
679␉// 0C20 - 0C2F␊
680␉// 0C30 - 0C3F␊
681␉// 0C40 - 0C4F␊
682␉// 0C50 - 0C5F␊
683␉// 0C60 - 0C6F␊
684␉// 0C70 - 0C7F␊
685␉// 0C80 - 0C8F␊
686␉// 0C90 - 0C9F␊
687␉// 0CA0 - 0CAF␊
688␉{ 0x10DE0CA0, "GeForce GT 330 " },␊
689␉{ 0x10DE0CA2, "GeForce GT 320" },␊
690␉{ 0x10DE0CA3, "GeForce GT 240" },␊
691␉{ 0x10DE0CA4, "GeForce GT 340" },␊
692␉{ 0x10DE0CA7, "GeForce GT 330" },␊
693␉{ 0x10DE0CA8, "GeForce GTS 260M" },␊
694␉{ 0x10DE0CA9, "GeForce GTS 250M" },␊
695␉{ 0x10DE0CAC, "GeForce 315" },␊
696␉{ 0x10DE0CAF, "GeForce GT 335M" },␊
697␉// 0CB0 - 0CBF␉␊
698␉{ 0x10DE0CB0, "GeForce GTS 350M" },␊
699␉{ 0x10DE0CB1, "GeForce GTS 360M" },␊
700␉{ 0x10DE0CBC, "Quadro FX 1800M" },␊
701␉// 0CC0 - 0CCF␊
702␉// 0CD0 - 0CDF␉␊
703␉// 0CE0 - 0CEF␊
704␉// 0CF0 - 0CFF␊
705␉// 0D00 - 0D0F␊
706␉// 0D10 - 0D1F␊
707␉// 0D20 - 0D2F␊
708␉// 0D30 - 0D3F␊
709␉// 0D40 - 0D4F␊
710␉// 0D50 - 0D5F␊
711␉// 0D60 - 0D6F␊
712␉// 0D70 - 0D7F␊
713␉// 0D80 - 0D8F␊
714␉// 0D90 - 0D9F␊
715␉// 0DA0 - 0DAF␉␊
716␉// 0DB0 - 0DBF␊
717␉// 0DC0 - 0DCF␊
718␉{ 0x10DE0DC0, "GeForce GT 440" },␊
719␉{ 0x10DE0DC1, "D12-P1-35" },␊
720␉{ 0x10DE0DC2, "D12-P1-35" },␊
721␉{ 0x10DE0DC4, "GeForce GTS 450" },␊
722␉{ 0x10DE0DC5, "GeForce GTS 450" },␊
723␉{ 0x10DE0DC6, "GeForce GTS 450" },␊
724␉{ 0x10DE0DCA, "GF10x" },␊
725␉// 0DD0 - 0DDF␉␊
726␉{ 0x10DE0DD1, "GeForce GTX 460M" },␊
727␉{ 0x10DE0DD2, "GeForce GT 445M" },␊
728␉{ 0x10DE0DD3, "GeForce GT 435M" },␊
729␉{ 0x10DE0DD8, "Quadro 2000" },␊
730␉{ 0x10DE0DDE, "GF106-ES" },␊
731␉{ 0x10DE0DDF, "GF106-INT" },␊
732␉// 0DE0 - 0DEF␉␊
733␉{ 0x10DE0DE0, "GeForce GT 440" },␊
734␉{ 0x10DE0DE1, "GeForce GT 430" },␊
735␉{ 0x10DE0DE2, "GeForce GT 420" },␊
736␉{ 0x10DE0DE5, "GeForce GT 530" },␊
737␉{ 0x10DE0DEB, "GeForce GT 555M" },␊
738␉{ 0x10DE0DEE, "GeForce GT 415M" },␊
739␉// 0DF0 - 0DFF␉␊
740␉{ 0x10DE0DF0, "GeForce GT 425M" },␊
741␉{ 0x10DE0DF1, "GeForce GT 420M" },␊
742␉{ 0x10DE0DF2, "GeForce GT 435M" },␊
743␉{ 0x10DE0DF3, "GeForce GT 420M" },␊
744␉{ 0x10DE0DF8, "Quadro 600" },␊
745␉{ 0x10DE0DFE, "GF108 ES" },␊
746␉{ 0x10DE0DFF, "GF108 INT" },␊
747␉// 0E00 - 0E0F␊
748␉// 0E10 - 0E1F␊
749␉// 0E20 - 0E2F␊
750␉{ 0x10DE0E21, "D12U-25" },␊
751␉{ 0x10DE0E22, "GeForce GTX 460" },␊
752␉{ 0x10DE0E23, "GeForce GTX 460 SE" },␊
753␉{ 0x10DE0E24, "GeForce GTX 460" },␊
754␉{ 0x10DE0E25, "D12U-50" },␊
755␉// 0E30 - 0E3F␉␊
756␉{ 0x10DE0E30, "GeForce GTX 470M" },␊
757␉{ 0x10DE0E38, "GF104GL" },␊
758␉{ 0x10DE0E3E, "GF104-ES" },␊
759␉{ 0x10DE0E3F, "GF104-INT" },␊
760␉// 0E40 - 0E4F␉␊
761␉// 0E50 - 0E5F␊
762␉// 0E60 - 0E6F␊
763␉// 0E70 - 0E7F␊
764␉// 0E80 - 0E8F␊
765␉// 0E90 - 0E9F␊
766␉// 0EA0 - 0EAF␊
767␉// 0EB0 - 0EBF␊
768␉// 0EC0 - 0ECF␊
769␉// 0ED0 - 0EDF␉␊
770␉// 0EE0 - 0EEF␊
771␉// 0EF0 - 0EFF␊
772␉// 0F00 - 0F0F␊
773␉// 0F10 - 0F1F␊
774␉// 0F20 - 0F2F␊
775␉// 0F30 - 0F3F␊
776␉// 0F40 - 0F4F␊
777␉// 0F50 - 0F5F␊
778␉// 0F60 - 0F6F␊
779␉// 0F70 - 0F7F␊
780␉// 0F80 - 0F8F␊
781␉// 0F90 - 0F9F␊
782␉// 0FA0 - 0FAF␊
783␉// 0FB0 - 0FBF␊
784␉// 0FC0 - 0FCF␊
785␉// 0FD0 - 0FDF␊
786␉// 0FE0 - 0FEF␊
787␉// 0FF0 - 0FFF␊
788␉// 1000 - 100F␊
789␉// 1010 - 101F␊
790␉// 1020 - 102F␊
791␉// 1030 - 103F␊
792␉// 1040 - 104F␊
793␉{ 0x10DE1040, "GeForce GT 520" },␉␊
794␉// 1050 - 105F␊
795␉{ 0x10DE1050, "GeForce GT 520M" },␊
796␉// 1060 - 106F␊
797␉// 1070 - 107F␊
798␉// 1080 - 108F␊
799␉{ 0x10DE1080, "GeForce GTX 580" },␊
800␉{ 0x10DE1081, "GeForce GTX 570" },␊
801␉{ 0x10DE1082, "GeForce GTX 560 Ti" },␊
802␉{ 0x10DE1083, "D13U" },␊
803␉{ 0x10DE1088, "GeForce GTX 590" },␊
804␉// 1090 - 109F␉␊
805␉{ 0x10DE1098, "D13U" },␊
806␉{ 0x10DE109A, "N12E-Q5" },␊
807␉// 10A0 - 10AF␊
808␉// 10B0 - 10BF␊
809␉// 10C0 - 10CF␊
810␉{ 0x10DE10C3, "GeForce 8400 GS" },␊
811␉// 1200 - ␊
812␉{ 0x10DE1200, "GeForce GTX 560 Ti" },␊
813␉{ 0x10DE1244, "GeForce GTX 550 Ti" },␊
814␉{ 0x10DE1245, "GeForce GTS 450" },␊
815};␊
816␊
817static uint16_t swap16(uint16_t x)␊
818{␊
819␉return (((x & 0x00FF) << 8) | ((x & 0xFF00) >> 8));␊
820}␊
821␊
822static uint16_t read16(uint8_t *ptr, uint16_t offset)␊
823{␊
824␉uint8_t ret[2];␊
825␉ret[0] = ptr[offset+1];␊
826␉ret[1] = ptr[offset];␊
827␉return *((uint16_t*)&ret);␊
828}␊
829␊
830#if 0␊
831static uint32_t swap32(uint32_t x)␊
832{␊
833␉return ((x & 0x000000FF) << 24) | ((x & 0x0000FF00) << 8 ) | ((x & 0x00FF0000) >> 8 ) | ((x & 0xFF000000) >> 24);␊
834}␊
835␊
836static uint8_t read8(uint8_t *ptr, uint16_t offset)␊
837{ ␊
838␉return ptr[offset];␊
839}␊
840␊
841static uint32_t read32(uint8_t *ptr, uint16_t offset)␊
842{␊
843␉uint8_t ret[4];␊
844␉ret[0] = ptr[offset+3];␊
845␉ret[1] = ptr[offset+2];␊
846␉ret[2] = ptr[offset+1];␊
847␉ret[3] = ptr[offset];␊
848␉return *((uint32_t*)&ret);␊
849}␊
850#endif␊
851␊
852static int patch_nvidia_rom(uint8_t *rom)␊
853{␊
854␉if (!rom || (rom[0] != 0x55 && rom[1] != 0xaa)) {␊
855␉␉printf("False ROM signature: 0x%02x%02x\n", rom[0], rom[1]);␊
856␉␉return PATCH_ROM_FAILED;␊
857␉}␊
858␉␊
859␉uint16_t dcbptr = swap16(read16(rom, 0x36));␊
860␉if(!dcbptr) {␊
861␉␉printf("no dcb table found\n");␊
862␉␉return PATCH_ROM_FAILED;␊
863␉}/* else␊
864␉ printf("dcb table at offset 0x%04x\n", dcbptr);␊
865␉ */␊
866␉uint8_t *dcbtable = &rom[dcbptr];␊
867␉uint8_t dcbtable_version = dcbtable[0];␊
868␉uint8_t headerlength = 0;␊
869␉uint8_t recordlength = 0;␊
870␉uint8_t numentries = 0;␊
871␉␊
872␉if(dcbtable_version >= 0x20) {␊
873␉␉uint32_t sig;␊
874␉␉␊
875␉␉if(dcbtable_version >= 0x30) {␊
876␉␉␉headerlength = dcbtable[1];␊
877␉␉␉numentries = dcbtable[2];␊
878␉␉␉recordlength = dcbtable[3];␊
879␉␉␉sig = *(uint32_t *)&dcbtable[6];␊
880␉␉} else {␊
881␉␉␉sig = *(uint32_t *)&dcbtable[4];␊
882␉␉␉headerlength = 8;␊
883␉␉}␊
884␉␉if (sig != 0x4edcbdcb) {␊
885␉␉␉printf("bad display config block signature (0x%8x)\n", sig);␊
886␉␉␉return PATCH_ROM_FAILED;␊
887␉␉}␊
888␉} else if (dcbtable_version >= 0x14) { /* some NV15/16, and NV11+ */␊
889␉␉char sig[8] = { 0 };␊
890␉␉␊
891␉␉strncpy(sig, (char *)&dcbtable[-7], 7);␊
892␉␉recordlength = 10;␊
893␉␉if (strcmp(sig, "DEV_REC")) {␊
894␉␉␉printf("Bad Display Configuration Block signature (%s)\n", sig);␊
895␉␉␉return PATCH_ROM_FAILED;␊
896␉␉}␊
897␉} else {␊
898␉␉printf("ERROR: dcbtable_version is 0x%X\n", dcbtable_version);␊
899␉␉return PATCH_ROM_FAILED;␊
900␉}␊
901␉␊
902␉if(numentries >= MAX_NUM_DCB_ENTRIES)␊
903␉␉numentries = MAX_NUM_DCB_ENTRIES;␊
904␉␊
905␉uint8_t num_outputs = 0, i=0;␊
906␉struct dcbentry {␊
907␉␉uint8_t type;␊
908␉␉uint8_t index;␊
909␉␉uint8_t *heads;␊
910␉} entries[numentries];␊
911␉␊
912␉for (i = 0; i < numentries; i++) {␊
913␉␉uint32_t connection;␊
914␉␉connection = *(uint32_t *)&dcbtable[headerlength + recordlength * i];␊
915␉␉/* Should we allow discontinuous DCBs? Certainly DCB I2C tables can be discontinuous */␊
916␉␉if ((connection & 0x0000000f) == 0x0000000f) /* end of records */ ␊
917␉␉␉continue;␊
918␉␉if (connection == 0x00000000) /* seen on an NV11 with DCB v1.5 */ ␊
919␉␉␉continue;␊
920␉␉if ((connection & 0xf) == 0x6) /* we skip type 6 as it doesnt appear on macbook nvcaps */␊
921␉␉␉continue;␊
922␉␉␊
923␉␉entries[num_outputs].type = connection & 0xf;␊
924␉␉entries[num_outputs].index = num_outputs;␊
925␉␉entries[num_outputs++].heads = (uint8_t*)&(dcbtable[(headerlength + recordlength * i) + 1]);␊
926␊
927␉}␊
928␉␊
929␉int has_lvds = false;␊
930␉uint8_t channel1 = 0, channel2 = 0;␊
931␉␊
932␉for(i=0; i<num_outputs; i++) {␊
933␉␉if(entries[i].type == 3) {␊
934␉␉␉has_lvds = true;␊
935␉␉␉//printf("found LVDS\n");␊
936␉␉␉channel1 |= ( 0x1 << entries[i].index);␊
937␉␉␉entries[i].type = TYPE_GROUPED;␊
938␉␉}␊
939␉}␊
940␉// if we have a LVDS output, we group the rest to the second channel␊
941␉if(has_lvds) {␊
942␉␉for(i=0; i<num_outputs; i++) {␊
943␉␉␉if(entries[i].type == TYPE_GROUPED)␊
944␉␉␉␉continue;␊
945␉␉␉channel2 |= ( 0x1 << entries[i].index);␊
946␉␉␉entries[i].type = TYPE_GROUPED;␊
947␉␉}␊
948␉} else {␊
949␉␉//␊
950␉␉int x;␊
951␉␉// we loop twice as we need to generate two channels␊
952␉␉for(x=0; x<=1; x++) {␊
953␉␉␉for(i=0; i<num_outputs; i++) {␊
954␉␉␉␉if(entries[i].type == TYPE_GROUPED)␊
955␉␉␉␉␉continue;␊
956␉␉␉␉// if type is TMDS, the prior output is ANALOG␊
957␉␉␉␉// we always group ANALOG and TMDS␊
958␉␉␉␉// if there is a TV output after TMDS, we group it to that channel as well␊
959␉␉␉␉if(i && entries[i].type == 0x2) {␊
960␉␉␉␉␉switch (x) {␊
961␉␉␉␉␉␉case 0:␊
962␉␉␉␉␉␉␉//printf("group channel 1\n");␊
963␉␉␉␉␉␉␉channel1 |= ( 0x1 << entries[i].index);␊
964␉␉␉␉␉␉␉entries[i].type = TYPE_GROUPED;␊
965␉␉␉␉␉␉␉if((entries[i-1].type == 0x0)) {␊
966␉␉␉␉␉␉␉␉channel1 |= ( 0x1 << entries[i-1].index);␊
967␉␉␉␉␉␉␉␉entries[i-1].type = TYPE_GROUPED;␊
968␉␉␉␉␉␉␉}␊
969␉␉␉␉␉␉␉// group TV as well if there is one␊
970␉␉␉␉␉␉␉if( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) ) {␊
971␉␉␉␉␉␉␉␉//␉printf("group tv1\n");␊
972␉␉␉␉␉␉␉␉channel1 |= ( 0x1 << entries[i+1].index);␊
973␉␉␉␉␉␉␉␉entries[i+1].type = TYPE_GROUPED;␊
974␉␉␉␉␉␉␉}␊
975␉␉␉␉␉␉␉break;␊
976␉␉␉␉␉␉case 1:␊
977␉␉␉␉␉␉␉//printf("group channel 2 : %d\n", i);␊
978␉␉␉␉␉␉␉channel2 |= ( 0x1 << entries[i].index);␊
979␉␉␉␉␉␉␉entries[i].type = TYPE_GROUPED;␊
980␉␉␉␉␉␉␉if((entries[i-1].type == 0x0)) {␊
981␉␉␉␉␉␉␉␉channel2 |= ( 0x1 << entries[i-1].index);␊
982␉␉␉␉␉␉␉␉entries[i-1].type = TYPE_GROUPED;␊
983␉␉␉␉␉␉␉}␊
984␉␉␉␉␉␉␉// group TV as well if there is one␊
985␉␉␉␉␉␉␉if( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) ) {␊
986␉␉␉␉␉␉␉␉//␉printf("group tv2\n");␊
987␉␉␉␉␉␉␉␉channel2 |= ( 0x1 << entries[i+1].index);␊
988␉␉␉␉␉␉␉␉entries[i+1].type = TYPE_GROUPED;␊
989␉␉␉␉␉␉␉}␊
990␉␉␉␉␉␉␉break;␊
991␉␉␉␉␉␉␉␊
992␉␉␉␉␉}␊
993␉␉␉␉␉break;␊
994␉␉␉␉}␊
995␉␉␉}␊
996␉␉}␊
997␉}␊
998␉␊
999␉// if we have left ungrouped outputs merge them to the empty channel␊
1000␉uint8_t *togroup;// = (channel1 ? (channel2 ? NULL : &channel2) : &channel1);␊
1001␉togroup = &channel2;␊
1002␉for(i=0; i<num_outputs;i++)␊
1003␉␉if(entries[i].type != TYPE_GROUPED) {␊
1004␉␉␉//printf("%d not grouped\n", i);␊
1005␉␉␉if(togroup)␊
1006␉␉␉␉*togroup |= ( 0x1 << entries[i].index);␊
1007␉␉␉entries[i].type = TYPE_GROUPED;␊
1008␉␉}␊
1009␉␊
1010␉if(channel1 > channel2) {␊
1011␉␉uint8_t buff = channel1;␊
1012␉␉channel1 = channel2;␊
1013␉␉channel2 = buff;␊
1014␉}␊
1015␉␊
1016␉default_NVCAP[6] = channel1;␊
1017␉default_NVCAP[8] = channel2;␊
1018␉␊
1019␉// patching HEADS␊
1020␉for(i=0; i<num_outputs;i++) {␊
1021␉␉if(channel1 & (1 << i))␊
1022␉␉␉*entries[i].heads = 1;␊
1023␉␉else if(channel2 & (1 << i))␊
1024␉␉␉*entries[i].heads = 2;␊
1025␉}␊
1026␉␊
1027␉return (has_lvds ? PATCH_ROM_SUCCESS_HAS_LVDS : PATCH_ROM_SUCCESS);␊
1028}␊
1029␊
1030static char *get_nvidia_model(uint32_t id) {␊
1031␉int␉i;␊
1032␊
1033␉for (i=1; i< (sizeof(NVKnownChipsets) / sizeof(NVKnownChipsets[0])); i++) {␊
1034␉␉if (NVKnownChipsets[i].device == id) {␊
1035␉␉␉return NVKnownChipsets[i].name;␊
1036␉␉}␊
1037␉}␊
1038␉return NVKnownChipsets[0].name;␊
1039}␊
1040␊
1041static uint32_t load_nvidia_bios_file(const char *filename, uint8_t *buf, int bufsize)␊
1042{␊
1043␉int␉fd;␊
1044␉int␉size;␊
1045␊
1046␉if ((fd = open_bvdev("bt(0,0)", filename, 0)) < 0) {␊
1047␉␉return 0;␊
1048␉}␊
1049␉size = file_size(fd);␊
1050␉if (size > bufsize) {␊
1051␉␉printf("Filesize of %s is bigger than expected! Truncating to 0x%x Bytes!\n", filename, bufsize);␊
1052␉␉size = bufsize;␊
1053␉}␊
1054␉size = read(fd, (char *)buf, size);␊
1055␉close(fd);␊
1056␉return size > 0 ? size : 0;␊
1057}␊
1058␊
1059static int devprop_add_nvidia_template(struct DevPropDevice *device)␊
1060{␊
1061␉char␉tmp[16]; ␊
1062␊
1063␉if(!device)␊
1064␉␉return 0;␊
1065␊
1066␉if(!DP_ADD_TEMP_VAL(device, nvidia_compatible_0))␊
1067␉␉return 0;␊
1068␉if(!DP_ADD_TEMP_VAL(device, nvidia_device_type_0))␊
1069␉␉return 0;␊
1070␉if(!DP_ADD_TEMP_VAL(device, nvidia_name_0))␊
1071␉␉return 0;␊
1072␉if(!DP_ADD_TEMP_VAL(device, nvidia_compatible_1))␊
1073␉␉return 0;␊
1074␉if(!DP_ADD_TEMP_VAL(device, nvidia_device_type_1))␊
1075␉␉return 0;␊
1076␉if(!DP_ADD_TEMP_VAL(device, nvidia_name_1))␊
1077␉␉return 0;␊
1078␉if(!DP_ADD_TEMP_VAL(device, nvidia_device_type))␊
1079␉␉return 0;␊
1080␉// Rek : Dont use sprintf return, it does not WORK !! our custom sprintf() always return 0!␊
1081␉// len = sprintf(tmp, "Slot-%x", devices_number);␊
1082␉sprintf(tmp, "Slot-%x",devices_number);␊
1083␉devprop_add_value(device, "AAPL,slot-name", (uint8_t *) tmp, strlen(tmp));␊
1084␉devices_number++;␊
1085␊
1086␉return 1;␊
1087}␊
1088␊
1089int hex2bin(const char *hex, uint8_t *bin, int len)␊
1090{␊
1091␉char␉*p;␊
1092␉int␉i;␊
1093␉char␉buf[3];␊
1094 ␊
1095␉if (hex == NULL || bin == NULL || len <= 0 || strlen(hex) != len * 2) {␊
1096␉␉printf("[ERROR] bin2hex input error\n");␊
1097␉␉return -1;␊
1098␉}␊
1099 ␊
1100␉buf[2] = '\0';␊
1101␉p = (char *) hex;␊
1102␉for (i=0; i<len; i++) {␊
1103␉␉if (p[0] == '\0' || p[1] == '\0' || !isxdigit(p[0]) || !isxdigit(p[1])) {␊
1104␉␉␉printf("[ERROR] bin2hex '%s' syntax error\n", hex);␊
1105␉␉␉return -2;␊
1106␉␉}␊
1107␉␉buf[0] = *p++;␊
1108␉␉buf[1] = *p++;␊
1109␉␉bin[i] = (unsigned char) strtoul(buf, NULL, 16);␊
1110␉}␊
1111␉return 0;␊
1112}␊
1113␊
1114unsigned long long mem_detect(volatile uint8_t *regs, uint8_t nvCardType, pci_dt_t *nvda_dev)␊
1115{␊
1116␉unsigned long long vram_size = 0;␊
1117␊
1118␉if (nvCardType < NV_ARCH_50) {␊
1119␉␉vram_size = REG32(NV04_PFB_FIFO_DATA);␊
1120␉␉vram_size &= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK;␊
1121␉}␊
1122␉else if (nvCardType < NV_ARCH_C0) {␊
1123␉␉vram_size = REG32(NV04_PFB_FIFO_DATA);␊
1124␉␉vram_size |= (vram_size & 0xff) << 32;␊
1125␉␉vram_size &= 0xffffffff00ll;␊
1126␉}␊
1127␉else { // >= NV_ARCH_C0␊
1128␉␉vram_size = REG32(NVC0_MEM_CTRLR_RAM_AMOUNT) << 20;␊
1129␉␉vram_size *= REG32(NVC0_MEM_CTRLR_COUNT);␊
1130␉}␊
1131␉␊
1132␉// workaround code for GT 420/430 & 9600M GT␊
1133␉switch (nvda_dev->device_id)␊
1134␉{␊
1135␉␉case 0x0DE1: vram_size = 1024*1024*1024; break; // GT 430␊
1136␉␉case 0x0DE2: vram_size = 1024*1024*1024; break; // GT 420␊
1137␉␉case 0x0649: vram_size = 512*1024*1024; break; // 9600M GT␊
1138␉␉default: break;␊
1139␉}␊
1140␉␊
1141␉return vram_size;␊
1142}␊
1143␊
1144bool setup_nvidia_devprop(pci_dt_t *nvda_dev)␊
1145{␊
1146␉struct DevPropDevice␉␉*device;␊
1147␉char␉␉␉␉␉␉*devicepath;␊
1148␉option_rom_pci_header_t␉␉*rom_pci_header;␉␊
1149␉volatile uint8_t␉*regs;␊
1150␉uint8_t␉␉␉␉*rom;␊
1151␉uint8_t␉␉␉␉*nvRom;␊
1152␉uint8_t␉␉␉␉nvCardType;␊
1153␉unsigned long long␉videoRam;␊
1154␉uint32_t␉␉␉nvBiosOveride;␊
1155␉uint32_t␉␉␉bar[7];␊
1156␉uint32_t␉␉␉boot_display;␊
1157␉int␉␉␉␉␉nvPatch;␊
1158␉int␉␉␉␉␉len;␊
1159␉char␉␉␉␉biosVersion[32];␊
1160␉char␉␉␉␉nvFilename[32];␊
1161␉char␉␉␉␉kNVCAP[12];␊
1162␉char␉␉␉␉*model;␊
1163␉const char␉␉␉*value;␊
1164␉bool␉␉␉␉doit;␊
1165␊
1166␉devicepath = get_pci_dev_path(nvda_dev);␊
1167␉bar[0] = pci_config_read32(nvda_dev->dev.addr, 0x10 );␊
1168␉regs = (uint8_t *) (bar[0] & ~0x0f);␊
1169␉␉␊
1170␉// get card type␊
1171␉nvCardType = (REG32(0) >> 20) & 0x1ff;␊
1172␊
1173␉// Amount of VRAM in kilobytes␊
1174␉videoRam = mem_detect(regs, nvCardType, nvda_dev);␊
1175␉model = get_nvidia_model((nvda_dev->vendor_id << 16) | nvda_dev->device_id);␊
1176␉␊
1177␉verbose("nVidia %s %dMB NV%02x [%04x:%04x] :: %s\n", ␊
1178␉␉␉model, (uint32_t)(videoRam / 1024 / 1024),␊
1179␉␉␉(REG32(0) >> 20) & 0x1ff, nvda_dev->vendor_id, nvda_dev->device_id,␊
1180␉␉␉devicepath);␊
1181␊
1182␉rom = malloc(NVIDIA_ROM_SIZE);␊
1183␉sprintf(nvFilename, "/Extra/%04x_%04x.rom", (uint16_t)nvda_dev->vendor_id, (uint16_t)nvda_dev->device_id);␊
1184␉if (getBoolForKey(kUseNvidiaROM, &doit, &bootInfo->bootConfig) && doit) {␊
1185␉␉verbose("Looking for nvidia video bios file %s\n", nvFilename);␊
1186␉␉nvBiosOveride = load_nvidia_bios_file(nvFilename, rom, NVIDIA_ROM_SIZE);␊
1187␉␉if (nvBiosOveride > 0) {␊
1188␉␉␉verbose("Using nVidia Video BIOS File %s (%d Bytes)\n", nvFilename, nvBiosOveride);␊
1189␉␉␉DBG("%s Signature 0x%02x%02x %d bytes\n", nvFilename, rom[0], rom[1], nvBiosOveride);␊
1190␉␉} else {␊
1191␉␉␉printf("ERROR: unable to open nVidia Video BIOS File %s\n", nvFilename);␊
1192␉␉␉return false;␊
1193␉␉}␊
1194␉} else {␊
1195␉␉// Otherwise read bios from card␊
1196␉␉nvBiosOveride = 0;␊
1197␊
1198␉␉// TODO: we should really check for the signature before copying the rom, i think.␊
1199␊
1200␉␉// PRAMIN first␊
1201␉␉nvRom = (uint8_t*)&regs[NV_PRAMIN_OFFSET];␊
1202␉␉bcopy((uint32_t *)nvRom, rom, NVIDIA_ROM_SIZE);␊
1203␉␉␊
1204␉␉// Valid Signature ?␊
1205␉␉if (rom[0] != 0x55 && rom[1] != 0xaa) {␊
1206␉␉␉// PROM next␊
1207␉␉␉// Enable PROM access␊
1208␉␉␉(REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED;␊
1209␊
1210␉␉␉nvRom = (uint8_t*)&regs[NV_PROM_OFFSET];␊
1211␉␉␉bcopy((uint8_t *)nvRom, rom, NVIDIA_ROM_SIZE);␊
1212␉␉␉␊
1213␉␉␉// disable PROM access␊
1214␉␉␉(REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED;␉␊
1215␊
1216␉␉␉// Valid Signature ?␊
1217␉␉␉if (rom[0] != 0x55 && rom[1] != 0xaa) {␊
1218␉␉␉␉// 0xC0000 last␊
1219␉␉␉␉bcopy((char *)0xc0000, rom, NVIDIA_ROM_SIZE);␊
1220␉␉␉␉␊
1221␉␉␉␉// Valid Signature ?␊
1222␉␉␉␉if (rom[0] != 0x55 && rom[1] != 0xaa) {␊
1223␉␉␉␉␉printf("ERROR: Unable to locate nVidia Video BIOS\n");␊
1224␉␉␉␉␉return false;␊
1225␉␉␉␉} else {␊
1226␉␉␉␉␉DBG("ROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);␊
1227␉␉␉␉}␊
1228␉␉␉} else {␊
1229␉␉␉␉DBG("PROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);␊
1230␉␉␉}␊
1231␉␉} else {␊
1232␉␉␉DBG("PRAM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);␊
1233␉␉}␊
1234␉}␊
1235␊
1236␉if ((nvPatch = patch_nvidia_rom(rom)) == PATCH_ROM_FAILED) {␊
1237␉␉printf("ERROR: nVidia ROM Patching Failed!\n");␊
1238␉␉//return false;␊
1239␉}␊
1240␊
1241␉rom_pci_header = (option_rom_pci_header_t*)(rom + *(uint16_t *)&rom[24]);␊
1242␊
1243␉// check for 'PCIR' sig␊
1244␉if (rom_pci_header->signature == 0x50434952) {␊
1245␉␉if (rom_pci_header->device_id != nvda_dev->device_id) {␊
1246␉␉␉// Get Model from the OpROM␊
1247␉␉␉model = get_nvidia_model((rom_pci_header->vendor_id << 16) | rom_pci_header->device_id);␊
1248␉␉} else {␊
1249␉␉␉printf("nVidia incorrect PCI ROM signature: 0x%x\n", rom_pci_header->signature);␊
1250␉␉}␊
1251␉}␊
1252␊
1253␉if (!string) {␊
1254␉␉string = devprop_create_string();␊
1255␉}␊
1256␉device = devprop_add_device(string, devicepath);␊
1257␊
1258␉/* FIXME: for primary graphics card only */␊
1259␉boot_display = 1;␊
1260␉devprop_add_value(device, "@0,AAPL,boot-display", (uint8_t*)&boot_display, 4);␊
1261␊
1262␉if(nvPatch == PATCH_ROM_SUCCESS_HAS_LVDS) {␊
1263␉␉uint8_t built_in = 0x01;␊
1264␉␉devprop_add_value(device, "@0,built-in", &built_in, 1);␊
1265␉}␊
1266␉␊
1267␉// get bios version␊
1268␉const int MAX_BIOS_VERSION_LENGTH = 32;␊
1269␉char* version_str = (char*)malloc(MAX_BIOS_VERSION_LENGTH);␊
1270␉memset(version_str, 0, MAX_BIOS_VERSION_LENGTH);␊
1271␉int i, version_start;␊
1272␉int crlf_count = 0;␊
1273␉// only search the first 384 bytes␊
1274␉for(i = 0; i < 0x180; i++) {␊
1275␉␉if(rom[i] == 0x0D && rom[i+1] == 0x0A) {␊
1276␉␉␉crlf_count++;␊
1277␉␉␉// second 0x0D0A was found, extract bios version␊
1278␉␉␉if(crlf_count == 2) {␊
1279␉␉␉␉if(rom[i-1] == 0x20) i--; // strip last " "␊
1280␉␉␉␉for(version_start = i; version_start > (i-MAX_BIOS_VERSION_LENGTH); version_start--) {␊
1281␉␉␉␉␉// find start␊
1282␉␉␉␉␉if(rom[version_start] == 0x00) {␊
1283␉␉␉␉␉␉version_start++;␊
1284␉␉␉␉␉␉␊
1285␉␉␉␉␉␉// strip "Version "␊
1286␉␉␉␉␉␉if(strncmp((const char*)rom+version_start, "Version ", 8) == 0) {␊
1287␉␉␉␉␉␉␉version_start += 8;␊
1288␉␉␉␉␉␉}␊
1289␉␉␉␉␉␉␊
1290␉␉␉␉␉␉strncpy(version_str, (const char*)rom+version_start, i-version_start);␊
1291␉␉␉␉␉␉break;␊
1292␉␉␉␉␉}␊
1293␉␉␉␉}␊
1294␉␉␉␉break;␊
1295␉␉␉}␊
1296␉␉}␊
1297␉}␊
1298␉␊
1299␉sprintf(biosVersion, "%s", (nvBiosOveride > 0) ? nvFilename : version_str);␊
1300␊
1301␉sprintf(kNVCAP, "NVCAP_%04x", nvda_dev->device_id);␊
1302␉if (getValueForKey(kNVCAP, &value, &len, &bootInfo->bootConfig) && len == NVCAP_LEN * 2) {␊
1303␉␉uint8_t␉new_NVCAP[NVCAP_LEN];␊
1304 ␊
1305␉␉if (hex2bin(value, new_NVCAP, NVCAP_LEN) == 0) {␊
1306␉␉␉verbose("Using user supplied NVCAP for %s :: %s\n", model, devicepath);␊
1307␉␉␉memcpy(default_NVCAP, new_NVCAP, NVCAP_LEN);␊
1308␉␉}␊
1309␉}␊
1310␊
1311 #if DEBUG_NVCAP␊
1312 printf("NVCAP: %02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x\n",␊
1313␉␉default_NVCAP[0], default_NVCAP[1], default_NVCAP[2], default_NVCAP[3],␊
1314␉␉default_NVCAP[4], default_NVCAP[5], default_NVCAP[6], default_NVCAP[7],␊
1315␉␉default_NVCAP[8], default_NVCAP[9], default_NVCAP[10], default_NVCAP[11],␊
1316␉␉default_NVCAP[12], default_NVCAP[13], default_NVCAP[14], default_NVCAP[15],␊
1317␉␉default_NVCAP[16], default_NVCAP[17], default_NVCAP[18], default_NVCAP[19]);␊
1318#endif␊
1319 ␊
1320␉␊
1321␉devprop_add_nvidia_template(device);␊
1322␉devprop_add_value(device, "NVCAP", default_NVCAP, NVCAP_LEN);␊
1323␉devprop_add_value(device, "VRAM,totalsize", (uint8_t*)&videoRam, 4);␊
1324␉devprop_add_value(device, "model", (uint8_t*)model, strlen(model) + 1);␊
1325␉devprop_add_value(device, "rom-revision", (uint8_t*)biosVersion, strlen(biosVersion) + 1);␊
1326␉if (getBoolForKey(kVBIOS, &doit, &bootInfo->bootConfig) && doit) {␊
1327␉␉devprop_add_value(device, "vbios", rom, (nvBiosOveride > 0) ? nvBiosOveride : (rom[2] * 512));␊
1328␉}␊
1329␊
1330␉stringdata = malloc(sizeof(uint8_t) * string->length);␊
1331␉memcpy(stringdata, (uint8_t*)devprop_generate_string(string), string->length);␊
1332␉stringlength = string->length;␊
1333␊
1334␉return true;␊
1335}␊
1336

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