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Root/branches/azimutz/Cleancut/i386/modules/AMDGraphicsEnabler/ati_reg.h

1/*
2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
3 * VA Linux Systems Inc., Fremont, California.
4 *
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining
8 * a copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation on the rights to use, copy, modify, merge,
11 * publish, distribute, sublicense, and/or sell copies of the Software,
12 * and to permit persons to whom the Software is furnished to do so,
13 * subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial
17 * portions of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
20 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
22 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
23 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
24 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26 * DEALINGS IN THE SOFTWARE.
27 */
28
29/*
30 * Authors:
31 * Kevin E. Martin <martin@xfree86.org>
32 * Rickard E. Faith <faith@valinux.com>
33 * Alan Hourihane <alanh@fairlite.demon.co.uk>
34 *
35 * References:
36 *
37 * !!!! FIXME !!!!
38 * RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical
39 * Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April
40 * 1999.
41 *
42 * !!!! FIXME !!!!
43 * RAGE 128 Software Development Manual (Technical Reference Manual P/N
44 * SDK-G04000 Rev. 0.01), ATI Technologies: June 1999.
45 *
46 */
47
48/* !!!! FIXME !!!!NOTE: THIS FILE HAS BEEN CONVERTED FROM r128_reg.h
49 * AND CONTAINS REGISTERS AND REGISTER DEFINITIONS THAT ARE NOT CORRECT
50 * ON THE RADEON. A FULL AUDIT OF THIS CODE IS NEEDED! */
51
52#ifndef _ATI_REG_H_
53#define _ATI_REG_H_
54
55#define ATI_DATATYPE_VQ0
56#define ATI_DATATYPE_CI41
57#define ATI_DATATYPE_CI82
58#define ATI_DATATYPE_ARGB15553
59#define ATI_DATATYPE_RGB5654
60#define ATI_DATATYPE_RGB8885
61#define ATI_DATATYPE_ARGB88886
62#define ATI_DATATYPE_RGB3327
63#define ATI_DATATYPE_Y88
64#define ATI_DATATYPE_RGB89
65#define ATI_DATATYPE_CI1610
66#define ATI_DATATYPE_VYUY_42211
67#define ATI_DATATYPE_YVYU_42212
68#define ATI_DATATYPE_AYUV_44414
69#define ATI_DATATYPE_ARGB444415
70
71/* Registers for 2D/Video/Overlay */
72#define RADEON_ADAPTER_ID0x0f2c/* PCI */
73#define RADEON_AGP_BASE0x0170
74#define RADEON_AGP_CNTL0x0174
75#define RADEON_AGP_APER_SIZE_256MB (0x00 << 0)
76#define RADEON_AGP_APER_SIZE_128MB (0x20 << 0)
77#define RADEON_AGP_APER_SIZE_64MB (0x30 << 0)
78#define RADEON_AGP_APER_SIZE_32MB (0x38 << 0)
79#define RADEON_AGP_APER_SIZE_16MB (0x3c << 0)
80#define RADEON_AGP_APER_SIZE_8MB (0x3e << 0)
81#define RADEON_AGP_APER_SIZE_4MB (0x3f << 0)
82#define RADEON_AGP_APER_SIZE_MASK (0x3f << 0)
83#define RADEON_STATUS_PCI_CONFIG0x06
84#define RADEON_CAP_LIST 0x100000
85#define RADEON_CAPABILITIES_PTR_PCI_CONFIG0x34/* offset in PCI config*/
86#define RADEON_CAP_PTR_MASK 0xfc/* mask off reserved bits of CAP_PTR */
87#define RADEON_CAP_ID_NULL 0x00/* End of capability list */
88#define RADEON_CAP_ID_AGP 0x02/* AGP capability ID */
89#define RADEON_CAP_ID_EXP 0x10/* PCI Express */
90#define RADEON_AGP_COMMAND0x0f60/* PCI */
91#define RADEON_AGP_COMMAND_PCI_CONFIG0x0060/* offset in PCI config*/
92#define RADEON_AGP_ENABLE (1 << 8)
93#define RADEON_AGP_PLL_CNTL0x000b/* PLL */
94#define RADEON_AGP_STATUS0x0f5c/* PCI */
95#define RADEON_AGP_1X_MODE 0x01
96#define RADEON_AGP_2X_MODE 0x02
97#define RADEON_AGP_4X_MODE 0x04
98#define RADEON_AGP_FW_MODE 0x10
99#define RADEON_AGP_MODE_MASK 0x17
100#define RADEON_AGPv3_MODE 0x08
101#define RADEON_AGPv3_4X_MODE 0x01
102#define RADEON_AGPv3_8X_MODE 0x02
103#define RADEON_ATTRDR0x03c1/* VGA */
104#define RADEON_ATTRDW0x03c0/* VGA */
105#define RADEON_ATTRX0x03c0/* VGA */
106#define RADEON_AUX_WINDOW_HORZ_CNTL0x02d8
107#define RADEON_AUX_WINDOW_VERT_CNTL0x02dc
108
109#define RADEON_BASE_CODE0x0f0b
110#define RADEON_BIOS_0_SCRATCH0x0010
111#define RADEON_FP_PANEL_SCALABLE (1 << 16)
112#define RADEON_FP_PANEL_SCALE_EN (1 << 17)
113#define RADEON_FP_CHIP_SCALE_EN (1 << 18)
114#define RADEON_DRIVER_BRIGHTNESS_EN (1 << 26)
115#define RADEON_DISPLAY_ROT_MASK (3 << 28)
116#define RADEON_DISPLAY_ROT_00 (0 << 28)
117#define RADEON_DISPLAY_ROT_90 (1 << 28)
118#define RADEON_DISPLAY_ROT_180 (2 << 28)
119#define RADEON_DISPLAY_ROT_270 (3 << 28)
120#define RADEON_BIOS_1_SCRATCH0x0014
121#define RADEON_BIOS_2_SCRATCH0x0018
122#define RADEON_BIOS_3_SCRATCH0x001c
123#define RADEON_BIOS_4_SCRATCH0x0020
124#define RADEON_CRT1_ATTACHED_MASK (3 << 0)
125#define RADEON_CRT1_ATTACHED_MONO (1 << 0)
126#define RADEON_CRT1_ATTACHED_COLOR (2 << 0)
127#define RADEON_LCD1_ATTACHED (1 << 2)
128#define RADEON_DFP1_ATTACHED (1 << 3)
129#define RADEON_TV1_ATTACHED_MASK (3 << 4)
130#define RADEON_TV1_ATTACHED_COMP (1 << 4)
131#define RADEON_TV1_ATTACHED_SVIDEO (2 << 4)
132#define RADEON_CRT2_ATTACHED_MASK (3 << 8)
133#define RADEON_CRT2_ATTACHED_MONO (1 << 8)
134#define RADEON_CRT2_ATTACHED_COLOR (2 << 8)
135#define RADEON_DFP2_ATTACHED (1 << 11)
136#define RADEON_BIOS_5_SCRATCH0x0024
137#define RADEON_LCD1_ON(1 << 0)
138#define RADEON_CRT1_ON(1 << 1)
139#define RADEON_TV1_ON(1 << 2)
140#define RADEON_DFP1_ON(1 << 3)
141#define RADEON_CRT2_ON(1 << 5)
142#define RADEON_CV1_ON(1 << 6)
143#define RADEON_DFP2_ON(1 << 7)
144#define RADEON_LCD1_CRTC_MASK(1 << 8)
145#define RADEON_LCD1_CRTC_SHIFT8
146#define RADEON_CRT1_CRTC_MASK(1 << 9)
147#define RADEON_CRT1_CRTC_SHIFT9
148#define RADEON_TV1_CRTC_MASK(1 << 10)
149#define RADEON_TV1_CRTC_SHIFT10
150#define RADEON_DFP1_CRTC_MASK(1 << 11)
151#define RADEON_DFP1_CRTC_SHIFT11
152#define RADEON_CRT2_CRTC_MASK(1 << 12)
153#define RADEON_CRT2_CRTC_SHIFT12
154#define RADEON_CV1_CRTC_MASK(1 << 13)
155#define RADEON_CV1_CRTC_SHIFT13
156#define RADEON_DFP2_CRTC_MASK(1 << 14)
157#define RADEON_DFP2_CRTC_SHIFT14
158#define RADEON_BIOS_6_SCRATCH0x0028
159#define RADEON_ACC_MODE_CHANGE(1 << 2)
160#define RADEON_EXT_DESKTOP_MODE(1 << 3)
161#define RADEON_LCD_DPMS_ON(1 << 20)
162#define RADEON_CRT_DPMS_ON(1 << 21)
163#define RADEON_TV_DPMS_ON(1 << 22)
164#define RADEON_DFP_DPMS_ON(1 << 23)
165#define RADEON_DPMS_MASK(3 << 24)
166#define RADEON_DPMS_ON(0 << 24)
167#define RADEON_DPMS_STANDBY(1 << 24)
168#define RADEON_DPMS_SUSPEND(2 << 24)
169#define RADEON_DPMS_OFF(3 << 24)
170#define RADEON_SCREEN_BLANKING(1 << 26)
171#define RADEON_DRIVER_CRITICAL(1 << 27)
172#define RADEON_DISPLAY_SWITCHING_DI(1 << 30)
173#define RADEON_BIOS_7_SCRATCH0x002c
174#define RADEON_SYS_HOTKEY(1 << 10)
175#define RADEON_DRV_LOADED(1 << 12)
176#define RADEON_BIOS_ROM0x0f30/* PCI */
177#define RADEON_BIST0x0f0f/* PCI */
178#define RADEON_BRUSH_DATA00x1480
179#define RADEON_BRUSH_DATA10x1484
180#define RADEON_BRUSH_DATA100x14a8
181#define RADEON_BRUSH_DATA110x14ac
182#define RADEON_BRUSH_DATA120x14b0
183#define RADEON_BRUSH_DATA130x14b4
184#define RADEON_BRUSH_DATA140x14b8
185#define RADEON_BRUSH_DATA150x14bc
186#define RADEON_BRUSH_DATA160x14c0
187#define RADEON_BRUSH_DATA170x14c4
188#define RADEON_BRUSH_DATA180x14c8
189#define RADEON_BRUSH_DATA190x14cc
190#define RADEON_BRUSH_DATA20x1488
191#define RADEON_BRUSH_DATA200x14d0
192#define RADEON_BRUSH_DATA210x14d4
193#define RADEON_BRUSH_DATA220x14d8
194#define RADEON_BRUSH_DATA230x14dc
195#define RADEON_BRUSH_DATA240x14e0
196#define RADEON_BRUSH_DATA250x14e4
197#define RADEON_BRUSH_DATA260x14e8
198#define RADEON_BRUSH_DATA270x14ec
199#define RADEON_BRUSH_DATA280x14f0
200#define RADEON_BRUSH_DATA290x14f4
201#define RADEON_BRUSH_DATA30x148c
202#define RADEON_BRUSH_DATA300x14f8
203#define RADEON_BRUSH_DATA310x14fc
204#define RADEON_BRUSH_DATA320x1500
205#define RADEON_BRUSH_DATA330x1504
206#define RADEON_BRUSH_DATA340x1508
207#define RADEON_BRUSH_DATA350x150c
208#define RADEON_BRUSH_DATA360x1510
209#define RADEON_BRUSH_DATA370x1514
210#define RADEON_BRUSH_DATA380x1518
211#define RADEON_BRUSH_DATA390x151c
212#define RADEON_BRUSH_DATA40x1490
213#define RADEON_BRUSH_DATA400x1520
214#define RADEON_BRUSH_DATA410x1524
215#define RADEON_BRUSH_DATA420x1528
216#define RADEON_BRUSH_DATA430x152c
217#define RADEON_BRUSH_DATA440x1530
218#define RADEON_BRUSH_DATA450x1534
219#define RADEON_BRUSH_DATA460x1538
220#define RADEON_BRUSH_DATA470x153c
221#define RADEON_BRUSH_DATA480x1540
222#define RADEON_BRUSH_DATA490x1544
223#define RADEON_BRUSH_DATA50x1494
224#define RADEON_BRUSH_DATA500x1548
225#define RADEON_BRUSH_DATA510x154c
226#define RADEON_BRUSH_DATA520x1550
227#define RADEON_BRUSH_DATA530x1554
228#define RADEON_BRUSH_DATA540x1558
229#define RADEON_BRUSH_DATA550x155c
230#define RADEON_BRUSH_DATA560x1560
231#define RADEON_BRUSH_DATA570x1564
232#define RADEON_BRUSH_DATA580x1568
233#define RADEON_BRUSH_DATA590x156c
234#define RADEON_BRUSH_DATA60x1498
235#define RADEON_BRUSH_DATA600x1570
236#define RADEON_BRUSH_DATA610x1574
237#define RADEON_BRUSH_DATA620x1578
238#define RADEON_BRUSH_DATA630x157c
239#define RADEON_BRUSH_DATA70x149c
240#define RADEON_BRUSH_DATA80x14a0
241#define RADEON_BRUSH_DATA90x14a4
242#define RADEON_BRUSH_SCALE0x1470
243#define RADEON_BRUSH_Y_X0x1474
244#define RADEON_BUS_CNTL0x0030
245#define RADEON_BUS_MASTER_DIS(1 << 6)
246#define RADEON_BUS_BIOS_DIS_ROM(1 << 12)
247#define RADEON_BUS_RD_DISCARD_EN(1 << 24)
248#define RADEON_BUS_RD_ABORT_EN(1 << 25)
249#define RADEON_BUS_MSTR_DISCONNECT_EN(1 << 28)
250#define RADEON_BUS_WRT_BURST(1 << 29)
251#define RADEON_BUS_READ_BURST(1 << 30)
252#define RADEON_BUS_CNTL10x0034
253#define RADEON_BUS_WAIT_ON_LOCK_EN(1 << 4)
254
255#define RADEON_PCIE_INDEX0x0030
256#define RADEON_PCIE_DATA0x0034
257#define R600_PCIE_PORT_INDEX0x0038
258#define R600_PCIE_PORT_DATA0x003c
259/* PCIE_LC_LINK_WIDTH_CNTL is PCIE on r1xx-r5xx, PCIE_PORT on r6xx-r7xx */
260#define RADEON_PCIE_LC_LINK_WIDTH_CNTL0xa2/* PCIE */
261#define RADEON_PCIE_LC_LINK_WIDTH_SHIFT0
262#define RADEON_PCIE_LC_LINK_WIDTH_MASK0x7
263#define RADEON_PCIE_LC_LINK_WIDTH_X00
264#define RADEON_PCIE_LC_LINK_WIDTH_X11
265#define RADEON_PCIE_LC_LINK_WIDTH_X22
266#define RADEON_PCIE_LC_LINK_WIDTH_X43
267#define RADEON_PCIE_LC_LINK_WIDTH_X84
268#define RADEON_PCIE_LC_LINK_WIDTH_X125
269#define RADEON_PCIE_LC_LINK_WIDTH_X166
270#define RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT4
271#define RADEON_PCIE_LC_LINK_WIDTH_RD_MASK0x70
272#define R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE(1 << 7)
273#define RADEON_PCIE_LC_RECONFIG_NOW(1 << 8)
274#define RADEON_PCIE_LC_RECONFIG_LATER(1 << 9)
275#define RADEON_PCIE_LC_SHORT_RECONFIG_EN(1 << 10)
276#define R600_PCIE_LC_RENEGOTIATE_EN(1 << 10)
277#define R600_PCIE_LC_SHORT_RECONFIG_EN(1 << 11)
278#define R600_TARGET_AND_CURRENT_PROFILE_INDEX0x70c
279#define R700_TARGET_AND_CURRENT_PROFILE_INDEX0x66c
280
281#define RADEON_CACHE_CNTL0x1724
282#define RADEON_CACHE_LINE0x0f0c/* PCI */
283#define RADEON_CAPABILITIES_ID0x0f50/* PCI */
284#define RADEON_CAPABILITIES_PTR0x0f34/* PCI */
285#define RADEON_CLK_PIN_CNTL0x0001/* PLL */
286#define RADEON_DONT_USE_XTALIN(1 << 4)
287#define RADEON_SCLK_DYN_START_CNTL(1 << 15)
288#define RADEON_CLOCK_CNTL_DATA0x000c
289#define RADEON_CLOCK_CNTL_INDEX0x0008
290#define RADEON_PLL_WR_EN(1 << 7)
291#define RADEON_PLL_DIV_SEL(3 << 8)
292#define RADEON_PLL2_DIV_SEL_MASK~(3 << 8)
293#define RADEON_M_SPLL_REF_FB_DIV0x000a/* PLL */
294#define RADEON_M_SPLL_REF_DIV_MASK0xff
295#define RADEON_M_SPLL_REF_DIV_SHIFT0
296#define RADEON_MPLL_FB_DIV_MASK0xff
297#define RADEON_MPLL_FB_DIV_SHIFT8
298#define RADEON_SPLL_FB_DIV_MASK0xff
299#define RADEON_SPLL_FB_DIV_SHIFT16
300#define RADEON_SPLL_CNTL0x000c/* PLL */
301#define RADEON_SPLL_SLEEP(1 << 0)
302#define RADEON_SPLL_RESET(1 << 1)
303#define RADEON_SPLL_PCP_MASK0x7
304#define RADEON_SPLL_PCP_SHIFT8
305#define RADEON_SPLL_PVG_MASK0x7
306#define RADEON_SPLL_PVG_SHIFT11
307#define RADEON_SPLL_PDC_MASK0x3
308#define RADEON_SPLL_PDC_SHIFT14
309#define RADEON_CLK_PWRMGT_CNTL0x0014/* PLL */
310#define RADEON_ENGIN_DYNCLK_MODE(1 << 12)
311#define RADEON_ACTIVE_HILO_LAT_MASK(3 << 13)
312#define RADEON_ACTIVE_HILO_LAT_SHIF13
313#define RADEON_DISP_DYN_STOP_LAT_MASK(1 << 12)
314#define RADEON_MC_BUSY(1 << 16)
315#define RADEON_DLL_READY(1 << 19)
316#define RADEON_CG_NO1_DEBUG_0(1 << 24)
317#define RADEON_CG_NO1_DEBUG_MASK(0x1f << 24)
318#define RADEON_DYN_STOP_MODE_MASK(7 << 21)
319#define RADEON_TVPLL_PWRMGT_OFF(1 << 30)
320#define RADEON_TVCLK_TURNOFF(1 << 31)
321#define RADEON_PLL_PWRMGT_CNTL0x0015/* PLL */
322#define RADEON_TCL_BYPASS_DISABLE(1 << 20)
323#define RADEON_CLR_CMP_CLR_3D0x1a24
324#define RADEON_CLR_CMP_CLR_DST0x15c8
325#define RADEON_CLR_CMP_CLR_SRC0x15c4
326#define RADEON_CLR_CMP_CNTL0x15c0
327#define RADEON_SRC_CMP_EQ_COLOR(4 << 0)
328#define RADEON_SRC_CMP_NEQ_COLOR(5 << 0)
329#define RADEON_CLR_CMP_SRC_SOURCE(1 << 24)
330#define RADEON_CLR_CMP_MASK0x15cc
331#define RADEON_CLR_CMP_MSK0xffffffff
332#define RADEON_CLR_CMP_MASK_3D0x1A28
333#define RADEON_COMMAND0x0f04/* PCI */
334#define RADEON_COMPOSITE_SHADOW_ID0x1a0c
335#define RADEON_CONFIG_APER_0_BASE0x0100
336#define RADEON_CONFIG_APER_1_BASE0x0104
337#define RADEON_CONFIG_APER_SIZE0x0108
338#define RADEON_CONFIG_BONDS0x00e8
339#define RADEON_CONFIG_CNTL0x00e0
340#define RADEON_CFG_ATI_REV_A11(0 << 16)
341#define RADEON_CFG_ATI_REV_A12(1 << 16)
342#define RADEON_CFG_ATI_REV_A13(2 << 16)
343#define RADEON_CFG_ATI_REV_ID_MASK(0xf << 16)
344#define RADEON_CONFIG_MEMSIZE0x00f8
345#define RADEON_CONFIG_MEMSIZE_EMBEDDED0x0114
346#define RADEON_CONFIG_REG_1_BASE0x010c
347#define RADEON_CONFIG_REG_APER_SIZE0x0110
348#define RADEON_CONFIG_XSTRAP0x00e4
349#define RADEON_CONSTANT_COLOR_C0x1d34
350#define RADEON_CONSTANT_COLOR_MASK0x00ffffff
351#define RADEON_CONSTANT_COLOR_ONE0x00ffffff
352#define RADEON_CONSTANT_COLOR_ZERO0x00000000
353#define RADEON_CRC_CMDFIFO_ADDR0x0740
354#define RADEON_CRC_CMDFIFO_DOUT0x0744
355#define RADEON_GRPH_BUFFER_CNTL0x02f0
356#define RADEON_GRPH_START_REQ_MASK(0x7f)
357#define RADEON_GRPH_START_REQ_SHIFT0
358#define RADEON_GRPH_STOP_REQ_MASK(0x7f << 8)
359#define RADEON_GRPH_STOP_REQ_SHIFT8
360#define RADEON_GRPH_CRITICAL_POINT_MASK(0x7f << 16)
361#define RADEON_GRPH_CRITICAL_POINT_SHIFT16
362#define RADEON_GRPH_CRITICAL_CNTL(1 << 28)
363#define RADEON_GRPH_BUFFER_SIZE(1 << 29)
364#define RADEON_GRPH_CRITICAL_AT_SOF(1 << 30)
365#define RADEON_GRPH_STOP_CNTL(1 << 31)
366#define RADEON_GRPH2_BUFFER_CNTL0x03f0
367#define RADEON_GRPH2_START_REQ_MASK(0x7f)
368#define RADEON_GRPH2_START_REQ_SHIFT0
369#define RADEON_GRPH2_STOP_REQ_MASK(0x7f << 8)
370#define RADEON_GRPH2_STOP_REQ_SHIFT8
371#define RADEON_GRPH2_CRITICAL_POINT_MASK(0x7f << 16)
372#define RADEON_GRPH2_CRITICAL_POINT_SHIFT16
373#define RADEON_GRPH2_CRITICAL_CNTL(1 << 28)
374#define RADEON_GRPH2_BUFFER_SIZE(1 << 29)
375#define RADEON_GRPH2_CRITICAL_AT_SOF(1 << 30)
376#define RADEON_GRPH2_STOP_CNTL(1 << 31)
377#define RADEON_CRTC_CRNT_FRAME0x0214
378#define RADEON_CRTC_EXT_CNTL0x0054
379#define RADEON_CRTC_VGA_XOVERSCAN(1 << 0)
380#define RADEON_VGA_ATI_LINEAR(1 << 3)
381#define RADEON_XCRT_CNT_EN(1 << 6)
382#define RADEON_CRTC_HSYNC_DIS(1 << 8)
383#define RADEON_CRTC_VSYNC_DIS(1 << 9)
384#define RADEON_CRTC_DISPLAY_DIS(1 << 10)
385#define RADEON_CRTC_SYNC_TRISTAT(1 << 11)
386#define RADEON_CRTC_CRT_ON(1 << 15)
387#define RADEON_CRTC_EXT_CNTL_DPMS_BYTE0x0055
388#define RADEON_CRTC_HSYNC_DIS_BYTE(1 << 0)
389#define RADEON_CRTC_VSYNC_DIS_BYTE(1 << 1)
390#define RADEON_CRTC_DISPLAY_DIS_BYT(1 << 2)
391#define RADEON_CRTC_GEN_CNTL0x0050
392#define RADEON_CRTC_DBL_SCAN_EN(1 << 0)
393#define RADEON_CRTC_INTERLACE_EN(1 << 1)
394#define RADEON_CRTC_CSYNC_EN(1 << 4)
395#define RADEON_CRTC_ICON_EN(1 << 15)
396#define RADEON_CRTC_CUR_EN(1 << 16)
397#define RADEON_CRTC_CUR_MODE_MASK(7 << 20)
398#define RADEON_CRTC_EXT_DISP_EN(1 << 24)
399#define RADEON_CRTC_EN(1 << 25)
400#define RADEON_CRTC_DISP_REQ_EN_B(1 << 26)
401#define RADEON_CRTC2_GEN_CNTL0x03f8
402#define RADEON_CRTC2_DBL_SCAN_EN(1 << 0)
403#define RADEON_CRTC2_INTERLACE_EN(1 << 1)
404#define RADEON_CRTC2_SYNC_TRISTAT(1 << 4)
405#define RADEON_CRTC2_HSYNC_TRISTAT(1 << 5)
406#define RADEON_CRTC2_VSYNC_TRISTAT(1 << 6)
407#define RADEON_CRTC2_CRT2_ON(1 << 7)
408#define RADEON_CRTC2_PIX_WIDTH_SHIF8
409#define RADEON_CRTC2_PIX_WIDTH_MASK(0xf << 8)
410#define RADEON_CRTC2_ICON_EN(1 << 15)
411#define RADEON_CRTC2_CUR_EN(1 << 16)
412#define RADEON_CRTC2_CUR_MODE_MASK(7 << 20)
413#define RADEON_CRTC2_DISP_DIS(1 << 23)
414#define RADEON_CRTC2_EN(1 << 25)
415#define RADEON_CRTC2_DISP_REQ_EN_B(1 << 26)
416#define RADEON_CRTC2_CSYNC_EN(1 << 27)
417#define RADEON_CRTC2_HSYNC_DIS(1 << 28)
418#define RADEON_CRTC2_VSYNC_DIS(1 << 29)
419#define RADEON_CRTC_MORE_CNTL0x27c
420#define RADEON_CRTC_AUTO_HORZ_CENTER_EN(1<<2)
421#define RADEON_CRTC_AUTO_VERT_CENTER_EN(1<<3)
422#define RADEON_CRTC_H_CUTOFF_ACTIVE_EN(1<<4)
423#define RADEON_CRTC_V_CUTOFF_ACTIVE_EN(1<<5)
424#define RADEON_CRTC_GUI_TRIG_VLINE0x0218
425#define RADEON_CRTC_GUI_TRIG_VLINE_START_SHIFT0
426#define RADEON_CRTC_GUI_TRIG_VLINE_INV(1 << 15)
427#define RADEON_CRTC_GUI_TRIG_VLINE_END_SHIFT16
428#define RADEON_CRTC_GUI_TRIG_VLINE_STALL(1 << 30)
429#define RADEON_CRTC_H_SYNC_STRT_WID0x0204
430#define RADEON_CRTC_H_SYNC_STRT_PIX(0x07 << 0)
431#define RADEON_CRTC_H_SYNC_STRT_CHAR(0x3ff << 3)
432#define RADEON_CRTC_H_SYNC_STRT_CHAR_SHIFT3
433#define RADEON_CRTC_H_SYNC_WID(0x3f << 16)
434#define RADEON_CRTC_H_SYNC_WID_SHIFT16
435#define RADEON_CRTC_H_SYNC_POL(1 << 23)
436#define RADEON_CRTC2_H_SYNC_STRT_WID0x0304
437#define RADEON_CRTC2_H_SYNC_STRT_PIX(0x07 << 0)
438#define RADEON_CRTC2_H_SYNC_STRT_CHAR(0x3ff << 3)
439#define RADEON_CRTC2_H_SYNC_STRT_CHAR_SHIFT 3
440#define RADEON_CRTC2_H_SYNC_WID(0x3f << 16)
441#define RADEON_CRTC2_H_SYNC_WID_SHIFT16
442#define RADEON_CRTC2_H_SYNC_POL(1 << 23)
443#define RADEON_CRTC_H_TOTAL_DISP0x0200
444#define RADEON_CRTC_H_TOTAL(0x03ff << 0)
445#define RADEON_CRTC_H_TOTAL_SHIFT0
446#define RADEON_CRTC_H_DISP(0x01ff << 16)
447#define RADEON_CRTC_H_DISP_SHIFT16
448#define RADEON_CRTC2_H_TOTAL_DISP0x0300
449#define RADEON_CRTC2_H_TOTAL(0x03ff << 0)
450#define RADEON_CRTC2_H_TOTAL_SHIFT0
451#define RADEON_CRTC2_H_DISP(0x01ff << 16)
452#define RADEON_CRTC2_H_DISP_SHIFT16
453
454#define RADEON_CRTC_OFFSET_RIGHT0x0220
455#define RADEON_CRTC_OFFSET0x0224
456#define RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET(1 << 30)
457#define RADEON_CRTC_OFFSET__OFFSET_LOCK(1 << 31)
458
459#define RADEON_CRTC2_OFFSET0x0324
460#define RADEON_CRTC2_OFFSET__GUI_TRIG_OFFSET(1 << 30)
461#define RADEON_CRTC2_OFFSET__OFFSET_LOCK(1 << 31)
462#define RADEON_CRTC_OFFSET_CNTL0x0228
463#define RADEON_CRTC_TILE_LINE_SHIFT0
464#define RADEON_CRTC_TILE_LINE_RIGHT_SHIFT4
465#define R300_CRTC_X_Y_MODE_EN_RIGHT(1 << 6)
466#define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_MASK(3 << 7)
467#define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_AUTO(0 << 7)
468#define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_SINGLE(1 << 7)
469#define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DOUBLE(2 << 7)
470#define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DIS(3 << 7)
471#define R300_CRTC_X_Y_MODE_EN(1 << 9)
472#define R300_CRTC_MICRO_TILE_BUFFER_MASK(3 << 10)
473#define R300_CRTC_MICRO_TILE_BUFFER_AUTO(0 << 10)
474#define R300_CRTC_MICRO_TILE_BUFFER_SINGLE(1 << 10)
475#define R300_CRTC_MICRO_TILE_BUFFER_DOUBLE(2 << 10)
476#define R300_CRTC_MICRO_TILE_BUFFER_DIS(3 << 10)
477#define R300_CRTC_MICRO_TILE_EN_RIGHT(1 << 12)
478#define R300_CRTC_MICRO_TILE_EN(1 << 13)
479#define R300_CRTC_MACRO_TILE_EN_RIGHT(1 << 14)
480#define R300_CRTC_MACRO_TILE_EN(1 << 15)
481#define RADEON_CRTC_TILE_EN_RIGHT(1 << 14)
482#define RADEON_CRTC_TILE_EN(1 << 15)
483#define RADEON_CRTC_OFFSET_FLIP_CNTL(1 << 16)
484#define RADEON_CRTC_STEREO_OFFSET_EN(1 << 17)
485
486#define R300_CRTC_TILE_X0_Y00x0350
487#define R300_CRTC2_TILE_X0_Y00x0358
488
489#define RADEON_CRTC2_OFFSET_CNTL0x0328
490#define RADEON_CRTC2_OFFSET_FLIP_CNTL(1 << 16)
491#define RADEON_CRTC2_TILE_EN(1 << 15)
492#define RADEON_CRTC_PITCH0x022c
493#define RADEON_CRTC_PITCH__SHIFT0
494#define RADEON_CRTC_PITCH__RIGHT_SHIFT16
495
496#define RADEON_CRTC2_PITCH0x032c
497#define RADEON_CRTC_STATUS0x005c
498#define RADEON_CRTC_VBLANK_SAVE(1 << 1)
499#define RADEON_CRTC_VBLANK_SAVE_CLEAR(1 << 1)
500#define RADEON_CRTC2_STATUS0x03fc
501#define RADEON_CRTC2_VBLANK_SAVE(1 << 1)
502#define RADEON_CRTC2_VBLANK_SAVE_CLEAR(1 << 1)
503#define RADEON_CRTC_V_SYNC_STRT_WID0x020c
504#define RADEON_CRTC_V_SYNC_STRT(0x7ff << 0)
505#define RADEON_CRTC_V_SYNC_STRT_SHIFT0
506#define RADEON_CRTC_V_SYNC_WID(0x1f << 16)
507#define RADEON_CRTC_V_SYNC_WID_SHIFT16
508#define RADEON_CRTC_V_SYNC_POL(1 << 23)
509#define RADEON_CRTC2_V_SYNC_STRT_WID0x030c
510#define RADEON_CRTC2_V_SYNC_STRT(0x7ff << 0)
511#define RADEON_CRTC2_V_SYNC_STRT_SHIFT0
512#define RADEON_CRTC2_V_SYNC_WID(0x1f << 16)
513#define RADEON_CRTC2_V_SYNC_WID_SHIFT16
514#define RADEON_CRTC2_V_SYNC_POL(1 << 23)
515#define RADEON_CRTC_V_TOTAL_DISP0x0208
516#define RADEON_CRTC_V_TOTAL(0x07ff << 0)
517#define RADEON_CRTC_V_TOTAL_SHIFT0
518#define RADEON_CRTC_V_DISP(0x07ff << 16)
519#define RADEON_CRTC_V_DISP_SHIFT16
520#define RADEON_CRTC2_V_TOTAL_DISP0x0308
521#define RADEON_CRTC2_V_TOTAL(0x07ff << 0)
522#define RADEON_CRTC2_V_TOTAL_SHIFT0
523#define RADEON_CRTC2_V_DISP(0x07ff << 16)
524#define RADEON_CRTC2_V_DISP_SHIFT16
525#define RADEON_CRTC_VLINE_CRNT_VLINE0x0210
526#define RADEON_CRTC_CRNT_VLINE_MASK(0x7ff << 16)
527#define RADEON_CRTC2_CRNT_FRAME0x0314
528#define RADEON_CRTC2_GUI_TRIG_VLINE0x0318
529#define RADEON_CRTC2_STATUS0x03fc
530#define RADEON_CRTC2_VLINE_CRNT_VLINE0x0310
531#define RADEON_CRTC8_DATA0x03d5/* VGA, 0x3b5 */
532#define RADEON_CRTC8_IDX0x03d4/* VGA, 0x3b4 */
533#define RADEON_CUR_CLR00x026c
534#define RADEON_CUR_CLR10x0270
535#define RADEON_CUR_HORZ_VERT_OFF0x0268
536#define RADEON_CUR_HORZ_VERT_POSN0x0264
537#define RADEON_CUR_OFFSET0x0260
538#define RADEON_CUR_LOCK(1 << 31)
539#define RADEON_CUR2_CLR00x036c
540#define RADEON_CUR2_CLR10x0370
541#define RADEON_CUR2_HORZ_VERT_OFF0x0368
542#define RADEON_CUR2_HORZ_VERT_POSN0x0364
543#define RADEON_CUR2_OFFSET0x0360
544#define RADEON_CUR2_LOCK(1 << 31)
545
546#define RADEON_DAC_CNTL0x0058
547#define RADEON_DAC_RANGE_CNTL(3 << 0)
548#define RADEON_DAC_RANGE_CNTL_PS2(2 << 0)
549#define RADEON_DAC_RANGE_CNTL_MASK0x03
550#define RADEON_DAC_BLANKING(1 << 2)
551#define RADEON_DAC_CMP_EN(1 << 3)
552#define RADEON_DAC_CMP_OUTPUT(1 << 7)
553#define RADEON_DAC_8BIT_EN(1 << 8)
554#define RADEON_DAC_TVO_EN(1 << 10)
555#define RADEON_DAC_VGA_ADR_EN(1 << 13)
556#define RADEON_DAC_PDWN(1 << 15)
557#define RADEON_DAC_MASK_ALL(0xff << 24)
558#define RADEON_DAC_CNTL20x007c
559#define RADEON_DAC2_TV_CLK_SEL(0 << 1)
560#define RADEON_DAC2_DAC_CLK_SEL(1 << 0)
561#define RADEON_DAC2_DAC2_CLK_SEL(1 << 1)
562#define RADEON_DAC2_PALETTE_ACC_CTL(1 << 5)
563#define RADEON_DAC2_CMP_EN(1 << 7)
564#define RADEON_DAC2_CMP_OUT_R(1 << 8)
565#define RADEON_DAC2_CMP_OUT_G(1 << 9)
566#define RADEON_DAC2_CMP_OUT_B(1 << 10)
567#define RADEON_DAC2_CMP_OUTPUT(1 << 11)
568#define RADEON_DAC_EXT_CNTL0x0280
569#define RADEON_DAC2_FORCE_BLANK_OFF_EN(1 << 0)
570#define RADEON_DAC2_FORCE_DATA_EN(1 << 1)
571#define RADEON_DAC_FORCE_BLANK_OFF_EN(1 << 4)
572#define RADEON_DAC_FORCE_DATA_EN(1 << 5)
573#define RADEON_DAC_FORCE_DATA_SEL_MASK(3 << 6)
574#define RADEON_DAC_FORCE_DATA_SEL_R(0 << 6)
575#define RADEON_DAC_FORCE_DATA_SEL_G(1 << 6)
576#define RADEON_DAC_FORCE_DATA_SEL_B(2 << 6)
577#define RADEON_DAC_FORCE_DATA_SEL_RGB(3 << 6)
578#define RADEON_DAC_FORCE_DATA_MASK0x0003ff00
579#define RADEON_DAC_FORCE_DATA_SHIFT8
580#define RADEON_DAC_MACRO_CNTL0x0d04
581#define RADEON_DAC_PDWN_R(1 << 16)
582#define RADEON_DAC_PDWN_G(1 << 17)
583#define RADEON_DAC_PDWN_B(1 << 18)
584#define RADEON_TV_DAC_CNTL0x088c
585#define RADEON_TV_DAC_NBLANK(1 << 0)
586#define RADEON_TV_DAC_NHOLD(1 << 1)
587#define RADEON_TV_DAC_PEDESTAL(1 << 2)
588#define RADEON_TV_MONITOR_DETECT_EN(1 << 4)
589#define RADEON_TV_DAC_CMPOUT(1 << 5)
590#define RADEON_TV_DAC_STD_MASK(3 << 8)
591#define RADEON_TV_DAC_STD_PAL(0 << 8)
592#define RADEON_TV_DAC_STD_NTSC(1 << 8)
593#define RADEON_TV_DAC_STD_PS2(2 << 8)
594#define RADEON_TV_DAC_STD_RS343(3 << 8)
595#define RADEON_TV_DAC_BGSLEEP(1 << 6)
596#define RADEON_TV_DAC_BGADJ_MASK(0xf << 16)
597#define RADEON_TV_DAC_BGADJ_SHIFT16
598#define RADEON_TV_DAC_DACADJ_MASK(0xf << 20)
599#define RADEON_TV_DAC_DACADJ_SHIFT20
600#define RADEON_TV_DAC_RDACPD(1 << 24)
601#define RADEON_TV_DAC_GDACPD(1 << 25)
602#define RADEON_TV_DAC_BDACPD(1 << 26)
603#define RADEON_TV_DAC_RDACDET(1 << 29)
604#define RADEON_TV_DAC_GDACDET(1 << 30)
605#define RADEON_TV_DAC_BDACDET(1 << 31)
606#define R420_TV_DAC_DACADJ_MASK(0x1f << 20)
607#define R420_TV_DAC_RDACPD(1 << 25)
608#define R420_TV_DAC_GDACPD(1 << 26)
609#define R420_TV_DAC_BDACPD(1 << 27)
610#define R420_TV_DAC_TVENABLE(1 << 28)
611#define RADEON_DISP_HW_DEBUG0x0d14
612#define RADEON_CRT2_DISP1_SEL(1 << 5)
613#define RADEON_DISP_OUTPUT_CNTL0x0d64
614#define RADEON_DISP_DAC_SOURCE_MASK0x03
615#define RADEON_DISP_DAC2_SOURCE_MASK0x0c
616#define RADEON_DISP_DAC_SOURCE_CRTC0x01
617#define RADEON_DISP_DAC_SOURCE_RMX0x02
618#define RADEON_DISP_DAC_SOURCE_LTU0x03
619#define RADEON_DISP_DAC2_SOURCE_CRTC20x04
620#define RADEON_DISP_TVDAC_SOURCE_MASK(0x03 << 2)
621#define RADEON_DISP_TVDAC_SOURCE_CRTC0x0
622#define RADEON_DISP_TVDAC_SOURCE_CRTC2(0x01 << 2)
623#define RADEON_DISP_TVDAC_SOURCE_RMX(0x02 << 2)
624#define RADEON_DISP_TVDAC_SOURCE_LTU(0x03 << 2)
625#define RADEON_DISP_TRANS_MATRIX_MASK(0x03 << 4)
626#define RADEON_DISP_TRANS_MATRIX_ALPHA_MSB(0x00 << 4)
627#define RADEON_DISP_TRANS_MATRIX_GRAPHICS(0x01 << 4)
628#define RADEON_DISP_TRANS_MATRIX_VIDEO(0x02 << 4)
629#define RADEON_DISP_TV_SOURCE_CRTC(1 << 16)/* crtc1 or crtc2 */
630#define RADEON_DISP_TV_SOURCE_LTU(0 << 16)/* linear transform unit */
631#define RADEON_DISP_TV_OUT_CNTL0x0d6c
632#define RADEON_DISP_TV_PATH_SRC_CRTC2(1 << 16)
633#define RADEON_DISP_TV_PATH_SRC_CRTC1(0 << 16)
634#define RADEON_DAC_CRC_SIG0x02cc
635#define RADEON_DAC_DATA0x03c9/* VGA */
636#define RADEON_DAC_MASK0x03c6/* VGA */
637#define RADEON_DAC_R_INDEX0x03c7/* VGA */
638#define RADEON_DAC_W_INDEX0x03c8/* VGA */
639#define RADEON_DDA_CONFIG0x02e0
640#define RADEON_DDA_ON_OFF0x02e4
641#define RADEON_DEFAULT_OFFSET0x16e0
642#define RADEON_DEFAULT_PITCH0x16e4
643#define RADEON_DEFAULT_SC_BOTTOM_RIGHT0x16e8
644#define RADEON_DEFAULT_SC_RIGHT_MAX(0x1fff << 0)
645#define RADEON_DEFAULT_SC_BOTTOM_MAX(0x1fff << 16)
646#define RADEON_DESTINATION_3D_CLR_CMP_VAL0x1820
647#define RADEON_DESTINATION_3D_CLR_CMP_MSK0x1824
648#define RADEON_DEVICE_ID0x0f02/* PCI */
649#define RADEON_DISP_MISC_CNTL0x0d00
650#define RADEON_SOFT_RESET_GRPH_PP(1 << 0)
651#define RADEON_DISP_MERGE_CNTL0x0d60
652#define RADEON_DISP_ALPHA_MODE_MASK0x03
653#define RADEON_DISP_ALPHA_MODE_KEY0
654#define RADEON_DISP_ALPHA_MODE_PER_PIXEL1
655#define RADEON_DISP_ALPHA_MODE_GLOBAL2
656#define RADEON_DISP_RGB_OFFSET_EN(1 << 8)
657#define RADEON_DISP_GRPH_ALPHA_MASK(0xff << 16)
658#define RADEON_DISP_OV0_ALPHA_MASK(0xff << 24)
659#define RADEON_DISP_LIN_TRANS_BYPAS(0x01 << 9)
660#define RADEON_DISP2_MERGE_CNTL0x0d68
661#define RADEON_DISP2_RGB_OFFSET_EN(1 << 8)
662#define RADEON_DISP_LIN_TRANS_GRPH_A0x0d80
663#define RADEON_DISP_LIN_TRANS_GRPH_B0x0d84
664#define RADEON_DISP_LIN_TRANS_GRPH_C0x0d88
665#define RADEON_DISP_LIN_TRANS_GRPH_D0x0d8c
666#define RADEON_DISP_LIN_TRANS_GRPH_E0x0d90
667#define RADEON_DISP_LIN_TRANS_GRPH_F0x0d98
668#define RADEON_DP_BRUSH_BKGD_CLR0x1478
669#define RADEON_DP_BRUSH_FRGD_CLR0x147c
670#define RADEON_DP_CNTL0x16c0
671#define RADEON_DST_X_LEFT_TO_RIGHT(1 << 0)
672#define RADEON_DST_Y_TOP_TO_BOTTOM(1 << 1)
673#define RADEON_DP_DST_TILE_LINEAR(0 << 3)
674#define RADEON_DP_DST_TILE_MACRO(1 << 3)
675#define RADEON_DP_DST_TILE_MICRO(2 << 3)
676#define RADEON_DP_DST_TILE_BOTH(3 << 3)
677#define RADEON_DP_CNTL_XDIR_YDIR_YMAJOR0x16d0
678#define RADEON_DST_Y_MAJOR(1 << 2)
679#define RADEON_DST_Y_DIR_TOP_TO_BOTTOM(1 << 15)
680#define RADEON_DST_X_DIR_LEFT_TO_RIGHT(1 << 31)
681#define RADEON_DP_DATATYPE0x16c4
682#define RADEON_HOST_BIG_ENDIAN_EN(1 << 29)
683#define RADEON_DP_GUI_MASTER_CNTL0x146c
684#define RADEON_GMC_SRC_PITCH_OFFSET_CNTL(1 << 0)
685#define RADEON_GMC_DST_PITCH_OFFSET_CNTL(1 << 1)
686#define RADEON_GMC_SRC_CLIPPING(1 << 2)
687#define RADEON_GMC_DST_CLIPPING(1 << 3)
688#define RADEON_GMC_BRUSH_DATATYPE_MASK(0x0f << 4)
689#define RADEON_GMC_BRUSH_8X8_MONO_FG_BG(0 << 4)
690#define RADEON_GMC_BRUSH_8X8_MONO_FG_LA(1 << 4)
691#define RADEON_GMC_BRUSH_1X8_MONO_FG_BG(4 << 4)
692#define RADEON_GMC_BRUSH_1X8_MONO_FG_LA(5 << 4)
693#define RADEON_GMC_BRUSH_32x1_MONO_FG_BG(6 << 4)
694#define RADEON_GMC_BRUSH_32x1_MONO_FG_LA(7 << 4)
695#define RADEON_GMC_BRUSH_32x32_MONO_FG_BG(8 << 4)
696#define RADEON_GMC_BRUSH_32x32_MONO_FG_LA(9 << 4)
697#define RADEON_GMC_BRUSH_8x8_COLOR(10 << 4)
698#define RADEON_GMC_BRUSH_1X8_COLOR(12 << 4)
699#define RADEON_GMC_BRUSH_SOLID_COLOR(13 << 4)
700#define RADEON_GMC_BRUSH_NONE(15 << 4)
701#define RADEON_GMC_DST_8BPP_CI(2 << 8)
702#define RADEON_GMC_DST_15BPP(3 << 8)
703#define RADEON_GMC_DST_16BPP(4 << 8)
704#define RADEON_GMC_DST_24BPP(5 << 8)
705#define RADEON_GMC_DST_32BPP(6 << 8)
706#define RADEON_GMC_DST_8BPP_RGB(7 << 8)
707#define RADEON_GMC_DST_Y8(8 << 8)
708#define RADEON_GMC_DST_RGB8(9 << 8)
709#define RADEON_GMC_DST_VYUY(11 << 8)
710#define RADEON_GMC_DST_YVYU(12 << 8)
711#define RADEON_GMC_DST_AYUV444(14 << 8)
712#define RADEON_GMC_DST_ARGB4444(15 << 8)
713#define RADEON_GMC_DST_DATATYPE_MASK(0x0f << 8)
714#define RADEON_GMC_DST_DATATYPE_SHIFT8
715#define RADEON_GMC_SRC_DATATYPE_MASK(3 << 12)
716#define RADEON_GMC_SRC_DATATYPE_MONO_FG_BG(0 << 12)
717#define RADEON_GMC_SRC_DATATYPE_MONO_FG_LA(1 << 12)
718#define RADEON_GMC_SRC_DATATYPE_COLOR(3 << 12)
719#define RADEON_GMC_BYTE_PIX_ORDER(1 << 14)
720#define RADEON_GMC_BYTE_MSB_TO_LSB(0 << 14)
721#define RADEON_GMC_BYTE_LSB_TO_MSB(1 << 14)
722#define RADEON_GMC_CONVERSION_TEMP(1 << 15)
723#define RADEON_GMC_CONVERSION_TEMP_6500(0 << 15)
724#define RADEON_GMC_CONVERSION_TEMP_9300(1 << 15)
725#define RADEON_GMC_ROP3_MASK(0xff << 16)
726#define RADEON_DP_SRC_SOURCE_MASK(7 << 24)
727#define RADEON_DP_SRC_SOURCE_MEMORY(2 << 24)
728#define RADEON_DP_SRC_SOURCE_HOST_DATA(3 << 24)
729#define RADEON_GMC_3D_FCN_EN(1 << 27)
730#define RADEON_GMC_CLR_CMP_CNTL_DIS(1 << 28)
731#define RADEON_GMC_AUX_CLIP_DIS(1 << 29)
732#define RADEON_GMC_WR_MSK_DIS(1 << 30)
733#define RADEON_GMC_LD_BRUSH_Y_X(1 << 31)
734#define RADEON_ROP3_ZERO0x00000000
735#define RADEON_ROP3_DSa0x00880000
736#define RADEON_ROP3_SDna0x00440000
737#define RADEON_ROP3_S0x00cc0000
738#define RADEON_ROP3_DSna0x00220000
739#define RADEON_ROP3_D0x00aa0000
740#define RADEON_ROP3_DSx0x00660000
741#define RADEON_ROP3_DSo0x00ee0000
742#define RADEON_ROP3_DSon0x00110000
743#define RADEON_ROP3_DSxn0x00990000
744#define RADEON_ROP3_Dn0x00550000
745#define RADEON_ROP3_SDno0x00dd0000
746#define RADEON_ROP3_Sn0x00330000
747#define RADEON_ROP3_DSno0x00bb0000
748#define RADEON_ROP3_DSan0x00770000
749#define RADEON_ROP3_ONE0x00ff0000
750#define RADEON_ROP3_DPa0x00a00000
751#define RADEON_ROP3_PDna0x00500000
752#define RADEON_ROP3_P0x00f00000
753#define RADEON_ROP3_DPna0x000a0000
754#define RADEON_ROP3_D0x00aa0000
755#define RADEON_ROP3_DPx0x005a0000
756#define RADEON_ROP3_DPo0x00fa0000
757#define RADEON_ROP3_DPon0x00050000
758#define RADEON_ROP3_PDxn0x00a50000
759#define RADEON_ROP3_PDno0x00f50000
760#define RADEON_ROP3_Pn0x000f0000
761#define RADEON_ROP3_DPno0x00af0000
762#define RADEON_ROP3_DPan0x005f0000
763#define RADEON_DP_GUI_MASTER_CNTL_C0x1c84
764#define RADEON_DP_MIX0x16c8
765#define RADEON_DP_SRC_BKGD_CLR0x15dc
766#define RADEON_DP_SRC_FRGD_CLR0x15d8
767#define RADEON_DP_WRITE_MASK0x16cc
768#define RADEON_DST_BRES_DEC0x1630
769#define RADEON_DST_BRES_ERR0x1628
770#define RADEON_DST_BRES_INC0x162c
771#define RADEON_DST_BRES_LNTH0x1634
772#define RADEON_DST_BRES_LNTH_SUB0x1638
773#define RADEON_DST_HEIGHT0x1410
774#define RADEON_DST_HEIGHT_WIDTH0x143c
775#define RADEON_DST_HEIGHT_WIDTH_80x158c
776#define RADEON_DST_HEIGHT_WIDTH_BW0x15b4
777#define RADEON_DST_HEIGHT_Y0x15a0
778#define RADEON_DST_LINE_START0x1600
779#define RADEON_DST_LINE_END0x1604
780#define RADEON_DST_LINE_PATCOUNT0x1608
781#define RADEON_BRES_CNTL_SHIFT8
782#define RADEON_DST_OFFSET0x1404
783#define RADEON_DST_PITCH0x1408
784#define RADEON_DST_PITCH_OFFSET0x142c
785#define RADEON_DST_PITCH_OFFSET_C0x1c80
786#define RADEON_PITCH_SHIFT21
787#define RADEON_DST_TILE_LINEAR(0 << 30)
788#define RADEON_DST_TILE_MACRO(1 << 30)
789#define RADEON_DST_TILE_MICRO(2 << 30)
790#define RADEON_DST_TILE_BOTH(3 << 30)
791#define RADEON_DST_WIDTH0x140c
792#define RADEON_DST_WIDTH_HEIGHT0x1598
793#define RADEON_DST_WIDTH_X0x1588
794#define RADEON_DST_WIDTH_X_INCY0x159c
795#define RADEON_DST_X0x141c
796#define RADEON_DST_X_SUB0x15a4
797#define RADEON_DST_X_Y0x1594
798#define RADEON_DST_Y0x1420
799#define RADEON_DST_Y_SUB0x15a8
800#define RADEON_DST_Y_X0x1438
801
802#define RADEON_FCP_CNTL0x0910
803#define RADEON_FCP0_SRC_PCICLK0
804#define RADEON_FCP0_SRC_PCLK1
805#define RADEON_FCP0_SRC_PCLKb2
806#define RADEON_FCP0_SRC_HREF3
807#define RADEON_FCP0_SRC_GND4
808#define RADEON_FCP0_SRC_HREFb5
809#define RADEON_FLUSH_10x1704
810#define RADEON_FLUSH_20x1708
811#define RADEON_FLUSH_30x170c
812#define RADEON_FLUSH_40x1710
813#define RADEON_FLUSH_50x1714
814#define RADEON_FLUSH_60x1718
815#define RADEON_FLUSH_70x171c
816#define RADEON_FOG_3D_TABLE_START0x1810
817#define RADEON_FOG_3D_TABLE_END0x1814
818#define RADEON_FOG_3D_TABLE_DENSITY0x181c
819#define RADEON_FOG_TABLE_INDEX0x1a14
820#define RADEON_FOG_TABLE_DATA0x1a18
821#define RADEON_FP_CRTC_H_TOTAL_DISP0x0250
822#define RADEON_FP_CRTC_V_TOTAL_DISP0x0254
823#define RADEON_FP_CRTC_H_TOTAL_MASK0x000003ff
824#define RADEON_FP_CRTC_H_DISP_MASK0x01ff0000
825#define RADEON_FP_CRTC_V_TOTAL_MASK0x00000fff
826#define RADEON_FP_CRTC_V_DISP_MASK0x0fff0000
827#define RADEON_FP_H_SYNC_STRT_CHAR_MASK0x00001ff8
828#define RADEON_FP_H_SYNC_WID_MASK0x003f0000
829#define RADEON_FP_V_SYNC_STRT_MASK0x00000fff
830#define RADEON_FP_V_SYNC_WID_MASK0x001f0000
831#define RADEON_FP_CRTC_H_TOTAL_SHIFT0x00000000
832#define RADEON_FP_CRTC_H_DISP_SHIFT0x00000010
833#define RADEON_FP_CRTC_V_TOTAL_SHIFT0x00000000
834#define RADEON_FP_CRTC_V_DISP_SHIFT0x00000010
835#define RADEON_FP_H_SYNC_STRT_CHAR_SHIF0x00000003
836#define RADEON_FP_H_SYNC_WID_SHIFT0x00000010
837#define RADEON_FP_V_SYNC_STRT_SHIFT0x00000000
838#define RADEON_FP_V_SYNC_WID_SHIFT0x00000010
839#define RADEON_FP_GEN_CNTL0x0284
840#define RADEON_FP_FPON(1 << 0)
841#define RADEON_FP_BLANK_EN(1 << 1)
842#define RADEON_FP_TMDS_EN(1 << 2)
843#define RADEON_FP_PANEL_FORMAT(1 << 3)
844#define RADEON_FP_EN_TMDS(1 << 7)
845#define RADEON_FP_DETECT_SENSE(1 << 8)
846#define R200_FP_SOURCE_SEL_MASK(3 << 10)
847#define R200_FP_SOURCE_SEL_CRTC1(0 << 10)
848#define R200_FP_SOURCE_SEL_CRTC2(1 << 10)
849#define R200_FP_SOURCE_SEL_RMX(2 << 10)
850#define R200_FP_SOURCE_SEL_TRANS(3 << 10)
851#define RADEON_FP_SEL_CRTC1(0 << 13)
852#define RADEON_FP_SEL_CRTC2(1 << 13)
853#define RADEON_FP_CRTC_DONT_SHADOW_HPAR (1 << 15)
854#define RADEON_FP_CRTC_DONT_SHADOW_VPAR (1 << 16)
855#define RADEON_FP_CRTC_DONT_SHADOW_HEND (1 << 17)
856#define RADEON_FP_CRTC_USE_SHADOW_VEND(1 << 18)
857#define RADEON_FP_RMX_HVSYNC_CONTROL_EN (1 << 20)
858#define RADEON_FP_DFP_SYNC_SEL(1 << 21)
859#define RADEON_FP_CRTC_LOCK_8DOT(1 << 22)
860#define RADEON_FP_CRT_SYNC_SEL(1 << 23)
861#define RADEON_FP_USE_SHADOW_EN(1 << 24)
862#define RADEON_FP_CRT_SYNC_ALT(1 << 26)
863#define RADEON_FP2_GEN_CNTL0x0288
864#define RADEON_FP2_BLANK_EN(1 << 1)
865#define RADEON_FP2_ON(1 << 2)
866#define RADEON_FP2_PANEL_FORMAT(1 << 3)
867#define RADEON_FP2_DETECT_SENSE(1 << 8)
868#define R200_FP2_SOURCE_SEL_MASK(3 << 10)
869#define R200_FP2_SOURCE_SEL_CRTC1(0 << 10)
870#define R200_FP2_SOURCE_SEL_CRTC2(1 << 10)
871#define R200_FP2_SOURCE_SEL_RMX(2 << 10)
872#define R200_FP2_SOURCE_SEL_TRANS_UNIT(3 << 10)
873#define RADEON_FP2_SRC_SEL_MASK(3 << 13)
874#define RADEON_FP2_SRC_SEL_CRTC2(1 << 13)
875#define RADEON_FP2_FP_POL(1 << 16)
876#define RADEON_FP2_LP_POL(1 << 17)
877#define RADEON_FP2_SCK_POL(1 << 18)
878#define RADEON_FP2_LCD_CNTL_MASK(7 << 19)
879#define RADEON_FP2_PAD_FLOP_EN(1 << 22)
880#define RADEON_FP2_CRC_EN(1 << 23)
881#define RADEON_FP2_CRC_READ_EN(1 << 24)
882#define RADEON_FP2_DVO_EN(1 << 25)
883#define RADEON_FP2_DVO_RATE_SEL_SDR(1 << 26)
884#define R200_FP2_DVO_RATE_SEL_SDR(1 << 27)
885#define R200_FP2_DVO_CLOCK_MODE_SINGLE(1 << 28)
886#define R300_FP2_DVO_DUAL_CHANNEL_EN(1 << 29)
887#define RADEON_FP_H_SYNC_STRT_WID0x02c4
888#define RADEON_FP_H2_SYNC_STRT_WID0x03c4
889#define RADEON_FP_HORZ_STRETCH0x028c
890#define RADEON_FP_HORZ2_STRETCH0x038c
891#define RADEON_HORZ_STRETCH_RATIO_MASK0xffff
892#define RADEON_HORZ_STRETCH_RATIO_MAX4096
893#define RADEON_HORZ_PANEL_SIZE(0x1ff << 16)
894#define RADEON_HORZ_PANEL_SHIFT16
895#define RADEON_HORZ_STRETCH_PIXREP(0 << 25)
896#define RADEON_HORZ_STRETCH_BLEND(1 << 26)
897#define RADEON_HORZ_STRETCH_ENABLE(1 << 25)
898#define RADEON_HORZ_AUTO_RATIO(1 << 27)
899#define RADEON_HORZ_FP_LOOP_STRETCH(0x7 << 28)
900#define RADEON_HORZ_AUTO_RATIO_INC(1 << 31)
901#define RADEON_FP_HORZ_VERT_ACTIVE0x0278
902#define RADEON_FP_V_SYNC_STRT_WID0x02c8
903#define RADEON_FP_VERT_STRETCH0x0290
904#define RADEON_FP_V2_SYNC_STRT_WID0x03c8
905#define RADEON_FP_VERT2_STRETCH0x0390
906#define RADEON_VERT_PANEL_SIZE(0xfff << 12)
907#define RADEON_VERT_PANEL_SHIFT12
908#define RADEON_VERT_STRETCH_RATIO_MASK0xfff
909#define RADEON_VERT_STRETCH_RATIO_SHIFT 0
910#define RADEON_VERT_STRETCH_RATIO_MAX4096
911#define RADEON_VERT_STRETCH_ENABLE(1 << 25)
912#define RADEON_VERT_STRETCH_LINEREP(0 << 26)
913#define RADEON_VERT_STRETCH_BLEND(1 << 26)
914#define RADEON_VERT_AUTO_RATIO_EN(1 << 27)
915#define RADEON_VERT_AUTO_RATIO_INC(1 << 31)
916#define RADEON_VERT_STRETCH_RESERVED0x71000000
917#define RS400_FP_2ND_GEN_CNTL0x0384
918#define RS400_FP_2ND_ON(1 << 0)
919#define RS400_FP_2ND_BLANK_EN (1 << 1)
920#define RS400_TMDS_2ND_EN (1 << 2)
921#define RS400_PANEL_FORMAT_2ND (1 << 3)
922#define RS400_FP_2ND_EN_TMDS (1 << 7)
923#define RS400_FP_2ND_DETECT_SENSE (1 << 8)
924#define RS400_FP_2ND_SOURCE_SEL_MASK(3 << 10)
925#define RS400_FP_2ND_SOURCE_SEL_CRTC1(0 << 10)
926#define RS400_FP_2ND_SOURCE_SEL_CRTC2(1 << 10)
927#define RS400_FP_2ND_SOURCE_SEL_RMX(2 << 10)
928#define RS400_FP_2ND_DETECT_EN (1 << 12)
929#define RS400_HPD_2ND_SEL (1 << 13)
930#define RS400_FP2_2_GEN_CNTL0x0388
931#define RS400_FP2_2_BLANK_EN (1 << 1)
932#define RS400_FP2_2_ON (1 << 2)
933#define RS400_FP2_2_PANEL_FORMAT (1 << 3)
934#define RS400_FP2_2_DETECT_SENSE (1 << 8)
935#define RS400_FP2_2_SOURCE_SEL_MASK (3 << 10)
936#define RS400_FP2_2_SOURCE_SEL_CRTC1 (0 << 10)
937#define RS400_FP2_2_SOURCE_SEL_CRTC2 (1 << 10)
938#define RS400_FP2_2_SOURCE_SEL_RMX (2 << 10)
939#define RS400_FP2_2_DVO2_EN (1 << 25)
940#define RS400_TMDS2_CNTL0x0394
941#define RS400_TMDS2_TRANSMITTER_CNTL0x03a4
942#define RS400_TMDS2_PLLEN (1 << 0)
943#define RS400_TMDS2_PLLRST (1 << 1)
944
945#define RADEON_GEN_INT_CNTL0x0040
946#define RADEON_GEN_INT_STATUS0x0044
947#define RADEON_VSYNC_INT_AK (1 << 2)
948#define RADEON_VSYNC_INT (1 << 2)
949#define RADEON_VSYNC2_INT_AK (1 << 6)
950#define RADEON_VSYNC2_INT (1 << 6)
951#define RADEON_GENENB0x03c3/* VGA */
952#define RADEON_GENFC_RD0x03ca/* VGA */
953#define RADEON_GENFC_WT0x03da/* VGA, 0x03ba */
954#define RADEON_GENMO_RD0x03cc/* VGA */
955#define RADEON_GENMO_WT0x03c2/* VGA */
956#define RADEON_GENS00x03c2/* VGA */
957#define RADEON_GENS10x03da/* VGA, 0x03ba */
958#define RADEON_GPIO_MONID0x0068/* DDC interface via I2C */ /* DDC3 */
959#define RADEON_GPIO_MONIDB0x006c
960#define RADEON_GPIO_CRT2_DDC0x006c
961#define RADEON_GPIO_DVI_DDC0x0064/* DDC2 */
962#define RADEON_GPIO_VGA_DDC0x0060/* DDC1 */
963#define RADEON_GPIO_A_0 (1 << 0)
964#define RADEON_GPIO_A_1 (1 << 1)
965#define RADEON_GPIO_Y_0 (1 << 8)
966#define RADEON_GPIO_Y_1 (1 << 9)
967#define RADEON_GPIO_Y_SHIFT_0 8
968#define RADEON_GPIO_Y_SHIFT_1 9
969#define RADEON_GPIO_EN_0 (1 << 16)
970#define RADEON_GPIO_EN_1 (1 << 17)
971#define RADEON_GPIO_MASK_0 (1 << 24)/*??*/
972#define RADEON_GPIO_MASK_1 (1 << 25)/*??*/
973#define RADEON_GRPH8_DATA0x03cf/* VGA */
974#define RADEON_GRPH8_IDX0x03ce/* VGA */
975#define RADEON_GUI_SCRATCH_REG00x15e0
976#define RADEON_GUI_SCRATCH_REG10x15e4
977#define RADEON_GUI_SCRATCH_REG20x15e8
978#define RADEON_GUI_SCRATCH_REG30x15ec
979#define RADEON_GUI_SCRATCH_REG40x15f0
980#define RADEON_GUI_SCRATCH_REG50x15f4
981
982#define RADEON_HEADER0x0f0e/* PCI */
983#define RADEON_HOST_DATA00x17c0
984#define RADEON_HOST_DATA10x17c4
985#define RADEON_HOST_DATA20x17c8
986#define RADEON_HOST_DATA30x17cc
987#define RADEON_HOST_DATA40x17d0
988#define RADEON_HOST_DATA50x17d4
989#define RADEON_HOST_DATA60x17d8
990#define RADEON_HOST_DATA70x17dc
991#define RADEON_HOST_DATA_LAST0x17e0
992#define RADEON_HOST_PATH_CNTL0x0130
993#define RADEON_HDP_SOFT_RESET (1 << 26)
994#define RADEON_HDP_APER_CNTL (1 << 23)
995#define RADEON_HTOTAL_CNTL0x0009/* PLL */
996#define RADEON_HTOT_CNTL_VGA_EN (1 << 28)
997#define RADEON_HTOTAL2_CNTL0x002e/* PLL */
998
999/* Multimedia I2C bus */
1000#define RADEON_I2C_CNTL_00x0090
1001#define RADEON_I2C_DONE(1 << 0)
1002#define RADEON_I2C_NACK(1 << 1)
1003#define RADEON_I2C_HALT(1 << 2)
1004#define RADEON_I2C_SOFT_RST(1 << 5)
1005#define RADEON_I2C_DRIVE_EN(1 << 6)
1006#define RADEON_I2C_DRIVE_SEL(1 << 7)
1007#define RADEON_I2C_START(1 << 8)
1008#define RADEON_I2C_STOP(1 << 9)
1009#define RADEON_I2C_RECEIVE(1 << 10)
1010#define RADEON_I2C_ABORT(1 << 11)
1011#define RADEON_I2C_GO(1 << 12)
1012#define RADEON_I2C_CNTL_10x0094
1013#define RADEON_I2C_SEL(1 << 16)
1014#define RADEON_I2C_EN(1 << 17)
1015#define RADEON_I2C_DATA0x0098
1016
1017#define RADEON_DVI_I2C_CNTL_00x02e0
1018#define R200_DVI_I2C_PIN_SEL(x) ((x) << 3)
1019#define R200_SEL_DDC1 0/* 0x60 - VGA_DDC */
1020#define R200_SEL_DDC2 1/* 0x64 - DVI_DDC */
1021#define R200_SEL_DDC3 2/* 0x68 - MONID_DDC */
1022#define RADEON_DVI_I2C_CNTL_10x02e4
1023#define RADEON_DVI_I2C_DATA0x02e8
1024
1025#define RADEON_INTERRUPT_LINE0x0f3c/* PCI */
1026#define RADEON_INTERRUPT_PIN0x0f3d/* PCI */
1027#define RADEON_IO_BASE0x0f14/* PCI */
1028
1029#define RADEON_LATENCY0x0f0d/* PCI */
1030#define RADEON_LEAD_BRES_DEC0x1608
1031#define RADEON_LEAD_BRES_LNTH0x161c
1032#define RADEON_LEAD_BRES_LNTH_SUB0x1624
1033#define RADEON_LVDS_GEN_CNTL0x02d0
1034#define RADEON_LVDS_ON (1 << 0)
1035#define RADEON_LVDS_DISPLAY_DIS (1 << 1)
1036#define RADEON_LVDS_PANEL_TYPE (1 << 2)
1037#define RADEON_LVDS_PANEL_FORMAT (1 << 3)
1038#define RADEON_LVDS_RST_FM (1 << 6)
1039#define RADEON_LVDS_EN (1 << 7)
1040#define RADEON_LVDS_BL_MOD_LEVEL_SHIFT 8
1041#define RADEON_LVDS_BL_MOD_LEVEL_MASK (0xff << 8)
1042#define RADEON_LVDS_BL_MOD_EN (1 << 16)
1043#define RADEON_LVDS_DIGON (1 << 18)
1044#define RADEON_LVDS_BLON (1 << 19)
1045#define RADEON_LVDS_SEL_CRTC2 (1 << 23)
1046#define RADEON_LVDS_PLL_CNTL0x02d4
1047#define RADEON_HSYNC_DELAY_SHIFT 28
1048#define RADEON_HSYNC_DELAY_MASK (0xf << 28)
1049#define RADEON_LVDS_PLL_EN (1 << 16)
1050#define RADEON_LVDS_PLL_RESET (1 << 17)
1051#define R300_LVDS_SRC_SEL_MASK (3<< 18)
1052#define R300_LVDS_SRC_SEL_CRTC1 (0<< 18)
1053#define R300_LVDS_SRC_SEL_CRTC2 (1<< 18)
1054#define R300_LVDS_SRC_SEL_RMX (2<< 18)
1055
1056#define RADEON_MAX_LATENCY0x0f3f/* PCI */
1057#define RADEON_MC_AGP_LOCATION0x014c
1058#define RADEON_MC_FB_LOCATION0x0148
1059#define RADEON_DISPLAY_BASE_ADDR0x23c
1060#define RADEON_DISPLAY2_BASE_ADDR0x33c
1061#define RADEON_OV0_BASE_ADDR0x43c
1062#define RADEON_NB_TOM0x15c
1063#define R300_MC_INIT_MISC_LAT_TIMER0x180
1064#define R300_MC_DISP0R_INIT_LAT_SHIFT 8
1065#define R300_MC_DISP0R_INIT_LAT_MASK 0xf
1066#define R300_MC_DISP1R_INIT_LAT_SHIFT 12
1067#define R300_MC_DISP1R_INIT_LAT_MASK 0xf
1068#define RADEON_MCLK_CNTL0x0012 /* PLL */
1069#define RADEON_FORCEON_MCLKA (1 << 16)
1070#define RADEON_FORCEON_MCLKB (1 << 17)
1071#define RADEON_FORCEON_YCLKA (1 << 18)
1072#define RADEON_FORCEON_YCLKB (1 << 19)
1073#define RADEON_FORCEON_MC (1 << 20)
1074#define RADEON_FORCEON_AIC (1 << 21)
1075#define R300_DISABLE_MC_MCLKA (1 << 21)
1076#define R300_DISABLE_MC_MCLKB (1 << 21)
1077#define RADEON_MCLK_MISC0x001f /* PLL */
1078#define RADEON_MC_MCLK_MAX_DYN_STOP_LAT (1 << 12)
1079#define RADEON_IO_MCLK_MAX_DYN_STOP_LAT (1 << 13)
1080#define RADEON_MC_MCLK_DYN_ENABLE (1 << 14)
1081#define RADEON_IO_MCLK_DYN_ENABLE (1 << 15)
1082#define RADEON_LCD_GPIO_MASK0x01a0
1083#define RADEON_GPIOPAD_EN0x01a0
1084#define RADEON_LCD_GPIO_Y_REG0x01a4
1085#define RADEON_MDGPIO_A_REG0x01ac
1086#define RADEON_MDGPIO_EN_REG0x01b0
1087#define RADEON_MDGPIO_MASK0x0198
1088#define RADEON_GPIOPAD_MASK0x0198
1089#define RADEON_GPIOPAD_A0x019c
1090#define RADEON_MDGPIO_Y_REG0x01b4
1091#define RADEON_MEM_ADDR_CONFIG0x0148
1092#define RADEON_MEM_BASE0x0f10 /* PCI */
1093#define RADEON_MEM_CNTL0x0140
1094#define RADEON_MEM_NUM_CHANNELS_MASK 0x01
1095#define RADEON_MEM_USE_B_CH_ONLY (1 <<1)
1096#define RV100_HALF_MODE (1 <<3)
1097#define R300_MEM_NUM_CHANNELS_MASK 0x03
1098#define R300_MEM_USE_CD_CH_ONLY (1 <<2)
1099#define RADEON_MEM_TIMING_CNTL0x0144 /* EXT_MEM_CNTL */
1100#define RADEON_MEM_INIT_LAT_TIMER0x0154
1101#define RADEON_MEM_INTF_CNTL0x014c
1102#define RADEON_MEM_SDRAM_MODE_REG0x0158
1103#define RADEON_SDRAM_MODE_MASK 0xffff0000
1104#define RADEON_B3MEM_RESET_MASK 0x6fffffff
1105#define RADEON_MEM_CFG_TYPE_DDR (1 << 30)
1106#define RADEON_MEM_STR_CNTL0x0150
1107#define RADEON_MEM_PWRUP_COMPL_A (1 <<0)
1108#define RADEON_MEM_PWRUP_COMPL_B (1 <<1)
1109#define R300_MEM_PWRUP_COMPL_C (1 <<2)
1110#define R300_MEM_PWRUP_COMPL_D (1 <<3)
1111#define RADEON_MEM_PWRUP_COMPLETE 0x03
1112#define R300_MEM_PWRUP_COMPLETE 0x0f
1113#define RADEON_MC_STATUS0x0150
1114#define RADEON_MC_IDLE (1 << 2)
1115#define R300_MC_IDLE (1 << 4)
1116#define RADEON_MEM_VGA_RP_SEL0x003c
1117#define RADEON_MEM_VGA_WP_SEL0x0038
1118#define RADEON_MIN_GRANT0x0f3e /* PCI */
1119#define RADEON_MM_DATA0x0004
1120#define RADEON_MM_INDEX0x0000
1121#define RADEON_MPLL_CNTL0x000e /* PLL */
1122#define RADEON_MPP_TB_CONFIG0x01c0 /* ? */
1123#define RADEON_MPP_GP_CONFIG0x01c8 /* ? */
1124#define RADEON_SEPROM_CNTL10x01c0
1125#define RADEON_SCK_PRESCALE_SHIFT 24
1126#define RADEON_SCK_PRESCALE_MASK (0xff << 24)
1127#define R300_MC_IND_INDEX0x01f8
1128#define R300_MC_IND_ADDR_MASK 0x3f
1129#define R300_MC_IND_WR_EN (1 << 8)
1130#define R300_MC_IND_DATA0x01fc
1131#define R300_MC_READ_CNTL_AB0x017c
1132#define R300_MEM_RBS_POSITION_A_MASK 0x03
1133#define R300_MC_READ_CNTL_CD_mcind0x24
1134#define R300_MEM_RBS_POSITION_C_MASK 0x03
1135
1136#define RADEON_N_VIF_COUNT0x0248
1137
1138#define RADEON_OV0_AUTO_FLIP_CNTL0x0470
1139#define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_BUF_NUM 0x00000007
1140#define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_REPEAT_FIELD 0x00000008
1141#define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD 0x00000010
1142#define RADEON_OV0_AUTO_FLIP_CNTL_IGNORE_REPEAT_FIELD0x00000020
1143#define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE 0x00000040
1144#define RADEON_OV0_AUTO_FLIP_CNTL_VID_PORT_SELECT 0x00000300
1145#define RADEON_OV0_AUTO_FLIP_CNTL_P1_FIRST_LINE_EVEN 0x00010000
1146#define RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_EVEN_DOWN 0x00040000
1147#define RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_ODD_DOWN 0x00080000
1148#define RADEON_OV0_AUTO_FLIP_CNTL_FIELD_POL_SOURCE 0x00800000
1149
1150#define RADEON_OV0_COLOUR_CNTL0x04E0
1151#define RADEON_OV0_DEINTERLACE_PATTERN0x0474
1152#define RADEON_OV0_EXCLUSIVE_HORZ0x0408
1153#define RADEON_EXCL_HORZ_START_MASK0x000000ff
1154#define RADEON_EXCL_HORZ_END_MASK0x0000ff00
1155#define RADEON_EXCL_HORZ_BACK_PORCH_MASK0x00ff0000
1156#define RADEON_EXCL_HORZ_EXCLUSIVE_EN0x80000000
1157#define RADEON_OV0_EXCLUSIVE_VERT0x040C
1158#define RADEON_EXCL_VERT_START_MASK0x000003ff
1159#define RADEON_EXCL_VERT_END_MASK0x03ff0000
1160#define RADEON_OV0_FILTER_CNTL0x04A0
1161#define RADEON_FILTER_PROGRAMMABLE_COEF 0x0
1162#define RADEON_FILTER_HC_COEF_HORZ_Y 0x1
1163#define RADEON_FILTER_HC_COEF_HORZ_UV 0x2
1164#define RADEON_FILTER_HC_COEF_VERT_Y 0x4
1165#define RADEON_FILTER_HC_COEF_VERT_UV 0x8
1166#define RADEON_FILTER_HARDCODED_COEF 0xf
1167#define RADEON_FILTER_COEF_MASK 0xf
1168
1169#define RADEON_OV0_FOUR_TAP_COEF_00x04B0
1170#define RADEON_OV0_FOUR_TAP_COEF_10x04B4
1171#define RADEON_OV0_FOUR_TAP_COEF_20x04B8
1172#define RADEON_OV0_FOUR_TAP_COEF_30x04BC
1173#define RADEON_OV0_FOUR_TAP_COEF_40x04C0
1174#define RADEON_OV0_FLAG_CNTL0x04DC
1175#define RADEON_OV0_GAMMA_000_00F0x0d40
1176#define RADEON_OV0_GAMMA_010_01F0x0d44
1177#define RADEON_OV0_GAMMA_020_03F0x0d48
1178#define RADEON_OV0_GAMMA_040_07F0x0d4c
1179#define RADEON_OV0_GAMMA_080_0BF0x0e00
1180#define RADEON_OV0_GAMMA_0C0_0FF0x0e04
1181#define RADEON_OV0_GAMMA_100_13F0x0e08
1182#define RADEON_OV0_GAMMA_140_17F0x0e0c
1183#define RADEON_OV0_GAMMA_180_1BF0x0e10
1184#define RADEON_OV0_GAMMA_1C0_1FF0x0e14
1185#define RADEON_OV0_GAMMA_200_23F0x0e18
1186#define RADEON_OV0_GAMMA_240_27F0x0e1c
1187#define RADEON_OV0_GAMMA_280_2BF0x0e20
1188#define RADEON_OV0_GAMMA_2C0_2FF0x0e24
1189#define RADEON_OV0_GAMMA_300_33F0x0e28
1190#define RADEON_OV0_GAMMA_340_37F0x0e2c
1191#define RADEON_OV0_GAMMA_380_3BF0x0d50
1192#define RADEON_OV0_GAMMA_3C0_3FF0x0d54
1193#define RADEON_OV0_GRAPHICS_KEY_CLR_LOW0x04EC
1194#define RADEON_OV0_GRAPHICS_KEY_CLR_HIGH0x04F0
1195#define RADEON_OV0_H_INC0x0480
1196#define RADEON_OV0_KEY_CNTL0x04F4
1197#define RADEON_VIDEO_KEY_FN_MASK 0x00000003L
1198#define RADEON_VIDEO_KEY_FN_FALSE 0x00000000L
1199#define RADEON_VIDEO_KEY_FN_TRUE 0x00000001L
1200#define RADEON_VIDEO_KEY_FN_EQ 0x00000002L
1201#define RADEON_VIDEO_KEY_FN_NE 0x00000003L
1202#define RADEON_GRAPHIC_KEY_FN_MASK 0x00000030L
1203#define RADEON_GRAPHIC_KEY_FN_FALSE 0x00000000L
1204#define RADEON_GRAPHIC_KEY_FN_TRUE 0x00000010L
1205#define RADEON_GRAPHIC_KEY_FN_EQ 0x00000020L
1206#define RADEON_GRAPHIC_KEY_FN_NE 0x00000030L
1207#define RADEON_CMP_MIX_MASK 0x00000100L
1208#define RADEON_CMP_MIX_OR 0x00000000L
1209#define RADEON_CMP_MIX_AND 0x00000100L
1210#define RADEON_OV0_LIN_TRANS_A0x0d20
1211#define RADEON_OV0_LIN_TRANS_B0x0d24
1212#define RADEON_OV0_LIN_TRANS_C0x0d28
1213#define RADEON_OV0_LIN_TRANS_D0x0d2c
1214#define RADEON_OV0_LIN_TRANS_E0x0d30
1215#define RADEON_OV0_LIN_TRANS_F0x0d34
1216#define RADEON_OV0_P1_BLANK_LINES_AT_TOP0x0430
1217#define RADEON_P1_BLNK_LN_AT_TOP_M1_MASK0x00000fffL
1218#define RADEON_P1_ACTIVE_LINES_M10x0fff0000L
1219#define RADEON_OV0_P1_H_ACCUM_INIT0x0488
1220#define RADEON_OV0_P1_V_ACCUM_INIT0x0428
1221#define RADEON_OV0_P1_MAX_LN_IN_PER_LN_OUT 0x00000003L
1222#define RADEON_OV0_P1_V_ACCUM_INIT_MASK0x01ff8000L
1223#define RADEON_OV0_P1_X_START_END0x0494
1224#define RADEON_OV0_P2_X_START_END0x0498
1225#define RADEON_OV0_P23_BLANK_LINES_AT_TOP0x0434
1226#define RADEON_P23_BLNK_LN_AT_TOP_M1_MASK0x000007ffL
1227#define RADEON_P23_ACTIVE_LINES_M10x07ff0000L
1228#define RADEON_OV0_P23_H_ACCUM_INIT0x048C
1229#define RADEON_OV0_P23_V_ACCUM_INIT0x042C
1230#define RADEON_OV0_P3_X_START_END0x049C
1231#define RADEON_OV0_REG_LOAD_CNTL0x0410
1232#define RADEON_REG_LD_CTL_LOCK0x00000001L
1233#define RADEON_REG_LD_CTL_VBLANK_DURING_LOCK0x00000002L
1234#define RADEON_REG_LD_CTL_STALL_GUI_UNTIL_FLIP 0x00000004L
1235#define RADEON_REG_LD_CTL_LOCK_READBACK0x00000008L
1236#define RADEON_REG_LD_CTL_FLIP_READBACK0x00000010L
1237#define RADEON_OV0_SCALE_CNTL0x0420
1238#define RADEON_SCALER_HORZ_PICK_NEAREST0x00000004L
1239#define RADEON_SCALER_VERT_PICK_NEAREST0x00000008L
1240#define RADEON_SCALER_SIGNED_UV0x00000010L
1241#define RADEON_SCALER_GAMMA_SEL_MASK0x00000060L
1242#define RADEON_SCALER_GAMMA_SEL_BRIGHT0x00000000L
1243#define RADEON_SCALER_GAMMA_SEL_G220x00000020L
1244#define RADEON_SCALER_GAMMA_SEL_G180x00000040L
1245#define RADEON_SCALER_GAMMA_SEL_G140x00000060L
1246#define RADEON_SCALER_COMCORE_SHIFT_UP_ONE 0x00000080L
1247#define RADEON_SCALER_SURFAC_FORMAT0x00000f00L
1248#define RADEON_SCALER_SOURCE_15BPP0x00000300L
1249#define RADEON_SCALER_SOURCE_16BPP0x00000400L
1250#define RADEON_SCALER_SOURCE_32BPP0x00000600L
1251#define RADEON_SCALER_SOURCE_YUV90x00000900L
1252#define RADEON_SCALER_SOURCE_YUV120x00000A00L
1253#define RADEON_SCALER_SOURCE_VYUY4220x00000B00L
1254#define RADEON_SCALER_SOURCE_YVYU4220x00000C00L
1255#define RADEON_SCALER_ADAPTIVE_DEINT0x00001000L
1256#define RADEON_SCALER_TEMPORAL_DEINT0x00002000L
1257#define RADEON_SCALER_CRTC_SEL0x00004000L
1258#define RADEON_SCALER_SMART_SWITCH0x00008000L
1259#define RADEON_SCALER_BURST_PER_PLANE0x007F0000L
1260#define RADEON_SCALER_DOUBLE_BUFFER0x01000000L
1261#define RADEON_SCALER_DIS_LIMIT0x08000000L
1262#define RADEON_SCALER_LIN_TRANS_BYPASS0x10000000L
1263#define RADEON_SCALER_INT_EMU0x20000000L
1264#define RADEON_SCALER_ENABLE0x40000000L
1265#define RADEON_SCALER_SOFT_RESET0x80000000L
1266#define RADEON_OV0_STEP_BY0x0484
1267#define RADEON_OV0_TEST0x04F8
1268#define RADEON_OV0_V_INC0x0424
1269#define RADEON_OV0_VID_BUF_PITCH0_VALUE0x0460
1270#define RADEON_OV0_VID_BUF_PITCH1_VALUE0x0464
1271#define RADEON_OV0_VID_BUF0_BASE_ADRS0x0440
1272#define RADEON_VIF_BUF0_PITCH_SEL0x00000001L
1273#define RADEON_VIF_BUF0_TILE_ADRS0x00000002L
1274#define RADEON_VIF_BUF0_BASE_ADRS_MASK0x03fffff0L
1275#define RADEON_VIF_BUF0_1ST_LINE_LSBS_MASK0x48000000L
1276#define RADEON_OV0_VID_BUF1_BASE_ADRS0x0444
1277#define RADEON_VIF_BUF1_PITCH_SEL0x00000001L
1278#define RADEON_VIF_BUF1_TILE_ADRS0x00000002L
1279#define RADEON_VIF_BUF1_BASE_ADRS_MASK0x03fffff0L
1280#define RADEON_VIF_BUF1_1ST_LINE_LSBS_MASK0x48000000L
1281#define RADEON_OV0_VID_BUF2_BASE_ADRS0x0448
1282#define RADEON_VIF_BUF2_PITCH_SEL0x00000001L
1283#define RADEON_VIF_BUF2_TILE_ADRS0x00000002L
1284#define RADEON_VIF_BUF2_BASE_ADRS_MASK0x03fffff0L
1285#define RADEON_VIF_BUF2_1ST_LINE_LSBS_MASK0x48000000L
1286#define RADEON_OV0_VID_BUF3_BASE_ADRS0x044C
1287#define RADEON_OV0_VID_BUF4_BASE_ADRS0x0450
1288#define RADEON_OV0_VID_BUF5_BASE_ADRS0x0454
1289#define RADEON_OV0_VIDEO_KEY_CLR_HIGH0x04E8
1290#define RADEON_OV0_VIDEO_KEY_CLR_LOW0x04E4
1291#define RADEON_OV0_Y_X_START0x0400
1292#define RADEON_OV0_Y_X_END0x0404
1293#define RADEON_OV1_Y_X_START0x0600
1294#define RADEON_OV1_Y_X_END0x0604
1295#define RADEON_OVR_CLR0x0230
1296#define RADEON_OVR_WID_LEFT_RIGHT0x0234
1297#define RADEON_OVR_WID_TOP_BOTTOM0x0238
1298
1299/* first capture unit */
1300#define RADEON_CAP0_BUF0_OFFSET 0x0920
1301#define RADEON_CAP0_BUF1_OFFSET 0x0924
1302#define RADEON_CAP0_BUF0_EVEN_OFFSET 0x0928
1303#define RADEON_CAP0_BUF1_EVEN_OFFSET 0x092C
1304
1305#define RADEON_CAP0_BUF_PITCH 0x0930
1306#define RADEON_CAP0_V_WINDOW 0x0934
1307#define RADEON_CAP0_H_WINDOW 0x0938
1308#define RADEON_CAP0_VBI0_OFFSET 0x093C
1309#define RADEON_CAP0_VBI1_OFFSET 0x0940
1310#define RADEON_CAP0_VBI_V_WINDOW 0x0944
1311#define RADEON_CAP0_VBI_H_WINDOW 0x0948
1312#define RADEON_CAP0_PORT_MODE_CNTL 0x094C
1313#define RADEON_CAP0_TRIG_CNTL 0x0950
1314#define RADEON_CAP0_DEBUG 0x0954
1315#define RADEON_CAP0_CONFIG 0x0958
1316#define RADEON_CAP0_CONFIG_CONTINUOS 0x00000001
1317#define RADEON_CAP0_CONFIG_START_FIELD_EVEN 0x00000002
1318#define RADEON_CAP0_CONFIG_START_BUF_GET 0x00000004
1319#define RADEON_CAP0_CONFIG_START_BUF_SET 0x00000008
1320#define RADEON_CAP0_CONFIG_BUF_TYPE_ALT 0x00000010
1321#define RADEON_CAP0_CONFIG_BUF_TYPE_FRAME 0x00000020
1322#define RADEON_CAP0_CONFIG_ONESHOT_MODE_FRAME 0x00000040
1323#define RADEON_CAP0_CONFIG_BUF_MODE_DOUBLE 0x00000080
1324#define RADEON_CAP0_CONFIG_BUF_MODE_TRIPLE 0x00000100
1325#define RADEON_CAP0_CONFIG_MIRROR_EN 0x00000200
1326#define RADEON_CAP0_CONFIG_ONESHOT_MIRROR_EN 0x00000400
1327#define RADEON_CAP0_CONFIG_VIDEO_SIGNED_UV 0x00000800
1328#define RADEON_CAP0_CONFIG_ANC_DECODE_EN 0x00001000
1329#define RADEON_CAP0_CONFIG_VBI_EN 0x00002000
1330#define RADEON_CAP0_CONFIG_SOFT_PULL_DOWN_EN 0x00004000
1331#define RADEON_CAP0_CONFIG_VIP_EXTEND_FLAG_EN 0x00008000
1332#define RADEON_CAP0_CONFIG_FAKE_FIELD_EN 0x00010000
1333#define RADEON_CAP0_CONFIG_ODD_ONE_MORE_LINE 0x00020000
1334#define RADEON_CAP0_CONFIG_EVEN_ONE_MORE_LINE 0x00040000
1335#define RADEON_CAP0_CONFIG_HORZ_DIVIDE_2 0x00080000
1336#define RADEON_CAP0_CONFIG_HORZ_DIVIDE_4 0x00100000
1337#define RADEON_CAP0_CONFIG_VERT_DIVIDE_2 0x00200000
1338#define RADEON_CAP0_CONFIG_VERT_DIVIDE_4 0x00400000
1339#define RADEON_CAP0_CONFIG_FORMAT_BROOKTREE 0x00000000
1340#define RADEON_CAP0_CONFIG_FORMAT_CCIR656 0x00800000
1341#define RADEON_CAP0_CONFIG_FORMAT_ZV 0x01000000
1342#define RADEON_CAP0_CONFIG_FORMAT_VIP 0x01800000
1343#define RADEON_CAP0_CONFIG_FORMAT_TRANSPORT 0x02000000
1344#define RADEON_CAP0_CONFIG_HORZ_DECIMATOR 0x04000000
1345#define RADEON_CAP0_CONFIG_VIDEO_IN_YVYU422 0x00000000
1346#define RADEON_CAP0_CONFIG_VIDEO_IN_VYUY422 0x20000000
1347#define RADEON_CAP0_CONFIG_VBI_DIVIDE_2 0x40000000
1348#define RADEON_CAP0_CONFIG_VBI_DIVIDE_4 0x80000000
1349#define RADEON_CAP0_ANC_ODD_OFFSET 0x095C
1350#define RADEON_CAP0_ANC_EVEN_OFFSET 0x0960
1351#define RADEON_CAP0_ANC_H_WINDOW 0x0964
1352#define RADEON_CAP0_VIDEO_SYNC_TEST 0x0968
1353#define RADEON_CAP0_ONESHOT_BUF_OFFSET 0x096C
1354#define RADEON_CAP0_BUF_STATUS 0x0970
1355/* #define RADEON_CAP0_DWNSC_XRATIO 0x0978 */
1356/* #define RADEON_CAP0_XSHARPNESS 0x097C */
1357#define RADEON_CAP0_VBI2_OFFSET 0x0980
1358#define RADEON_CAP0_VBI3_OFFSET 0x0984
1359#define RADEON_CAP0_ANC2_OFFSET 0x0988
1360#define RADEON_CAP0_ANC3_OFFSET 0x098C
1361#define RADEON_VID_BUFFER_CONTROL 0x0900
1362
1363/* second capture unit */
1364#define RADEON_CAP1_BUF0_OFFSET 0x0990
1365#define RADEON_CAP1_BUF1_OFFSET 0x0994
1366#define RADEON_CAP1_BUF0_EVEN_OFFSET 0x0998
1367#define RADEON_CAP1_BUF1_EVEN_OFFSET 0x099C
1368
1369#define RADEON_CAP1_BUF_PITCH 0x09A0
1370#define RADEON_CAP1_V_WINDOW 0x09A4
1371#define RADEON_CAP1_H_WINDOW 0x09A8
1372#define RADEON_CAP1_VBI_ODD_OFFSET 0x09AC
1373#define RADEON_CAP1_VBI_EVEN_OFFSET 0x09B0
1374#define RADEON_CAP1_VBI_V_WINDOW 0x09B4
1375#define RADEON_CAP1_VBI_H_WINDOW 0x09B8
1376#define RADEON_CAP1_PORT_MODE_CNTL 0x09BC
1377#define RADEON_CAP1_TRIG_CNTL 0x09C0
1378#define RADEON_CAP1_DEBUG 0x09C4
1379#define RADEON_CAP1_CONFIG 0x09C8
1380#define RADEON_CAP1_ANC_ODD_OFFSET 0x09CC
1381#define RADEON_CAP1_ANC_EVEN_OFFSET 0x09D0
1382#define RADEON_CAP1_ANC_H_WINDOW 0x09D4
1383#define RADEON_CAP1_VIDEO_SYNC_TEST 0x09D8
1384#define RADEON_CAP1_ONESHOT_BUF_OFFSET 0x09DC
1385#define RADEON_CAP1_BUF_STATUS 0x09E0
1386#define RADEON_CAP1_DWNSC_XRATIO 0x09E8
1387#define RADEON_CAP1_XSHARPNESS 0x09EC
1388
1389/* misc multimedia registers */
1390#define RADEON_IDCT_RUNS 0x1F80
1391#define RADEON_IDCT_LEVELS 0x1F84
1392#define RADEON_IDCT_CONTROL 0x1FBC
1393#define RADEON_IDCT_AUTH_CONTROL 0x1F88
1394#define RADEON_IDCT_AUTH 0x1F8C
1395
1396#define RADEON_P2PLL_CNTL0x002a /* P2PLL */
1397#define RADEON_P2PLL_RESET (1 << 0)
1398#define RADEON_P2PLL_SLEEP (1 << 1)
1399#define RADEON_P2PLL_PVG_MASK (7 << 11)
1400#define RADEON_P2PLL_PVG_SHIFT 11
1401#define RADEON_P2PLL_ATOMIC_UPDATE_EN (1 << 16)
1402#define RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN (1 << 17)
1403#define RADEON_P2PLL_ATOMIC_UPDATE_VSYNC (1 << 18)
1404#define RADEON_P2PLL_DIV_00x002c
1405#define RADEON_P2PLL_FB0_DIV_MASK 0x07ff
1406#define RADEON_P2PLL_POST0_DIV_MASK 0x00070000
1407#define RADEON_P2PLL_REF_DIV0x002B /* PLL */
1408#define RADEON_P2PLL_REF_DIV_MASK 0x03ff
1409#define RADEON_P2PLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */
1410#define RADEON_P2PLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */
1411#define R300_PPLL_REF_DIV_ACC_MASK (0x3ff << 18)
1412#define R300_PPLL_REF_DIV_ACC_SHIFT 18
1413#define RADEON_PALETTE_DATA0x00b4
1414#define RADEON_PALETTE_30_DATA0x00b8
1415#define RADEON_PALETTE_INDEX0x00b0
1416#define RADEON_PCI_GART_PAGE0x017c
1417#define RADEON_PIXCLKS_CNTL0x002d
1418#define RADEON_PIX2CLK_SRC_SEL_MASK0x03
1419#define RADEON_PIX2CLK_SRC_SEL_CPUCLK0x00
1420#define RADEON_PIX2CLK_SRC_SEL_PSCANCLK 0x01
1421#define RADEON_PIX2CLK_SRC_SEL_BYTECLK0x02
1422#define RADEON_PIX2CLK_SRC_SEL_P2PLLCLK 0x03
1423#define RADEON_PIX2CLK_ALWAYS_ONb(1<<6)
1424#define RADEON_PIX2CLK_DAC_ALWAYS_ONb(1<<7)
1425#define RADEON_PIXCLK_TV_SRC_SEL(1 << 8)
1426#define RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb (1 << 9)
1427#define R300_DVOCLK_ALWAYS_ONb(1 << 10)
1428#define RADEON_PIXCLK_BLEND_ALWAYS_ONb(1 << 11)
1429#define RADEON_PIXCLK_GV_ALWAYS_ONb(1 << 12)
1430#define RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb (1 << 13)
1431#define R300_PIXCLK_DVO_ALWAYS_ONb(1 << 13)
1432#define RADEON_PIXCLK_LVDS_ALWAYS_ONb(1 << 14)
1433#define RADEON_PIXCLK_TMDS_ALWAYS_ONb(1 << 15)
1434#define R300_PIXCLK_TRANS_ALWAYS_ONb(1 << 16)
1435#define R300_PIXCLK_TVO_ALWAYS_ONb(1 << 17)
1436#define R300_P2G2CLK_ALWAYS_ONb(1 << 18)
1437#define R300_P2G2CLK_DAC_ALWAYS_ONb(1 << 19)
1438#define R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF (1 << 23)
1439#define RADEON_PLANE_3D_MASK_C0x1d44
1440#define RADEON_PLL_TEST_CNTL0x0013 /* PLL */
1441#define RADEON_PLL_MASK_READ_B(1 << 9)
1442#define RADEON_PMI_CAP_ID0x0f5c /* PCI */
1443#define RADEON_PMI_DATA0x0f63 /* PCI */
1444#define RADEON_PMI_NXT_CAP_PTR0x0f5d /* PCI */
1445#define RADEON_PMI_PMC_REG0x0f5e /* PCI */
1446#define RADEON_PMI_PMCSR_REG0x0f60 /* PCI */
1447#define RADEON_PMI_REGISTER0x0f5c /* PCI */
1448#define RADEON_PPLL_CNTL0x0002 /* PLL */
1449#define RADEON_PPLL_RESET (1 <<0)
1450#define RADEON_PPLL_SLEEP (1 <<1)
1451#define RADEON_PPLL_PVG_MASK (7 << 11)
1452#define RADEON_PPLL_PVG_SHIFT 11
1453#define RADEON_PPLL_ATOMIC_UPDATE_EN (1 << 16)
1454#define RADEON_PPLL_VGA_ATOMIC_UPDATE_EN (1 << 17)
1455#define RADEON_PPLL_ATOMIC_UPDATE_VSYNC (1 << 18)
1456#define RADEON_PPLL_DIV_00x0004 /* PLL */
1457#define RADEON_PPLL_DIV_10x0005 /* PLL */
1458#define RADEON_PPLL_DIV_20x0006 /* PLL */
1459#define RADEON_PPLL_DIV_30x0007 /* PLL */
1460#define RADEON_PPLL_FB3_DIV_MASK 0x07ff
1461#define RADEON_PPLL_POST3_DIV_MASK 0x00070000
1462#define RADEON_PPLL_REF_DIV0x0003 /* PLL */
1463#define RADEON_PPLL_REF_DIV_MASK 0x03ff
1464#define RADEON_PPLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */
1465#define RADEON_PPLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */
1466#define RADEON_PWR_MNGMT_CNTL_STATUS0x0f60 /* PCI */
1467
1468#define RADEON_RBBM_GUICNTL0x172c
1469#define RADEON_HOST_DATA_SWAP_NONE (0 << 0)
1470#define RADEON_HOST_DATA_SWAP_16BIT (1 << 0)
1471#define RADEON_HOST_DATA_SWAP_32BIT (2 << 0)
1472#define RADEON_HOST_DATA_SWAP_HDW (3 << 0)
1473#define RADEON_RBBM_SOFT_RESET0x00f0
1474#define RADEON_SOFT_RESET_CP (1 <<0)
1475#define RADEON_SOFT_RESET_HI (1 <<1)
1476#define RADEON_SOFT_RESET_SE (1 <<2)
1477#define RADEON_SOFT_RESET_RE (1 <<3)
1478#define RADEON_SOFT_RESET_PP (1 <<4)
1479#define RADEON_SOFT_RESET_E2 (1 <<5)
1480#define RADEON_SOFT_RESET_RB (1 <<6)
1481#define RADEON_SOFT_RESET_HDP (1 <<7)
1482#define RADEON_RBBM_STATUS0x0e40
1483#define RADEON_RBBM_FIFOCNT_MASK 0x007f
1484#define RADEON_RBBM_ACTIVE (1 << 31)
1485#define RADEON_RB2D_DSTCACHE_CTLSTAT0x342c
1486#define RADEON_RB2D_DC_FLUSH (3 << 0)
1487#define RADEON_RB2D_DC_FREE (3 << 2)
1488#define RADEON_RB2D_DC_FLUSH_ALL 0xf
1489#define RADEON_RB2D_DC_BUSY (1 << 31)
1490#define RADEON_RB2D_DSTCACHE_MODE0x3428
1491#define RADEON_DSTCACHE_CTLSTAT0x1714
1492
1493#define RADEON_RB3D_ZCACHE_MODE0x3250
1494#define RADEON_RB3D_ZCACHE_CTLSTAT0x3254
1495#define RADEON_RB3D_ZC_FLUSH_ALL 0x5
1496#define RADEON_RB3D_DSTCACHE_MODE0x3258
1497#define RADEON_RB3D_DC_CACHE_ENABLE (0)
1498#define RADEON_RB3D_DC_2D_CACHE_DISABLE (1)
1499#define RADEON_RB3D_DC_3D_CACHE_DISABLE (2)
1500#define RADEON_RB3D_DC_CACHE_DISABLE (3)
1501#define RADEON_RB3D_DC_2D_CACHE_LINESIZE_128 (1 << 2)
1502#define RADEON_RB3D_DC_3D_CACHE_LINESIZE_128 (2 << 2)
1503#define RADEON_RB3D_DC_2D_CACHE_AUTOFLUSH (1 << 8)
1504#define RADEON_RB3D_DC_3D_CACHE_AUTOFLUSH (2 << 8)
1505#define R200_RB3D_DC_2D_CACHE_AUTOFREE (1 << 10)
1506#define R200_RB3D_DC_3D_CACHE_AUTOFREE (2 << 10)
1507#define RADEON_RB3D_DC_FORCE_RMW (1 << 16)
1508#define RADEON_RB3D_DC_DISABLE_RI_FILL (1 << 24)
1509#define RADEON_RB3D_DC_DISABLE_RI_READ (1 << 25)
1510
1511#define RADEON_RB3D_DSTCACHE_CTLSTAT0x325C
1512#define RADEON_RB3D_DC_FLUSH (3 << 0)
1513#define RADEON_RB3D_DC_FREE (3 << 2)
1514#define RADEON_RB3D_DC_FLUSH_ALL 0xf
1515#define RADEON_RB3D_DC_BUSY (1 << 31)
1516
1517#define RADEON_REG_BASE0x0f18 /* PCI */
1518#define RADEON_REGPROG_INF0x0f09 /* PCI */
1519#define RADEON_REVISION_ID0x0f08 /* PCI */
1520
1521#define RADEON_SC_BOTTOM0x164c
1522#define RADEON_SC_BOTTOM_RIGHT0x16f0
1523#define RADEON_SC_BOTTOM_RIGHT_C0x1c8c
1524#define RADEON_SC_LEFT0x1640
1525#define RADEON_SC_RIGHT0x1644
1526#define RADEON_SC_TOP0x1648
1527#define RADEON_SC_TOP_LEFT0x16ec
1528#define RADEON_SC_TOP_LEFT_C0x1c88
1529#define RADEON_SC_SIGN_MASK_LO 0x8000
1530#define RADEON_SC_SIGN_MASK_HI 0x80000000
1531#define RADEON_SCLK_CNTL0x000d /* PLL */
1532#define RADEON_SCLK_SRC_SEL_MASK 0x0007
1533#define RADEON_DYN_STOP_LAT_MASK 0x00007ff8
1534#define RADEON_CP_MAX_DYN_STOP_LAT 0x0008
1535#define RADEON_SCLK_FORCEON_MASK 0xffff8000
1536#define RADEON_SCLK_FORCE_DISP2 (1<<15)
1537#define RADEON_SCLK_FORCE_CP (1<<16)
1538#define RADEON_SCLK_FORCE_HDP (1<<17)
1539#define RADEON_SCLK_FORCE_DISP1 (1<<18)
1540#define RADEON_SCLK_FORCE_TOP (1<<19)
1541#define RADEON_SCLK_FORCE_E2 (1<<20)
1542#define RADEON_SCLK_FORCE_SE (1<<21)
1543#define RADEON_SCLK_FORCE_IDCT (1<<22)
1544#define RADEON_SCLK_FORCE_VIP (1<<23)
1545#define RADEON_SCLK_FORCE_RE (1<<24)
1546#define RADEON_SCLK_FORCE_PB (1<<25)
1547#define RADEON_SCLK_FORCE_TAM (1<<26)
1548#define RADEON_SCLK_FORCE_TDM (1<<27)
1549#define RADEON_SCLK_FORCE_RB (1<<28)
1550#define RADEON_SCLK_FORCE_TV_SCLK (1<<29)
1551#define RADEON_SCLK_FORCE_SUBPIC (1<<30)
1552#define RADEON_SCLK_FORCE_OV0 (1<<31)
1553#define R300_SCLK_FORCE_VAP (1<<21)
1554#define R300_SCLK_FORCE_SR (1<<25)
1555#define R300_SCLK_FORCE_PX (1<<26)
1556#define R300_SCLK_FORCE_TX (1<<27)
1557#define R300_SCLK_FORCE_US (1<<28)
1558#define R300_SCLK_FORCE_SU (1<<30)
1559#define R300_SCLK_CNTL20x1e /* PLL */
1560#define R300_SCLK_TCL_MAX_DYN_STOP_LAT (1<<10)
1561#define R300_SCLK_GA_MAX_DYN_STOP_LAT (1<<11)
1562#define R300_SCLK_CBA_MAX_DYN_STOP_LAT (1<<12)
1563#define R300_SCLK_FORCE_TCL (1<<13)
1564#define R300_SCLK_FORCE_CBA (1<<14)
1565#define R300_SCLK_FORCE_GA (1<<15)
1566#define RADEON_SCLK_MORE_CNTL0x0035 /* PLL */
1567#define RADEON_SCLK_MORE_MAX_DYN_STOP_LAT 0x0007
1568#define RADEON_SCLK_MORE_FORCEON 0x0700
1569#define RADEON_SDRAM_MODE_REG0x0158
1570#define RADEON_SEQ8_DATA0x03c5 /* VGA */
1571#define RADEON_SEQ8_IDX0x03c4 /* VGA */
1572#define RADEON_SNAPSHOT_F_COUNT0x0244
1573#define RADEON_SNAPSHOT_VH_COUNTS0x0240
1574#define RADEON_SNAPSHOT_VIF_COUNT0x024c
1575#define RADEON_SRC_OFFSET0x15ac
1576#define RADEON_SRC_PITCH0x15b0
1577#define RADEON_SRC_PITCH_OFFSET0x1428
1578#define RADEON_SRC_SC_BOTTOM0x165c
1579#define RADEON_SRC_SC_BOTTOM_RIGHT0x16f4
1580#define RADEON_SRC_SC_RIGHT0x1654
1581#define RADEON_SRC_X0x1414
1582#define RADEON_SRC_X_Y0x1590
1583#define RADEON_SRC_Y0x1418
1584#define RADEON_SRC_Y_X0x1434
1585#define RADEON_STATUS0x0f06 /* PCI */
1586#define RADEON_SUBPIC_CNTL0x0540 /* ? */
1587#define RADEON_SUB_CLASS0x0f0a /* PCI */
1588#define RADEON_SURFACE_CNTL0x0b00
1589#define RADEON_SURF_TRANSLATION_DIS (1 << 8)
1590#define RADEON_NONSURF_AP0_SWP_16BPP (1 << 20)
1591#define RADEON_NONSURF_AP0_SWP_32BPP (1 << 21)
1592#define RADEON_NONSURF_AP1_SWP_16BPP (1 << 22)
1593#define RADEON_NONSURF_AP1_SWP_32BPP (1 << 23)
1594#define RADEON_SURFACE0_INFO0x0b0c
1595#define RADEON_SURF_TILE_COLOR_MACRO (0 << 16)
1596#define RADEON_SURF_TILE_COLOR_BOTH (1 << 16)
1597#define RADEON_SURF_TILE_DEPTH_32BPP (2 << 16)
1598#define RADEON_SURF_TILE_DEPTH_16BPP (3 << 16)
1599#define R200_SURF_TILE_NONE (0 << 16)
1600#define R200_SURF_TILE_COLOR_MACRO (1 << 16)
1601#define R200_SURF_TILE_COLOR_MICRO (2 << 16)
1602#define R200_SURF_TILE_COLOR_BOTH (3 << 16)
1603#define R200_SURF_TILE_DEPTH_32BPP (4 << 16)
1604#define R200_SURF_TILE_DEPTH_16BPP (5 << 16)
1605#define R300_SURF_TILE_NONE (0 << 16)
1606#define R300_SURF_TILE_COLOR_MACRO (1 << 16)
1607#define R300_SURF_TILE_DEPTH_32BPP (2 << 16)
1608#define RADEON_SURF_AP0_SWP_16BPP (1 << 20)
1609#define RADEON_SURF_AP0_SWP_32BPP (1 << 21)
1610#define RADEON_SURF_AP1_SWP_16BPP (1 << 22)
1611#define RADEON_SURF_AP1_SWP_32BPP (1 << 23)
1612#define RADEON_SURFACE0_LOWER_BOUND0x0b04
1613#define RADEON_SURFACE0_UPPER_BOUND0x0b08
1614#define RADEON_SURFACE1_INFO0x0b1c
1615#define RADEON_SURFACE1_LOWER_BOUND0x0b14
1616#define RADEON_SURFACE1_UPPER_BOUND0x0b18
1617#define RADEON_SURFACE2_INFO0x0b2c
1618#define RADEON_SURFACE2_LOWER_BOUND0x0b24
1619#define RADEON_SURFACE2_UPPER_BOUND0x0b28
1620#define RADEON_SURFACE3_INFO0x0b3c
1621#define RADEON_SURFACE3_LOWER_BOUND0x0b34
1622#define RADEON_SURFACE3_UPPER_BOUND0x0b38
1623#define RADEON_SURFACE4_INFO0x0b4c
1624#define RADEON_SURFACE4_LOWER_BOUND0x0b44
1625#define RADEON_SURFACE4_UPPER_BOUND0x0b48
1626#define RADEON_SURFACE5_INFO0x0b5c
1627#define RADEON_SURFACE5_LOWER_BOUND0x0b54
1628#define RADEON_SURFACE5_UPPER_BOUND0x0b58
1629#define RADEON_SURFACE6_INFO0x0b6c
1630#define RADEON_SURFACE6_LOWER_BOUND0x0b64
1631#define RADEON_SURFACE6_UPPER_BOUND0x0b68
1632#define RADEON_SURFACE7_INFO0x0b7c
1633#define RADEON_SURFACE7_LOWER_BOUND0x0b74
1634#define RADEON_SURFACE7_UPPER_BOUND0x0b78
1635#define RADEON_SW_SEMAPHORE0x013c
1636
1637#define RADEON_TEST_DEBUG_CNTL0x0120
1638#define RADEON_TEST_DEBUG_CNTL__TEST_DEBUG_OUT_EN0x00000001
1639
1640#define RADEON_TEST_DEBUG_MUX0x0124
1641#define RADEON_TEST_DEBUG_OUT0x012c
1642#define RADEON_TMDS_PLL_CNTL0x02a8
1643#define RADEON_TMDS_TRANSMITTER_CNTL0x02a4
1644#define RADEON_TMDS_TRANSMITTER_PLLEN1
1645#define RADEON_TMDS_TRANSMITTER_PLLRST2
1646#define RADEON_TRAIL_BRES_DEC0x1614
1647#define RADEON_TRAIL_BRES_ERR0x160c
1648#define RADEON_TRAIL_BRES_INC0x1610
1649#define RADEON_TRAIL_X0x1618
1650#define RADEON_TRAIL_X_SUB0x1620
1651
1652#define RADEON_VCLK_ECP_CNTL0x0008 /* PLL */
1653#define RADEON_VCLK_SRC_SEL_MASK 0x03
1654#define RADEON_VCLK_SRC_SEL_CPUCLK 0x00
1655#define RADEON_VCLK_SRC_SEL_PSCANCLK 0x01
1656#define RADEON_VCLK_SRC_SEL_BYTECLK 0x02
1657#define RADEON_VCLK_SRC_SEL_PPLLCLK 0x03
1658#define RADEON_PIXCLK_ALWAYS_ONb (1<<6)
1659#define RADEON_PIXCLK_DAC_ALWAYS_ONb (1<<7)
1660#define R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF (1<<23)
1661
1662#define RADEON_VENDOR_ID0x0f00 /* PCI */
1663#define RADEON_VGA_DDA_CONFIG0x02e8
1664#define RADEON_VGA_DDA_ON_OFF0x02ec
1665#define RADEON_VID_BUFFER_CONTROL0x0900
1666#define RADEON_VIDEOMUX_CNTL0x0190
1667
1668/* VIP bus */
1669#define RADEON_VIPH_CH0_DATA0x0c00
1670#define RADEON_VIPH_CH1_DATA0x0c04
1671#define RADEON_VIPH_CH2_DATA0x0c08
1672#define RADEON_VIPH_CH3_DATA0x0c0c
1673#define RADEON_VIPH_CH0_ADDR0x0c10
1674#define RADEON_VIPH_CH1_ADDR0x0c14
1675#define RADEON_VIPH_CH2_ADDR0x0c18
1676#define RADEON_VIPH_CH3_ADDR0x0c1c
1677#define RADEON_VIPH_CH0_SBCNT0x0c20
1678#define RADEON_VIPH_CH1_SBCNT0x0c24
1679#define RADEON_VIPH_CH2_SBCNT0x0c28
1680#define RADEON_VIPH_CH3_SBCNT0x0c2c
1681#define RADEON_VIPH_CH0_ABCNT0x0c30
1682#define RADEON_VIPH_CH1_ABCNT0x0c34
1683#define RADEON_VIPH_CH2_ABCNT0x0c38
1684#define RADEON_VIPH_CH3_ABCNT0x0c3c
1685#define RADEON_VIPH_CONTROL0x0c40
1686#define RADEON_VIP_BUSY 0
1687#define RADEON_VIP_IDLE 1
1688#define RADEON_VIP_RESET 2
1689#define RADEON_VIPH_EN (1 << 21)
1690#define RADEON_VIPH_DV_LAT0x0c44
1691#define RADEON_VIPH_BM_CHUNK0x0c48
1692#define RADEON_VIPH_DV_INT0x0c4c
1693#define RADEON_VIPH_TIMEOUT_STAT0x0c50
1694#define RADEON_VIPH_TIMEOUT_STAT__VIPH_REG_STAT 0x00000010
1695#define RADEON_VIPH_TIMEOUT_STAT__VIPH_REG_AK0x00000010
1696#define RADEON_VIPH_TIMEOUT_STAT__VIPH_REGR_DIS 0x01000000
1697
1698#define RADEON_VIPH_REG_DATA0x0084
1699#define RADEON_VIPH_REG_ADDR0x0080
1700
1701#define RADEON_WAIT_UNTIL0x1720
1702#define RADEON_WAIT_CRTC_PFLIP (1 << 0)
1703#define RADEON_WAIT_RE_CRTC_VLINE (1 << 1)
1704#define RADEON_WAIT_FE_CRTC_VLINE (1 << 2)
1705#define RADEON_WAIT_CRTC_VLINE (1 << 3)
1706#define RADEON_WAIT_DMA_VID_IDLE (1 << 8)
1707#define RADEON_WAIT_DMA_GUI_IDLE (1 << 9)
1708#define RADEON_WAIT_CMDFIFO (1 << 10) /* wait for CMDFIFO_ENTRIES */
1709#define RADEON_WAIT_OV0_FLIP (1 << 11)
1710#define RADEON_WAIT_AGP_FLUSH (1 << 13)
1711#define RADEON_WAIT_2D_IDLE (1 << 14)
1712#define RADEON_WAIT_3D_IDLE (1 << 15)
1713#define RADEON_WAIT_2D_IDLECLEAN (1 << 16)
1714#define RADEON_WAIT_3D_IDLECLEAN (1 << 17)
1715#define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)
1716#define RADEON_CMDFIFO_ENTRIES_SHIFT 10
1717#define RADEON_CMDFIFO_ENTRIES_MASK 0x7f
1718#define RADEON_WAIT_VAP_IDLE (1 << 28)
1719#define RADEON_WAIT_BOTH_CRTC_PFLIP (1 << 30)
1720#define RADEON_ENG_DISPLAY_SELECT_CRTC0 (0 << 31)
1721#define RADEON_ENG_DISPLAY_SELECT_CRTC1 (1 << 31)
1722
1723#define RADEON_X_MPLL_REF_FB_DIV0x000a /* PLL */
1724#define RADEON_XCLK_CNTL0x000d /* PLL */
1725#define RADEON_XDLL_CNTL0x000c /* PLL */
1726#define RADEON_XPLL_CNTL0x000b /* PLL */
1727
1728
1729
1730/* Registers for 3D/TCL */
1731#define RADEON_PP_BORDER_COLOR_00x1d40
1732#define RADEON_PP_BORDER_COLOR_10x1d44
1733#define RADEON_PP_BORDER_COLOR_20x1d48
1734#define RADEON_PP_CNTL0x1c38
1735#define RADEON_STIPPLE_ENABLE (1 <<0)
1736#define RADEON_SCISSOR_ENABLE (1 <<1)
1737#define RADEON_PATTERN_ENABLE (1 <<2)
1738#define RADEON_SHADOW_ENABLE (1 <<3)
1739#define RADEON_TEX_ENABLE_MASK (0xf << 4)
1740#define RADEON_TEX_0_ENABLE (1 <<4)
1741#define RADEON_TEX_1_ENABLE (1 <<5)
1742#define RADEON_TEX_2_ENABLE (1 <<6)
1743#define RADEON_TEX_3_ENABLE (1 <<7)
1744#define RADEON_TEX_BLEND_ENABLE_MASK (0xf << 12)
1745#define RADEON_TEX_BLEND_0_ENABLE (1 << 12)
1746#define RADEON_TEX_BLEND_1_ENABLE (1 << 13)
1747#define RADEON_TEX_BLEND_2_ENABLE (1 << 14)
1748#define RADEON_TEX_BLEND_3_ENABLE (1 << 15)
1749#define RADEON_PLANAR_YUV_ENABLE (1 << 20)
1750#define RADEON_SPECULAR_ENABLE (1 << 21)
1751#define RADEON_FOG_ENABLE (1 << 22)
1752#define RADEON_ALPHA_TEST_ENABLE (1 << 23)
1753#define RADEON_ANTI_ALIAS_NONE (0 << 24)
1754#define RADEON_ANTI_ALIAS_LINE (1 << 24)
1755#define RADEON_ANTI_ALIAS_POLY (2 << 24)
1756#define RADEON_ANTI_ALIAS_LINE_POLY (3 << 24)
1757#define RADEON_BUMP_MAP_ENABLE (1 << 26)
1758#define RADEON_BUMPED_MAP_T0 (0 << 27)
1759#define RADEON_BUMPED_MAP_T1 (1 << 27)
1760#define RADEON_BUMPED_MAP_T2 (2 << 27)
1761#define RADEON_TEX_3D_ENABLE_0 (1 << 29)
1762#define RADEON_TEX_3D_ENABLE_1 (1 << 30)
1763#define RADEON_MC_ENABLE (1 << 31)
1764#define RADEON_PP_FOG_COLOR0x1c18
1765#define RADEON_FOG_COLOR_MASK 0x00ffffff
1766#define RADEON_FOG_VERTEX (0 << 24)
1767#define RADEON_FOG_TABLE (1 << 24)
1768#define RADEON_FOG_USE_DEPTH (0 << 25)
1769#define RADEON_FOG_USE_DIFFUSE_ALPHA (2 << 25)
1770#define RADEON_FOG_USE_SPEC_ALPHA (3 << 25)
1771#define RADEON_PP_LUM_MATRIX0x1d00
1772#define RADEON_PP_MISC0x1c14
1773#define RADEON_REF_ALPHA_MASK 0x000000ff
1774#define RADEON_ALPHA_TEST_FAIL (0 << 8)
1775#define RADEON_ALPHA_TEST_LESS (1 << 8)
1776#define RADEON_ALPHA_TEST_LEQUAL (2 << 8)
1777#define RADEON_ALPHA_TEST_EQUAL (3 << 8)
1778#define RADEON_ALPHA_TEST_GEQUAL (4 << 8)
1779#define RADEON_ALPHA_TEST_GREATER (5 << 8)
1780#define RADEON_ALPHA_TEST_NEQUAL (6 << 8)
1781#define RADEON_ALPHA_TEST_PASS (7 << 8)
1782#define RADEON_ALPHA_TEST_OP_MASK (7 << 8)
1783#define RADEON_CHROMA_FUNC_FAIL (0 << 16)
1784#define RADEON_CHROMA_FUNC_PASS (1 << 16)
1785#define RADEON_CHROMA_FUNC_NEQUAL (2 << 16)
1786#define RADEON_CHROMA_FUNC_EQUAL (3 << 16)
1787#define RADEON_CHROMA_KEY_NEAREST (0 << 18)
1788#define RADEON_CHROMA_KEY_ZERO (1 << 18)
1789#define RADEON_SHADOW_ID_AUTO_INC (1 << 20)
1790#define RADEON_SHADOW_FUNC_EQUAL (0 << 21)
1791#define RADEON_SHADOW_FUNC_NEQUAL (1 << 21)
1792#define RADEON_SHADOW_PASS_1 (0 << 22)
1793#define RADEON_SHADOW_PASS_2 (1 << 22)
1794#define RADEON_RIGHT_HAND_CUBE_D3D (0 << 24)
1795#define RADEON_RIGHT_HAND_CUBE_OGL (1 << 24)
1796#define RADEON_PP_ROT_MATRIX_00x1d58
1797#define RADEON_PP_ROT_MATRIX_10x1d5c
1798#define RADEON_PP_TXFILTER_00x1c54
1799#define RADEON_PP_TXFILTER_10x1c6c
1800#define RADEON_PP_TXFILTER_20x1c84
1801#define RADEON_MAG_FILTER_NEAREST(0<<0)
1802#define RADEON_MAG_FILTER_LINEAR(1<<0)
1803#define RADEON_MAG_FILTER_MASK(1<<0)
1804#define RADEON_MIN_FILTER_NEAREST(0<<1)
1805#define RADEON_MIN_FILTER_LINEAR(1<<1)
1806#define RADEON_MIN_FILTER_NEAREST_MIP_NEAREST(2<<1)
1807#define RADEON_MIN_FILTER_NEAREST_MIP_LINEAR(3<<1)
1808#define RADEON_MIN_FILTER_LINEAR_MIP_NEAREST(6<<1)
1809#define RADEON_MIN_FILTER_LINEAR_MIP_LINEAR(7<<1)
1810#define RADEON_MIN_FILTER_ANISO_NEAREST(8<<1)
1811#define RADEON_MIN_FILTER_ANISO_LINEAR(9<<1)
1812#define RADEON_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (10 <<1)
1813#define RADEON_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR(11 <<1)
1814#define RADEON_MIN_FILTER_MASK(15 <<1)
1815#define RADEON_MAX_ANISO_1_TO_1(0<<5)
1816#define RADEON_MAX_ANISO_2_TO_1(1<<5)
1817#define RADEON_MAX_ANISO_4_TO_1(2<<5)
1818#define RADEON_MAX_ANISO_8_TO_1(3<<5)
1819#define RADEON_MAX_ANISO_16_TO_1(4<<5)
1820#define RADEON_MAX_ANISO_MASK(7<<5)
1821#define RADEON_LOD_BIAS_MASK(0xff << 8)
1822#define RADEON_LOD_BIAS_SHIFT8
1823#define RADEON_MAX_MIP_LEVEL_MASK(0x0f << 16)
1824#define RADEON_MAX_MIP_LEVEL_SHIFT16
1825#define RADEON_YUV_TO_RGB(1<< 20)
1826#define RADEON_YUV_TEMPERATURE_COOL(0<< 21)
1827#define RADEON_YUV_TEMPERATURE_HOT(1<< 21)
1828#define RADEON_YUV_TEMPERATURE_MASK(1<< 21)
1829#define RADEON_WRAPEN_S(1<< 22)
1830#define RADEON_CLAMP_S_WRAP(0<< 23)
1831#define RADEON_CLAMP_S_MIRROR(1<< 23)
1832#define RADEON_CLAMP_S_CLAMP_LAST(2<< 23)
1833#define RADEON_CLAMP_S_MIRROR_CLAMP_LAST(3<< 23)
1834#define RADEON_CLAMP_S_CLAMP_BORDER(4<< 23)
1835#define RADEON_CLAMP_S_MIRROR_CLAMP_BORDER(5<< 23)
1836#define RADEON_CLAMP_S_CLAMP_GL(6<< 23)
1837#define RADEON_CLAMP_S_MIRROR_CLAMP_GL(7<< 23)
1838#define RADEON_CLAMP_S_MASK(7<< 23)
1839#define RADEON_WRAPEN_T(1<< 26)
1840#define RADEON_CLAMP_T_WRAP(0<< 27)
1841#define RADEON_CLAMP_T_MIRROR(1<< 27)
1842#define RADEON_CLAMP_T_CLAMP_LAST(2<< 27)
1843#define RADEON_CLAMP_T_MIRROR_CLAMP_LAST(3<< 27)
1844#define RADEON_CLAMP_T_CLAMP_BORDER(4<< 27)
1845#define RADEON_CLAMP_T_MIRROR_CLAMP_BORDER(5<< 27)
1846#define RADEON_CLAMP_T_CLAMP_GL(6<< 27)
1847#define RADEON_CLAMP_T_MIRROR_CLAMP_GL(7<< 27)
1848#define RADEON_CLAMP_T_MASK(7<< 27)
1849#define RADEON_BORDER_MODE_OGL(0<< 31)
1850#define RADEON_BORDER_MODE_D3D(1<< 31)
1851#define RADEON_PP_TXFORMAT_00x1c58
1852#define RADEON_PP_TXFORMAT_10x1c70
1853#define RADEON_PP_TXFORMAT_20x1c88
1854#define RADEON_TXFORMAT_I8 (0 << 0)
1855#define RADEON_TXFORMAT_AI88 (1 << 0)
1856#define RADEON_TXFORMAT_RGB332 (2 << 0)
1857#define RADEON_TXFORMAT_ARGB1555 (3 << 0)
1858#define RADEON_TXFORMAT_RGB565 (4 << 0)
1859#define RADEON_TXFORMAT_ARGB4444 (5 << 0)
1860#define RADEON_TXFORMAT_ARGB8888 (6 << 0)
1861#define RADEON_TXFORMAT_RGBA8888 (7 << 0)
1862#define RADEON_TXFORMAT_Y8 (8 << 0)
1863#define RADEON_TXFORMAT_VYUY422 (10 << 0)
1864#define RADEON_TXFORMAT_YVYU422 (11 << 0)
1865#define RADEON_TXFORMAT_DXT1 (12 << 0)
1866#define RADEON_TXFORMAT_DXT23 (14 << 0)
1867#define RADEON_TXFORMAT_DXT45 (15 << 0)
1868#define RADEON_TXFORMAT_FORMAT_MASK (31 << 0)
1869#define RADEON_TXFORMAT_FORMAT_SHIFT 0
1870#define RADEON_TXFORMAT_APPLE_YUV_MODE (1 << 5)
1871#define RADEON_TXFORMAT_ALPHA_IN_MAP (1 << 6)
1872#define RADEON_TXFORMAT_NON_POWER2 (1 << 7)
1873#define RADEON_TXFORMAT_WIDTH_MASK (15 << 8)
1874#define RADEON_TXFORMAT_WIDTH_SHIFT 8
1875#define RADEON_TXFORMAT_HEIGHT_MASK (15 << 12)
1876#define RADEON_TXFORMAT_HEIGHT_SHIFT 12
1877#define RADEON_TXFORMAT_F5_WIDTH_MASK (15 << 16)
1878#define RADEON_TXFORMAT_F5_WIDTH_SHIFT 16
1879#define RADEON_TXFORMAT_F5_HEIGHT_MASK (15 << 20)
1880#define RADEON_TXFORMAT_F5_HEIGHT_SHIFT 20
1881#define RADEON_TXFORMAT_ST_ROUTE_STQ0 (0 << 24)
1882#define RADEON_TXFORMAT_ST_ROUTE_MASK (3 << 24)
1883#define RADEON_TXFORMAT_ST_ROUTE_STQ1 (1 << 24)
1884#define RADEON_TXFORMAT_ST_ROUTE_STQ2 (2 << 24)
1885#define RADEON_TXFORMAT_ENDIAN_NO_SWAP (0 << 26)
1886#define RADEON_TXFORMAT_ENDIAN_16BPP_SWAP (1 << 26)
1887#define RADEON_TXFORMAT_ENDIAN_32BPP_SWAP (2 << 26)
1888#define RADEON_TXFORMAT_ENDIAN_HALFDW_SWAP (3 << 26)
1889#define RADEON_TXFORMAT_ALPHA_MASK_ENABLE (1 << 28)
1890#define RADEON_TXFORMAT_CHROMA_KEY_ENABLE (1 << 29)
1891#define RADEON_TXFORMAT_CUBIC_MAP_ENABLE (1 << 30)
1892#define RADEON_TXFORMAT_PERSPECTIVE_ENABLE (1 << 31)
1893#define RADEON_PP_CUBIC_FACES_00x1d24
1894#define RADEON_PP_CUBIC_FACES_10x1d28
1895#define RADEON_PP_CUBIC_FACES_20x1d2c
1896#define RADEON_FACE_WIDTH_1_SHIFT 0
1897#define RADEON_FACE_HEIGHT_1_SHIFT 4
1898#define RADEON_FACE_WIDTH_1_MASK (0xf << 0)
1899#define RADEON_FACE_HEIGHT_1_MASK (0xf << 4)
1900#define RADEON_FACE_WIDTH_2_SHIFT 8
1901#define RADEON_FACE_HEIGHT_2_SHIFT 12
1902#define RADEON_FACE_WIDTH_2_MASK (0xf << 8)
1903#define RADEON_FACE_HEIGHT_2_MASK (0xf << 12)
1904#define RADEON_FACE_WIDTH_3_SHIFT 16
1905#define RADEON_FACE_HEIGHT_3_SHIFT 20
1906#define RADEON_FACE_WIDTH_3_MASK (0xf << 16)
1907#define RADEON_FACE_HEIGHT_3_MASK (0xf << 20)
1908#define RADEON_FACE_WIDTH_4_SHIFT 24
1909#define RADEON_FACE_HEIGHT_4_SHIFT 28
1910#define RADEON_FACE_WIDTH_4_MASK (0xf << 24)
1911#define RADEON_FACE_HEIGHT_4_MASK (0xf << 28)
1912
1913#define RADEON_PP_TXOFFSET_00x1c5c
1914#define RADEON_PP_TXOFFSET_10x1c74
1915#define RADEON_PP_TXOFFSET_20x1c8c
1916#define RADEON_TXO_ENDIAN_NO_SWAP (0 << 0)
1917#define RADEON_TXO_ENDIAN_BYTE_SWAP (1 << 0)
1918#define RADEON_TXO_ENDIAN_WORD_SWAP (2 << 0)
1919#define RADEON_TXO_ENDIAN_HALFDW_SWAP (3 << 0)
1920#define RADEON_TXO_MACRO_LINEAR (0 << 2)
1921#define RADEON_TXO_MACRO_TILE (1 << 2)
1922#define RADEON_TXO_MICRO_LINEAR (0 << 3)
1923#define RADEON_TXO_MICRO_TILE_X2 (1 << 3)
1924#define RADEON_TXO_MICRO_TILE_OPT (2 << 3)
1925#define RADEON_TXO_OFFSET_MASK 0xffffffe0
1926#define RADEON_TXO_OFFSET_SHIFT 5
1927
1928#define RADEON_PP_CUBIC_OFFSET_T0_00x1dd0/* bits [31:5] */
1929#define RADEON_PP_CUBIC_OFFSET_T0_10x1dd4
1930#define RADEON_PP_CUBIC_OFFSET_T0_20x1dd8
1931#define RADEON_PP_CUBIC_OFFSET_T0_30x1ddc
1932#define RADEON_PP_CUBIC_OFFSET_T0_40x1de0
1933#define RADEON_PP_CUBIC_OFFSET_T1_00x1e00
1934#define RADEON_PP_CUBIC_OFFSET_T1_10x1e04
1935#define RADEON_PP_CUBIC_OFFSET_T1_20x1e08
1936#define RADEON_PP_CUBIC_OFFSET_T1_30x1e0c
1937#define RADEON_PP_CUBIC_OFFSET_T1_40x1e10
1938#define RADEON_PP_CUBIC_OFFSET_T2_00x1e14
1939#define RADEON_PP_CUBIC_OFFSET_T2_10x1e18
1940#define RADEON_PP_CUBIC_OFFSET_T2_20x1e1c
1941#define RADEON_PP_CUBIC_OFFSET_T2_30x1e20
1942#define RADEON_PP_CUBIC_OFFSET_T2_40x1e24
1943
1944#define RADEON_PP_TEX_SIZE_00x1d04/* NPOT */
1945#define RADEON_PP_TEX_SIZE_10x1d0c
1946#define RADEON_PP_TEX_SIZE_20x1d14
1947#define RADEON_TEX_USIZE_MASK (0x7ff << 0)
1948#define RADEON_TEX_USIZE_SHIFT 0
1949#define RADEON_TEX_VSIZE_MASK (0x7ff << 16)
1950#define RADEON_TEX_VSIZE_SHIFT 16
1951#define RADEON_SIGNED_RGB_MASK (1 << 30)
1952#define RADEON_SIGNED_RGB_SHIFT 30
1953#define RADEON_SIGNED_ALPHA_MASK (1 << 31)
1954#define RADEON_SIGNED_ALPHA_SHIFT 31
1955#define RADEON_PP_TEX_PITCH_00x1d08/* NPOT */
1956#define RADEON_PP_TEX_PITCH_10x1d10/* NPOT */
1957#define RADEON_PP_TEX_PITCH_20x1d18/* NPOT */
1958/* note: bits 13-5: 32 byte aligned stride of texture map */
1959
1960#define RADEON_PP_TXCBLEND_00x1c60
1961#define RADEON_PP_TXCBLEND_10x1c78
1962#define RADEON_PP_TXCBLEND_20x1c90
1963#define RADEON_COLOR_ARG_A_SHIFT 0
1964#define RADEON_COLOR_ARG_A_MASK (0x1f << 0)
1965#define RADEON_COLOR_ARG_A_ZERO (0<< 0)
1966#define RADEON_COLOR_ARG_A_CURRENT_COLOR (2<< 0)
1967#define RADEON_COLOR_ARG_A_CURRENT_ALPHA (3<< 0)
1968#define RADEON_COLOR_ARG_A_DIFFUSE_COLOR (4<< 0)
1969#define RADEON_COLOR_ARG_A_DIFFUSE_ALPHA (5<< 0)
1970#define RADEON_COLOR_ARG_A_SPECULAR_COLOR (6<< 0)
1971#define RADEON_COLOR_ARG_A_SPECULAR_ALPHA (7<< 0)
1972#define RADEON_COLOR_ARG_A_TFACTOR_COLOR (8<< 0)
1973#define RADEON_COLOR_ARG_A_TFACTOR_ALPHA (9<< 0)
1974#define RADEON_COLOR_ARG_A_T0_COLOR (10<< 0)
1975#define RADEON_COLOR_ARG_A_T0_ALPHA (11<< 0)
1976#define RADEON_COLOR_ARG_A_T1_COLOR (12<< 0)
1977#define RADEON_COLOR_ARG_A_T1_ALPHA (13<< 0)
1978#define RADEON_COLOR_ARG_A_T2_COLOR (14<< 0)
1979#define RADEON_COLOR_ARG_A_T2_ALPHA (15<< 0)
1980#define RADEON_COLOR_ARG_A_T3_COLOR (16<< 0)
1981#define RADEON_COLOR_ARG_A_T3_ALPHA (17<< 0)
1982#define RADEON_COLOR_ARG_B_SHIFT 5
1983#define RADEON_COLOR_ARG_B_MASK (0x1f << 5)
1984#define RADEON_COLOR_ARG_B_ZERO (0<< 5)
1985#define RADEON_COLOR_ARG_B_CURRENT_COLOR (2<< 5)
1986#define RADEON_COLOR_ARG_B_CURRENT_ALPHA (3<< 5)
1987#define RADEON_COLOR_ARG_B_DIFFUSE_COLOR (4<< 5)
1988#define RADEON_COLOR_ARG_B_DIFFUSE_ALPHA (5<< 5)
1989#define RADEON_COLOR_ARG_B_SPECULAR_COLOR (6<< 5)
1990#define RADEON_COLOR_ARG_B_SPECULAR_ALPHA (7<< 5)
1991#define RADEON_COLOR_ARG_B_TFACTOR_COLOR (8<< 5)
1992#define RADEON_COLOR_ARG_B_TFACTOR_ALPHA (9<< 5)
1993#define RADEON_COLOR_ARG_B_T0_COLOR (10<< 5)
1994#define RADEON_COLOR_ARG_B_T0_ALPHA (11<< 5)
1995#define RADEON_COLOR_ARG_B_T1_COLOR (12<< 5)
1996#define RADEON_COLOR_ARG_B_T1_ALPHA (13<< 5)
1997#define RADEON_COLOR_ARG_B_T2_COLOR (14<< 5)
1998#define RADEON_COLOR_ARG_B_T2_ALPHA (15<< 5)
1999#define RADEON_COLOR_ARG_B_T3_COLOR (16<< 5)
2000#define RADEON_COLOR_ARG_B_T3_ALPHA (17<< 5)
2001#define RADEON_COLOR_ARG_C_SHIFT 10
2002#define RADEON_COLOR_ARG_C_MASK (0x1f << 10)
2003#define RADEON_COLOR_ARG_C_ZERO (0<< 10)
2004#define RADEON_COLOR_ARG_C_CURRENT_COLOR (2<< 10)
2005#define RADEON_COLOR_ARG_C_CURRENT_ALPHA (3<< 10)
2006#define RADEON_COLOR_ARG_C_DIFFUSE_COLOR (4<< 10)
2007#define RADEON_COLOR_ARG_C_DIFFUSE_ALPHA (5<< 10)
2008#define RADEON_COLOR_ARG_C_SPECULAR_COLOR (6<< 10)
2009#define RADEON_COLOR_ARG_C_SPECULAR_ALPHA (7<< 10)
2010#define RADEON_COLOR_ARG_C_TFACTOR_COLOR (8<< 10)
2011#define RADEON_COLOR_ARG_C_TFACTOR_ALPHA (9<< 10)
2012#define RADEON_COLOR_ARG_C_T0_COLOR (10<< 10)
2013#define RADEON_COLOR_ARG_C_T0_ALPHA (11<< 10)
2014#define RADEON_COLOR_ARG_C_T1_COLOR (12<< 10)
2015#define RADEON_COLOR_ARG_C_T1_ALPHA (13<< 10)
2016#define RADEON_COLOR_ARG_C_T2_COLOR (14<< 10)
2017#define RADEON_COLOR_ARG_C_T2_ALPHA (15<< 10)
2018#define RADEON_COLOR_ARG_C_T3_COLOR (16<< 10)
2019#define RADEON_COLOR_ARG_C_T3_ALPHA (17<< 10)
2020#define RADEON_COMP_ARG_A (1 << 15)
2021#define RADEON_COMP_ARG_A_SHIFT 15
2022#define RADEON_COMP_ARG_B (1 << 16)
2023#define RADEON_COMP_ARG_B_SHIFT 16
2024#define RADEON_COMP_ARG_C (1 << 17)
2025#define RADEON_COMP_ARG_C_SHIFT 17
2026#define RADEON_BLEND_CTL_MASK (7 << 18)
2027#define RADEON_BLEND_CTL_ADD (0 << 18)
2028#define RADEON_BLEND_CTL_SUBTRACT (1 << 18)
2029#define RADEON_BLEND_CTL_ADDSIGNED (2 << 18)
2030#define RADEON_BLEND_CTL_BLEND (3 << 18)
2031#define RADEON_BLEND_CTL_DOT3 (4 << 18)
2032#define RADEON_SCALE_SHIFT 21
2033#define RADEON_SCALE_MASK (3 << 21)
2034#define RADEON_SCALE_1X (0 << 21)
2035#define RADEON_SCALE_2X (1 << 21)
2036#define RADEON_SCALE_4X (2 << 21)
2037#define RADEON_CLAMP_TX (1 << 23)
2038#define RADEON_T0_EQ_TCUR (1 << 24)
2039#define RADEON_T1_EQ_TCUR (1 << 25)
2040#define RADEON_T2_EQ_TCUR (1 << 26)
2041#define RADEON_T3_EQ_TCUR (1 << 27)
2042#define RADEON_COLOR_ARG_MASK 0x1f
2043#define RADEON_COMP_ARG_SHIFT 15
2044#define RADEON_PP_TXABLEND_00x1c64
2045#define RADEON_PP_TXABLEND_10x1c7c
2046#define RADEON_PP_TXABLEND_20x1c94
2047#define RADEON_ALPHA_ARG_A_SHIFT 0
2048#define RADEON_ALPHA_ARG_A_MASK (0xf << 0)
2049#define RADEON_ALPHA_ARG_A_ZERO (0 << 0)