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Root/branches/azimutz/Cleancut/i386/modules/NVIDIAGraphicsEnabler/nvidia.c

1/*␊
2 *␉NVidia injector␊
3 *␊
4 *␉Copyright (C) 2009␉Jasmin Fazlic, iNDi␊
5 *␊
6 *␉NVidia injector is free software: you can redistribute it and/or modify␊
7 *␉it under the terms of the GNU General Public License as published by␊
8 *␉the Free Software Foundation, either version 3 of the License, or␊
9 *␉(at your option) any later version.␊
10 *␊
11 *␉NVidia driver and injector is distributed in the hope that it will be useful,␊
12 *␉but WITHOUT ANY WARRANTY; without even the implied warranty of␊
13 *␉MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the␊
14 *␉GNU General Public License for more details.␊
15 *␊
16 *␉You should have received a copy of the GNU General Public License␊
17 *␉along with NVidia injector.␉ If not, see <http://www.gnu.org/licenses/>.␊
18 */ ␊
19/*␊
20 * Alternatively you can choose to comply with APSL␊
21 */␊
22 ␊
23 ␊
24/*␊
25 * DCB-Table parsing is based on software (nouveau driver) originally distributed under following license:␊
26 *␊
27 *␊
28 * Copyright 2005-2006 Erik Waling␊
29 * Copyright 2006 Stephane Marchesin␊
30 * Copyright 2007-2009 Stuart Bennett␊
31 *␊
32 * Permission is hereby granted, free of charge, to any person obtaining a␊
33 * copy of this software and associated documentation files (the "Software"),␊
34 * to deal in the Software without restriction, including without limitation␊
35 * the rights to use, copy, modify, merge, publish, distribute, sublicense,␊
36 * and/or sell copies of the Software, and to permit persons to whom the␊
37 * Software is furnished to do so, subject to the following conditions:␊
38 *␊
39 * The above copyright notice and this permission notice shall be included in␊
40 * all copies or substantial portions of the Software.␊
41 *␊
42 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR␊
43 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,␊
44 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL␊
45 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,␊
46 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF␊
47 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE␊
48 * SOFTWARE.␊
49 */␊
50␊
51#include "libsa.h"␊
52#include "saio_internal.h"␊
53#include "bootstruct.h"␊
54#include "pci.h"␊
55#include "platform.h"␊
56#include "device_inject.h"␊
57#include "nvidia.h"␊
58␊
59#ifndef DEBUG_NVIDIA␊
60#define DEBUG_NVIDIA 0␊
61#endif␊
62␊
63#if DEBUG_NVIDIA␊
64#define DBG(x...)␉printf(x)␊
65#else␊
66#define DBG(x...)␊
67#endif␊
68␊
69#define kUseNvidiaROM␉␉␉␉"UseNvidiaROM"␊
70#define kVBIOS␉␉␉␉␉␉"VBIOS"␊
71␊
72#define NVIDIA_ROM_SIZE␉␉␉␉0x10000␊
73#define PATCH_ROM_SUCCESS␉␉␉1␊
74#define PATCH_ROM_SUCCESS_HAS_LVDS␉2␊
75#define PATCH_ROM_FAILED␉␉␉0␊
76#define MAX_NUM_DCB_ENTRIES␉␉␉16␊
77#define TYPE_GROUPED␉␉␉␉0xff␊
78␊
79extern uint32_t devices_number;␊
80␊
81const char *nvidia_compatible_0[]␉=␉{ "@0,compatible",␉"NVDA,NVMac"␉ };␊
82const char *nvidia_compatible_1[]␉=␉{ "@1,compatible",␉"NVDA,NVMac"␉ };␊
83const char *nvidia_device_type_0[]␉=␉{ "@0,device_type", "display"␉␉ };␊
84const char *nvidia_device_type_1[]␉=␉{ "@1,device_type", "display"␉␉ };␊
85const char *nvidia_device_type[]␉=␉{ "device_type",␉"NVDA,Parent"␉ };␊
86const char *nvidia_name_0[]␉␉␉=␉{ "@0,name",␉␉"NVDA,Display-A" };␊
87const char *nvidia_name_1[]␉␉␉=␉{ "@1,name",␉␉"NVDA,Display-B" };␊
88const char *nvidia_slot_name[]␉␉=␉{ "AAPL,slot-name", "Slot-1"␉␉ };␊
89␊
90static uint8_t default_NVCAP[]= {␊
91␉0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0d, 0x00,␊
92␉0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a,␊
93␉0x00, 0x00, 0x00, 0x00␊
94};␊
95␊
96#define NVCAP_LEN ( sizeof(default_NVCAP) / sizeof(uint8_t) )␊
97␊
98static struct nv_chipsets_t NVKnownChipsets[] = {␊
99␉//Azi: REVIEW and style␊
100␉{ 0x00000000, "Unknown" },␊
101␉{ 0x10DE0040, "GeForce 6800 Ultra" },␊
102␉{ 0x10DE0041, "GeForce 6800" },␊
103␉{ 0x10DE0042, "GeForce 6800 LE" },␊
104␉{ 0x10DE0043, "GeForce 6800 XE" },␊
105␉{ 0x10DE0044, "GeForce 6800 XT" },␊
106␉{ 0x10DE0045, "GeForce 6800 GT" },␊
107␉{ 0x10DE0046, "GeForce 6800 GT" },␊
108␉{ 0x10DE0047, "GeForce 6800 GS" },␊
109␉{ 0x10DE0048, "GeForce 6800 XT" },␊
110␉{ 0x10DE004E, "Quadro FX 4000" },␊
111␉{ 0x10DE0090, "GeForce 7800 GTX" },␊
112␉{ 0x10DE0091, "GeForce 7800 GTX" },␊
113␉{ 0x10DE0092, "GeForce 7800 GT" },␊
114␉{ 0x10DE0093, "GeForce 7800 GS" },␊
115␉{ 0x10DE0095, "GeForce 7800 SLI" },␊
116␉{ 0x10DE0098, "GeForce Go 7800" },␊
117␉{ 0x10DE0099, "GeForce Go 7800 GTX" },␊
118␉{ 0x10DE009D, "Quadro FX 4500" },␊
119␉{ 0x10DE00C0, "GeForce 6800 GS" },␊
120␉{ 0x10DE00C1, "GeForce 6800" },␊
121␉{ 0x10DE00C2, "GeForce 6800 LE" },␊
122␉{ 0x10DE00C3, "GeForce 6800 XT" },␊
123␉{ 0x10DE00C8, "GeForce Go 6800" },␊
124␉{ 0x10DE00C9, "GeForce Go 6800 Ultra" },␊
125␉{ 0x10DE00CC, "Quadro FX Go1400" },␊
126␉{ 0x10DE00CD, "Quadro FX 3450/4000 SDI" },␊
127␉{ 0x10DE00CE, "Quadro FX 1400" },␊
128␉{ 0x10DE0140, "GeForce 6600 GT" },␊
129␉{ 0x10DE0141, "GeForce 6600" },␊
130␉{ 0x10DE0142, "GeForce 6600 LE" },␊
131␉{ 0x10DE0143, "GeForce 6600 VE" },␊
132␉{ 0x10DE0144, "GeForce Go 6600" },␊
133␉{ 0x10DE0145, "GeForce 6610 XL" },␊
134␉{ 0x10DE0146, "GeForce Go 6600 TE/6200 TE" },␊
135␉{ 0x10DE0147, "GeForce 6700 XL" },␊
136␉{ 0x10DE0148, "GeForce Go 6600" },␊
137␉{ 0x10DE0149, "GeForce Go 6600 GT" },␊
138␉{ 0x10DE014C, "Quadro FX 550" },␊
139␉{ 0x10DE014D, "Quadro FX 550" },␊
140␉{ 0x10DE014E, "Quadro FX 540" },␊
141␉{ 0x10DE014F, "GeForce 6200" },␊
142␉{ 0x10DE0160, "GeForce 6500" },␊
143␉{ 0x10DE0161, "GeForce 6200 TurboCache(TM)" },␊
144␉{ 0x10DE0162, "GeForce 6200SE TurboCache(TM)" },␊
145␉{ 0x10DE0163, "GeForce 6200 LE" },␊
146␉{ 0x10DE0164, "GeForce Go 6200" },␊
147␉{ 0x10DE0165, "Quadro NVS 285" },␊
148␉{ 0x10DE0166, "GeForce Go 6400" },␊
149␉{ 0x10DE0167, "GeForce Go 6200" },␊
150␉{ 0x10DE0168, "GeForce Go 6400" },␊
151␉{ 0x10DE0169, "GeForce 6250" },␊
152␉{ 0x10DE016A, "GeForce 7100 GS" },␊
153␉{ 0x10DE0191, "GeForce 8800 GTX" },␊
154␉{ 0x10DE0193, "GeForce 8800 GTS" },␊
155␉{ 0x10DE0194, "GeForce 8800 Ultra" },␊
156␉{ 0x10DE019D, "Quadro FX 5600" },␊
157␉{ 0x10DE019E, "Quadro FX 4600" },␊
158␉{ 0x10DE01D1, "GeForce 7300 LE" },␊
159␉{ 0x10DE01D3, "GeForce 7300 SE" },␊
160␉{ 0x10DE01D6, "GeForce Go 7200" },␊
161␉{ 0x10DE01D7, "GeForce Go 7300" },␊
162␉{ 0x10DE01D8, "GeForce Go 7400" },␊
163␉{ 0x10DE01D9, "GeForce Go 7400 GS" },␊
164␉{ 0x10DE01DA, "Quadro NVS 110M" },␊
165␉{ 0x10DE01DB, "Quadro NVS 120M" },␊
166␉{ 0x10DE01DC, "Quadro FX 350M" },␊
167␉{ 0x10DE01DD, "GeForce 7500 LE" },␊
168␉{ 0x10DE01DE, "Quadro FX 350" },␊
169␉{ 0x10DE01DF, "GeForce 7300 GS" },␊
170␉{ 0x10DE0211, "GeForce 6800" },␊
171␉{ 0x10DE0212, "GeForce 6800 LE" },␊
172␉{ 0x10DE0215, "GeForce 6800 GT" },␊
173␉{ 0x10DE0218, "GeForce 6800 XT" },␊
174␉{ 0x10DE0221, "GeForce 6200" },␊
175␉{ 0x10DE0222, "GeForce 6200 A-LE" },␊
176␉{ 0x10DE0240, "GeForce 6150" },␊
177␉{ 0x10DE0241, "GeForce 6150 LE" },␊
178␉{ 0x10DE0242, "GeForce 6100" },␊
179␉{ 0x10DE0244, "GeForce Go 6150" },␊
180␉{ 0x10DE0247, "GeForce Go 6100" },␊
181␉{ 0x10DE0290, "GeForce 7900 GTX" },␊
182␉{ 0x10DE0291, "GeForce 7900 GT" },␊
183␉{ 0x10DE0292, "GeForce 7900 GS" },␊
184␉{ 0x10DE0298, "GeForce Go 7900 GS" },␊
185␉{ 0x10DE0299, "GeForce Go 7900 GTX" },␊
186␉{ 0x10DE029A, "Quadro FX 2500M" },␊
187␉{ 0x10DE029B, "Quadro FX 1500M" },␊
188␉{ 0x10DE029C, "Quadro FX 5500" },␊
189␉{ 0x10DE029D, "Quadro FX 3500" },␊
190␉{ 0x10DE029E, "Quadro FX 1500" },␊
191␉{ 0x10DE029F, "Quadro FX 4500 X2" },␊
192␉{ 0x10DE0301, "GeForce FX 5800 Ultra" },␊
193␉{ 0x10DE0302, "GeForce FX 5800" },␊
194␉{ 0x10DE0308, "Quadro FX 2000" },␊
195␉{ 0x10DE0309, "Quadro FX 1000" },␊
196␉{ 0x10DE0311, "GeForce FX 5600 Ultra" },␊
197␉{ 0x10DE0312, "GeForce FX 5600" },␊
198␉{ 0x10DE0314, "GeForce FX 5600XT" },␊
199␉{ 0x10DE031A, "GeForce FX Go5600" },␊
200␉{ 0x10DE031B, "GeForce FX Go5650" },␊
201␉{ 0x10DE031C, "Quadro FX Go700" },␊
202␉{ 0x10DE0324, "GeForce FX Go5200" },␊
203␉{ 0x10DE0325, "GeForce FX Go5250" },␊
204␉{ 0x10DE0326, "GeForce FX 5500" },␊
205␉{ 0x10DE0328, "GeForce FX Go5200 32M/64M" },␊
206␉{ 0x10DE032A, "Quadro NVS 55/280 PCI" },␊
207␉{ 0x10DE032B, "Quadro FX 500/600 PCI" },␊
208␉{ 0x10DE032C, "GeForce FX Go53xx Series" },␊
209␉{ 0x10DE032D, "GeForce FX Go5100" },␊
210␉{ 0x10DE0330, "GeForce FX 5900 Ultra" },␊
211␉{ 0x10DE0331, "GeForce FX 5900" },␊
212␉{ 0x10DE0332, "GeForce FX 5900XT" },␊
213␉{ 0x10DE0333, "GeForce FX 5950 Ultra" },␊
214␉{ 0x10DE0334, "GeForce FX 5900ZT" },␊
215␉{ 0x10DE0338, "Quadro FX 3000" },␊
216␉{ 0x10DE033F, "Quadro FX 700" },␊
217␉{ 0x10DE0341, "GeForce FX 5700 Ultra" },␊
218␉{ 0x10DE0342, "GeForce FX 5700" },␊
219␉{ 0x10DE0343, "GeForce FX 5700LE" },␊
220␉{ 0x10DE0344, "GeForce FX 5700VE" },␊
221␉{ 0x10DE0347, "GeForce FX Go5700" },␊
222␉{ 0x10DE0348, "GeForce FX Go5700" },␊
223␉{ 0x10DE034C, "Quadro FX Go1000" },␊
224␉{ 0x10DE034E, "Quadro FX 1100" },␊
225␉{ 0x10DE0391, "GeForce 7600 GT" },␊
226␉{ 0x10DE0392, "GeForce 7600 GS" },␊
227␉{ 0x10DE0393, "GeForce 7300 GT" },␊
228␉{ 0x10DE0394, "GeForce 7600 LE" },␊
229␉{ 0x10DE0395, "GeForce 7300 GT" },␊
230␉{ 0x10DE0397, "GeForce Go 7700" },␊
231␉{ 0x10DE0398, "GeForce Go 7600" },␊
232␉{ 0x10DE0399, "GeForce Go 7600 GT"},␊
233␉{ 0x10DE039A, "Quadro NVS 300M" },␊
234␉{ 0x10DE039B, "GeForce Go 7900 SE" },␊
235␉{ 0x10DE039C, "Quadro FX 550M" },␊
236␉{ 0x10DE039E, "Quadro FX 560" },␊
237␉{ 0x10DE0400, "GeForce 8600 GTS" },␊
238␉{ 0x10DE0401, "GeForce 8600 GT" },␊
239␉{ 0x10DE0402, "GeForce 8600 GT" },␊
240␉{ 0x10DE0403, "GeForce 8600 GS" },␊
241␉{ 0x10DE0404, "GeForce 8400 GS" },␊
242␉{ 0x10DE0405, "GeForce 9500M GS" },␊
243␉{ 0x10DE0407, "GeForce 8600M GT" },␊
244␉{ 0x10DE0408, "GeForce 9650M GS" },␊
245␉{ 0x10DE0409, "GeForce 8700M GT" },␊
246␉{ 0x10DE040A, "Quadro FX 370" },␊
247␉{ 0x10DE040B, "Quadro NVS 320M" },␊
248␉{ 0x10DE040C, "Quadro FX 570M" },␊
249␉{ 0x10DE040D, "Quadro FX 1600M" },␊
250␉{ 0x10DE040E, "Quadro FX 570" },␊
251␉{ 0x10DE040F, "Quadro FX 1700" },␊
252␉{ 0x10DE0420, "GeForce 8400 SE" },␊
253␉{ 0x10DE0421, "GeForce 8500 GT" },␊
254␉{ 0x10DE0422, "GeForce 8400 GS" },␊
255␉{ 0x10DE0423, "GeForce 8300 GS" },␊
256␉{ 0x10DE0424, "GeForce 8400 GS" },␊
257␉{ 0x10DE0425, "GeForce 8600M GS" },␊
258␉{ 0x10DE0426, "GeForce 8400M GT" },␊
259␉{ 0x10DE0427, "GeForce 8400M GS" },␊
260␉{ 0x10DE0428, "GeForce 8400M G" },␊
261␉{ 0x10DE0429, "Quadro NVS 140M" },␊
262␉{ 0x10DE042A, "Quadro NVS 130M" },␊
263␉{ 0x10DE042B, "Quadro NVS 135M" },␊
264␉{ 0x10DE042C, "GeForce 9400 GT" },␊
265␉{ 0x10DE042D, "Quadro FX 360M" },␊
266␉{ 0x10DE042E, "GeForce 9300M G" },␊
267␉{ 0x10DE042F, "Quadro NVS 290" },␊
268␉{ 0x10DE05E0, "GeForce GTX 295" },␊
269␉{ 0x10DE05E1, "GeForce GTX 280" },␊
270␉{ 0x10DE05E2, "GeForce GTX 260" },␊
271␉{ 0x10DE05E3, "GeForce GTX 285" },␊
272␉{ 0x10DE05E6, "GeForce GTX 275" },␊
273␉{ 0x10DE05EA, "GeForce GTX 260" },␊
274␉{ 0x10DE05EB, "GeForce GTX 295" },␊
275␉{ 0x10DE05F9, "Quadro CX" },␊
276␉{ 0x10DE05FD, "Quadro FX 5800" },␊
277␉{ 0x10DE05FE, "Quadro FX 4800" },␊
278␉{ 0x10DE0600, "GeForce 8800 GTS 512" },␊
279␉{ 0x10DE0602, "GeForce 8800 GT" },␊
280␉{ 0x10DE0604, "GeForce 9800 GX2" },␊
281␉{ 0x10DE0605, "GeForce 9800 GT" },␊
282␉{ 0x10DE0606, "GeForce 8800 GS" },␊
283␉{ 0x10DE0607, "GeForce GTS 240" },␊
284␉{ 0x10DE0608, "GeForce 9800M GTX" },␊
285␉{ 0x10DE0609, "GeForce 8800M GTS" },␊
286␉{ 0x10DE060A, "GeForce GTX 280M" },␊
287␉{ 0x10DE060B, "GeForce 9800M GT" },␊
288␉{ 0x10DE060C, "GeForce 8800M GTX" },␊
289␉{ 0x10DE060D, "GeForce 8800 GS" },␊
290␉{ 0x10DE0610, "GeForce 9600 GSO" },␊
291␉{ 0x10DE0611, "GeForce 8800 GT" },␊
292␉{ 0x10DE0612, "GeForce 9800 GTX" },␊
293␉{ 0x10DE0613, "GeForce 9800 GTX+" },␊
294␉{ 0x10DE0614, "GeForce 9800 GT" },␊
295␉{ 0x10DE0615, "GeForce GTS 250" },␊
296␉{ 0x10DE0617, "GeForce 9800M GTX" },␊
297␉{ 0x10DE0618, "GeForce GTX 260M" }, ␊
298␉{ 0x10DE061A, "Quadro FX 3700" },␊
299␉{ 0x10DE061C, "Quadro FX 3600M" },␊
300␉{ 0x10DE061D, "Quadro FX 2800M" },␊
301␉{ 0x10DE061F, "Quadro FX 3800M" },␊
302␉{ 0x10DE0622, "GeForce 9600 GT" },␊
303␉{ 0x10DE0623, "GeForce 9600 GS" },␊
304␉{ 0x10DE0625, "GeForce 9600 GSO 512"},␊
305␉{ 0x10DE0626, "GeForce GT 130" },␊
306␉{ 0x10DE0627, "GeForce GT 140" },␊
307␉{ 0x10DE0628, "GeForce 9800M GTS" },␊
308␉{ 0x10DE062A, "GeForce 9700M GTS" },␊
309␉{ 0x10DE062C, "GeForce 9800M GTS" },␊
310␉{ 0x10DE0640, "GeForce 9500 GT" },␊
311␉{ 0x10DE0641, "GeForce 9400 GT" },␊
312␉{ 0x10DE0642, "GeForce 8400 GS" },␊
313␉{ 0x10DE0643, "GeForce 9500 GT" },␊
314␉{ 0x10DE0644, "GeForce 9500 GS" },␊
315␉{ 0x10DE0645, "GeForce 9500 GS" },␊
316␉{ 0x10DE0646, "GeForce GT 120" },␊
317␉{ 0x10DE0647, "GeForce 9600M GT" },␊
318␉{ 0x10DE0648, "GeForce 9600M GS" },␊
319␉{ 0x10DE0649, "GeForce 9600M GT" },␊
320␉{ 0x10DE064A, "GeForce 9700M GT" },␊
321␉{ 0x10DE064B, "GeForce 9500M G" },␊
322␉{ 0x10DE064C, "GeForce 9650M GT" },␊
323␉{ 0x10DE0652, "GeForce GT 130M" },␊
324␉{ 0x10DE0658, "Quadro FX 380" },␊
325␉{ 0x10DE0659, "Quadro FX 580" },␊
326␉{ 0x10DE065A, "Quadro FX 1700M" },␊
327␉{ 0x10DE065B, "GeForce 9400 GT" },␊
328␉{ 0x10DE065C, "Quadro FX 770M" },␊
329␉{ 0x10DE06E0, "GeForce 9300 GE" },␊
330␉{ 0x10DE06E1, "GeForce 9300 GS" },␊
331␉{ 0x10DE06E4, "GeForce 8400 GS" },␊
332␉{ 0x10DE06E5, "GeForce 9300M GS" },␊
333␉{ 0x10DE06E8, "GeForce 9200M GS" },␊
334␉{ 0x10DE06E9, "GeForce 9300M GS" },␊
335␉{ 0x10DE06EA, "Quadro NVS 150M" },␊
336␉{ 0x10DE06EB, "Quadro NVS 160M" },␊
337␉{ 0x10DE06EC, "GeForce G 105M" },␊
338␉{ 0x10DE06EF, "GeForce G 103M" },␊
339␉{ 0x10DE06F8, "Quadro NVS 420" },␊
340␉{ 0x10DE06F9, "Quadro FX 370 LP" },␊
341␉{ 0x10DE06FA, "Quadro NVS 450" },␊
342␉{ 0x10DE06FD, "Quadro NVS 295" },␊
343␉{ 0x10DE086A, "GeForce 9400" },␊
344␉{ 0x10DE0874, "ION 9300M" },␉␊
345␉{ 0x10DE086C, "GeForce 9300/nForce 730i" },␊
346␉{ 0x10DE087D, "ION 9400M" },␊
347␉{ 0x10DE087E, "ION LE" },␊
348␉{ 0x10DE0A20, "GeForce GT220" },␊
349␉{ 0x10DE0A23, "GeForce 210" },␊
350␉{ 0x10DE0A28, "GeForce GT 230M" },␊
351␉{ 0x10DE0A29, "GeForce GT 330M" },␊
352␉{ 0x10DE0A2A, "GeForce GT 230M" },␊
353␉{ 0x10DE0A34, "GeForce GT 240M" },␊
354␉{ 0x10DE0A60, "GeForce G210" },␊
355␉{ 0x10DE0A62, "GeForce 205" },␊
356␉{ 0x10DE0A63, "GeForce 310" },␊
357␉{ 0x10DE0A65, "GeForce 210" },␊
358␉{ 0x10DE0A66, "GeForce 310" },␊
359␉{ 0x10DE0A74, "GeForce G210M" },␊
360␉{ 0x10DE0A75, "GeForce G310M" },␊
361␉{ 0x10DE0A78, "Quadro FX 380 LP" },␊
362␉{ 0x10DE0CA3, "GeForce GT 240" },␊
363␉{ 0x10DE0CA8, "GeForce GTS 260M" },␊
364␉{ 0x10DE0CA9, "GeForce GTS 250M" },␊
365␉{ 0x10DE0CB1, "GeForce GTS 360M" },␊
366␉{ 0x10DE0CA3, "GeForce GT240" },␊
367␉␊
368␉// 06C0 - 06DFF␊
369␉{ 0x10DE06C0, "GeForce GTX 480" },␊
370␉{ 0x10DE06C3, "GeForce GTX D12U" },␊
371␉{ 0x10DE06C4, "GeForce GTX 465" },␊
372␉{ 0x10DE06CA, "GeForce GTX 480M" },␊
373␉{ 0x10DE06CD, "GeForce GTX 470" },␊
374␉{ 0x10DE06D1, "Tesla C2050" },␉// TODO: sub-device id: 0x0771␊
375␉{ 0x10DE06D1, "Tesla C2070" },␉// TODO: sub-device id: 0x0772␊
376␉{ 0x10DE06D2, "Tesla M2070" },␊
377␉{ 0x10DE06D8, "Quadro 6000" },␊
378␉{ 0x10DE06D9, "Quadro 5000" },␊
379␉{ 0x10DE06DA, "Quadro 5000M" },␊
380␉{ 0x10DE06DC, "Quadro 6000" },␊
381␉{ 0x10DE06DE, "Tesla M2050" },␉// TODO: sub-device id: 0x0846␊
382␉{ 0x10DE06DE, "Tesla M2070" },␉// TODO: sub-device id: ?␊
383␉// 0x10DE06DE also applies to misc S2050, X2070, M2050, M2070␊
384␉{ 0x10DE06DD, "Quadro 4000" },␊
385␉␊
386␉// 0DC0 - 0DFF␊
387␉{ 0x10DE0DC0, "GeForce GT 440" },␊
388␉{ 0x10DE0DC1, "D12-P1-35" },␊
389␉{ 0x10DE0DC2, "D12-P1-35" },␊
390␉{ 0x10DE0DC4, "GeForce GTS 450" },␊
391␉{ 0x10DE0DC5, "GeForce GTS 450" },␊
392␉{ 0x10DE0DC6, "GeForce GTS 450" },␊
393␉{ 0x10DE0DCA, "GF10x" },␊
394␉{ 0x10DE0DD1, "GeForce GTX 460M" },␊
395␉{ 0x10DE0DD2, "GeForce GT 445M" },␊
396␉{ 0x10DE0DD3, "GeForce GT 435M" },␊
397␉{ 0x10DE0DD8, "Quadro 2000" },␊
398␉{ 0x10DE0DDE, "GF106-ES" },␊
399␉{ 0x10DE0DDF, "GF106-INT" },␊
400␉{ 0x10DE0DE1, "GeForce GT 430" },␊
401␉{ 0x10DE0DE2, "GeForce GT 420" },␊
402␉{ 0x10DE0DEB, "GeForce GT 555M" },␊
403␉{ 0x10DE0DEE, "GeForce GT 415M" },␊
404␉{ 0x10DE0DF0, "GeForce GT 425M" },␊
405␉{ 0x10DE0DF1, "GeForce GT 420M" },␊
406␉{ 0x10DE0DF2, "GeForce GT 435M" },␊
407␉{ 0x10DE0DF3, "GeForce GT 420M" },␊
408␉{ 0x10DE0DF8, "Quadro 600" },␊
409␉{ 0x10DE0DFE, "GF108 ES" },␊
410␉{ 0x10DE0DFF, "GF108 INT" },␊
411␉␊
412␉// 0E20 - 0E3F␊
413␉{ 0x10DE0E21, "D12U-25" },␊
414␉{ 0x10DE0E22, "GeForce GTX 460" },␊
415␉{ 0x10DE0E23, "GeForce GTX 460 SE" },␊
416␉{ 0x10DE0E24, "GeForce GTX 460" },␊
417␉{ 0x10DE0E25, "D12U-50" },␊
418␉{ 0x10DE0E30, "GeForce GTX 470M" },␊
419␉{ 0x10DE0E38, "GF104GL" },␊
420␉{ 0x10DE0E3E, "GF104-ES" },␊
421␉{ 0x10DE0E3F, "GF104-INT" },␊
422␉␊
423␉// 0EE0 - 0EFF: none yet␊
424␉// 0F00 - 0F3F: none yet␊
425␉// 1040 - 107F: none yet␊
426␉␊
427␉// 1080 - 109F␊
428␉{ 0x10DE1080, "GeForce GTX 580" },␊
429␉{ 0x10DE1081, "D13U" },␊
430␉{ 0x10DE1082, "D13U" },␊
431␉{ 0x10DE1083, "D13U" },␊
432␉{ 0x10DE1098, "D13U" },␊
433␉{ 0x10DE109A, "N12E-Q5" },␊
434};␊
435␊
436static uint16_t swap16(uint16_t x)␊
437{␊
438␉return (((x & 0x00FF) << 8) | ((x & 0xFF00) >> 8));␊
439}␊
440␊
441static uint16_t read16(uint8_t *ptr, uint16_t offset)␊
442{␊
443␉uint8_t ret[2];␊
444␉␊
445␉ret[0] = ptr[offset+1];␊
446␉ret[1] = ptr[offset];␊
447␉␊
448␉return *((uint16_t*)&ret);␊
449}␊
450␊
451#if 0␊
452static uint32_t swap32(uint32_t x)␊
453{␊
454␉return ((x & 0x000000FF) << 24) | ((x & 0x0000FF00) << 8 ) | ((x & 0x00FF0000) >> 8 ) | ((x & 0xFF000000) >> 24);␊
455}␊
456␊
457static uint8_t␉read8(uint8_t *ptr, uint16_t offset)␊
458{ ␊
459␉return ptr[offset];␊
460}␊
461␊
462static uint32_t read32(uint8_t *ptr, uint16_t offset)␊
463{␊
464␉uint8_t ret[4];␊
465␉␊
466␉ret[0] = ptr[offset+3];␊
467␉ret[1] = ptr[offset+2];␊
468␉ret[2] = ptr[offset+1];␊
469␉ret[3] = ptr[offset];␊
470␉␊
471␉return *((uint32_t*)&ret);␊
472}␊
473#endif␊
474␊
475static int patch_nvidia_rom(uint8_t *rom)␊
476{␊
477␉if (!rom || (rom[0] != 0x55 && rom[1] != 0xaa)) {␊
478␉␉printf("False ROM signature: 0x%02x%02x\n", rom[0], rom[1]);␊
479␉␉return PATCH_ROM_FAILED;␊
480␉}␊
481␉␊
482␉uint16_t dcbptr = swap16(read16(rom, 0x36));␊
483␉␊
484␉if (!dcbptr) {␊
485␉␉printf("no dcb table found\n");␊
486␉␉return PATCH_ROM_FAILED;␊
487␉}␊
488//␉else␊
489//␉␉printf("dcb table at offset 0x%04x\n", dcbptr);␊
490␉ ␊
491␉uint8_t *dcbtable␉␉ = &rom[dcbptr];␊
492␉uint8_t dcbtable_version = dcbtable[0];␊
493␉uint8_t headerlength␉ = 0;␊
494␉uint8_t recordlength␉ = 0;␊
495␉uint8_t numentries␉␉ = 0;␊
496␉␊
497␉if (dcbtable_version >= 0x20)␊
498␉{␊
499␉␉uint32_t sig;␊
500␉␉␊
501␉␉if (dcbtable_version >= 0x30)␊
502␉␉{␊
503␉␉␉headerlength = dcbtable[1];␊
504␉␉␉numentries␉ = dcbtable[2];␊
505␉␉␉recordlength = dcbtable[3];␊
506␉␉␉␊
507␉␉␉sig = *(uint32_t *)&dcbtable[6];␊
508␉␉}␊
509␉␉else␊
510␉␉{␊
511␉␉␉sig = *(uint32_t *)&dcbtable[4];␊
512␉␉␉headerlength = 8;␊
513␉␉}␊
514␉␉␊
515␉␉if (sig != 0x4edcbdcb)␊
516␉␉{␊
517␉␉␉printf("bad display config block signature (0x%8x)\n", sig);␊
518␉␉␉return PATCH_ROM_FAILED;␊
519␉␉}␊
520␉}␊
521␉else if (dcbtable_version >= 0x14) /* some NV15/16, and NV11+ */␊
522␉{␊
523␉␉char sig[8] = { 0 };␊
524␉␉␊
525␉␉strncpy(sig, (char *)&dcbtable[-7], 7);␊
526␉␉recordlength = 10;␊
527␉␉␊
528␉␉if (strcmp(sig, "DEV_REC"))␊
529␉␉{␊
530␉␉␉printf("Bad Display Configuration Block signature (%s)\n", sig);␊
531␉␉␉return PATCH_ROM_FAILED;␊
532␉␉}␊
533␉}␊
534␉else␊
535␉{␊
536␉␉printf("ERROR: dcbtable_version is 0x%X\n", dcbtable_version);␊
537␉␉return PATCH_ROM_FAILED;␊
538␉}␊
539␉␊
540␉if (numentries >= MAX_NUM_DCB_ENTRIES)␊
541␉␉numentries = MAX_NUM_DCB_ENTRIES;␊
542␉␊
543␉uint8_t num_outputs = 0, i = 0;␊
544␉␊
545␉struct dcbentry␊
546␉{␊
547␉␉uint8_t type;␊
548␉␉uint8_t index;␊
549␉␉uint8_t *heads;␊
550␉} entries[numentries];␊
551␉␊
552␉for (i = 0; i < numentries; i++)␊
553␉{␊
554␉␉uint32_t connection;␊
555␉␉connection = *(uint32_t *)&dcbtable[headerlength + recordlength * i];␊
556␉␉␊
557␉␉/* Should we allow discontinuous DCBs? Certainly DCB I2C tables can be discontinuous */␊
558␉␉if ((connection & 0x0000000f) == 0x0000000f) /* end of records */ ␊
559␉␉␉continue;␊
560␉␉if (connection == 0x00000000) /* seen on an NV11 with DCB v1.5 */ ␊
561␉␉␉continue;␊
562␉␉if ((connection & 0xf) == 0x6) /* we skip type 6 as it doesnt appear on macbook nvcaps */␊
563␉␉␉continue;␊
564␉␉␊
565␉␉entries[num_outputs].type = connection & 0xf;␊
566␉␉entries[num_outputs].index = num_outputs;␊
567␉␉entries[num_outputs++].heads = (uint8_t*)&(dcbtable[(headerlength + recordlength * i) + 1]);␊
568␉}␊
569␉␊
570␉int has_lvds = false;␊
571␉uint8_t channel1 = 0, channel2 = 0;␊
572␉␊
573␉for (i = 0; i < num_outputs; i++)␊
574␉{␊
575␉␉if (entries[i].type == 3)␊
576␉␉{␊
577␉␉␉has_lvds = true;␊
578␉␉␉//printf("found LVDS\n");␊
579␉␉␉channel1 |= ( 0x1 << entries[i].index);␊
580␉␉␉entries[i].type = TYPE_GROUPED;␊
581␉␉}␊
582␉}␊
583␉␊
584␉// if we have a LVDS output, we group the rest to the second channel␊
585␉if (has_lvds)␊
586␉{␊
587␉␉for (i = 0; i < num_outputs; i++)␊
588␉␉{␊
589␉␉␉if (entries[i].type == TYPE_GROUPED)␊
590␉␉␉␉continue;␊
591␉␉␉␊
592␉␉␉channel2 |= ( 0x1 << entries[i].index);␊
593␉␉␉entries[i].type = TYPE_GROUPED;␊
594␉␉}␊
595␉}␊
596␉else␊
597␉{␊
598␉␉int x;␊
599␉␉// we loop twice as we need to generate two channels␊
600␉␉for (x = 0; x <= 1; x++)␊
601␉␉{␊
602␉␉␉for (i=0; i<num_outputs; i++)␊
603␉␉␉{␊
604␉␉␉␉if (entries[i].type == TYPE_GROUPED)␊
605␉␉␉␉␉continue;␊
606␉␉␉␉// if type is TMDS, the prior output is ANALOG␊
607␉␉␉␉// we always group ANALOG and TMDS␊
608␉␉␉␉// if there is a TV output after TMDS, we group it to that channel as well␊
609␉␉␉␉if (i && entries[i].type == 0x2)␊
610␉␉␉␉{␊
611␉␉␉␉␉switch (x)␊
612␉␉␉␉␉{␊
613␉␉␉␉␉␉case 0:␊
614␉␉␉␉␉␉␉//printf("group channel 1\n");␊
615␉␉␉␉␉␉␉channel1 |= ( 0x1 << entries[i].index);␊
616␉␉␉␉␉␉␉entries[i].type = TYPE_GROUPED;␊
617␉␉␉␉␉␉␉␊
618␉␉␉␉␉␉␉if ((entries[i-1].type == 0x0))␊
619␉␉␉␉␉␉␉{␊
620␉␉␉␉␉␉␉␉channel1 |= ( 0x1 << entries[i-1].index);␊
621␉␉␉␉␉␉␉␉entries[i-1].type = TYPE_GROUPED;␊
622␉␉␉␉␉␉␉}␊
623␉␉␉␉␉␉␉// group TV as well if there is one␊
624␉␉␉␉␉␉␉if ( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) )␊
625␉␉␉␉␉␉␉{␊
626␉␉␉␉␉␉␉␉//␉printf("group tv1\n");␊
627␉␉␉␉␉␉␉␉channel1 |= ( 0x1 << entries[i+1].index);␊
628␉␉␉␉␉␉␉␉entries[i+1].type = TYPE_GROUPED;␊
629␉␉␉␉␉␉␉}␊
630␉␉␉␉␉␉␉break;␊
631␉␉␉␉␉␉␊
632␉␉␉␉␉␉case 1:␊
633␉␉␉␉␉␉␉//printf("group channel 2 : %d\n", i);␊
634␉␉␉␉␉␉␉channel2 |= ( 0x1 << entries[i].index);␊
635␉␉␉␉␉␉␉entries[i].type = TYPE_GROUPED;␊
636␉␉␉␉␉␉␉␊
637␉␉␉␉␉␉␉if ((entries[i - 1].type == 0x0))␊
638␉␉␉␉␉␉␉{␊
639␉␉␉␉␉␉␉␉channel2 |= ( 0x1 << entries[i-1].index);␊
640␉␉␉␉␉␉␉␉entries[i-1].type = TYPE_GROUPED;␊
641␉␉␉␉␉␉␉}␊
642␉␉␉␉␉␉␉// group TV as well if there is one␊
643␉␉␉␉␉␉␉if ( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) )␊
644␉␉␉␉␉␉␉{␊
645␉␉␉␉␉␉␉␉//␉printf("group tv2\n");␊
646␉␉␉␉␉␉␉␉channel2 |= ( 0x1 << entries[i+1].index);␊
647␉␉␉␉␉␉␉␉entries[i+1].type = TYPE_GROUPED;␊
648␉␉␉␉␉␉␉}␊
649␉␉␉␉␉␉␉break;␊
650␉␉␉␉␉}␊
651␉␉␉␉␉break;␊
652␉␉␉␉}␊
653␉␉␉}␊
654␉␉}␊
655␉}␊
656␉␊
657␉// if we have left ungrouped outputs merge them to the empty channel␊
658␉uint8_t *togroup;// = (channel1 ? (channel2 ? NULL : &channel2) : &channel1);␊
659␉togroup = &channel2;␊
660␉␊
661␉for (i = 0; i < num_outputs; i++)␊
662␉{␊
663␉␉if (entries[i].type != TYPE_GROUPED)␊
664␉␉{␊
665␉␉␉//printf("%d not grouped\n", i);␊
666␉␉␉if (togroup)␊
667␉␉␉{␊
668␉␉␉␉*togroup |= ( 0x1 << entries[i].index);␊
669␉␉␉}␊
670␉␉␉entries[i].type = TYPE_GROUPED;␊
671␉␉}␊
672␉}␊
673␉␊
674␉if (channel1 > channel2)␊
675␉{␊
676␉␉uint8_t buff = channel1;␊
677␉␉channel1 = channel2;␊
678␉␉channel2 = buff;␊
679␉}␊
680␉␊
681␉default_NVCAP[6] = channel1;␊
682␉default_NVCAP[8] = channel2;␊
683␉␊
684␉// patching HEADS␊
685␉for (i = 0; i < num_outputs; i++)␊
686␉{␊
687␉␉if (channel1 & (1 << i))␊
688␉␉{␊
689␉␉␉*entries[i].heads = 1;␊
690␉␉}␊
691␉␉else if(channel2 & (1 << i))␊
692␉␉{␊
693␉␉␉*entries[i].heads = 2;␊
694␉␉}␊
695␉}␊
696␉return (has_lvds ? PATCH_ROM_SUCCESS_HAS_LVDS : PATCH_ROM_SUCCESS);␊
697}␊
698␊
699static char *get_nvidia_model(uint32_t id)␊
700{␊
701␉int i;␊
702␉␊
703␉for (i = 1; i < (sizeof(NVKnownChipsets) / sizeof(NVKnownChipsets[0])); i++) {␊
704␉␉if (NVKnownChipsets[i].device == id)␊
705␉␉{␊
706␉␉␉return NVKnownChipsets[i].name;␊
707␉␉}␊
708␉}␊
709␉return NVKnownChipsets[0].name;␊
710}␊
711␊
712static uint32_t load_nvidia_bios_file(const char *filename, uint8_t *buf, int bufsize)␊
713{␊
714␉int fd;␊
715␉int size;␊
716␉␊
717␉if ((fd = open_bvdev("bt(0,0)", filename, 0)) < 0)␊
718␉{␊
719␉␉return 0;␊
720␉}␊
721␉␊
722␉size = file_size(fd);␊
723␉␊
724␉if (size > bufsize)␊
725␉{␊
726␉␉printf("Filesize of %s is bigger than expected! Truncating to 0x%x Bytes!\n",␊
727␉␉␉␉filename, bufsize);␊
728␉␉size = bufsize;␊
729␉}␊
730␉size = read(fd, (char *)buf, size);␊
731␉close(fd);␊
732␉␊
733␉return size > 0 ? size : 0;␊
734}␊
735␊
736static int devprop_add_nvidia_template(struct DevPropDevice *device)␊
737{␊
738␉char tmp[16];␊
739␉␊
740␉if (!device)␊
741␉␉return 0;␊
742␉␊
743␉if (!DP_ADD_TEMP_VAL(device, nvidia_compatible_0))␊
744␉␉return 0;␊
745␉if (!DP_ADD_TEMP_VAL(device, nvidia_device_type_0))␊
746␉␉return 0;␊
747␉if (!DP_ADD_TEMP_VAL(device, nvidia_name_0))␊
748␉␉return 0;␊
749␉if (!DP_ADD_TEMP_VAL(device, nvidia_compatible_1))␊
750␉␉return 0;␊
751␉if (!DP_ADD_TEMP_VAL(device, nvidia_device_type_1))␊
752␉␉return 0;␊
753␉if (!DP_ADD_TEMP_VAL(device, nvidia_name_1))␊
754␉␉return 0;␊
755␉if (!DP_ADD_TEMP_VAL(device, nvidia_device_type))␊
756␉␉return 0;␊
757␉␊
758␉// Rek : Dont use sprintf return, it does not WORK !! our custom sprintf() always return 0!␊
759␉// len = sprintf(tmp, "Slot-%x", devices_number);␊
760␉sprintf(tmp, "Slot-%x",devices_number);␊
761␉devprop_add_value(device, "AAPL,slot-name", (uint8_t *) tmp, strlen(tmp));␊
762␉devices_number++;␊
763␉␊
764␉return 1;␊
765}␊
766␊
767int hex2bin(const char *hex, uint8_t *bin, int len)␊
768{␊
769␉char␉*p;␊
770␉int␉␉i;␊
771␉char␉buf[3];␊
772␉␊
773␉if (hex == NULL || bin == NULL || len <= 0 || strlen(hex) != len * 2) {␊
774␉␉printf("[ERROR] bin2hex input error\n");␊
775␉␉return -1;␊
776␉}␊
777␉␊
778␉buf[2] = '\0';␊
779␉p = (char *) hex;␊
780␉␊
781␉for (i = 0; i < len; i++)␊
782␉{␊
783␉␉if (p[0] == '\0' || p[1] == '\0' || !isxdigit(p[0]) || !isxdigit(p[1])) {␊
784␉␉␉printf("[ERROR] bin2hex '%s' syntax error\n", hex);␊
785␉␉␉return -2;␊
786␉␉}␊
787␉␉buf[0] = *p++;␊
788␉␉buf[1] = *p++;␊
789␉␉bin[i] = (unsigned char) strtoul(buf, NULL, 16);␊
790␉}␊
791␉return 0;␊
792}␊
793␊
794unsigned long long mem_detect(volatile uint8_t *regs, uint8_t nvCardType, pci_dt_t *nvda_dev)␊
795{␊
796␉unsigned long long vram_size = 0;␊
797␉␊
798␉if (nvCardType < NV_ARCH_50)␊
799␉{␊
800␉␉vram_size = REG32(NV04_PFB_FIFO_DATA);␊
801␉␉vram_size &= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK;␊
802␉}␊
803␉else if (nvCardType < NV_ARCH_C0)␊
804␉{␊
805␉␉vram_size = REG32(NV04_PFB_FIFO_DATA);␊
806␉␉vram_size |= (vram_size & 0xff) << 32;␊
807␉␉vram_size &= 0xffffffff00ll;␊
808␉}␊
809␉else // >= NV_ARCH_C0␊
810␉{␊
811␉␉vram_size = REG32(NVC0_MEM_CTRLR_RAM_AMOUNT) << 20;␊
812␉␉vram_size *= REG32(NVC0_MEM_CTRLR_COUNT);␊
813␉}␊
814␉␊
815␉return vram_size;␊
816}␊
817␊
818bool setup_nvidia_devprop(pci_dt_t *nvda_dev)␊
819{␊
820␉struct DevPropDevice␉*device;␊
821␉char␉␉␉␉␉*devicepath;␊
822␉option_rom_pci_header_t *rom_pci_header;␊
823␉volatile uint8_t␉␉*regs;␊
824␉uint8_t␉␉␉␉␉*rom;␊
825␉uint8_t␉␉␉␉␉*nvRom;␊
826␉uint8_t␉␉␉␉␉nvCardType;␊
827␉unsigned long long␉␉videoRam;␊
828␉uint32_t␉␉␉␉nvBiosOveride;␊
829␉uint32_t␉␉␉␉bar[7];␊
830␉uint32_t␉␉␉␉boot_display;␊
831␉int␉␉␉␉␉␉nvPatch;␊
832␉int␉␉␉␉␉␉len;␊
833␉char␉␉␉␉␉biosVersion[32];␊
834␉char␉␉␉␉␉nvFilename[32];␊
835␉char␉␉␉␉␉kNVCAP[12];␊
836␉char␉␉␉␉␉*model;␊
837␉const char␉␉␉␉*value;␊
838␉bool␉␉␉␉␉doit;␊
839␉␊
840␉devicepath = get_pci_dev_path(nvda_dev);␊
841␉bar[0] = pci_config_read32(nvda_dev->dev.addr, 0x10 );␊
842␉regs = (uint8_t *) (bar[0] & ~0x0f);␊
843␉␊
844␉// get card type␊
845␉nvCardType = (REG32(0) >> 20) & 0x1ff;␊
846␉␊
847␉// Amount of VRAM in kilobytes␊
848␉videoRam = mem_detect(regs, nvCardType, nvda_dev);␊
849␉model = get_nvidia_model((nvda_dev->vendor_id << 16) | nvda_dev->device_id);␊
850␉␊
851␉verbose("nVidia %s %dMB NV%02x [%04x:%04x] :: %s\n",␊
852␉␉␉model, (uint32_t)(videoRam / 1024 / 1024),␊
853␉␉␉(REG32(0) >> 20) & 0x1ff, nvda_dev->vendor_id, nvda_dev->device_id,␊
854␉␉␉devicepath);␊
855␉␊
856␉rom = malloc(NVIDIA_ROM_SIZE);␊
857␉sprintf(nvFilename, "/Extra/%04x_%04x.rom", (uint16_t)nvda_dev->vendor_id,␊
858␉␉␉(uint16_t)nvda_dev->device_id);␊
859␉␊
860␉if (getBoolForKey(kUseNvidiaROM, &doit, &bootInfo->bootConfig) && doit)␊
861␉{␊
862␉␉verbose("Looking for nvidia video bios file %s\n", nvFilename);␊
863␉␉nvBiosOveride = load_nvidia_bios_file(nvFilename, rom, NVIDIA_ROM_SIZE);␊
864␉␉␊
865␉␉if (nvBiosOveride > 0)␊
866␉␉{␊
867␉␉␉verbose("Using nVidia Video BIOS File %s (%d Bytes)\n", nvFilename, nvBiosOveride);␊
868␉␉␉DBG("%s Signature 0x%02x%02x %d bytes\n", nvFilename, rom[0], rom[1], nvBiosOveride);␊
869␉␉}␊
870␉␉else␊
871␉␉{␊
872␉␉␉printf("ERROR: unable to open nVidia Video BIOS File %s\n", nvFilename);␊
873␉␉␉return false;␊
874␉␉}␊
875␉}␊
876␉else␊
877␉{␊
878␉␉// Otherwise read bios from card␊
879␉␉nvBiosOveride = 0;␊
880␉␉␊
881␉␉// TODO: we should really check for the signature before copying the rom, i think.␊
882␉␉␊
883␉␉// PRAMIN first␊
884␉␉nvRom = (uint8_t*)&regs[NV_PRAMIN_OFFSET];␊
885␉␉bcopy((uint32_t *)nvRom, rom, NVIDIA_ROM_SIZE);␊
886␉␉␊
887␉␉// Valid Signature ?␊
888␉␉if (rom[0] != 0x55 && rom[1] != 0xaa)␊
889␉␉{␊
890␉␉␉// PROM next␊
891␉␉␉// Enable PROM access␊
892␉␉␉(REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED;␊
893␉␉␉␊
894␉␉␉nvRom = (uint8_t*)&regs[NV_PROM_OFFSET];␊
895␉␉␉bcopy((uint8_t *)nvRom, rom, NVIDIA_ROM_SIZE);␊
896␉␉␉␊
897␉␉␉// disable PROM access␊
898␉␉␉(REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED;␊
899␉␉␉␊
900␉␉␉// Valid Signature ?␊
901␉␉␉if (rom[0] != 0x55 && rom[1] != 0xaa)␊
902␉␉␉{␊
903␉␉␉␉// 0xC0000 last␊
904␉␉␉␉bcopy((char *)0xc0000, rom, NVIDIA_ROM_SIZE);␊
905␉␉␉␉␊
906␉␉␉␉// Valid Signature ?␊
907␉␉␉␉if (rom[0] != 0x55 && rom[1] != 0xaa)␊
908␉␉␉␉{␊
909␉␉␉␉␉printf("ERROR: Unable to locate nVidia Video BIOS\n");␊
910␉␉␉␉␉return false;␊
911␉␉␉␉}␊
912␉␉␉␉else␊
913␉␉␉␉{␊
914␉␉␉␉␉DBG("ROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);␊
915␉␉␉␉}␊
916␉␉␉}␊
917␉␉␉else␊
918␉␉␉{␊
919␉␉␉␉DBG("PROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);␊
920␉␉␉}␊
921␉␉}␊
922␉␉else␊
923␉␉{␊
924␉␉␉DBG("PRAM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);␊
925␉␉}␊
926␉}␊
927␉␊
928␉if ((nvPatch = patch_nvidia_rom(rom)) == PATCH_ROM_FAILED) {␊
929␉␉printf("ERROR: nVidia ROM Patching Failed!\n");␊
930␉␉//return false;␊
931␉}␊
932␉␊
933␉rom_pci_header = (option_rom_pci_header_t*)(rom + *(uint16_t *)&rom[24]);␊
934␉␊
935␉// check for 'PCIR' sig␊
936␉if (rom_pci_header->signature == 0x50434952)␊
937␉{␊
938␉␉if (rom_pci_header->device_id != nvda_dev->device_id)␊
939␉␉{␊
940␉␉␉// Get Model from the OpROM␊
941␉␉␉model = get_nvidia_model((rom_pci_header->vendor_id << 16) | rom_pci_header->device_id);␊
942␉␉}␊
943␉␉else␊
944␉␉{␊
945␉␉␉printf("nVidia incorrect PCI ROM signature: 0x%x\n", rom_pci_header->signature);␊
946␉␉}␊
947␉}␊
948␉␊
949␉if (!string) {␊
950␉␉string = devprop_create_string();␊
951␉}␊
952␉device = devprop_add_device(string, devicepath);␊
953␉␊
954␉/* FIXME: for primary graphics card only */␊
955␉boot_display = 1;␊
956␉devprop_add_value(device, "@0,AAPL,boot-display", (uint8_t*)&boot_display, 4);␊
957␉␊
958␉if (nvPatch == PATCH_ROM_SUCCESS_HAS_LVDS) {␊
959␉␉uint8_t built_in = 0x01;␊
960␉␉devprop_add_value(device, "@0,built-in", &built_in, 1);␊
961␉}␊
962␉␊
963␉// get bios version␊
964␉const int MAX_BIOS_VERSION_LENGTH = 32;␊
965␉char* version_str = (char*)malloc(MAX_BIOS_VERSION_LENGTH);␊
966␉␊
967␉memset(version_str, 0, MAX_BIOS_VERSION_LENGTH);␊
968␉␊
969␉int i, version_start;␊
970␉int crlf_count = 0;␊
971␉␊
972␉// only search the first 384 bytes␊
973␉for (i = 0; i < 0x180; i++)␊
974␉{␊
975␉␉if (rom[i] == 0x0D && rom[i+1] == 0x0A)␊
976␉␉{␊
977␉␉␉crlf_count++;␊
978␉␉␉// second 0x0D0A was found, extract bios version␊
979␉␉␉if (crlf_count == 2)␊
980␉␉␉{␊
981␉␉␉␉if (rom[i-1] == 0x20) i--; // strip last " "␊
982␉␉␉␉{␊
983␉␉␉␉␉for (version_start = i; version_start > (i-MAX_BIOS_VERSION_LENGTH); version_start--)␊
984␉␉␉␉␉{␊
985␉␉␉␉␉␉// find start␊
986␉␉␉␉␉␉if (rom[version_start] == 0x00)␊
987␉␉␉␉␉␉{␊
988␉␉␉␉␉␉␉version_start++;␊
989␉␉␉␉␉␉␉␊
990␉␉␉␉␉␉␉// strip "Version "␊
991␉␉␉␉␉␉␉if (strncmp((const char*)rom+version_start, "Version ", 8) == 0)␊
992␉␉␉␉␉␉␉{␊
993␉␉␉␉␉␉␉␉version_start += 8;␊
994␉␉␉␉␉␉␉}␊
995␉␉␉␉␉␉␉strncpy(version_str, (const char*)rom+version_start, i-version_start);␊
996␉␉␉␉␉␉␉␊
997␉␉␉␉␉␉␉break;␊
998␉␉␉␉␉␉}␊
999␉␉␉␉␉}␊
1000␉␉␉␉}␊
1001␉␉␉␉break; //Azi: reminder␊
1002␉␉␉}␊
1003␉␉}␊
1004␉}␊
1005␉␊
1006␉sprintf(biosVersion, "%s", (nvBiosOveride > 0) ? nvFilename : version_str);␊
1007␉sprintf(kNVCAP, "NVCAP_%04x", nvda_dev->device_id);␊
1008␉␊
1009␉if (getValueForKey(kNVCAP, &value, &len, &bootInfo->bootConfig) && len == NVCAP_LEN * 2)␊
1010␉{␊
1011␉␉uint8_t new_NVCAP[NVCAP_LEN];␊
1012␉␉␊
1013␉␉if (hex2bin(value, new_NVCAP, NVCAP_LEN) == 0)␊
1014␉␉{␊
1015␉␉␉verbose("Using user supplied NVCAP for %s :: %s\n", model, devicepath);␊
1016␉␉␉memcpy(default_NVCAP, new_NVCAP, NVCAP_LEN);␊
1017␉␉}␊
1018␉}␊
1019␉␊
1020#if DEBUG_NVCAP␊
1021␉printf("NVCAP: %02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x\n",␊
1022␉default_NVCAP[0], default_NVCAP[1], default_NVCAP[2], default_NVCAP[3],␊
1023␉default_NVCAP[4], default_NVCAP[5], default_NVCAP[6], default_NVCAP[7],␊
1024␉default_NVCAP[8], default_NVCAP[9], default_NVCAP[10], default_NVCAP[11],␊
1025␉default_NVCAP[12], default_NVCAP[13], default_NVCAP[14], default_NVCAP[15],␊
1026␉default_NVCAP[16], default_NVCAP[17], default_NVCAP[18], default_NVCAP[19]);␊
1027#endif␊
1028␉␊
1029␉devprop_add_nvidia_template(device);␊
1030␉devprop_add_value(device, "NVCAP", default_NVCAP, NVCAP_LEN);␊
1031␉devprop_add_value(device, "VRAM,totalsize", (uint8_t*)&videoRam, 4);␊
1032␉devprop_add_value(device, "model", (uint8_t*)model, strlen(model) + 1);␊
1033␉devprop_add_value(device, "rom-revision", (uint8_t*)biosVersion, strlen(biosVersion) + 1);␊
1034␉␊
1035␉if (getBoolForKey(kVBIOS, &doit, &bootInfo->bootConfig) && doit)␊
1036␉{␊
1037␉␉devprop_add_value(device, "vbios", rom, (nvBiosOveride > 0) ? nvBiosOveride : (rom[2] * 512));␊
1038␉}␊
1039␉␊
1040␉stringdata = malloc(sizeof(uint8_t) * string->length);␊
1041␉memcpy(stringdata, (uint8_t*)devprop_generate_string(string), string->length);␊
1042␉stringlength = string->length;␊
1043␉␊
1044␉return true;␊
1045}␊
1046

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