| 1 | /*␊ |
| 2 | * Copyright 2008 Islam Ahmed Zaid. All rights reserved. <azismed@gmail.com>␊ |
| 3 | * AsereBLN: 2009: cleanup and bugfix␊ |
| 4 | */␊ |
| 5 | ␊ |
| 6 | #ifndef __LIBSAIO_CPU_H␊ |
| 7 | #define __LIBSAIO_CPU_H␊ |
| 8 | ␊ |
| 9 | #include "libsaio.h"␊ |
| 10 | ␊ |
| 11 | extern void scan_cpu(PlatformInfo_t *);␊ |
| 12 | ␊ |
| 13 | #define bit(n)␉␉␉(1UL << (n))␊ |
| 14 | #define bitmask(h,l)␉␉((bit(h)|(bit(h)-1)) & ~(bit(l)-1))␊ |
| 15 | #define bitfield(x,h,l)␉␉(((x) & bitmask(h,l)) >> l)␊ |
| 16 | ␊ |
| 17 | #define CPU_STRING_UNKNOWN␉␉"Unknown CPU Type"␊ |
| 18 | ␊ |
| 19 | #define␉MSR_IA32_PERF_STATUS␉0x198␊ |
| 20 | #define MSR_IA32_PERF_CONTROL␉0x199␊ |
| 21 | #define MSR_IA32_EXT_CONFIG␉␉0x00EE␊ |
| 22 | #define MSR_FLEX_RATIO␉␉␉0x194␊ |
| 23 | #define MSR_TURBO_RATIO_LIMIT␉0x1AD␊ |
| 24 | #define␉MSR_PLATFORM_INFO␉␉0xCE␊ |
| 25 | #define MSR_CORE_THREAD_COUNT␉0x35␉␉␉// Undocumented␊ |
| 26 | ␊ |
| 27 | #define K8_FIDVID_STATUS␉␉0xC0010042␊ |
| 28 | #define K10_COFVID_STATUS␉␉0xC0010071␊ |
| 29 | ␊ |
| 30 | #define DEFAULT_FSB␉␉100000 /* for now, hardcoding 100MHz for old CPUs */␊ |
| 31 | ␊ |
| 32 | // DFE: This constant comes from older xnu:␊ |
| 33 | #define CLKNUM␉␉␉1193182␉␉/* formerly 1193167 */␊ |
| 34 | ␊ |
| 35 | // DFE: These two constants come from Linux except CLOCK_TICK_RATE replaced with CLKNUM␊ |
| 36 | #define CALIBRATE_TIME_MSEC␉30␉␉/* 30 msecs */␊ |
| 37 | #define CALIBRATE_LATCH␉␉((CLKNUM * CALIBRATE_TIME_MSEC + 1000/2)/1000)␊ |
| 38 | ␊ |
| 39 | // CPUID Values␊ |
| 40 | #define CPUID_MODEL_YONAH␉␉14␉// Intel Mobile Core Solo, Duo␊ |
| 41 | #define CPUID_MODEL_MEROM␉␉15␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊ |
| 42 | #define CPUID_MODEL_PENRYN␉␉23␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊ |
| 43 | #define CPUID_MODEL_NEHALEM␉␉26␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊ |
| 44 | #define CPUID_MODEL_ATOM␉␉28␉// Intel Atom (45nm)␊ |
| 45 | #define CPUID_MODEL_FIELDS␉␉30␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊ |
| 46 | #define CPUID_MODEL_DALES␉␉31␉// Havendale, Auburndale␊ |
| 47 | #define CPUID_MODEL_NEHALEM_EX␉46␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x␊ |
| 48 | #define CPUID_MODEL_DALES_32NM␉37␉// Intel Core i3, i5 LGA1156 (32nm)␊ |
| 49 | #define CPUID_MODEL_WESTMERE␉44␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊ |
| 50 | #define CPUID_MODEL_WESTMERE_EX␉47␉// Intel Xeon E7␊ |
| 51 | ␊ |
| 52 | ␊ |
| 53 | static inline uint64_t rdtsc64(void)␊ |
| 54 | {␊ |
| 55 | ␉uint64_t ret;␊ |
| 56 | ␉__asm__ volatile("rdtsc" : "=A" (ret));␊ |
| 57 | ␉return ret;␊ |
| 58 | }␊ |
| 59 | ␊ |
| 60 | static inline uint64_t rdmsr64(uint32_t msr)␊ |
| 61 | {␊ |
| 62 | uint64_t ret;␊ |
| 63 | __asm__ volatile("rdmsr" : "=A" (ret) : "c" (msr));␊ |
| 64 | return ret;␊ |
| 65 | }␊ |
| 66 | ␊ |
| 67 | static inline void wrmsr64(uint32_t msr, uint64_t val)␊ |
| 68 | {␊ |
| 69 | ␉__asm__ volatile("wrmsr" : : "c" (msr), "A" (val));␊ |
| 70 | }␊ |
| 71 | ␊ |
| 72 | static inline void intel_waitforsts(void) {␊ |
| 73 | ␉uint32_t inline_timeout = 100000;␊ |
| 74 | ␉while (rdmsr64(MSR_IA32_PERF_STATUS) & (1 << 21)) { if (!inline_timeout--) break; }␊ |
| 75 | }␊ |
| 76 | ␊ |
| 77 | static inline void do_cpuid(uint32_t selector, uint32_t *data)␊ |
| 78 | {␊ |
| 79 | ␉asm volatile ("cpuid"␊ |
| 80 | ␉␉␉␉ : "=a" (data[0]),␊ |
| 81 | ␉␉␉␉ "=b" (data[1]),␊ |
| 82 | ␉␉␉␉ "=c" (data[2]),␊ |
| 83 | ␉␉␉␉ "=d" (data[3])␊ |
| 84 | ␉␉␉␉ : "a" (selector));␊ |
| 85 | }␊ |
| 86 | ␊ |
| 87 | static inline void do_cpuid2(uint32_t selector, uint32_t selector2, uint32_t *data)␊ |
| 88 | {␊ |
| 89 | ␉asm volatile ("cpuid"␊ |
| 90 | ␉␉␉␉ : "=a" (data[0]),␊ |
| 91 | ␉␉␉␉ "=b" (data[1]),␊ |
| 92 | ␉␉␉␉ "=c" (data[2]),␊ |
| 93 | ␉␉␉␉ "=d" (data[3])␊ |
| 94 | ␉␉␉␉ : "a" (selector), "c" (selector2));␊ |
| 95 | }␊ |
| 96 | ␊ |
| 97 | // DFE: enable_PIT2 and disable_PIT2 come from older xnu␊ |
| 98 | ␊ |
| 99 | /*␊ |
| 100 | * Enable or disable timer 2.␊ |
| 101 | * Port 0x61 controls timer 2:␊ |
| 102 | * bit 0 gates the clock,␊ |
| 103 | * bit 1 gates output to speaker.␊ |
| 104 | */␊ |
| 105 | static inline void enable_PIT2(void)␊ |
| 106 | {␊ |
| 107 | /* Enable gate, disable speaker */␊ |
| 108 | __asm__ volatile(␊ |
| 109 | ␉␉␉␉␉ " inb $0x61,%%al \n\t"␊ |
| 110 | ␉␉␉␉␉ " and $0xFC,%%al \n\t" /* & ~0x03 */␊ |
| 111 | ␉␉␉␉␉ " or $1,%%al \n\t"␊ |
| 112 | ␉␉␉␉␉ " outb %%al,$0x61 \n\t"␊ |
| 113 | ␉␉␉␉␉ : : : "%al" );␊ |
| 114 | }␊ |
| 115 | ␊ |
| 116 | static inline void disable_PIT2(void)␊ |
| 117 | {␊ |
| 118 | /* Disable gate and output to speaker */␊ |
| 119 | __asm__ volatile(␊ |
| 120 | ␉␉␉␉␉ " inb $0x61,%%al \n\t"␊ |
| 121 | ␉␉␉␉␉ " and $0xFC,%%al \n\t"␉/* & ~0x03 */␊ |
| 122 | ␉␉␉␉␉ " outb %%al,$0x61 \n\t"␊ |
| 123 | ␉␉␉␉␉ : : : "%al" );␊ |
| 124 | }␊ |
| 125 | ␊ |
| 126 | // DFE: set_PIT2_mode0, poll_PIT2_gate, and measure_tsc_frequency are␊ |
| 127 | // roughly based on Linux code␊ |
| 128 | ␊ |
| 129 | /* Set the 8254 channel 2 to mode 0 with the specified value.␊ |
| 130 | In mode 0, the counter will initially set its gate low when the␊ |
| 131 | timer expires. For this to be useful, you ought to set it high␊ |
| 132 | before calling this function. The enable_PIT2 function does this.␊ |
| 133 | */␊ |
| 134 | static inline void set_PIT2_mode0(uint16_t value)␊ |
| 135 | {␊ |
| 136 | __asm__ volatile(␊ |
| 137 | ␉␉␉␉␉ " movb $0xB0,%%al \n\t"␊ |
| 138 | ␉␉␉␉␉ " outb␉%%al,$0x43␉\n\t"␊ |
| 139 | ␉␉␉␉␉ " movb␉%%dl,%%al␉\n\t"␊ |
| 140 | ␉␉␉␉␉ " outb␉%%al,$0x42␉\n\t"␊ |
| 141 | ␉␉␉␉␉ " movb␉%%dh,%%al␉\n\t"␊ |
| 142 | ␉␉␉␉␉ " outb␉%%al,$0x42"␊ |
| 143 | ␉␉␉␉␉ : : "d"(value) /*: no clobber */ );␊ |
| 144 | }␊ |
| 145 | ␊ |
| 146 | /* Returns the number of times the loop ran before the PIT2 signaled */␊ |
| 147 | static inline unsigned long poll_PIT2_gate(void)␊ |
| 148 | {␊ |
| 149 | unsigned long count = 0;␊ |
| 150 | unsigned char nmi_sc_val;␊ |
| 151 | do {␊ |
| 152 | ++count;␊ |
| 153 | __asm__ volatile(␊ |
| 154 | ␉␉␉␉␉␉ "inb␉$0x61,%0"␊ |
| 155 | ␉␉␉␉␉␉ : "=q"(nmi_sc_val) /*:*/ /* no input */ /*:*/ /* no clobber */);␊ |
| 156 | } while( (nmi_sc_val & 0x20) == 0);␊ |
| 157 | return count;␊ |
| 158 | }␊ |
| 159 | ␊ |
| 160 | #endif /* !__LIBSAIO_CPU_H */␊ |
| 161 | |
