Chameleon

Chameleon Svn Source Tree

Root/trunk/i386/libsaio/spd.c

1/*␊
2 * spd.c - serial presence detect memory information␊
3 * (restored from pcefi10.5)␊
4 */␊
5␊
6#include "libsaio.h"␊
7#include "pci.h"␊
8#include "platform.h"␊
9#include "spd.h"␊
10#include "saio_internal.h"␊
11#include "bootstruct.h"␊
12#include "memvendors.h"␊
13␊
14#ifndef DEBUG_SPD␊
15#define DEBUG_SPD 0␊
16#endif␊
17␊
18#if DEBUG_SPD␊
19#define DBG(x...)␉printf(x)␊
20#else␊
21#define DBG(x...)␊
22#endif␊
23␊
24static const char *spd_memory_types[] =␊
25{␊
26␉"RAM", /* 00h Undefined */␊
27␉"FPM", /* 01h FPM */␊
28␉"EDO", /* 02h EDO */␊
29␉"",␉␉␉␉/* 03h PIPELINE NIBBLE */␊
30␉"SDRAM", /* 04h SDRAM */␊
31␉"",␉␉␉␉/* 05h MULTIPLEXED ROM */␊
32␉"DDR SGRAM",␉/* 06h SGRAM DDR */␊
33␉"DDR SDRAM",␉/* 07h SDRAM DDR */␊
34␉"DDR2 SDRAM", /* 08h SDRAM DDR 2 */␊
35␉"",␉␉␉␉/* 09h Undefined */␊
36␉"",␉␉␉␉/* 0Ah Undefined */␊
37␉"DDR3 SDRAM" /* 0Bh SDRAM DDR 3 */␊
38};␊
39␊
40#define UNKNOWN_MEM_TYPE 2␊
41static uint8_t spd_mem_to_smbios[] =␊
42{␊
43␉UNKNOWN_MEM_TYPE, /* 00h Undefined */␊
44␉UNKNOWN_MEM_TYPE, /* 01h FPM */␊
45␉UNKNOWN_MEM_TYPE, /* 02h EDO */␊
46␉UNKNOWN_MEM_TYPE,␉ /* 03h PIPELINE NIBBLE */␊
47␉SMB_MEM_TYPE_SDRAM, /* 04h SDRAM */␊
48␉SMB_MEM_TYPE_ROM,␉ /* 05h MULTIPLEXED ROM */␊
49␉SMB_MEM_TYPE_SGRAM, /* 06h SGRAM DDR */␊
50␉SMB_MEM_TYPE_DDR, /* 07h SDRAM DDR */␊
51␉SMB_MEM_TYPE_DDR2, /* 08h SDRAM DDR 2 */␊
52␉UNKNOWN_MEM_TYPE, ␉ /* 09h Undefined */␊
53␉UNKNOWN_MEM_TYPE,␉ /* 0Ah Undefined */␊
54␉SMB_MEM_TYPE_DDR3 /* 0Bh SDRAM DDR 3 */␊
55};␊
56#define SPD_TO_SMBIOS_SIZE (sizeof(spd_mem_to_smbios)/sizeof(uint8_t))␊
57␊
58#define rdtsc(low,high) \␊
59__asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high))␊
60␊
61#define SMBHSTSTS 0␊
62#define SMBHSTCNT 2␊
63#define SMBHSTCMD 3␊
64#define SMBHSTADD 4␊
65#define SMBHSTDAT 5␊
66␊
67/** Get Vendor Name from spd, 2 cases handled DDR3 and DDR2, have different formats.*/␊
68const char * getVendorName(const char * spd)␊
69{␊
70 uint8_t code;␊
71 int i;␊
72 uint8_t bank=0;␊
73␊
74 if (spd[2]==0x0b) { // DDR3␊
75 bank = spd[0x75];␊
76 code = spd[0x76];␊
77 for (i=0; i < VEN_MAP_SIZE; i++)␊
78 if (bank==vendorMap[i].bank && code==vendorMap[i].code)␊
79 return vendorMap[i].name;␊
80 }␊
81 else if (spd[2]==0x08 || spd[2]==0x07) { // DDR2 or DDR␊
82 if(spd[0x40]==0x7f) {␊
83 for (i=0x40; i<0x48 && spd[i]==0x7f;i++) bank++;␊
84 code = spd[i];␊
85 } else {␊
86 code = spd[0x40]; ␊
87 bank = 0;␊
88 }␊
89 for (i=0; i < VEN_MAP_SIZE; i++)␊
90 if (bank==vendorMap[i].bank && code==vendorMap[i].code)␊
91 return vendorMap[i].name;␊
92 }␊
93␊
94 return "NoName";␊
95}␊
96␊
97/** Get Default Memory Module Speed (no overclocking handled) */␊
98int getDDRspeedMhz(const char * spd)␊
99{␊
100 if (spd[2]==0x0b) { // DDR3␊
101 switch(spd[12]) {␊
102 case 0x0f:␊
103 return 1066;␊
104 case 0x0c:␊
105 return 1333;␊
106 case 0x0a:␊
107 return 1600;␊
108 case 0x14:␊
109 default:␊
110 return 800;␊
111 }␊
112 } ␊
113 else if (spd[2]==0x08) { // DDR2␊
114 switch(spd[9]) {␊
115 case 0x50:␊
116 return 400;␊
117 case 0x3d:␊
118 return 533;␊
119 case 0x30:␊
120 return 667;␊
121 case 0x25:␊
122 default:␊
123 return 800;␊
124 }␊
125 }␊
126 return 800; // default freq for unknown types␊
127}␊
128␊
129#define UIS(a) ((uint32_t)spd[a])␊
130␊
131/** Get DDR3 or DDR2 serial number, 0 most of the times */␊
132uint32_t getDDRSerial(const char* spd)␊
133{␊
134 uint32_t ret=0;␊
135␊
136 if (spd[2]==0x0b) // DDR3␊
137 // assume it is lsb to msb␊
138 ret = UIS(122) | (UIS(123)<<8) | (UIS(124)<<16) | (UIS(125)<<24);␊
139 else if (spd[2]==0x08 || spd[2]==0x07) // DDR2 or DDR␊
140 ret = UIS(95) | (UIS(96)<<8) | (UIS(97)<<16) | (UIS(98)<<24);␊
141 return ret;␊
142}␊
143␊
144/** Get DDR3 or DDR2 Part Number */␊
145const char * getDDRPartNum(const char* spd)␊
146{␊
147 if (spd[2]==0x0b) // DDR3␊
148 return &spd[128];␊
149 else if (spd[2]==0x08 || spd[2]==0x07) // DDR2 or DDR␊
150 return &spd[73];␊
151 return "N/A";␊
152}␊
153␊
154/** Read one byte from the intel i2c, used for reading SPD on intel chipsets only. */␊
155unsigned char smb_read_byte_intel(uint32_t base, uint8_t adr, uint8_t cmd)␊
156{␊
157␉int l1, h1, l2, h2;␊
158 unsigned long long t;␊
159␉␊
160 outb(base + SMBHSTSTS, 0x1f);␉␉␉␉␉// reset SMBus Controller␊
161 outb(base + SMBHSTDAT, 0xff);␊
162␉␊
163 while( inb(base + SMBHSTSTS) & 0x01);␉␉␉// wait until ready␊
164␉␊
165 outb(base + SMBHSTCMD, cmd);␊
166 outb(base + SMBHSTADD, (adr << 1) | 0x01 );␊
167 outb(base + SMBHSTCNT, 0x48 );␊
168␉␊
169 rdtsc(l1, h1);␊
170␉␊
171 ␉while (!( inb(base + SMBHSTSTS) & 0x02))␉␉// wait til command finished␊
172␉{␉␊
173␉␉rdtsc(l2, h2);␊
174␉␉t = ((h2 - h1) * 0xffffffff + (l2 - l1)) / (Platform.CPU.TSCFrequency / 40);␊
175␉␉if (t > 10)␊
176␉␉␉break;␉␉␉␉␉␉␉␉␉// break after 10ms␊
177 }␊
178 return inb(base + SMBHSTDAT);␊
179}␊
180␊
181int mapping []= {0,1,2,3,4,5}; // RAM_SLOT_ENUMERATOR;␊
182␊
183/** Read from smbus the SPD content and interpret it for detecting memory attributes */␊
184static void read_smb_intel(pci_dt_t *smbus_dev)␊
185{ ␊
186 static int serialnum=0;␊
187 int i, x, ser;␊
188 uint8_t␉␉spd_size, spd_type;␊
189 uint32_t␉base;␊
190 bool dump = false;␊
191 RamSlotInfo_t* slot;␊
192␊
193 base = pci_config_read16(smbus_dev->dev.addr, 0x20) & 0xFFFE;␊
194 DBG("Scanning smbus_dev <%04x, %04x> ...\n",smbus_dev->vendor_id, smbus_dev->device_id);␊
195␊
196 getBoolForKey("DumpSPD", &dump, &bootInfo->bootConfig);␊
197␊
198 // Search MAX_RAM_SLOTS slots␊
199 for (i = 0; i < MAX_RAM_SLOTS; i++){␊
200 slot = &Platform.RAM.DIMM[i];␊
201 Platform.DMI.DIMM[i]=mapping[i]; // for now no special mapping␊
202 spd_size = smb_read_byte_intel(base, 0x50 + i, 0);␊
203 ␊
204 // Check spd is present␊
205 if (spd_size && spd_size != 0xff)␊
206 {␊
207 slot->InUse = true;␊
208 ␊
209 slot->spd = malloc(spd_size);␊
210 if (slot->spd) {␊
211 bzero(slot->spd, spd_size);␊
212 ␊
213 // Copy spd data into buffer␊
214 for (x = 0; x < spd_size; x++)␊
215 slot->spd[x] = smb_read_byte_intel(base, 0x50 + i, x);␊
216 ␊
217 switch (slot->spd[SPD_MEMORY_TYPE]) {␊
218 case SPD_MEMORY_TYPE_SDRAM_DDR2:␊
219 ␊
220 slot->ModuleSize = ((1 << (slot->spd[SPD_NUM_ROWS] & 0x0f) + (slot->spd[SPD_NUM_COLUMNS] & 0x0f) - 17) * ␊
221 ((slot->spd[SPD_NUM_DIMM_BANKS] & 0x7) + 1) * slot->spd[SPD_NUM_BANKS_PER_SDRAM]);␊
222 break;␊
223 ␊
224 case SPD_MEMORY_TYPE_SDRAM_DDR3:␊
225 ␊
226 slot->ModuleSize = ((slot->spd[4] & 0x0f) + 28 ) + ((slot->spd[8] & 0x7) + 3 );␊
227 slot->ModuleSize -= (slot->spd[7] & 0x7) + 25;␊
228 slot->ModuleSize = ((1 << slot->ModuleSize) * (((slot->spd[7] >> 3) & 0x1f) + 1));␊
229 ␊
230 break;␊
231 }␊
232 }␊
233 ␊
234 spd_type = (slot->spd[SPD_MEMORY_TYPE] < ((char) 12) ? slot->spd[SPD_MEMORY_TYPE] : 0);␊
235 slot->Type = spd_mem_to_smbios[spd_type];␊
236 strncpy(slot->PartNo, getDDRPartNum(slot->spd), 64);␊
237 strncpy(slot->Vendor, getVendorName(slot->spd), 64);␊
238␊
239 ser = getDDRSerial(slot->spd);␊
240 if (ser==0) {␊
241 sprintf(slot->SerialNo, "10000000%d", serialnum);␊
242 serialnum++;␊
243 }␊
244 else␊
245 sprintf(slot->SerialNo, "%d", ser);␊
246 // determine speed␊
247 slot->Frequency = getDDRspeedMhz(slot->spd);␊
248 if(dump) {␊
249 printf("Slot %d Type %d %dMB (%s) %dMHz Vendor=%s, PartNo=%s SerialNo=%s\n", ␊
250 i, ␊
251 (int)slot->Type,␊
252 slot->ModuleSize, ␊
253 spd_memory_types[spd_type],␊
254 slot->Frequency,␊
255 slot->Vendor,␊
256 slot->PartNo,␊
257 slot->SerialNo); ␊
258 dumpPhysAddr("spd content: ",slot->spd, spd_size);␊
259 getc();␊
260 }␊
261 }␊
262 }␊
263#if DEBUG_SPD␊
264 printf("Press a key to continue\n");␊
265 getc();␊
266#endif␊
267}␊
268␊
269static struct smbus_controllers_t smbus_controllers[] = {␊
270␊
271␉{0x8086, 0x269B, "ESB2", read_smb_intel },␊
272␉{0x8086, 0x25A4, "6300ESB", read_smb_intel },␊
273␉{0x8086, 0x24C3, "ICH4", read_smb_intel },␊
274␉{0x8086, 0x24D3, "ICH5", read_smb_intel },␊
275␉{0x8086, 0x266A, "ICH6", read_smb_intel },␊
276␉{0x8086, 0x27DA, "ICH7", read_smb_intel },␊
277␉{0x8086, 0x283E, "ICH8", read_smb_intel },␊
278␉{0x8086, 0x2930, "ICH9", read_smb_intel },␉␊
279␉{0x8086, 0x3A30, "ICH10R", read_smb_intel },␊
280␉{0x8086, 0x3A60, "ICH10B", read_smb_intel },␊
281␉{0x8086, 0x3B30, "P55", read_smb_intel },␊
282␉{0x8086, 0x5032, "EP80579", read_smb_intel }␊
283␊
284};␊
285␊
286void scan_smbus_controller(pci_dt_t *smbus_dev)␊
287{␊
288␉int␉i;␊
289␊
290␉for( i = 1; i < sizeof(smbus_controllers) / sizeof(smbus_controllers[0]); i++ )␊
291␉␉if (( smbus_controllers[i].vendor == smbus_dev->vendor_id) ␊
292␉␉␉&& ( smbus_controllers[i].device == smbus_dev->device_id))␊
293␉␉{␊
294␉␉␉verbose("%s%s SMBus Controller [%4x:%4x] at %02x:%02x.%x\n", ␊
295␉␉␉␉ (smbus_dev->vendor_id == 0x8086) ? "Intel(R) " : "",␊
296␉␉␉␉ smbus_controllers[i].name,␊
297␉␉␉␉ smbus_dev->vendor_id, smbus_dev->device_id,␊
298␉␉␉␉ smbus_dev->dev.bits.bus, smbus_dev->dev.bits.dev, smbus_dev->dev.bits.func);␊
299␉␉␉␊
300␉␉␉smbus_controllers[i].read_smb(smbus_dev);␊
301␉␉␉␊
302␉␉}␊
303␉␊
304}␊
305␊
306// initial call : pci_dt = root_pci_dev;␊
307// find_and_read_smbus_controller(root_pci_dev);␊
308bool find_and_read_smbus_controller(pci_dt_t* pci_dt)␊
309{␊
310 pci_dt_t␉*current = pci_dt;␊
311 int i;␊
312␊
313 while (current) {␊
314#if DEBUG_SPD␊
315 printf("%02x:%02x.%x [%04x] [%04x:%04x] :: %s\n", ␊
316 current->dev.bits.bus, current->dev.bits.dev, current->dev.bits.func, ␊
317 current->class_id, current->vendor_id, current->device_id, ␊
318 get_pci_dev_path(current));␊
319#endif␊
320␉for ( i = 0; i < sizeof(smbus_controllers) / sizeof(smbus_controllers[0]); i++ )␊
321 {␊
322 if (current->vendor_id == smbus_controllers[i].vendor &&␊
323 current->device_id == smbus_controllers[i].device)␊
324 {␊
325 smbus_controllers[i].read_smb(current); // read smb␊
326 return true;␊
327 } ␊
328 }␊
329 find_and_read_smbus_controller(current->children);␊
330 current = current->next;␊
331 }␊
332 return false; // not found␊
333}␊
334␊
335void scan_spd(PlatformInfo_t *p)␊
336{␊
337 find_and_read_smbus_controller(root_pci_dev);␊
338}␊
339

Archive Download this file

Revision: 97