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1/*␊
2 * Copyright 2008 Islam Ahmed Zaid. All rights reserved. <azismed@gmail.com>␊
3 * AsereBLN: 2009: cleanup and bugfix␊
4 */␊
5␊
6//#include "libsaio.h"␊
7#include "platform.h"␊
8#include "cpu.h"␊
9#include "boot.h"␊
10␊
11#ifndef DEBUG_CPU␊
12#define DEBUG_CPU 0␊
13#endif␊
14␊
15#if DEBUG_CPU␊
16#define DBG(x...)␉␉printf(x)␊
17#else␊
18#define DBG(x...)␉␉msglog(x)␊
19#endif␊
20␊
21/*␊
22 * DFE: Measures the TSC frequency in Hz (64-bit) using the ACPI PM timer␊
23 */␊
24static uint64_t measure_tsc_frequency(void)␊
25{␊
26 uint64_t tscStart;␊
27 uint64_t tscEnd;␊
28 uint64_t tscDelta = 0xffffffffffffffffULL;␊
29 unsigned long pollCount;␊
30 uint64_t retval = 0;␊
31 int i;␊
32␊
33 /* Time how many TSC ticks elapse in 30 msec using the 8254 PIT␊
34 * counter 2. We run this loop 3 times to make sure the cache␊
35 * is hot and we take the minimum delta from all of the runs.␊
36 * That is to say that we're biased towards measuring the minimum␊
37 * number of TSC ticks that occur while waiting for the timer to␊
38 * expire. That theoretically helps avoid inconsistencies when␊
39 * running under a VM if the TSC is not virtualized and the host␊
40 * steals time. The TSC is normally virtualized for VMware.␊
41 */␊
42 for(i = 0; i < 10; ++i)␊
43 {␊
44 enable_PIT2();␊
45 set_PIT2_mode0(CALIBRATE_LATCH);␊
46 tscStart = rdtsc64();␊
47 pollCount = poll_PIT2_gate();␊
48 tscEnd = rdtsc64();␊
49 /* The poll loop must have run at least a few times for accuracy */␊
50 if(pollCount <= 1)␊
51 continue;␊
52 /* The TSC must increment at LEAST once every millisecond. We␊
53 * should have waited exactly 30 msec so the TSC delta should␊
54 * be >= 30. Anything less and the processor is way too slow.␊
55 */␊
56 if((tscEnd - tscStart) <= CALIBRATE_TIME_MSEC)␊
57 continue;␊
58 // tscDelta = MIN(tscDelta, (tscEnd - tscStart))␊
59 if( (tscEnd - tscStart) < tscDelta )␊
60 tscDelta = tscEnd - tscStart;␊
61 }␊
62 /* tscDelta is now the least number of TSC ticks the processor made in␊
63 * a timespan of 0.03 s (e.g. 30 milliseconds)␊
64 * Linux thus divides by 30 which gives the answer in kiloHertz because␊
65 * 1 / ms = kHz. But we're xnu and most of the rest of the code uses␊
66 * Hz so we need to convert our milliseconds to seconds. Since we're␊
67 * dividing by the milliseconds, we simply multiply by 1000.␊
68 */␊
69␊
70 /* Unlike linux, we're not limited to 32-bit, but we do need to take care␊
71 * that we're going to multiply by 1000 first so we do need at least some␊
72 * arithmetic headroom. For now, 32-bit should be enough.␊
73 * Also unlike Linux, our compiler can do 64-bit integer arithmetic.␊
74 */␊
75 if(tscDelta > (1ULL<<32))␊
76 retval = 0;␊
77 else␊
78 {␊
79 retval = tscDelta * 1000 / 30;␊
80 }␊
81 disable_PIT2();␊
82 return retval;␊
83}␊
84␊
85/*␊
86 * Calculates the FSB and CPU frequencies using specific MSRs for each CPU␊
87 * - multi. is read from a specific MSR. In the case of Intel, there is:␊
88 * a max multi. (used to calculate the FSB freq.),␊
89 * and a current multi. (used to calculate the CPU freq.)␊
90 * - fsbFrequency = tscFrequency / multi␊
91 * - cpuFrequency = fsbFrequency * multi␊
92 */␊
93␊
94void scan_cpu(PlatformInfo_t *p)␊
95{␊
96␉const char *newratio;␊
97␉int␉␉␉len, myfsb;␊
98␉uint8_t␉␉maxcoef, maxdiv, currcoef, bus_ratio_max, bus_ratio_min, currdiv;␊
99␉uint32_t␉max_ratio, min_ratio;␊
100␉uint64_t␉tscFrequency, fsbFrequency, cpuFrequency, msr, flex_ratio;␊
101␊
102␉max_ratio = min_ratio = myfsb = bus_ratio_min = 0;␊
103␉maxcoef = maxdiv = bus_ratio_max = currcoef = currdiv = 0;␊
104␊
105␉/* get cpuid values */␊
106␉do_cpuid(0x00000000, p->CPU.CPUID[CPUID_0]);␊
107␉do_cpuid(0x00000001, p->CPU.CPUID[CPUID_1]);␊
108␉do_cpuid(0x00000002, p->CPU.CPUID[CPUID_2]);␊
109␉do_cpuid(0x00000003, p->CPU.CPUID[CPUID_3]);␊
110␉do_cpuid2(0x00000004, 0, p->CPU.CPUID[CPUID_4]);␊
111␉do_cpuid(0x80000000, p->CPU.CPUID[CPUID_80]);␊
112␉if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 1) {␊
113␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊
114␉}␊
115#if DEBUG_CPU␊
116␉{␊
117␉␉int␉␉i;␊
118␉␉printf("CPUID Raw Values:\n");␊
119␉␉for (i=0; i<CPUID_MAX; i++) {␊
120␉␉␉printf("%02d: %08x-%08x-%08x-%08x\n", i,␊
121␉␉␉␉p->CPU.CPUID[i][0], p->CPU.CPUID[i][1],␊
122␉␉␉␉p->CPU.CPUID[i][2], p->CPU.CPUID[i][3]);␊
123␉␉}␊
124␉}␊
125#endif␊
126␉p->CPU.Vendor␉␉= p->CPU.CPUID[CPUID_0][1];␊
127␉p->CPU.Signature␉= p->CPU.CPUID[CPUID_1][0];␊
128␉p->CPU.Stepping␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 3, 0);␊
129␉p->CPU.Model␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 7, 4);␊
130␉p->CPU.Family␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 11, 8);␊
131␉p->CPU.ExtModel␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 19, 16);␊
132␉p->CPU.ExtFamily␉= bitfield(p->CPU.CPUID[CPUID_1][0], 27, 20);␊
133␉␊
134 p->CPU.Model += (p->CPU.ExtModel << 4);␊
135 ␊
136 if (p->CPU.Vendor == 0x756E6547 /* Intel */ && ␊
137 p->CPU.Family == 0x06 && ␊
138 p->CPU.Model >= CPUID_MODEL_NEHALEM && ␊
139 p->CPU.Model != CPUID_MODEL_ATOM // MSR is *NOT* available on the Intel Atom CPU␊
140 ){␊
141 msr = rdmsr64(MSR_CORE_THREAD_COUNT);␉␉␉␉␉␉␉␉␉// Undocumented MSR in Nehalem and newer CPUs␊
142 p->CPU.NoCores␉␉= bitfield((uint32_t)msr, 31, 16);␉␉␉␉␉// Using undocumented MSR to get actual values␊
143 p->CPU.NoThreads␉= bitfield((uint32_t)msr, 15, 0);␉␉␉␉␉// Using undocumented MSR to get actual values␊
144␉} else {␊
145 p->CPU.NoThreads␉= bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␉␉// Use previous method for Cores and Threads␊
146 p->CPU.NoCores␉␉= bitfield(p->CPU.CPUID[CPUID_4][0], 31, 26) + 1;␊
147␉}␊
148␉␊
149␉/* get brand string (if supported) */␊
150␉/* Copyright: from Apple's XNU cpuid.c */␊
151␉if (p->CPU.CPUID[CPUID_80][0] > 0x80000004) {␊
152␉␉uint32_t␉reg[4];␊
153 char str[128], *s;␊
154␉␉/*␊
155␉␉ * The brand string 48 bytes (max), guaranteed to␊
156␉␉ * be NULL terminated.␊
157␉␉ */␊
158␉␉do_cpuid(0x80000002, reg);␊
159␉␉bcopy((char *)reg, &str[0], 16);␊
160␉␉do_cpuid(0x80000003, reg);␊
161␉␉bcopy((char *)reg, &str[16], 16);␊
162␉␉do_cpuid(0x80000004, reg);␊
163␉␉bcopy((char *)reg, &str[32], 16);␊
164␉␉for (s = str; *s != '\0'; s++) {␊
165␉␉␉if (*s != ' ') break;␊
166␉␉}␊
167␉␉␊
168␉␉strlcpy(p->CPU.BrandString,␉s, sizeof(p->CPU.BrandString));␊
169␉␉␊
170␉␉if (!strncmp(p->CPU.BrandString, CPU_STRING_UNKNOWN, MIN(sizeof(p->CPU.BrandString), strlen(CPU_STRING_UNKNOWN) + 1))) {␊
171␉␉␉ /*␊
172␉␉␉ * This string means we have a firmware-programmable brand string,␊
173␉␉␉ * and the firmware couldn't figure out what sort of CPU we have.␊
174␉␉␉ */␊
175␉␉␉ p->CPU.BrandString[0] = '\0';␊
176␉␉ }␊
177␉}␊
178␉␊
179␉/* setup features */␊
180␉if ((bit(23) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
181␉␉p->CPU.Features |= CPU_FEATURE_MMX;␊
182␉}␊
183␉if ((bit(25) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
184␉␉p->CPU.Features |= CPU_FEATURE_SSE;␊
185␉}␊
186␉if ((bit(26) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
187␉␉p->CPU.Features |= CPU_FEATURE_SSE2;␊
188␉}␊
189␉if ((bit(0) & p->CPU.CPUID[CPUID_1][2]) != 0) {␊
190␉␉p->CPU.Features |= CPU_FEATURE_SSE3;␊
191␉}␊
192␉if ((bit(19) & p->CPU.CPUID[CPUID_1][2]) != 0) {␊
193␉␉p->CPU.Features |= CPU_FEATURE_SSE41;␊
194␉}␊
195␉if ((bit(20) & p->CPU.CPUID[CPUID_1][2]) != 0) {␊
196␉␉p->CPU.Features |= CPU_FEATURE_SSE42;␊
197␉}␊
198␉if ((bit(29) & p->CPU.CPUID[CPUID_81][3]) != 0) {␊
199␉␉p->CPU.Features |= CPU_FEATURE_EM64T;␊
200␉}␊
201␉if ((bit(5) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
202␉␉p->CPU.Features |= CPU_FEATURE_MSR;␊
203␉}␊
204␉//if ((bit(28) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
205␉if (p->CPU.NoThreads > p->CPU.NoCores) {␊
206␉␉p->CPU.Features |= CPU_FEATURE_HTT;␊
207␉}␊
208␊
209␉tscFrequency = measure_tsc_frequency();␊
210␉fsbFrequency = 0;␊
211␉cpuFrequency = 0;␊
212␊
213␉if ((p->CPU.Vendor == 0x756E6547 /* Intel */) && ((p->CPU.Family == 0x06) || (p->CPU.Family == 0x0f))) {␊
214␉␉int intelCPU = p->CPU.Model;␊
215␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) || (p->CPU.Family == 0x0f && p->CPU.Model >= 0x03)) {␊
216␉␉␉/* Nehalem CPU model */␊
217␉␉␉if (p->CPU.Family == 0x06 && (p->CPU.Model == CPU_MODEL_NEHALEM || ␊
218 p->CPU.Model == CPU_MODEL_FIELDS || ␊
219 p->CPU.Model == CPU_MODEL_DALES || ␊
220 p->CPU.Model == CPU_MODEL_DALES_32NM || ␊
221 p->CPU.Model == CPU_MODEL_WESTMERE ||␊
222 p->CPU.Model == CPU_MODEL_NEHALEM_EX ||␊
223 p->CPU.Model == CPU_MODEL_WESTMERE_EX ||␊
224 p->CPU.Model == CPU_MODEL_SANDY ||␊
225 p->CPU.Model == CPU_MODEL_SANDY_XEON)) {␊
226␉␉␉␉msr = rdmsr64(MSR_PLATFORM_INFO);␊
227␉␉␉␉DBG("msr(%d): platform_info %08x\n", __LINE__, msr & 0xffffffff);␊
228//kabyl␉␉␉␉DBG("MSR_PLATFORM_INFO (0xCE): 0x%08X%08X\n", (uint32_t)(msr >> 32), (uint32_t)msr);␊
229␉␉␉␉bus_ratio_max = (msr >> 8) & 0xff;␊
230␉␉␉␉bus_ratio_min = (msr >> 40) & 0xff; //valv: not sure about this one (Remarq.1)␊
231␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊
232␉␉␉␉DBG("msr(%d): flex_ratio %08x\n", __LINE__, msr & 0xffffffff);␊
233//kabyl␉␉␉␉DBG("MSR_FLEX_RATIO (0x194): 0x%08X%08X\n", (uint32_t)(msr >> 32), (uint32_t)msr);␊
234␉␉␉␉if ((msr >> 16) & 0x01) {␊
235␉␉␉␉␉flex_ratio = (msr >> 8) & 0xff;␊
236␉␉␉␉␉/* bcc9: at least on the gigabyte h67ma-ud2h,␊
237␉␉␉␉␉ where the cpu multipler can't be changed to␊
238␉␉␉␉␉ allow overclocking, the flex_ratio msr has unexpected (to OSX)␊
239␉␉␉␉␉ contents. These contents cause mach_kernel to␊
240␉␉␉␉␉ fail to compute the bus ratio correctly, instead␊
241␉␉␉␉␉ causing the system to crash since tscGranularity␊
242␉␉␉␉␉ is inadvertently set to 0.␊
243␉␉␉␉␉*/␊
244␉␉␉␉␉if (flex_ratio == 0) {␊
245␉␉␉␉␉␉/* Clear bit 16 (evidently the␊
246␉␉␉␉␉␉ presence bit) */␊
247␉␉␉␉␉␉wrmsr64(MSR_FLEX_RATIO, (msr & 0xFFFFFFFFFFFEFFFFULL));␊
248␉␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊
249␉␉␉␉␉␉verbose("Unusable flex ratio detected. Patched MSR now %08x\n", msr & 0xffffffff);␊
250␉␉␉␉␉} else {␊
251␉␉␉␉␉␉if (bus_ratio_max > flex_ratio) {␊
252␉␉␉␉␉␉␉bus_ratio_max = flex_ratio;␊
253␉␉␉␉␉␉}␊
254␉␉␉␉␉}␊
255␉␉␉␉}␊
256␊
257␉␉␉␉if (bus_ratio_max) {␊
258␉␉␉␉␉fsbFrequency = (tscFrequency / bus_ratio_max);␊
259␉␉␉␉}␊
260␉␉␉␉//valv: Turbo Ratio Limit␊
261␉␉␉␉if ((intelCPU != 0x2e) && (intelCPU != 0x2f)) {␊
262␉␉␉␉␉msr = rdmsr64(MSR_TURBO_RATIO_LIMIT);␊
263␉␉␉␉␉cpuFrequency = bus_ratio_max * fsbFrequency;␊
264␉␉␉␉␉max_ratio = bus_ratio_max * 10;␊
265␉␉␉␉} else {␊
266␉␉␉␉␉cpuFrequency = tscFrequency;␊
267␉␉␉␉}␊
268␉␉␉␉if ((getValueForKey(kBusRatioKey, &newratio, &len, &bootInfo->bootConfig)) && (len <= 4)) {␊
269␉␉␉␉␉max_ratio = atoi(newratio);␊
270␉␉␉␉␉max_ratio = (max_ratio * 10);␊
271␉␉␉␉␉if (len >= 3) max_ratio = (max_ratio + 5);␊
272␊
273␉␉␉␉␉verbose("Bus-Ratio: min=%d, max=%s\n", bus_ratio_min, newratio);␊
274␊
275␉␉␉␉␉// extreme overclockers may love 320 ;)␊
276␉␉␉␉␉if ((max_ratio >= min_ratio) && (max_ratio <= 320)) {␊
277␉␉␉␉␉␉cpuFrequency = (fsbFrequency * max_ratio) / 10;␊
278␉␉␉␉␉␉if (len >= 3) maxdiv = 1;␊
279␉␉␉␉␉␉else maxdiv = 0;␊
280␉␉␉␉␉} else {␊
281␉␉␉␉␉␉max_ratio = (bus_ratio_max * 10);␊
282␉␉␉␉␉}␊
283␉␉␉␉}␊
284␉␉␉␉//valv: to be uncommented if Remarq.1 didn't stick␊
285␉␉␉␉/*if(bus_ratio_max > 0) bus_ratio = flex_ratio;*/␊
286␉␉␉␉p->CPU.MaxRatio = max_ratio;␊
287␉␉␉␉p->CPU.MinRatio = min_ratio;␊
288␊
289␉␉␉␉myfsb = fsbFrequency / 1000000;␊
290␉␉␉␉verbose("Sticking with [BCLK: %dMhz, Bus-Ratio: %d]\n", myfsb, max_ratio);␊
291␉␉␉␉currcoef = bus_ratio_max;␊
292␉␉␉} else {␊
293␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_STATUS);␊
294//Azi: __FILE__ %d, __LINE__ %d, __FUNCTION__ %s␊
295//␉␉␉␉msglog("%s - %d\n", __FUNCTION__, __LINE__);␊
296␉␉␉␉DBG("msr(%d): ia32_perf_stat 0x%08x\n", __LINE__, msr & 0xffffffff);␊
297␉␉␉␉//Azi: 0x00000F2700000F27␊
298//kabyl␉␉␉␉DBG("MSR_IA32_PERF_STATUS (0x198): 0x%08X%08X\n", (uint32_t)(msr >> 32), (uint32_t)msr);␊
299␉␉␉␉currcoef = (msr >> 8) & 0x1f;␊
300␉␉␉␉/* Non-integer bus ratio for the max-multi*/␊
301␉␉␉␉maxdiv = (msr >> 46) & 0x01;␊
302␉␉␉␉/* Non-integer bus ratio for the current-multi (undocumented)*/␊
303␉␉␉␉currdiv = (msr >> 14) & 0x01;␊
304␊
305␉␉␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0e) || (p->CPU.Family == 0x0f)) // This will always be model >= 3␊
306␉␉␉␉{␊
307␉␉␉␉␉/* On these models, maxcoef defines TSC freq */␊
308␉␉␉␉␉maxcoef = (msr >> 40) & 0x1f;␊
309␉␉␉␉} else {␊
310␉␉␉␉␉/* On lower models, currcoef defines TSC freq */␊
311␉␉␉␉␉/* XXX */␊
312␉␉␉␉␉maxcoef = currcoef;␊
313␉␉␉␉}␊
314␊
315␉␉␉␉if (maxcoef) {␊
316␉␉␉␉␉if (maxdiv) {␊
317␉␉␉␉␉␉fsbFrequency = ((tscFrequency * 2) / ((maxcoef * 2) + 1));␊
318␉␉␉␉␉} else {␊
319␉␉␉␉␉␉fsbFrequency = (tscFrequency / maxcoef);␊
320␉␉␉␉␉}␊
321␉␉␉␉␉if (currdiv) {␊
322␉␉␉␉␉␉cpuFrequency = (fsbFrequency * ((currcoef * 2) + 1) / 2);␊
323␉␉␉␉␉} else {␊
324␉␉␉␉␉␉cpuFrequency = (fsbFrequency * currcoef);␊
325␉␉␉␉␉}␊
326␉␉␉␉␉DBG("max: %d%s current: %d%s\n", maxcoef, maxdiv ? ".5" : "",currcoef, currdiv ? ".5" : "");␊
327␉␉␉␉}␊
328␉␉␉}␊
329␉␉}␊
330␉␉/* Mobile CPU */␊
331␉␉if (rdmsr64(MSR_IA32_PLATFORM_ID) & (1<<28)) {␊
332␉␉␉p->CPU.Features |= CPU_FEATURE_MOBILE;␊
333␉␉}␊
334␉}␊
335#if 0␊
336␉else if((p->CPU.Vendor == 0x68747541 /* AMD */) && (p->CPU.Family == 0x0f)) {␊
337␉␉if(p->CPU.ExtFamily == 0x00 /* K8 */) {␊
338␉␉␉msr = rdmsr64(K8_FIDVID_STATUS);␊
339␉␉␉currcoef = (msr & 0x3f) / 2 + 4;␊
340␉␉␉currdiv = (msr & 0x01) * 2;␊
341␉␉} else if(p->CPU.ExtFamily >= 0x01 /* K10+ */) {␊
342␉␉␉msr = rdmsr64(K10_COFVID_STATUS);␊
343␉␉␉if(p->CPU.ExtFamily == 0x01 /* K10 */)␊
344␉␉␉␉currcoef = (msr & 0x3f) + 0x10;␊
345␉␉␉else /* K11+ */␊
346␉␉␉␉currcoef = (msr & 0x3f) + 0x08;␊
347␉␉␉currdiv = (2 << ((msr >> 6) & 0x07));␊
348␉␉}␊
349␊
350␉␉if (currcoef) {␊
351␉␉␉if (currdiv) {␊
352␉␉␉␉fsbFrequency = ((tscFrequency * currdiv) / currcoef);␊
353␉␉␉␉DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);␊
354␉␉␉} else {␊
355␉␉␉␉fsbFrequency = (tscFrequency / currcoef);␊
356␉␉␉␉DBG("%d\n", currcoef);␊
357␉␉␉}␊
358␉␉␉fsbFrequency = (tscFrequency / currcoef);␊
359␉␉␉cpuFrequency = tscFrequency;␊
360␉␉}␊
361␉}␊
362␊
363␉if (!fsbFrequency) {␊
364␉␉fsbFrequency = (DEFAULT_FSB * 1000);␊
365␉␉cpuFrequency = tscFrequency;␊
366␉␉DBG("0 ! using the default value for FSB !\n");␊
367␉}␊
368#endif␊
369␊
370␉p->CPU.MaxCoef = maxcoef;␊
371␉p->CPU.MaxDiv = maxdiv;␊
372␉p->CPU.CurrCoef = currcoef;␊
373␉p->CPU.CurrDiv = currdiv;␊
374␉p->CPU.TSCFrequency = tscFrequency;␊
375␉p->CPU.FSBFrequency = fsbFrequency;␊
376␉p->CPU.CPUFrequency = cpuFrequency;␊
377␊
378␉DBG("CPU: Brand String: %s\n",␉␉␉␉p->CPU.BrandString);␊
379␉DBG("CPU: Vendor/Family/ExtFamily: 0x%x/0x%x/0x%x\n",␉p->CPU.Vendor, p->CPU.Family, p->CPU.ExtFamily);␊
380␉DBG("CPU: Model/ExtModel/Stepping: 0x%x/0x%x/0x%x\n",␉p->CPU.Model, p->CPU.ExtModel, p->CPU.Stepping);␊
381␉DBG("CPU: MaxCoef/CurrCoef: 0x%x/0x%x\n",␉␉p->CPU.MaxCoef, p->CPU.CurrCoef);␊
382␉DBG("CPU: MaxDiv/CurrDiv: 0x%x/0x%x\n",␉␉p->CPU.MaxDiv, p->CPU.CurrDiv);␊
383␉DBG("CPU: TSCFreq: %dMHz\n",␉␉␉p->CPU.TSCFrequency / 1000000);␊
384␉DBG("CPU: FSBFreq: %dMHz\n",␉␉␉p->CPU.FSBFrequency / 1000000);␊
385␉DBG("CPU: CPUFreq: %dMHz\n",␉␉␉p->CPU.CPUFrequency / 1000000);␊
386␉DBG("CPU: NoCores/NoThreads: %d/%d\n",␉␉␉p->CPU.NoCores, p->CPU.NoThreads);␊
387␉DBG("CPU: Features: 0x%08x\n",␉␉␉p->CPU.Features);␊
388#if DEBUG_CPU␊
389␉pause();␊
390#endif␊
391}␊
392

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