Chameleon

Chameleon Svn Source Tree

Root/branches/azimutz/Chazi/i386/libsaio/cpu.h

1/*␊
2 * Copyright 2008 Islam Ahmed Zaid. All rights reserved. <azismed@gmail.com>␊
3 * AsereBLN: 2009: cleanup and bugfix␊
4 */␊
5␊
6#ifndef __LIBSAIO_CPU_H␊
7#define __LIBSAIO_CPU_H␊
8␊
9//#include "libsaio.h" - enabled on trunk␊
10␊
11extern void scan_cpu(PlatformInfo_t *);␊
12␊
13#define bit(n)␉␉␉(1UL << (n))␊
14#define bitmask(h,l)␉␉((bit(h)|(bit(h)-1)) & ~(bit(l)-1))␊
15#define bitfield(x,h,l)␉␉(((x) & bitmask(h,l)) >> l)␊
16␊
17#define CPU_STRING_UNKNOWN␉␉"Unknown CPU Type"␊
18␊
19#define␉MSR_IA32_PERF_STATUS␉0x198␊
20#define MSR_IA32_PERF_CONTROL␉0x199␊
21#define MSR_IA32_EXT_CONFIG␉␉0x00EE␊
22#define MSR_FLEX_RATIO␉␉␉0x194␊
23#define MSR_TURBO_RATIO_LIMIT␉0x1AD␊
24#define␉MSR_PLATFORM_INFO␉␉0xCE␊
25#define MSR_CORE_THREAD_COUNT␉0x35␉␉␉// Undocumented␊
26#define MSR_IA32_PLATFORM_ID␉0x17␊
27␊
28#define K8_FIDVID_STATUS␉␉0xC0010042␊
29#define K10_COFVID_STATUS␉␉0xC0010071␊
30␊
31//#define DEFAULT_FSB␉␉100000 // for now, hardcoding 100MHz for old CPUs - disabled␊
32␊
33// DFE: This constant comes from older xnu:␊
34#define CLKNUM␉␉␉1193182␉␉/* formerly 1193167 */␊
35␊
36// DFE: These two constants come from Linux except CLOCK_TICK_RATE replaced with CLKNUM␊
37#define CALIBRATE_TIME_MSEC␉30␉␉/* 30 msecs */␊
38#define CALIBRATE_LATCH␉␉((CLKNUM * CALIBRATE_TIME_MSEC + 1000/2)/1000)␊
39␊
40// CPUID Values␊
41#define CPUID_MODEL_YONAH␉␉14␉// Intel Mobile Core Solo, Duo␊
42#define CPUID_MODEL_MEROM␉␉15␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊
43#define CPUID_MODEL_PENRYN␉␉23␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊
44#define CPUID_MODEL_NEHALEM␉␉26␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
45#define CPUID_MODEL_ATOM␉␉28␉// Intel Atom (45nm)␊
46#define CPUID_MODEL_FIELDS␉␉30␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
47#define CPUID_MODEL_DALES␉␉31␉// Havendale, Auburndale␊
48#define CPUID_MODEL_DALES_32NM␉37␉// Intel Core i3, i5 LGA1156 (32nm)␊
49#define CPUID_MODEL_SANDY␉␉42␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊
50#define CPUID_MODEL_WESTMERE␉44␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
51#define CPUID_MODEL_NEHALEM_EX␉46␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x␊
52#define CPUID_MODEL_WESTMERE_EX␉47␉// Intel Xeon E7␊
53␊
54␊
55static inline uint64_t rdtsc64(void)␊
56{␊
57␉uint64_t ret;␊
58␉__asm__ volatile("rdtsc" : "=A" (ret));␊
59␉return ret;␊
60}␊
61␊
62static inline uint64_t rdmsr64(uint32_t msr)␊
63{␊
64 uint64_t ret;␊
65 __asm__ volatile("rdmsr" : "=A" (ret) : "c" (msr));␊
66 return ret;␊
67}␊
68␊
69static inline void wrmsr64(uint32_t msr, uint64_t val)␊
70{␊
71␉__asm__ volatile("wrmsr" : : "c" (msr), "A" (val));␊
72}␊
73␊
74static inline void intel_waitforsts(void) {␊
75␉uint32_t inline_timeout = 100000;␊
76␉while (rdmsr64(MSR_IA32_PERF_STATUS) & (1 << 21)) { if (!inline_timeout--) break; }␊
77}␊
78␊
79static inline void do_cpuid(uint32_t selector, uint32_t *data)␊
80{␊
81␉asm volatile ("cpuid"␊
82␉␉␉␉ : "=a" (data[0]),␊
83␉␉␉␉ "=b" (data[1]),␊
84␉␉␉␉ "=c" (data[2]),␊
85␉␉␉␉ "=d" (data[3])␊
86␉␉␉␉ : "a" (selector));␊
87}␊
88␊
89static inline void do_cpuid2(uint32_t selector, uint32_t selector2, uint32_t *data)␊
90{␊
91␉asm volatile ("cpuid"␊
92␉␉␉␉ : "=a" (data[0]),␊
93␉␉␉␉ "=b" (data[1]),␊
94␉␉␉␉ "=c" (data[2]),␊
95␉␉␉␉ "=d" (data[3])␊
96␉␉␉␉ : "a" (selector), "c" (selector2));␊
97}␊
98␊
99// DFE: enable_PIT2 and disable_PIT2 come from older xnu␊
100␊
101/*␊
102 * Enable or disable timer 2.␊
103 * Port 0x61 controls timer 2:␊
104 * bit 0 gates the clock,␊
105 * bit 1 gates output to speaker.␊
106 */␊
107static inline void enable_PIT2(void)␊
108{␊
109 /* Enable gate, disable speaker */␊
110 __asm__ volatile(␊
111␉␉␉␉␉ " inb $0x61,%%al \n\t"␊
112␉␉␉␉␉ " and $0xFC,%%al \n\t" /* & ~0x03 */␊
113␉␉␉␉␉ " or $1,%%al \n\t"␊
114␉␉␉␉␉ " outb %%al,$0x61 \n\t"␊
115␉␉␉␉␉ : : : "%al" );␊
116}␊
117␊
118static inline void disable_PIT2(void)␊
119{␊
120 /* Disable gate and output to speaker */␊
121 __asm__ volatile(␊
122␉␉␉␉␉ " inb $0x61,%%al \n\t"␊
123␉␉␉␉␉ " and $0xFC,%%al \n\t"␉/* & ~0x03 */␊
124␉␉␉␉␉ " outb %%al,$0x61 \n\t"␊
125␉␉␉␉␉ : : : "%al" );␊
126}␊
127␊
128// DFE: set_PIT2_mode0, poll_PIT2_gate, and measure_tsc_frequency are␊
129// roughly based on Linux code␊
130␊
131/* Set the 8254 channel 2 to mode 0 with the specified value.␊
132 In mode 0, the counter will initially set its gate low when the␊
133 timer expires. For this to be useful, you ought to set it high␊
134 before calling this function. The enable_PIT2 function does this.␊
135 */␊
136static inline void set_PIT2_mode0(uint16_t value)␊
137{␊
138 __asm__ volatile(␊
139␉␉␉␉␉ " movb $0xB0,%%al \n\t"␊
140␉␉␉␉␉ " outb␉%%al,$0x43␉\n\t"␊
141␉␉␉␉␉ " movb␉%%dl,%%al␉\n\t"␊
142␉␉␉␉␉ " outb␉%%al,$0x42␉\n\t"␊
143␉␉␉␉␉ " movb␉%%dh,%%al␉\n\t"␊
144␉␉␉␉␉ " outb␉%%al,$0x42"␊
145␉␉␉␉␉ : : "d"(value) /*: no clobber */ );␊
146}␊
147␊
148/* Returns the number of times the loop ran before the PIT2 signaled */␊
149static inline unsigned long poll_PIT2_gate(void)␊
150{␊
151 unsigned long count = 0;␊
152 unsigned char nmi_sc_val;␊
153 do {␊
154 ++count;␊
155 __asm__ volatile(␊
156␉␉␉␉␉␉ "inb␉$0x61,%0"␊
157␉␉␉␉␉␉ : "=q"(nmi_sc_val) /*:*/ /* no input */ /*:*/ /* no clobber */);␊
158 } while( (nmi_sc_val & 0x20) == 0);␊
159 return count;␊
160}␊
161␊
162#endif /* !__LIBSAIO_CPU_H */␊
163

Archive Download this file

Revision: 980