Chameleon Applications

Chameleon Applications Commit Details

Date:2011-06-07 03:32:37 (9 years 4 months ago)
Author:ErmaC
Commit:310
Parents: 309
Message:Some update and directory changes.
Changes:
R/branches/iFabio/Chameleon/i386/modules/NVIDIAGraphicsEnabler → /branches/iFabio/Chameleon/i386/modules/GraphicsEnabler/NVIDIAGraphicsEnabler
R/branches/iFabio/Chameleon/i386/modules/IntelGraphicsEnabler → /branches/iFabio/Chameleon/i386/modules/GraphicsEnabler/IntelGraphicsEnabler
R/branches/iFabio/Chameleon/i386/modules/AMDGraphicsEnabler → /branches/iFabio/Chameleon/i386/modules/GraphicsEnabler/AMDGraphicsEnabler
R/branches/iFabio/Chameleon/i386/modules/ATiGraphicsEnabler → /branches/iFabio/Chameleon/i386/modules/GraphicsEnabler/ATiGraphicsEnabler
A/branches/iFabio/Chameleon/i386/modules/GraphicsEnabler
M/branches/iFabio/Chameleon/i386/libsaio/smbios.c
M/branches/iFabio/Chameleon/i386/boot2/options.c
M/branches/iFabio/Chameleon/i386/libsaio/xml.c
M/branches/iFabio/Chameleon/doc/BootHelp.txt
M/branches/iFabio/Chameleon/Make.rules
M/branches/iFabio/Chameleon/i386/libsaio/ati.c
M/branches/iFabio/Chameleon/i386/modules/Cconfig
M/branches/iFabio/Chameleon/i386/modules/Makefile
M/branches/iFabio/Chameleon/i386/modules/Resolution/Makefile
M/branches/iFabio/Chameleon/i386/libsaio/spd.c
M/branches/iFabio/Chameleon/package/builddmg
M/branches/iFabio/Chameleon/i386/libsaio/cpu.c
M/branches/iFabio/Chameleon/i386/libsaio/smbios_getters.c
M/branches/iFabio/Chameleon/i386/modules/Resolution/915resolution.c
M/branches/iFabio/Chameleon/i386/libsaio/cpu.h
M/branches/iFabio/Chameleon/i386/modules/Resolution/edid.c
M/branches/iFabio/Chameleon/package/buildpkg
M/branches/iFabio/Chameleon/i386/modules/Resolution/915resolution.h
M/branches/iFabio/Chameleon/package/slimpkg
M/branches/iFabio/Chameleon/TODO
M/branches/iFabio/Chameleon/i386/boot2/modules.c
M/branches/iFabio/Chameleon/i386/boot2/boot.h
M/branches/iFabio/Chameleon/i386/libsaio/pci.h
M/branches/iFabio/Chameleon/i386/boot2/modules.h
M/branches/iFabio/Chameleon/i386/libsaio/acpi_patcher.c
M/branches/iFabio/Chameleon/i386/libsaio/platform.c
M/branches/iFabio/Chameleon/i386/modules/Resolution/include/edid.h
M/branches/iFabio/Chameleon/i386/boot2/gui.c
M/branches/iFabio/Chameleon/i386/modules/MakeInc.dir
M/branches/iFabio/Chameleon/i386/libsaio/platform.h

File differences

branches/iFabio/Chameleon/i386/libsaio/xml.c
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};
#define USEMALLOC 1
#define DOFREE 1
static long ParseTagList(char *buffer, TagPtr *tag, long type, long empty);
branches/iFabio/Chameleon/i386/libsaio/acpi_patcher.c
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{
switch (Platform.CPU.Model)
{
case 0x0D: // ?
case CPU_MODEL_YONAH: // Yonah
case CPU_MODEL_MEROM: // Merom
case CPU_MODEL_PENRYN: // Penryn
case CPU_MODEL_ATOM: // Intel Atom (45nm)
case 0x0D:// ???
case CPU_MODEL_YONAH:// Intel Mobile Core Solo, Duo
case CPU_MODEL_MEROM:// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx
case CPU_MODEL_PENRYN:// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx
case CPU_MODEL_ATOM:// Intel Atom (45nm)
{
bool cpu_dynamic_fsb = false;
break;
}
case CPU_MODEL_FIELDS:
case CPU_MODEL_DALES:
case CPU_MODEL_DALES_32NM:
case CPU_MODEL_NEHALEM:
case CPU_MODEL_NEHALEM_EX:
case CPU_MODEL_WESTMERE:
case CPU_MODEL_WESTMERE_EX:
case CPU_MODEL_SANDY:
case CPU_MODEL_SANDY_XEON:
case CPU_MODEL_FIELDS:// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)
case CPU_MODEL_DALES:
case CPU_MODEL_DALES_32NM:// Intel Core i3, i5 LGA1156 (32nm)
case CPU_MODEL_NEHALEM:// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)
case CPU_MODEL_NEHALEM_EX:// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x
case CPU_MODEL_WESTMERE:// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core
case CPU_MODEL_WESTMERE_EX:// Intel Xeon E7
case CPU_MODEL_SANDY:// Intel Core i3, i5, i7 LGA1155 (32nm)
case CPU_MODEL_SANDY_XEON:// Intel Xeon E3
{
maximum.Control = rdmsr64(MSR_IA32_PERF_STATUS) & 0xff; // Seems it always contains maximum multiplier value (with turbo, that's we need)...
minimum.Control = (rdmsr64(MSR_PLATFORM_INFO) >> 40) & 0xff;
branches/iFabio/Chameleon/i386/libsaio/spd.c
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outb(base + SMBHSTDAT, 0xff);
rdtsc(l1, h1);
while ( inb(base + SMBHSTSTS) & 0x01) // wait until ready
while ( inb(base + SMBHSTSTS) & 0x01) // wait until read
{
rdtsc(l2, h2);
t = ((h2 - h1) * 0xffffffff + (l2 - l1)) / (Platform.CPU.TSCFrequency / 100);
slot->SerialNo);
#if DEBUG_SPD
// prevously located on mem.c; temporarily on platform.c now
dumpPhysAddr("spd content: ", slot->spd, spd_size);
getchar();
getc();
#endif
}
branches/iFabio/Chameleon/i386/libsaio/ati.c
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{ 0x6738,0x67381002,CHIP_FAMILY_BARTS,"AMD Radeon HD 6870",kDuckweed},
{ 0x6739,0x67391002,CHIP_FAMILY_BARTS,"AMD Radeon HD 6850",kDuckweed},
{ 0x6739,0x21F81458,CHIP_FAMILY_BARTS,"AMD Radeon HD 6850",kDuckweed},
{ 0x6759,0xE193174B,CHIP_FAMILY_TURKS,"AMD Radeon HD 6570",kNull},
{ 0x68F9,0x00000000,CHIP_FAMILY_CEDAR,"ATI Radeon HD 5400 Series",kNull},
{ 0x6718,0x00000000,CHIP_FAMILY_CAYMAN,"AMD Radeon HD 6900 Series",kNull},
/* Northen Islands */
{ 0x6718,0x00000000,CHIP_FAMILY_CAYMAN,"AMD Radeon HD 6970 Series",kNull},
/* Northen Islands */
{ 0x6758,0x00000000,CHIP_FAMILY_TURKS,"AMD Radeon HD 6670",kNull},
{ 0x6738,0x00000000,CHIP_FAMILY_BARTS,"AMD Radeon HD 6870 Series",kDuckweed},
{ 0x6739,0x00000000,CHIP_FAMILY_BARTS,"AMD Radeon HD 6850 Series",kDuckweed},
{ 0x673E,0x00000000,CHIP_FAMILY_BARTS,"AMD Radeon HD 6790 Series",kNull},
{ 0x6758,0x00000000,CHIP_FAMILY_TURKS,"AMD Radeon HD 6670 Series",kNull},
{ 0x6759,0x00000000,CHIP_FAMILY_TURKS,"AMD Radeon HD 6500 Series",kNull},
{ 0x6770,0x00000000,CHIP_FAMILY_CAICOS,"AMD Radeon HD 6400 Series",kNull},
{ 0x6779,0x00000000,CHIP_FAMILY_CAICOS,"AMD Radeon HD 6450 Series",kNull},
{ 0x68F9,0x00000000,CHIP_FAMILY_CEDAR,"ATI Radeon HD 5400 Series",kNull},
{ 0x0000,0x00000000,CHIP_FAMILY_UNKNOW,NULL,kNull}
};
else
{
if (devprop_list[i].default_val.type != kNul)
devprop_add_value(card->device, devprop_list[i].name,
devprop_list[i].default_val.type == kCst ?
(uint8_t *)&(devprop_list[i].default_val.data) : devprop_list[i].default_val.data,
devprop_add_value(card->device, devprop_list[i].name,
devprop_list[i].default_val.type == kCst ?
(uint8_t *)&(devprop_list[i].default_val.data) : devprop_list[i].default_val.data,
devprop_list[i].default_val.size);
if (devprop_list[i].all_ports)
if (devprop_list[i].default_val.type != kNul)
{
devprop_list[i].name[1] = 0x30 + pnum; // convert to ascii
devprop_add_value(card->device, devprop_list[i].name,
devprop_list[i].default_val.type == kCst ?
(uint8_t *)&(devprop_list[i].default_val.data) : devprop_list[i].default_val.data,
devprop_add_value(card->device, devprop_list[i].name,
devprop_list[i].default_val.type == kCst ?
(uint8_t *)&(devprop_list[i].default_val.data) : devprop_list[i].default_val.data,
devprop_list[i].default_val.size);
}
}
card->mmio= (uint8_t *)(pci_config_read32(pci_dev->dev.addr, PCI_BASE_ADDRESS_2) & ~0x0f);
card->io= (uint8_t *)(pci_config_read32(pci_dev->dev.addr, PCI_BASE_ADDRESS_4) & ~0x03);
verbose("Framebuffer @0x%08X MMIO @0x%08X I/O Port @0x%08X ROM Addr @0x%08X\n",
verbose("Framebuffer @0x%08X MMIO @0x%08X I/O Port @0x%08X ROM Addr @0x%08X\n",
card->fb, card->mmio, card->io, pci_config_read32(pci_dev->dev.addr, PCI_ROM_ADDRESS));
card->posted= radeon_card_posted();
chip_family_name[card->info->chip_family], card->info->model_name,
(uint32_t)(card->vram_size / (1024 * 1024)), card->cfg_name,
ati_dev->vendor_id, ati_dev->device_id,
ati_dev->subsys_id.subsys.vendor_id, ati_dev->subsys_id.subsys.device_id,
ati_dev->subsys_id.subsys.vendor_id, ati_dev->subsys_id.subsys.device_id,
devicepath);
free(card);
branches/iFabio/Chameleon/i386/libsaio/platform.c
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PlatformInfo_t Platform;
pci_dt_t * dram_controller_dev = NULL;
//Azi: temporarily placing this here; from removed mem.c, needed by DEBUG_PLATFORM
// check if replaceable by other or completely remove?? whatever...
#define DC(c) (c >= 0x20 && c < 0x7f ? (char) c : '.')
#define STEP 16
void dumpPhysAddr(const char * title, void * a, int len)
{
int i,j;
u_int8_t* ad = (u_int8_t*) a;
char buffer[80];
char str[16];
if(ad==NULL) return;
printf("%s addr=0x%08x len=%04d\n",title ? title : "Dump of ", a, len);
printf("Ofs-00-01-02-03-04-05-06-07-08-09-0A-0B-0C-0D-0E-0F ASCII\n");
i = (len/STEP)*STEP;
for (j=0; j < i; j+=STEP)
{
printf("%02x: %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %c%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c\n",
j,
ad[j], ad[j+1], ad[j+2], ad[j+3] , ad[j+4], ad[j+5], ad[j+6], ad[j+7],
ad[j+8], ad[j+9], ad[j+10], ad[j+11] , ad[j+12], ad[j+13], ad[j+14], ad[j+15],
DC(ad[j]), DC(ad[j+1]), DC(ad[j+2]), DC(ad[j+3]) , DC(ad[j+4]), DC(ad[j+5]), DC(ad[j+6]), DC(ad[j+7]),
DC(ad[j+8]), DC(ad[j+9]), DC(ad[j+10]), DC(ad[j+11]) , DC(ad[j+12]), DC(ad[j+13]), DC(ad[j+14]), DC(ad[j+15])
);
}
if (len%STEP==0) return;
sprintf(buffer,"%02x:", i);
for (j=0; j < STEP; j++) {
if (j<(len%STEP))
sprintf(str, " %02x", ad[i+j]);
else
strcpy(str, " " );
strncat(buffer, str, sizeof(buffer));
}
strncat(buffer," ", sizeof(buffer));
for (j=0; j < (len%STEP); j++) {
sprintf(str, "%c", DC(ad[i+j]));
strncat(buffer, str, sizeof(buffer));
}
printf("%s\n",buffer);
}
/** Return if a CPU feature specified by feature is activated (true) or not (false) */
bool platformCPUFeature(uint32_t feature)
{
branches/iFabio/Chameleon/i386/libsaio/cpu.c
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char str[128], *s;
/*
* The brand string 48 bytes (max), guaranteed to
* be NUL terminated.
* be NULL terminated.
*/
do_cpuid(0x80000002, reg);
bcopy((char *)reg, &str[0], 16);
branches/iFabio/Chameleon/i386/libsaio/platform.h
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#define CPUID_816
#define CPUID_MAX7
#define CPU_MODEL_YONAH0x0E
#define CPU_MODEL_MEROM0x0F
#define CPU_MODEL_PENRYN0x17
#define CPU_MODEL_NEHALEM0x1A
#define CPU_MODEL_ATOM0x1C
#define CPU_MODEL_FIELDS0x1E/* Lynnfield, Clarksfield, Jasper */
#define CPU_MODEL_DALES0x1F/* Havendale, Auburndale */
#define CPU_MODEL_DALES_32NM0x25/* Clarkdale, Arrandale */
#define CPU_MODEL_SANDY0x2a/* Sandy bridge */
#define CPU_MODEL_WESTMERE0x2C/* Gulftown, Westmere-EP, Westmere-WS */
#define CPU_MODEL_SANDY_XEON0x2D
#define CPU_MODEL_NEHALEM_EX0x2E
#define CPU_MODEL_YONAH0x0E// Sossaman, Yonah
#define CPU_MODEL_MEROM0x0F// Allendale, Conroe, Kentsfield, Woodcrest, Clovertown, Tigerton, Merom
#define CPU_MODEL_PENRYN0x17// Wolfdale, Yorkfield, Harpertown, Penryn
#define CPU_MODEL_NEHALEM0x1A// Bloomfield. Nehalem-EP, Nehalem-WS, Gainestown
#define CPU_MODEL_ATOM0x1C// Atom
#define CPU_MODEL_FIELDS0x1E// Lynnfield, Clarksfield, Jasper Forest
#define CPU_MODEL_DALES0x1F// Havendale, Auburndale
#define CPU_MODEL_DALES_32NM0x25// Clarkdale, Arrandale
#define CPU_MODEL_SANDY0x2A// Sandy Bridge
#define CPU_MODEL_WESTMERE0x2C// Gulftown, Westmere-EP, Westmere-WS
#define CPU_MODEL_SANDY_XEON0x2D// Sandy Bridge Xeon
#define CPU_MODEL_NEHALEM_EX0x2E// Beckton
#define CPU_MODEL_WESTMERE_EX0x2F
/* CPU Features */
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#define CALIBRATE_LATCH((CLKNUM * CALIBRATE_TIME_MSEC + 1000/2)/1000)
// CPUID Values
#define CPUID_MODEL_YONAH14
#define CPUID_MODEL_MEROM15
#define CPUID_MODEL_PENRYN23
#define CPUID_MODEL_NEHALEM26
#define CPUID_MODEL_ATOM 28
#define CPUID_MODEL_FIELDS30/* Lynnfield, Clarksfield, Jasper */
#define CPUID_MODEL_DALES31/* Havendale, Auburndale */
#define CPUID_MODEL_NEHALEM_EX46
#define CPUID_MODEL_DALES_32NM37/* Clarkdale, Arrandale */
#define CPUID_MODEL_WESTMERE44/* Gulftown, Westmere-EP, Westmere-WS */
#define CPUID_MODEL_WESTMERE_EX47
#define CPUID_MODEL_YONAH14// Intel Mobile Core Solo, Duo
#define CPUID_MODEL_MEROM15// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx
#define CPUID_MODEL_PENRYN23// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx
#define CPUID_MODEL_NEHALEM26// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)
#define CPUID_MODEL_ATOM28// Intel Atom (45nm)
#define CPUID_MODEL_FIELDS30// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)
#define CPUID_MODEL_DALES31// Havendale, Auburndale
#define CPUID_MODEL_NEHALEM_EX46// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x
#define CPUID_MODEL_DALES_32NM37// Intel Core i3, i5 LGA1156 (32nm)
#define CPUID_MODEL_WESTMERE44// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core
#define CPUID_MODEL_WESTMERE_EX47// Intel Xeon E7
static inline uint64_t rdtsc64(void)
branches/iFabio/Chameleon/i386/libsaio/smbios.c
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{
switch (Platform.CPU.Model)
{
case CPU_MODEL_FIELDS:// Intel Core i5, i7 LGA1156 (45nm)
case CPU_MODEL_DALES:// Intel Core i5, i7 LGA1156 (45nm) ???
case CPU_MODEL_DALES_32NM:// Intel Core i3, i5, i7 LGA1156 (32nm) (Clarkdale, Arrandale)
case 0x19:// Intel Core i5 650 @3.20 Ghz
case CPU_MODEL_FIELDS:// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)
case CPU_MODEL_DALES:
case CPU_MODEL_DALES_32NM:// Intel Core i3, i5 LGA1156 (32nm)
case 0x19:// ??? Intel Core i5 650 @3.20 GHz
defaultBIOSInfo.version= kDefaultiMacNehalemBIOSVersion;
defaultSystemInfo.productName= kDefaultiMacNehalem;
defaultSystemInfo.family= kDefaultiMacFamily;
break;
case CPU_MODEL_SANDY:
case CPU_MODEL_SANDY_XEON:
case CPU_MODEL_SANDY:// Intel Core i3, i5, i7 LGA1155 (32nm)
case CPU_MODEL_SANDY_XEON:// Intel Xeon E3
defaultBIOSInfo.version= kDefaultiMacSandyBIOSVersion;
defaultSystemInfo.productName= kDefaultiMacSandy;
defaultSystemInfo.family= kDefaultiMacFamily;
break;
case CPU_MODEL_NEHALEM:
case CPU_MODEL_NEHALEM_EX:
case CPU_MODEL_NEHALEM:// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)
case CPU_MODEL_NEHALEM_EX:// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x
defaultBIOSInfo.version= kDefaultMacProNehalemBIOSVersion;
defaultSystemInfo.productName= kDefaultMacProNehalem;
defaultSystemInfo.family= kDefaultMacProFamily;
break;
case CPU_MODEL_WESTMERE:
case CPU_MODEL_WESTMERE_EX:
case CPU_MODEL_WESTMERE:// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core
case CPU_MODEL_WESTMERE_EX:// Intel Xeon E7
defaultBIOSInfo.version= kDefaultMacProWestmereBIOSVersion;
defaultBIOSInfo.releaseDate= kDefaulMacProWestmereBIOSReleaseDate;
defaultSystemInfo.productName= kDefaultMacProWestmere;
{
switch (Platform.CPU.Model)
{
case 0x19:// Intel Core i5 650 @3.20 Ghz
case CPU_MODEL_FIELDS:// Intel Core i5, i7 LGA1156 (45nm)
case CPU_MODEL_DALES:// Intel Core i5, i7 LGA1156 (45nm) ???
case CPU_MODEL_DALES_32NM:// Intel Core i3, i5, i7 LGA1156 (32nm)
case CPU_MODEL_NEHALEM:// Intel Core i7 LGA1366 (45nm)
case CPU_MODEL_NEHALEM_EX:// Intel Core i7 LGA1366 (45nm) 6 Core ???
case CPU_MODEL_WESTMERE:// Intel Core i7 LGA1366 (32nm) 6 Core
case CPU_MODEL_WESTMERE_EX:// Intel Core i7 LGA1366 (45nm) 6 Core ???
case 0x19:// ??? Intel Core i5 650 @3.20 GHz
case CPU_MODEL_FIELDS:// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)
case CPU_MODEL_DALES:
case CPU_MODEL_DALES_32NM:// Intel Core i3, i5 LGA1156 (32nm)
case CPU_MODEL_NEHALEM:// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)
case CPU_MODEL_NEHALEM_EX:// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x
case CPU_MODEL_WESTMERE:// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core
case CPU_MODEL_WESTMERE_EX:// Intel Xeon E7
break;
default:
for (i = 0; i < numOfSetters; i++)
if ((structPtr->orig->type == SMBSetters[i].type) && (SMBSetters[i].fieldOffset < structPtr->orig->length))
{
if (SMBSetters[i].fieldOffset > structPtr->orig->length)
continue;
setterFound = true;
setSMBValue(structPtr, i, (returnType *)((uint8_t *)structPtr->new + SMBSetters[i].fieldOffset));
}
branches/iFabio/Chameleon/i386/libsaio/pci.h
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uint16_tvendor_id;
uint16_tdevice_id;
} subsys;
uint32_t subsys_id;
uint32_tsubsys_id;
}subsys_id;
uint16_tclass_id;
struct pci_dt_t*next;
} pci_dt_t;
#define PCIADDR(bus, dev, func)(1 << 31) | (bus << 16) | (dev << 11) | (func << 8)
#define PCIADDR(bus, dev, func) (1 << 31) | (bus << 16) | (dev << 11) | (func << 8)
#define PCI_ADDR_REG0xcf8
#define PCI_DATA_REG0xcfc
/* Option ROM PCI Data Structure */
typedef struct {
uint32_tsignature;// 0x52494350'PCIR'
uint16_tvendor_id;
uint16_tdevice_id;
uint16_tvital_product_data_offset;
uint16_tstructure_length;
uint8_tstructure_revision;
uint8_tclass_code[3];
uint16_timage_length;
uint16_timage_revision;
uint8_tcode_type;
uint8_tindicator;
uint16_treserved;
uint32_tsignature;// ati - 0x52494350, nvidia - 0x50434952, 'PCIR'
uint16_tvendor_id;
uint16_tdevice_id;
uint16_tvital_product_data_offset;
uint16_tstructure_length;
uint8_tstructure_revision;
uint8_tclass_code[3];
uint16_timage_length;
uint16_timage_revision;
uint8_tcode_type;
uint8_tindicator;
uint16_treserved;
} option_rom_pci_header_t;
//-----------------------------------------------------------------------------
// added by iNDi
typedef struct {
uint32_tsignature;// 0x24506E50 '$PnP'
uint8_trevision;// 1
uint8_tlength;//
uint16_toffset;
uint8_tchecksum;
uint32_tidentifier;
uint16_tmanufacturer;
uint16_tproduct;
uint8_tclass[3];
uint8_tindicators;
uint16_tboot_vector;
uint16_tdisconnect_vector;
uint16_tbootstrap_vector;
uint16_treserved;
uint16_tresource_vector;
uint32_tsignature;// 0x24506E50 '$PnP'
uint8_trevision;//1
uint8_tlength;
uint16_toffset;
uint8_tchecksum;
uint32_tidentifier;
uint16_tmanufacturer;
uint16_tproduct;
uint8_tclass[3];
uint8_tindicators;
uint16_tboot_vector;
uint16_tdisconnect_vector;
uint16_tbootstrap_vector;
uint16_treserved;
uint16_tresource_vector;
} option_rom_pnp_header_t;
/*
branches/iFabio/Chameleon/i386/libsaio/smbios_getters.c
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{
switch (Platform.CPU.Model)
{
case 0x0D:// ?
case 0x0D:// ???
case CPU_MODEL_YONAH:// Yonah0x0E
case CPU_MODEL_MEROM:// Merom0x0F
case CPU_MODEL_PENRYN:// Penryn0x17
case CPU_MODEL_ATOM:// Atom 45nm0x1C
return false;
case 0x19:// Intel Core i5 650 @3.20 Ghz
case 0x19:// ??? Intel Core i5 650 @3.20 GHz
case CPU_MODEL_NEHALEM:// Intel Core i7 LGA1366 (45nm)
case CPU_MODEL_FIELDS:// Intel Core i5, i7 LGA1156 (45nm)
case CPU_MODEL_DALES:// Intel Core i5, i7 LGA1156 (45nm) ???
{
switch (Platform.CPU.Model)
{
case 0x0D:// ?
case CPU_MODEL_YONAH:// Yonah
case CPU_MODEL_MEROM:// Merom
case CPU_MODEL_PENRYN:// Penryn
case 0x0D:// ???
case CPU_MODEL_YONAH:// Intel Mobile Core Solo, Duo
case CPU_MODEL_MEROM:// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx
case CPU_MODEL_PENRYN:// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx
case CPU_MODEL_ATOM:// Intel Atom (45nm)
return true;
case CPU_MODEL_NEHALEM:// Intel Core i7 LGA1366 (45nm)
case CPU_MODEL_NEHALEM:// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)
if (strstr(Platform.CPU.BrandString, "Xeon(R)"))
value->word = 0x0501;// Xeon
else
return true;
case CPU_MODEL_FIELDS:// Lynnfield, Clarksfield, Jasper
case CPU_MODEL_FIELDS:// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)
if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))
value->word = 0x601;// Core i5
else
value->word = 0x0701;// Core i7
return true;
case CPU_MODEL_DALES:// Intel Core i5, i7 LGA1156 (45nm) (Havendale, Auburndale)
case CPU_MODEL_DALES:// Havendale, Auburndale
if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))
value->word = 0x601;// Core i5
else
value->word = 0x0701;// Core i7
return true;
case CPU_MODEL_SANDY:// Intel Core i3, i5, i7 LGA1155 sandy bridge
case CPU_MODEL_SANDY_XEON:
case CPU_MODEL_DALES_32NM:// Intel Core i3, i5, i7 LGA1156 (32nm) (Clarkdale, Arrandale)
case CPU_MODEL_SANDY:// Intel Core i3, i5, i7 LGA1155 (32nm)
case CPU_MODEL_SANDY_XEON:// Intel Xeon E3
case CPU_MODEL_DALES_32NM:// Intel Core i3, i5 LGA1156 (32nm)
if (strstr(Platform.CPU.BrandString, "Core(TM) i3"))
value->word = 0x901;// Core i3
else
value->word = 0x0701;// Core i7
return true;
case CPU_MODEL_WESTMERE:// Intel Core i7 LGA1366 (32nm) 6 Core (Gulftown, Westmere-EP, Westmere-WS)
case CPU_MODEL_WESTMERE_EX:// Intel Core i7 LGA1366 (45nm) 6 Core ???
case CPU_MODEL_WESTMERE:// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core
case CPU_MODEL_WESTMERE_EX:// Intel Xeon E7
value->word = 0x0501;// Core i7
return true;
case 0x19:// Intel Core i5 650 @3.20 Ghz
case 0x19:// ??? Intel Core i5 650 @3.20 GHz
value->word = 0x601;// Core i5
return true;
}
branches/iFabio/Chameleon/i386/boot2/boot.h
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#define kBootBannerKey"Boot Banner"
#define kWaitForKeypressKey"Wait"
#define kDSDT"DSDT"/* acpi_patcher.c */
#define kDropSSDT"DropSSDT"/* acpi_patcher.c */
#define kRestartFix"RestartFix"/* acpi_patcher.c */
#define kGeneratePStates"GeneratePStates"/* acpi_patcher.c */
#define kGenerateCStates"GenerateCStates"/* acpi_patcher.c */
#define kEnableC2States"EnableC2State"/* acpi_patcher.c */
#define kEnableC3States"EnableC3State"/* acpi_patcher.c */
#define kEnableC4States"EnableC4State"/* acpi_patcher.c */
#define kUseAtiROM"UseAtiROM"/* ati.c */
#define kAtiConfig"AtiConfig"/* ati.c */
#define kATYbinimage"ATYbinimage"/* ati.c */
#define karch"arch"/* boot.c */
#define kUseKernelCache"UseKernelCache"/* boot.c */
#define kDSDT"DSDT"/* acpi_patcher.c */
#define kDropSSDT"DropSSDT"/* acpi_patcher.c */
#define kRestartFix"RestartFix"/* acpi_patcher.c */
#define kGeneratePStates"GeneratePStates"/* acpi_patcher.c */
#define kGenerateCStates"GenerateCStates"/* acpi_patcher.c */
#define kEnableC2States"EnableC2State"/* acpi_patcher.c */
#define kEnableC3States"EnableC3State"/* acpi_patcher.c */
#define kEnableC4States"EnableC4State"/* acpi_patcher.c */
#define kbusratio"busratio"/* cpu.c */
#define kDeviceProperties"device-properties"/* device_inject.c */
#define kUseMemDetect"UseMemDetect" /* platform.c */
#define kMD0Image"md0"/* ramdisk.h */
#define kSMBIOSdefaults"SMBIOSdefaults"/* smbios_patcher.c */
#define kDefaultPartition"Default Partition"/* sys.c */
#define kUSBBusFix"USBBusFix"/* usb.c */
#define kEHCIacquire"EHCIacquire"/* usb.c */
#define kUHCIreset"UHCIreset"/* usb.c */
#define kLegacyOff"USBLegacyOff"/* usb.c */
#define kEHCIhard"EHCIhard"/* usb.c */
#define kDefaultPartition"Default Partition"/* sys.c */
#define kMD0Image"md0"/* ramdisk.h */
#define kbusratio"busratio"/* cpu.c */
/*
* Flags to the booter or kernel
*/
branches/iFabio/Chameleon/i386/boot2/modules.c
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#include "bootstruct.h"
#include "modules.h"
#include "boot_modules.h"
#include <vers.h>
#if CONFIG_MODULE_DEBUG
if(module_start && module_start != (void*)0xFFFFFFFF)
{
// Notify the system that it was laoded
module_loaded(SYMBOLS_MODULE /*moduleName, moduleVersion, moduleCompat*/);
module_loaded(SYMBOLS_MODULE, SYMBOLS_AUTHOR, SYMBOLS_DESCRIPTION, SYMBOLS_VERSION, SYMBOLS_COMPAT);
(*module_start)();// Start the module. This will point to load_all_modules due to the way the dylib was constructed.
execute_hook("ModulesLoaded", NULL, NULL, NULL, NULL);
if(module_start && module_start != (void*)0xFFFFFFFF)
{
// Notify the system that it was laoded
module_loaded(SYMBOLS_MODULE /*moduleName, moduleVersion, moduleCompat*/);
module_loaded(SYMBOLS_MODULE, SYMBOLS_AUTHOR, SYMBOLS_DESCRIPTION, SYMBOLS_VERSION, SYMBOLS_COMPAT);
(*module_start)();// Start the module. This will point to load_all_modules due to the way the dylib was constructed.
execute_hook("ModulesLoaded", NULL, NULL, NULL, NULL);
return retVal;
}
void start_built_in_module(char* name, void(*start_function)(void))
void start_built_in_module(const char* name,
const char* author,
const char* description,
UInt32 version,
UInt32 compat,
void(*start_function)(void))
{
start_function();
// Notify the module system that this module really exists, specificaly, let other module link with it
module_loaded(name /*, moduleName, moduleVersion, moduleCompat*/);
module_loaded(name, author, description, version, compat);
}
if(module_start && module_start != (void*)0xFFFFFFFF)
{
// Notify the system that it was laoded
module_loaded(module/*moduleName, moduleVersion, moduleCompat*/);
module_loaded(module, NULL, NULL, 0, 0 /*moduleName, moduleVersion, moduleCompat*/);
(*module_start)();// Start the module
DBG("Module %s Loaded.\n", module); DBGPAUSE();
}
/*
* print out the information about the loaded module
*/
void module_loaded(const char* name/*, UInt32 version, UInt32 compat*/)
void module_loaded(const char* name, const char* author, const char* description, UInt32 version, UInt32 compat)
{
moduleList_t* new_entry = malloc(sizeof(moduleList_t));
new_entry->next = loadedModules;
loadedModules = new_entry;
new_entry->name = (char*)name;
//new_entry->version = version;
//new_entry->compat = compat;
if(!name) name = "Unknown";
if(!author) author = "Unknown";
if(!description) description = "";
new_entry->name = name;
new_entry->author = author;
new_entry->description = description;
new_entry->version = version;
new_entry->compat = compat;
msglog("Module '%s' by '%s' Loaded.\n", name, author);
msglog("\tDescription: %s\n", description);
msglog("\tVersion: %d\n", version); // todo: sperate to major.minor.bugfix
msglog("\tCompat: %d\n", compat); // todo: ^^^ major.minor.bugfix
}
int is_module_loaded(const char* name)
branches/iFabio/Chameleon/i386/boot2/modules.h
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#define __BOOT_MODULES_H
#define MODULE_PATH"/Extra/modules/"
#define SYMBOLS_MODULE "Symbols.dylib"
#define SYMBOLS_AUTHOR "Chameleon"
#define SYMBOLS_DESCRIPTION "Chameleon symbols for linking"
#define SYMBOLS_VERSION 0
#define SYMBOLS_COMPAT 0
#define VOID_SYMBOL"dyld_void_start"
extern UInt64 textAddress;
extern UInt64 textSection;
struct moduleHook_t* next;
} moduleHook_t;
typedef struct moduleList_t //Azi: modules or module? see modules/include/modules
typedef struct modulesList_t
{
char*name;
//UInt32version;
//UInt32compat;
struct moduleList_t*next;
const char*name;
const char* author;
const char* description;
UInt32version;
UInt32compat;
struct modulesList_t* next;
} moduleList_t;
int init_module_system();
void load_all_modules();
void start_built_in_module(char* name, void(*start_function)(void));
void start_built_in_module(const char* name,
const char* author,
const char* description,
UInt32 version,
UInt32 compat,
void(*start_function)(void));
int load_module(char* module);
int is_module_loaded(const char* name);
void module_loaded(const char* name/*, UInt32 version, UInt32 compat*/);
void module_loaded(const char* name, const char* author, const char* description, UInt32 version, UInt32 compat);
branches/iFabio/Chameleon/i386/boot2/gui.c
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extern MenuItem *menuItems;
char prompt[BOOT_STRING_LEN];
//char prompt[BOOT_STRING_LEN];
extern char gBootArgs[BOOT_STRING_LEN];
int prompt_pos=0;
char prompt_text[] = "boot: ";
menuitem_t infoMenuItems[] =
void clearGraphicBootPrompt()
{
// clear text buffer
prompt[0] = '\0';
prompt_pos=0;
//prompt[0] = '\0';
//prompt_pos=0;
if(gui.bootprompt.draw == true )
void updateGraphicBootPrompt(int key)
{
if ( key == kBackspaceKey )
prompt[--prompt_pos] = '\0';
else
{
prompt[prompt_pos] = key;
prompt_pos++;
prompt[prompt_pos] = '\0';
}
fillPixmapWithColor( gui.bootprompt.pixmap, gui.bootprompt.bgcolor);
makeRoundedCorners( gui.bootprompt.pixmap);
position_t p_prompt = pos( p_text.x + ( ( strlen(prompt_text) ) * font_console.chars[0]->width ), p_text.y );
// calculate the position of the cursor
intoffset = ( prompt_pos - ( ( gui.bootprompt.width / font_console.chars[0]->width ) - strlen(prompt_text) - 2 ) );
intoffset = ( strlen(gBootArgs) - ( ( gui.bootprompt.width / font_console.chars[0]->width ) - strlen(prompt_text) - 2 ) );
if ( offset < 0)
offset = 0;
drawStr( prompt+offset, &font_console, gui.bootprompt.pixmap, p_prompt);
drawStr( gBootArgs, &font_console, gui.bootprompt.pixmap, p_prompt);
gui.menu.draw = false;
gui.bootprompt.draw = true;
branches/iFabio/Chameleon/i386/boot2/options.c
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//==========================================================================
static char gBootArgs[BOOT_STRING_LEN];
char gBootArgs[BOOT_STRING_LEN];
static char * gBootArgsPtr = gBootArgs;
static char * gBootArgsEnd = gBootArgs + BOOT_STRING_LEN - 1;
static char booterCommand[BOOT_STRING_LEN];
extern char bootRescanPrompt[];
if( bootArgs->Video.v_display == VGA_TEXT_MODE ) {
changeCursor( 0, row, kCursorTypeUnderline, 0 );
clearScreenRows( row, kScreenLastRow );
changeCursor( strlen(gBootArgs), row, kCursorTypeUnderline, 0 );
//clearScreenRows( row, kScreenLastRow );
}
clearBootArgs();
//clearBootArgs();
if (visible) {
if (bootArgs->Video.v_display == VGA_TEXT_MODE) {
printf( bootRescanPrompt );
} else {
printf( bootPrompt );
printf( gBootArgs );
}
}
} else {
if (bootArgs->Video.v_display == GRAPHICS_MODE) {
clearGraphicBootPrompt();
//clearGraphicBootPrompt();
} else {
printf("Press Enter to start up the foreign OS. ");
}
{
setCursorPosition( x, y, 0 );
putca(' ', 0x07, 1);
} else
updateGraphicBootPrompt(kBackspaceKey);
*gBootArgsPtr-- = '\0';
}
}
*gBootArgsPtr-- = '\0';
updateGraphicBootPrompt(kBackspaceKey);
}
else
{
*gBootArgsPtr = '\0';
if( bootArgs->Video.v_display == VGA_TEXT_MODE ) putca(' ', 0x07, 1);
updateGraphicBootPrompt(kBackspaceKey);
}
break;
default:
if ( key >= ' ' && gBootArgsPtr < gBootArgsEnd)
{
if( bootArgs->Video.v_display == VGA_TEXT_MODE )
putchar(key); // echo to screen
else
updateGraphicBootPrompt(key);
*gBootArgsPtr++ = key;
*gBootArgsPtr++ = key;
updateGraphicBootPrompt(key);
}
break;
branches/iFabio/Chameleon/i386/modules/Resolution/915resolution.c
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#ifndef _RESOLUTION_H_
#define _RESOLUTION_H_
#include "libsaio.h"
#include "edid.h"
//#include "libsaio.h"
//#include "edid.h" //included
#include "915resolution.h"
UInt32 x = 0, y = 0, bp = 0;
getResolution(&x, &y, &bp);
verbose("getResolution: %dx%dx%d\n", (int)x, (int)y, (int)bp);
if (x != 0 &&
y != 0 &&
bp != 0)
int i = 0;
while (i < 512)
{ // we don't need to look through the whole bios, just the firs 512 bytes
{ // we don't need to look through the whole bios, just the first 512 bytes
if ((map->bios_ptr[i] == 'N')
&& (map->bios_ptr[i+1] == 'V')
&& (map->bios_ptr[i+2] == 'I')
char* edidInfo = readEDID();
if(!edidInfo) return 1;
mode->pixel_clock = (edidInfo[55] << 8) | edidInfo[54];
//Slice
if(!fb_parse_edid((struct EDID *)edidInfo, mode))
{
free( edidInfo );
return 1;
}
/*mode->pixel_clock = (edidInfo[55] << 8) | edidInfo[54];
mode->h_active = edidInfo[56] | ((edidInfo[58] & 0xF0) << 4);
mode->h_blanking = ((edidInfo[58] & 0x0F) << 8) | edidInfo[57];
mode->v_active = edidInfo[59] | ((edidInfo[61] & 0xF0) << 4);
mode->h_sync_width = (edidInfo[65] & 0x30) | edidInfo[63];
mode->v_sync_offset = (edidInfo[65] & 0x0C) | ((edidInfo[64] & 0x0C) >> 2);
mode->v_sync_width = ((edidInfo[65] & 0x3) << 2) | (edidInfo[64] & 0x03);
*/
free( edidInfo );
if(!mode->h_active) return 1;
//for (i=0; i < map->mode_table_size; i++) {
//if (map->mode_table[0].mode == mode) {
switch(map->bios) {
case BT_INTEL:
return;
case BT_1:
{
vbios_resolution_type1 * res = map_type1_resolution(map, map->mode_table[i].resolution);
branches/iFabio/Chameleon/i386/modules/Resolution/include/edid.h
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* Created by Evan Lojewski on 12/1/09.
* Copyright 2009. All rights reserved.
*
* Slice 2010, based on Joblo works
*/
//#ifndef __EDID_H__
//#define __EDID_H__
#ifndef _EDID_H_
#define _EDID_H_
#include "libsaio.h"
#define EDID_BLOCK_SIZE128
#define EDID_V1_BLOCKS_TO_GO_OFFSET 126
//Slice - some more info about EDID
#define EDID_LENGTH0x80
#define EDID_HEADER0x00
#define EDID_HEADER_END0x07
#define ID_MANUFACTURER_NAME0x08
#define ID_MANUFACTURER_NAME_END0x09
#define ID_MODEL0x0a
#define ID_SERIAL_NUMBER0x0c
#define MANUFACTURE_WEEK0x10
#define MANUFACTURE_YEAR0x11
#define EDID_STRUCT_VERSION0x12
#define EDID_STRUCT_REVISION0x13
#define EDID_STRUCT_DISPLAY 0x14
#define DPMS_FLAGS0x18
#define ESTABLISHED_TIMING_10x23
#define ESTABLISHED_TIMING_20x24
#define MANUFACTURERS_TIMINGS0x25
/* standard timings supported */
#define STD_TIMING 8
#define STD_TIMING_DESCRIPTION_SIZE 2
#define STD_TIMING_DESCRIPTIONS_START 0x26
#define DETAILED_TIMING_DESCRIPTIONS_START0x36
#define DETAILED_TIMING_DESCRIPTION_SIZE18
#define NO_DETAILED_TIMING_DESCRIPTIONS4
#define DETAILED_TIMING_DESCRIPTION_10x36
#define DETAILED_TIMING_DESCRIPTION_20x48
#define DETAILED_TIMING_DESCRIPTION_30x5a
#define DETAILED_TIMING_DESCRIPTION_40x6c
#define DESCRIPTOR_DATA5
#define UPPER_NIBBLE( x ) \
(((128|64|32|16) & (x)) >> 4)
#define LOWER_NIBBLE( x ) \
((1|2|4|8) & (x))
#define COMBINE_HI_8LO( hi, lo ) \
( (((unsigned)hi) << 8) | (unsigned)lo )
#define COMBINE_HI_4LO( hi, lo ) \
( (((unsigned)hi) << 4) | (unsigned)lo )
#define PIXEL_CLOCK_LO (unsigned)block[ 0 ]
#define PIXEL_CLOCK_HI (unsigned)block[ 1 ]
#define PIXEL_CLOCK (COMBINE_HI_8LO( PIXEL_CLOCK_HI,PIXEL_CLOCK_LO )*10000)
#define H_ACTIVE_LO (unsigned)block[ 2 ]
#define H_BLANKING_LO (unsigned)block[ 3 ]
#define H_ACTIVE_HI UPPER_NIBBLE( (unsigned)block[ 4 ] )
#define H_ACTIVE COMBINE_HI_8LO( H_ACTIVE_HI, H_ACTIVE_LO )
#define H_BLANKING_HI LOWER_NIBBLE( (unsigned)block[ 4 ] )
#define H_BLANKING COMBINE_HI_8LO( H_BLANKING_HI, H_BLANKING_LO )
#define V_ACTIVE_LO (unsigned)block[ 5 ]
#define V_BLANKING_LO (unsigned)block[ 6 ]
#define V_ACTIVE_HI UPPER_NIBBLE( (unsigned)block[ 7 ] )
#define V_ACTIVE COMBINE_HI_8LO( V_ACTIVE_HI, V_ACTIVE_LO )
#define V_BLANKING_HI LOWER_NIBBLE( (unsigned)block[ 7 ] )
#define V_BLANKING COMBINE_HI_8LO( V_BLANKING_HI, V_BLANKING_LO )
#define H_SYNC_OFFSET_LO (unsigned)block[ 8 ]
#define H_SYNC_WIDTH_LO (unsigned)block[ 9 ]
#define V_SYNC_OFFSET_LO UPPER_NIBBLE( (unsigned)block[ 10 ] )
#define V_SYNC_WIDTH_LO LOWER_NIBBLE( (unsigned)block[ 10 ] )
#define V_SYNC_WIDTH_HI ((unsigned)block[ 11 ] & (1|2))
#define V_SYNC_OFFSET_HI (((unsigned)block[ 11 ] & (4|8)) >> 2)
#define H_SYNC_WIDTH_HI (((unsigned)block[ 11 ] & (16|32)) >> 4)
#define H_SYNC_OFFSET_HI (((unsigned)block[ 11 ] & (64|128)) >> 6)
#define V_SYNC_WIDTH COMBINE_HI_4LO( V_SYNC_WIDTH_HI, V_SYNC_WIDTH_LO )
#define V_SYNC_OFFSET COMBINE_HI_4LO( V_SYNC_OFFSET_HI, V_SYNC_OFFSET_LO )
#define H_SYNC_WIDTH COMBINE_HI_4LO( H_SYNC_WIDTH_HI, H_SYNC_WIDTH_LO )
#define H_SYNC_OFFSET COMBINE_HI_4LO( H_SYNC_OFFSET_HI, H_SYNC_OFFSET_LO )
#define H_SIZE_LO (unsigned)block[ 12 ]
#define V_SIZE_LO (unsigned)block[ 13 ]
#define H_SIZE_HI UPPER_NIBBLE( (unsigned)block[ 14 ] )
#define V_SIZE_HI LOWER_NIBBLE( (unsigned)block[ 14 ] )
#define H_SIZE COMBINE_HI_8LO( H_SIZE_HI, H_SIZE_LO )
#define V_SIZE COMBINE_HI_8LO( V_SIZE_HI, V_SIZE_LO )
#define H_BORDER (unsigned)block[ 15 ]
#define V_BORDER (unsigned)block[ 16 ]
#define FLAGS (unsigned)block[ 17 ]
#define INTERLACED (FLAGS&128)
#define SYNC_TYPE (FLAGS&3<<3)/* bits 4,3 */
#define SYNC_SEPARATE (3<<3)
#define HSYNC_POSITIVE (FLAGS & 4)
#define VSYNC_POSITIVE (FLAGS & 2)
#define V_MIN_RATE block[ 5 ]
#define V_MAX_RATE block[ 6 ]
#define H_MIN_RATE block[ 7 ]
#define H_MAX_RATE block[ 8 ]
#define MAX_PIXEL_CLOCK (((int)block[ 9 ]) * 10)
#define GTF_SUPPORTblock[10]
#define DPMS_ACTIVE_OFF(1 << 5)
#define DPMS_SUSPEND(1 << 6)
#define DPMS_STANDBY(1 << 7)
struct EDID
{
UInt8header[8];//0
UInt8vendorProduct[4];//8
UInt8serialNumber[4];//12
UInt8weekOfManufacture;//16
UInt8yearOfManufacture;//17
UInt8version;//18
UInt8revision;//19
UInt8displayParams[5];//20
UInt8colorCharacteristics[10];//25
UInt8establishedTimings[3];//35
UInt16standardTimings[8];//38
UInt8detailedTimings[72];//54
UInt8extension;//126
UInt8checksum;//127
};
typedef struct _edid_mode {
unsigned short pixel_clock;
unsigned short h_active;
unsigned short h_blanking;
unsigned short v_active;
unsigned short v_blanking;
unsigned short h_sync_offset;
unsigned short h_sync_width;
unsigned short v_sync_offset;
unsigned short v_sync_width;
} edid_mode;
char* readEDID();
void getResolution(UInt32* x, UInt32* y, UInt32* bp);
int fb_parse_edid(struct EDID *edid, edid_mode* var);
int getEDID( void * edidBlock, UInt8 block);
void getResolution(UInt32* x, UInt32* y, UInt32* bp);
#endif /* _EDID_H_ */
//#endif
branches/iFabio/Chameleon/i386/modules/Resolution/edid.c
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*
* Created by Evan Lojewski on 12/1/09.
* Copyright 2009. All rights reserved.
*
*
*Slice 2010, based on Joblo works
*/
//#include "libsaio.h"
#include "edid.h"
#include "vbe.h"
#include "graphics.h"
#include "boot.h"
//----------------------------------------------------------------------------------
#define FBMON_FIX_HEADER 1
#define FBMON_FIX_INPUT 2
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
//----------------------------------------------------------------------------------
/*
struct broken_edid {
const char manufacturer[4];
UInt32 model;
UInt32 fix;
};
//----------------------------------------------------------------------------------
broken_edid brokendb[] = {
// DEC FR-PCXAV-YZ *
{ "DEC", 0x073a, FBMON_FIX_HEADER,},
// ViewSonic PF775a *
{ "VSC", 0x5a44, FBMON_FIX_INPUT,}
};
//----------------------------------------------------------------------------------
*/
const unsigned char edid_v1_header[] = { 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00};
//----------------------------------------------------------------------------------
int edid_compare(unsigned char *edid1, unsigned char *edid2)
{
int result = 0;
unsigned char *block = edid1 + ID_MANUFACTURER_NAME, manufacturer1[4], manufacturer2[4];;
manufacturer1[0] = ((block[0] & 0x7c) >> 2) + '@';
manufacturer1[1] = ((block[0] & 0x03) << 3) + ((block[1] & 0xe0) >> 5) + '@';
manufacturer1[2] = (block[1] & 0x1f) + '@';
manufacturer1[3] = 0;
block = edid2 + ID_MANUFACTURER_NAME;
manufacturer2[0] = ((block[0] & 0x7c) >> 2) + '@';
manufacturer2[1] = ((block[0] & 0x03) << 3) + ((block[1] & 0xe0) >> 5) + '@';
manufacturer2[2] = (block[1] & 0x1f) + '@';
manufacturer2[3] = 0;
int x;
for(x = 0; x < 4; x++)
{
if(manufacturer1[x] == manufacturer2[x])
result++;
}
return result;
}
int check_edid(unsigned char *edid)
{
unsigned char *block = edid + ID_MANUFACTURER_NAME, manufacturer[4];
//unsigned char *b;
UInt32 model;
//int i, fix = 0, ret = 0;
manufacturer[0] = ((block[0] & 0x7c) >> 2) + '@';
manufacturer[1] = ((block[0] & 0x03) << 3) +
((block[1] & 0xe0) >> 5) + '@';
manufacturer[2] = (block[1] & 0x1f) + '@';
manufacturer[3] = 0;
model = block[2] + (block[3] << 8);
/*
for (i = 0; i < (int)ARRAY_SIZE(brokendb); i++) {
if (!strncmp((const char *)manufacturer, brokendb[i].manufacturer, 4) &&
brokendb[i].model == model) {
DEBG("ATIFB: The EDID Block of "
"Manufacturer: %s Model: 0x%08lx is known to "
"be broken,\n", manufacturer, model);
fix = brokendb[i].fix;
break;
}
}
switch (fix) {
case FBMON_FIX_HEADER:
for (i = 0; i < 8; i++) {
if (edid[i] != edid_v1_header[i])
ret = fix;
}
break;
case FBMON_FIX_INPUT:
b = edid + EDID_STRUCT_DISPLAY;
/// Only if display is GTF capable will
//the input type be reset to analog *
if (b[4] & 0x01 && b[0] & 0x80)
ret = fix;
break;
}
*/
return 0; //ret;
}
//----------------------------------------------------------------------------------
static void fix_edid(unsigned char *edid, int fix)
{
unsigned char *b;
switch (fix) {
case FBMON_FIX_HEADER:
msglog("EDID: trying a header reconstruct\n");
memcpy(edid, edid_v1_header, 8);
break;
case FBMON_FIX_INPUT:
msglog("EDID: trying to fix input type\n");
b = edid + EDID_STRUCT_DISPLAY;
b[0] &= ~0x80;
edid[127] += 0x80;
}
}
//----------------------------------------------------------------------------------
int edid_checksum(unsigned char *edid)
{
unsigned char i, csum = 0, all_null = 0;
int err = 0, fix = check_edid(edid);
if (fix)
fix_edid(edid, fix);
for (i = 0; i < EDID_LENGTH; i++) {
csum += edid[i];
all_null |= edid[i];
}
if (csum == 0x00 && all_null) {
/* checksum passed, everything's good */
err = 1;
}
return err;
}
//----------------------------------------------------------------------------------
static int edid_check_header(unsigned char *edid)
{
int i, err = 1, fix = check_edid(edid);
if (fix)
fix_edid(edid, fix);
for (i = 0; i < 8; i++) {
if (edid[i] != edid_v1_header[i])
err = 0;
}
return err;
}
//------------------------------------------------------------------------
bool verifyEDID(unsigned char *edid)
{
if (edid == NULL || !edid_checksum(edid) ||!edid_check_header(edid))
{
return false;
}
return true;
}
int edid_is_timing_block(unsigned char *block)
{
if ((block[0] != 0x00) || (block[1] != 0x00) ||
(block[2] != 0x00) || (block[4] != 0x00))
return 1;
else
return 0;
}
//----------------------------------------------------------------------------------
int fb_parse_edid(struct EDID *edid, edid_mode* var) //(struct EDID *edid, UInt32* x, UInt32* y)
{
int i;
unsigned char *block;
if(!verifyEDID((unsigned char *)edid)) return 1;
block = (unsigned char *)edid + DETAILED_TIMING_DESCRIPTIONS_START; //54
for (i = 0; i < 4; i++, block += DETAILED_TIMING_DESCRIPTION_SIZE) {
if (edid_is_timing_block(block)) {
var->h_active = H_ACTIVE;
var->v_active = V_ACTIVE;
var->h_sync_offset = H_SYNC_OFFSET;
var->h_sync_width = H_SYNC_WIDTH;
var->h_blanking = H_BLANKING;
var->v_blanking = V_BLANKING;
var->pixel_clock = PIXEL_CLOCK;
var->h_sync_width = H_SYNC_WIDTH;
var->v_sync_width = V_SYNC_WIDTH;
/*
var->xres = var->xres_virtual = H_ACTIVE;
var->yres = var->yres_virtual = V_ACTIVE;
var->height = var->width = -1;
var->right_margin = H_SYNC_OFFSET;
var->left_margin = (H_ACTIVE + H_BLANKING) -
(H_ACTIVE + H_SYNC_OFFSET + H_SYNC_WIDTH);
var->upper_margin = V_BLANKING - V_SYNC_OFFSET -
V_SYNC_WIDTH;
var->lower_margin = V_SYNC_OFFSET;
var->hsync_len = H_SYNC_WIDTH;
var->vsync_len = V_SYNC_WIDTH;
var->pixclock = PIXEL_CLOCK;
var->pixclock /= 1000;
var->pixclock = KHZ2PICOS(var->pixclock);
if (HSYNC_POSITIVE)
var->sync |= FB_SYNC_HOR_HIGH_ACT;
if (VSYNC_POSITIVE)
var->sync |= FB_SYNC_VERT_HIGH_ACT;
*/
return 1;
}
}
return 0;
}
void getResolution(UInt32* x, UInt32* y, UInt32* bp)
{
//int val;
static UInt32 xResolution, yResolution, bpResolution;
/*
if(getIntForKey(kScreenWidth, &val, &bootInfo->bootConfig))
{
xResolution = val;
}
if(getIntForKey(kScreenHeight, &val, &bootInfo->bootConfig))
{
yResolution = val;
}
*/
bpResolution = 32;// assume 32bits
bpResolution = 32;// assume 32bits
if(!xResolution || !yResolution || !bpResolution)
{
char* edidInfo = readEDID();
if(!edidInfo) return;
edid_mode mode;
// TODO: check *all* resolutions reported and either use the highest, or the native resolution (if there is a flag for that)
xResolution = edidInfo[56] | ((edidInfo[58] & 0xF0) << 4);
yResolution = edidInfo[59] | ((edidInfo[61] & 0xF0) << 4);
//xResolution = edidInfo[56] | ((edidInfo[58] & 0xF0) << 4);
//yResolution = edidInfo[59] | ((edidInfo[61] & 0xF0) << 4);
//Slice - done here
//printf("H Active = %d", edidInfo[56] | ((edidInfo[58] & 0xF0) << 4) );
//printf("V Active = %d", edidInfo[59] | ((edidInfo[61] & 0xF0) << 4) );
if(fb_parse_edid((struct EDID *)edidInfo, &mode) == 0)
{
xResolution = DEFAULT_SCREEN_WIDTH;
yResolution = DEFAULT_SCREEN_HEIGHT;
}
else {
xResolution = mode.h_active;
yResolution = mode.v_active;
}
/*
0x00 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0x00 0x32 0x0C
0x00 0xDF 0x00 0x00 0x00 0x00 0xFF 0xFF 0xFF 0x00
0x0C 0xDF 0x00 0x00 0x12 0x03 0x21 0x78 0xE9 0x99
0x53 0x28 0xFF 0xFF 0x32 0xDF 0x00 0x12 0x80 0x78
0xD5 0x53 0x26 0x00 0x01 0x01 0x01 0x01 0xFF 0x00
0xDF 0x00 0x03 0x78 0x99 0x28 0x00 0x01 0x01 0x01
0x01 0x21 0x84 0x20 0xFF 0x0C 0x00 0x03 0x0A 0x53
0x54 0x01 0x01 0x01 0xDE 0x84 0x56 0x00 0xA0 0x30
0xFF 0xDF 0x12 0x78 0x53 0x00 0x01 0x01 0x01 0x84
0x00 0x18 0x84 0x00 0x00 0x57 0xFF 0x00 0x80 0x99
0x54 0x01 0x01 0x21 0x20 0x00 0x50 0x00 0x00 0x35
0x57 0xFE 0x00 0x00 0x78 0x28 0x01 0x01 0x21 0x20
0x18 0x30 0x00 0x57 0x34 0xFE 0xAA 0x9A
*/
//msglog("H Active = %d ", edidInfo[56] | ((edidInfo[58] & 0xF0) << 4) );
//msglog("V Active = %d \n", edidInfo[59] | ((edidInfo[61] & 0xF0) << 4) );
free( edidInfo );
if(!xResolution) xResolution = DEFAULT_SCREEN_WIDTH;
if(!yResolution) yResolution = DEFAULT_SCREEN_HEIGHT;
//if(!xResolution) xResolution = DEFAULT_SCREEN_WIDTH;
//if(!yResolution) yResolution = DEFAULT_SCREEN_HEIGHT;
}
SInt16 status;
UInt16 blocks_left = 1;
//msglog("readEDID\n");
do
{
// TODO: This currently only retrieves the *last* block, make the block buffer expand as needed / calculated from the first block
status = getEDID(edidInfo, blocks_left);
//printf("Buffer location: 0x%X\n", SEG(buffer) << 16 | OFF(buffer));
/*
msglog("Buffer location: 0x%X status: %d\n", SEG(edidInfo) << 16 | OFF(edidInfo), status);
int j, i;
for (j = 0; j < 8; j++) {
for(i = 0; i < 16; i++) printf("0x%X ", ebiosInfo[((i+1) * (j + 1)) - 1]);
for(i = 0; i < 16; i++) msglog("0x%02X ", edidInfo[((i+1) * (j + 1)) - 1]);
msglog("\n");
}
printf("\n");
*/
if(status == 0)
{
//if( edidInfo[0] == 0x00 || edidInfo[0] == 0xFF)
if ( reported > blocks_left )
{
printf("EDID claims %d more blocks left\n", reported);
msglog("EDID claims %d more blocks left\n", reported);
}
if ( (last_reported <= reported && last_reported != -1)
//|| reported == MAGIC
)
{
printf("Last reported %d\n", last_reported);
printf( "EDID blocks left is wrong.\n"
msglog("Last reported %d\n", last_reported);
msglog( "EDID blocks left is wrong.\n"
"Your EDID is probably invalid.\n");
return 0;
}
}
else
{
printf("Invalid block %d\n", blocks_left);
printf("Header1 = %d", memcmp(edidInfo, header1, sizeof(header1)) );
printf("Header2 = %d", memcmp(edidInfo, header2, sizeof(header2)) );
msglog("Invalid block %d\n", blocks_left);
msglog("Header1 = %d", memcmp(edidInfo, header1, sizeof(header1)) );
msglog("Header2 = %d", memcmp(edidInfo, header2, sizeof(header2)) );
return 0;
}
}
bios( &bb );
return(bb.eax.r.h);
}
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*/
#ifndef __RESOLUTION_H
#define __RESOLUTION_H
#include "shortatombios.h"
#include "edid.h"
#ifndef __RESOLUTION_H
#define __RESOLUTION_H
//Slice - moved to edid.h
/*
typedef struct _edid_mode {
unsigned short pixel_clock;
unsigned short h_active;
unsigned short v_sync_offset;
unsigned short v_sync_width;
} edid_mode;
*/
void patchVideoBios();
typedef enum {
BT_UNKNOWN, BT_1, BT_2, BT_3, BT_ATI_1, BT_ATI_2, BT_NVDA
BT_UNKNOWN, BT_1, BT_2, BT_3, BT_ATI_1, BT_ATI_2, BT_NVDA, BT_INTEL
} bios_type;
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MODULE_NAME = Resolution
MODULE_DESCRIPTION = This module provides
MODULE_AUTHOR =
MODULE_AUTHOR = Chameleon
MODULE_DESCRIPTION = This module reads the edid information from the monitor attached to the main display. The module will also patch the vesa modes available in pre intel hd graphics cards to provide proper resolution while booting.
MODULE_VERSION = "1.0.0"
MODULE_COMPAT_VERSION = "1.0.0"
MODULE_START = $(MODULE_NAME)_start
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ifeq ($(BUILT_IN),yes)
$(SYMROOT)/modules/$(MODULE_NAME).dylib: $(addprefix $(OBJROOT)/, ${MODULE_OBJS}) $(MODULE_DEPENDENCIES)
$(SYMROOT)/modules/$(MODULE_NAME).dylib: $(addprefix $(OBJROOT)/, ${MODULE_OBJS}) $(MODULE_DEPENDENCIES) $(OBJROOT)/$(MODULE_NAME).desc $(OBJROOT)/$(MODULE_NAME).author Makefile
@echo "\t[LD] $(MODULE_NAME).dylib"
@ld -arch i386 -undefined dynamic_lookup \
-dylib -read_only_relocs suppress \
-final_output $(MODULE_NAME) \
$(filter %.o,$^) \
-macosx_version_min 10.6 \
-sectcreate __INFO __author $(OBJROOT)/$(MODULE_NAME).author \
-sectcreate __INFO __description $(OBJROOT)/$(MODULE_NAME).desc \
-o $(SYMROOT)/modules/$(MODULE_NAME).dylib
else
$(SYMROOT)/modules/$(MODULE_NAME).dylib: $(addprefix $(OBJROOT)/, ${MODULE_OBJS}) $(MODULE_DEPENDENCIES) $(SRCROOT)/obj/i386/boot2/Symbols_LINKER_ONLY.dylib
$(SYMROOT)/modules/$(MODULE_NAME).dylib: $(addprefix $(OBJROOT)/, ${MODULE_OBJS}) $(MODULE_DEPENDENCIES) $(OBJROOT)/$(MODULE_NAME).desc $(OBJROOT)/$(MODULE_NAME).author $(SRCROOT)/obj/i386/boot2/Symbols_LINKER_ONLY.dylib Makefile
@echo "\t[LD] $(MODULE_NAME).dylib"
@ld -arch i386 \
$(filter %.o,$^) \
-weak_library $(SRCROOT)/obj/i386/boot2/Symbols_LINKER_ONLY.dylib \
$(MODULE_DEPENDENCIES_CMD) \
-sectcreate __INFO __author $(OBJROOT)/$(MODULE_NAME).author \
-sectcreate __INFO __description $(OBJROOT)/$(MODULE_NAME).desc \
-macosx_version_min 10.6 \
-o $@
endif
.PHONY: $(SRCROOT)/sym/i386/boot_modules.c
$(SRCROOT)/sym/i386/boot_modules.c:
@echo "\tstart_built_in_module(\"$(MODULE_NAME)\", &$(MODULE_START));" >> $@
@echo "\tstart_built_in_module(\"$(MODULE_NAME)\", \"$(MODULE_AUTHOR)\", \"$(MODULE_DESCRIPTION)\", 0, 0, &$(MODULE_START));" >> $@
$(SRCROOT)/sym/i386/boot_modules.h:
@echo "void $(MODULE_START)(); // $(MODULE_NAME)" >> $@
$(OBJROOT)/$(MODULE_NAME).author: Makefile
@echo "$(MODULE_AUTHOR)" > $@
$(OBJROOT)/$(MODULE_NAME).desc: Makefile
@echo "$(MODULE_DESCRIPTION)" > $@
#dependencies
-include $(OBJROOT)/Makedep
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source "i386/modules/klibc/Cconfig"
source "i386/modules/uClibcxx/Cconfig"
source "i386/modules/HelloWorld/Cconfig"
source "i386/modules/AMDGraphicsEnabler/Cconfig"
source "i386/modules/ATiGraphicsEnabler/Cconfig"
source "i386/modules/IntelGraphicsEnabler/Cconfig"
source "i386/modules/NVIDIAGraphicsEnabler/Cconfig"
source "i386/modules/GraphicsEnabler/AMDGraphicsEnabler/Cconfig"
source "i386/modules/GraphicsEnabler/ATiGraphicsEnabler/Cconfig"
source "i386/modules/GraphicsEnabler/IntelGraphicsEnabler/Cconfig"
source "i386/modules/GraphicsEnabler/NVIDIAGraphicsEnabler/Cconfig"
endmenu
branches/iFabio/Chameleon/i386/modules/GraphicsEnabler/NVIDIAGraphicsEnabler/nvidia.h
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/*
* NVidia injector
*
* Copyright (C) 2009 Jasmin Fazlic, iNDi
*
* NVidia injector is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* NVidia driver and injector is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with NVidia injector. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Alternatively you can choose to comply with APSL
*/
/*
* DCB-Table parsing is based on software (nouveau driver) originally distributed under following license:
*
*
* Copyright 2005-2006 Erik Waling
* Copyright 2006 Stephane Marchesin
* Copyright 2007-2009 Stuart Bennett
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef __LIBSAIO_NVIDIA_H
#define __LIBSAIO_NVIDIA_H
bool setup_nvidia_devprop(pci_dt_t *nvda_dev);
struct nv_chipsets_t {
unsigned device;
char *name;
};
#define DCB_MAX_NUM_ENTRIES 16
#define DCB_MAX_NUM_I2C_ENTRIES 16
#define DCB_LOC_ON_CHIP 0
struct bios {
uint16_tsignature;/* 0x55AA */
uint8_tsize;/* Size in multiples of 512 */
};
#define NV_PROM_OFFSET0x300000
#define NV_PROM_SIZE0x0000ffff
#define NV_PRAMIN_OFFSET0x00700000
#define NV_PRAMIN_SIZE0x00100000
#define NV04_PFB_FIFO_DATA0x0010020c
#define NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK0xfff00000
#define NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_SHIFT20
#define NVC0_MEM_CTRLR_COUNT0x00121c74
#define NVC0_MEM_CTRLR_RAM_AMOUNT0x0010f20c
#define NV_PBUS_PCI_NV_200x00001850
#define NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED(0 << 0)
#define NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED(1 << 0)
#define REG8(reg) ((volatile uint8_t *)regs)[(reg)]
#define REG16(reg) ((volatile uint16_t *)regs)[(reg) >> 1]
#define REG32(reg) ((volatile uint32_t *)regs)[(reg) >> 2]
#define NV_ARCH_03 0x03
#define NV_ARCH_04 0x04
#define NV_ARCH_10 0x10
#define NV_ARCH_20 0x20
#define NV_ARCH_30 0x30
#define NV_ARCH_40 0x40
#define NV_ARCH_50 0x50
#define NV_ARCH_C0 0xC0
#define CHIPSET_NV03 0x0010
#define CHIPSET_NV04 0x0020
#define CHIPSET_NV10 0x0100
#define CHIPSET_NV11 0x0110
#define CHIPSET_NV15 0x0150
#define CHIPSET_NV17 0x0170
#define CHIPSET_NV18 0x0180
#define CHIPSET_NFORCE 0x01A0
#define CHIPSET_NFORCE2 0x01F0
#define CHIPSET_NV20 0x0200
#define CHIPSET_NV25 0x0250
#define CHIPSET_NV28 0x0280
#define CHIPSET_NV30 0x0300
#define CHIPSET_NV31 0x0310
#define CHIPSET_NV34 0x0320
#define CHIPSET_NV35 0x0330
#define CHIPSET_NV36 0x0340
#define CHIPSET_NV40 0x0040
#define CHIPSET_NV41 0x00C0
#define CHIPSET_NV43 0x0140
#define CHIPSET_NV44 0x0160
#define CHIPSET_NV44A 0x0220
#define CHIPSET_NV45 0x0210
#define CHIPSET_NV50 0x0190
#define CHIPSET_NV84 0x0400
#define CHIPSET_MISC_BRIDGED 0x00F0
#define CHIPSET_G70 0x0090
#define CHIPSET_G71 0x0290
#define CHIPSET_G72 0x01D0
#define CHIPSET_G73 0x0390
// integrated GeForces (6100, 6150)
#define CHIPSET_C51 0x0240
// variant of C51, seems based on a G70 design
#define CHIPSET_C512 0x03D0
#define CHIPSET_G73_BRIDGED 0x02E0
#endif /* !__LIBSAIO_NVIDIA_H */
branches/iFabio/Chameleon/i386/modules/GraphicsEnabler/NVIDIAGraphicsEnabler/NVIDIAGraphicsEnabler.c
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/*
* GraphicsEnabler Module
*Enabled many nvidia and ati cards to be used out of the box in
*OS X. This was converted from boot2 code to a boot2 module.
*
*/
#include "saio_internal.h"
#include "bootstruct.h"
#include "pci.h"
#include "nvidia.h"
#include "modules.h"
#define kGraphicsEnablerKey"GraphicsEnabler"
void GraphicsEnabler_hook(void* arg1, void* arg2, void* arg3, void* arg4);
void NVIDIAGraphicsEnabler_start()
{
register_hook_callback("PCIDevice", &GraphicsEnabler_hook);
}
void GraphicsEnabler_hook(void* arg1, void* arg2, void* arg3, void* arg4)
{
pci_dt_t* current = arg1;
if (current->class_id != PCI_CLASS_DISPLAY_VGA) return;
char *devicepath = get_pci_dev_path(current);
bool do_gfx_devprop = true;
getBoolForKey(kGraphicsEnablerKey, &do_gfx_devprop, &bootInfo->bootConfig);
if (do_gfx_devprop && (current->vendor_id == PCI_VENDOR_ID_NVIDIA))
{
verbose("NVIDIA VGA Controller [%04x:%04x] :: %s \n",
current->vendor_id, current->device_id, devicepath);
setup_nvidia_devprop(current);
}
else
verbose("[%04x:%04x] :: %s, is not a NVIDIA VGA Controller.\n",
current->vendor_id, current->device_id, devicepath);
}
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#
# Chameleon Modules
#
config NVIDIAGRAPHICSENABLER_MODULE
tristate "NVIDIAGraphicsEnabler Module"
default m
---help---
Say Y here if you want to enable the use of this module.
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Module:GraphicsEnabler
Description: the GraphicsEnabler nVidia code ported to a module.
Based on Meklort's work.
Dependencies: none
Keys: GraphicsEnabler(enabled by default)
UseNvidiaROM(disabled by default)
VBIOS...
TODO: ---
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/*
* NVidia injector
*
* Copyright (C) 2009 Jasmin Fazlic, iNDi
*
* NVidia injector is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* NVidia driver and injector is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with NVidia injector. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Alternatively you can choose to comply with APSL
*/
/*
* DCB-Table parsing is based on software (nouveau driver) originally distributed under following license:
*
*
* Copyright 2005-2006 Erik Waling
* Copyright 2006 Stephane Marchesin
* Copyright 2007-2009 Stuart Bennett
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#include "libsa.h"
#include "saio_internal.h"
#include "bootstruct.h"
#include "pci.h"
#include "platform.h"
#include "device_inject.h"
#include "nvidia.h"
#ifndef DEBUG_NVIDIA
#define DEBUG_NVIDIA 0
#endif
#if DEBUG_NVIDIA
#define DBG(x...)printf(x)
#else
#define DBG(x...)
#endif
#define kUseNvidiaROM"UseNvidiaROM"
#define kVBIOS"VBIOS"
#define NVIDIA_ROM_SIZE 0x10000
#define PATCH_ROM_SUCCESS 1
#define PATCH_ROM_SUCCESS_HAS_LVDS 2
#define PATCH_ROM_FAILED 0
#define MAX_NUM_DCB_ENTRIES 16
#define TYPE_GROUPED 0xff
extern uint32_t devices_number;
const char *nvidia_compatible_0[]={ "@0,compatible","NVDA,NVMac" };
const char *nvidia_compatible_1[]={ "@1,compatible","NVDA,NVMac" };
const char *nvidia_device_type_0[]={ "@0,device_type","display" };
const char *nvidia_device_type_1[]={ "@1,device_type","display" };
const char *nvidia_device_type[]={ "device_type","NVDA,Parent" };
const char *nvidia_name_0[]={ "@0,name","NVDA,Display-A" };
const char *nvidia_name_1[]={ "@1,name","NVDA,Display-B" };
const char *nvidia_slot_name[]={ "AAPL,slot-name","Slot-1" };
static uint8_t default_NVCAP[]= {
0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0d, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a,
0x00, 0x00, 0x00, 0x00
};
#define NVCAP_LEN ( sizeof(default_NVCAP) / sizeof(uint8_t) )
static struct nv_chipsets_t NVKnownChipsets[] = {
{ 0x00000000, "Unknown" },
{ 0x10DE0040, "GeForce 6800 Ultra" },
{ 0x10DE0041, "GeForce 6800" },
{ 0x10DE0042, "GeForce 6800 LE" },
{ 0x10DE0043, "GeForce 6800 XE" },
{ 0x10DE0044, "GeForce 6800 XT" },
{ 0x10DE0045, "GeForce 6800 GT" },
{ 0x10DE0046, "GeForce 6800 GT" },
{ 0x10DE0047, "GeForce 6800 GS" },
{ 0x10DE0048, "GeForce 6800 XT" },
{ 0x10DE004E, "Quadro FX 4000" },
{ 0x10DE0090, "GeForce 7800 GTX" },
{ 0x10DE0091, "GeForce 7800 GTX" },
{ 0x10DE0092, "GeForce 7800 GT" },
{ 0x10DE0093, "GeForce 7800 GS" },
{ 0x10DE0095, "GeForce 7800 SLI" },
{ 0x10DE0098, "GeForce Go 7800" },
{ 0x10DE0099, "GeForce Go 7800 GTX" },
{ 0x10DE009D, "Quadro FX 4500" },
{ 0x10DE00C0, "GeForce 6800 GS" },
{ 0x10DE00C1, "GeForce 6800" },
{ 0x10DE00C2, "GeForce 6800 LE" },
{ 0x10DE00C3, "GeForce 6800 XT" },
{ 0x10DE00C8, "GeForce Go 6800" },
{ 0x10DE00C9, "GeForce Go 6800 Ultra" },
{ 0x10DE00CC, "Quadro FX Go1400" },
{ 0x10DE00CD, "Quadro FX 3450/4000 SDI" },
{ 0x10DE00CE, "Quadro FX 1400" },
{ 0x10DE0140, "GeForce 6600 GT" },
{ 0x10DE0141, "GeForce 6600" },
{ 0x10DE0142, "GeForce 6600 LE" },
{ 0x10DE0143, "GeForce 6600 VE" },
{ 0x10DE0144, "GeForce Go 6600" },
{ 0x10DE0145, "GeForce 6610 XL" },
{ 0x10DE0146, "GeForce Go 6600 TE/6200 TE" },
{ 0x10DE0147, "GeForce 6700 XL" },
{ 0x10DE0148, "GeForce Go 6600" },
{ 0x10DE0149, "GeForce Go 6600 GT" },
{ 0x10DE014C, "Quadro FX 550" },
{ 0x10DE014D, "Quadro FX 550" },
{ 0x10DE014E, "Quadro FX 540" },
{ 0x10DE014F, "GeForce 6200" },
{ 0x10DE0160, "GeForce 6500" },
{ 0x10DE0161, "GeForce 6200 TurboCache(TM)" },
{ 0x10DE0162, "GeForce 6200SE TurboCache(TM)" },
{ 0x10DE0163, "GeForce 6200 LE" },
{ 0x10DE0164, "GeForce Go 6200" },
{ 0x10DE0165, "Quadro NVS 285" },
{ 0x10DE0166, "GeForce Go 6400" },
{ 0x10DE0167, "GeForce Go 6200" },
{ 0x10DE0168, "GeForce Go 6400" },
{ 0x10DE0169, "GeForce 6250" },
{ 0x10DE016A, "GeForce 7100 GS" },
{ 0x10DE0191, "GeForce 8800 GTX" },
{ 0x10DE0193, "GeForce 8800 GTS" },
{ 0x10DE0194, "GeForce 8800 Ultra" },
{ 0x10DE019D, "Quadro FX 5600" },
{ 0x10DE019E, "Quadro FX 4600" },
{ 0x10DE01D1, "GeForce 7300 LE" },
{ 0x10DE01D3, "GeForce 7300 SE" },
{ 0x10DE01D6, "GeForce Go 7200" },
{ 0x10DE01D7, "GeForce Go 7300" },
{ 0x10DE01D8, "GeForce Go 7400" },
{ 0x10DE01D9, "GeForce Go 7400 GS" },
{ 0x10DE01DA, "Quadro NVS 110M" },
{ 0x10DE01DB, "Quadro NVS 120M" },
{ 0x10DE01DC, "Quadro FX 350M" },
{ 0x10DE01DD, "GeForce 7500 LE" },
{ 0x10DE01DE, "Quadro FX 350" },
{ 0x10DE01DF, "GeForce 7300 GS" },
{ 0x10DE0211, "GeForce 6800" },
{ 0x10DE0212, "GeForce 6800 LE" },
{ 0x10DE0215, "GeForce 6800 GT" },
{ 0x10DE0218, "GeForce 6800 XT" },
{ 0x10DE0221, "GeForce 6200" },
{ 0x10DE0222, "GeForce 6200 A-LE" },
{ 0x10DE0240, "GeForce 6150" },
{ 0x10DE0241, "GeForce 6150 LE" },
{ 0x10DE0242, "GeForce 6100" },
{ 0x10DE0244, "GeForce Go 6150" },
{ 0x10DE0247, "GeForce Go 6100" },
{ 0x10DE0290, "GeForce 7900 GTX" },
{ 0x10DE0291, "GeForce 7900 GT" },
{ 0x10DE0292, "GeForce 7900 GS" },
{ 0x10DE0298, "GeForce Go 7900 GS" },
{ 0x10DE0299, "GeForce Go 7900 GTX" },
{ 0x10DE029A, "Quadro FX 2500M" },
{ 0x10DE029B, "Quadro FX 1500M" },
{ 0x10DE029C, "Quadro FX 5500" },
{ 0x10DE029D, "Quadro FX 3500" },
{ 0x10DE029E, "Quadro FX 1500" },
{ 0x10DE029F, "Quadro FX 4500 X2" },
{ 0x10DE0301, "GeForce FX 5800 Ultra" },
{ 0x10DE0302, "GeForce FX 5800" },
{ 0x10DE0308, "Quadro FX 2000" },
{ 0x10DE0309, "Quadro FX 1000" },
{ 0x10DE0311, "GeForce FX 5600 Ultra" },
{ 0x10DE0312, "GeForce FX 5600" },
{ 0x10DE0314, "GeForce FX 5600XT" },
{ 0x10DE031A, "GeForce FX Go5600" },
{ 0x10DE031B, "GeForce FX Go5650" },
{ 0x10DE031C, "Quadro FX Go700" },
{ 0x10DE0324, "GeForce FX Go5200" },
{ 0x10DE0325, "GeForce FX Go5250" },
{ 0x10DE0326, "GeForce FX 5500" },
{ 0x10DE0328, "GeForce FX Go5200 32M/64M" },
{ 0x10DE032A, "Quadro NVS 55/280 PCI" },
{ 0x10DE032B, "Quadro FX 500/600 PCI" },
{ 0x10DE032C, "GeForce FX Go53xx Series" },
{ 0x10DE032D, "GeForce FX Go5100" },
{ 0x10DE0330, "GeForce FX 5900 Ultra" },
{ 0x10DE0331, "GeForce FX 5900" },
{ 0x10DE0332, "GeForce FX 5900XT" },
{ 0x10DE0333, "GeForce FX 5950 Ultra" },
{ 0x10DE0334, "GeForce FX 5900ZT" },
{ 0x10DE0338, "Quadro FX 3000" },
{ 0x10DE033F, "Quadro FX 700" },
{ 0x10DE0341, "GeForce FX 5700 Ultra" },
{ 0x10DE0342, "GeForce FX 5700" },
{ 0x10DE0343, "GeForce FX 5700LE" },
{ 0x10DE0344, "GeForce FX 5700VE" },
{ 0x10DE0347, "GeForce FX Go5700" },
{ 0x10DE0348, "GeForce FX Go5700" },
{ 0x10DE034C, "Quadro FX Go1000" },
{ 0x10DE034E, "Quadro FX 1100" },
{ 0x10DE0391, "GeForce 7600 GT" },
{ 0x10DE0392, "GeForce 7600 GS" },
{ 0x10DE0393, "GeForce 7300 GT" },
{ 0x10DE0394, "GeForce 7600 LE" },
{ 0x10DE0395, "GeForce 7300 GT" },
{ 0x10DE0397, "GeForce Go 7700" },
{ 0x10DE0398, "GeForce Go 7600" },
{ 0x10DE0399, "GeForce Go 7600 GT"},
{ 0x10DE039A, "Quadro NVS 300M" },
{ 0x10DE039B, "GeForce Go 7900 SE" },
{ 0x10DE039C, "Quadro FX 550M" },
{ 0x10DE039E, "Quadro FX 560" },
{ 0x10DE0400, "GeForce 8600 GTS" },
{ 0x10DE0401, "GeForce 8600 GT" },
{ 0x10DE0402, "GeForce 8600 GT" },
{ 0x10DE0403, "GeForce 8600 GS" },
{ 0x10DE0404, "GeForce 8400 GS" },
{ 0x10DE0405, "GeForce 9500M GS" },
{ 0x10DE0407, "GeForce 8600M GT" },
{ 0x10DE0408, "GeForce 9650M GS" },
{ 0x10DE0409, "GeForce 8700M GT" },
{ 0x10DE040A, "Quadro FX 370" },
{ 0x10DE040B, "Quadro NVS 320M" }, //Azi: 320M
{ 0x10DE040C, "Quadro FX 570M" },
{ 0x10DE040D, "Quadro FX 1600M" },
{ 0x10DE040E, "Quadro FX 570" },
{ 0x10DE040F, "Quadro FX 1700" },
{ 0x10DE0420, "GeForce 8400 SE" },
{ 0x10DE0421, "GeForce 8500 GT" },
{ 0x10DE0422, "GeForce 8400 GS" },
{ 0x10DE0423, "GeForce 8300 GS" },
{ 0x10DE0424, "GeForce 8400 GS" },
{ 0x10DE0425, "GeForce 8600M GS" },
{ 0x10DE0426, "GeForce 8400M GT" },
{ 0x10DE0427, "GeForce 8400M GS" },
{ 0x10DE0428, "GeForce 8400M G" },
{ 0x10DE0429, "Quadro NVS 140M" },
{ 0x10DE042A, "Quadro NVS 130M" },
{ 0x10DE042B, "Quadro NVS 135M" },
{ 0x10DE042C, "GeForce 9400 GT" },
{ 0x10DE042D, "Quadro FX 360M" },
{ 0x10DE042E, "GeForce 9300M G" },
{ 0x10DE042F, "Quadro NVS 290" },
{ 0x10DE05E0, "GeForce GTX 295" },
{ 0x10DE05E1, "GeForce GTX 280" },
{ 0x10DE05E2, "GeForce GTX 260" },
{ 0x10DE05E3, "GeForce GTX 285" },
{ 0x10DE05E6, "GeForce GTX 275" },
{ 0x10DE05EA, "GeForce GTX 260" },
{ 0x10DE05EB, "GeForce GTX 295" },
{ 0x10DE05F9, "Quadro CX" },
{ 0x10DE05FD, "Quadro FX 5800" },
{ 0x10DE05FE, "Quadro FX 4800" },
{ 0x10DE0600, "GeForce 8800 GTS 512" },
{ 0x10DE0602, "GeForce 8800 GT" },
{ 0x10DE0604, "GeForce 9800 GX2" },
{ 0x10DE0605, "GeForce 9800 GT" },
{ 0x10DE0606, "GeForce 8800 GS" },
{ 0x10DE0607, "GeForce GTS 240" },
{ 0x10DE0608, "GeForce 9800M GTX" },
{ 0x10DE0609, "GeForce 8800M GTS" },
{ 0x10DE060A, "GeForce GTX 280M" },
{ 0x10DE060B, "GeForce 9800M GT" },
{ 0x10DE060C, "GeForce 8800M GTX" },
{ 0x10DE060D, "GeForce 8800 GS" },
{ 0x10DE0610, "GeForce 9600 GSO" },
{ 0x10DE0611, "GeForce 8800 GT" },
{ 0x10DE0612, "GeForce 9800 GTX" },
{ 0x10DE0613, "GeForce 9800 GTX+" },
{ 0x10DE0614, "GeForce 9800 GT" },
{ 0x10DE0615, "GeForce GTS 250" },
{ 0x10DE0617, "GeForce 9800M GTX" },
{ 0x10DE0618, "GeForce GTX 260M" },
{ 0x10DE061A, "Quadro FX 3700" },
{ 0x10DE061C, "Quadro FX 3600M" },
{ 0x10DE061D, "Quadro FX 2800M" },
{ 0x10DE061F, "Quadro FX 3800M" },
{ 0x10DE0622, "GeForce 9600 GT" },
{ 0x10DE0623, "GeForce 9600 GS" },
{ 0x10DE0625, "GeForce 9600 GSO 512"},
{ 0x10DE0626, "GeForce GT 130" },
{ 0x10DE0627, "GeForce GT 140" },
{ 0x10DE0628, "GeForce 9800M GTS" },
{ 0x10DE062A, "GeForce 9700M GTS" },
{ 0x10DE062C, "GeForce 9800M GTS" },
{ 0x10DE0640, "GeForce 9500 GT" },
{ 0x10DE0641, "GeForce 9400 GT" },
{ 0x10DE0642, "GeForce 8400 GS" },
{ 0x10DE0643, "GeForce 9500 GT" },
{ 0x10DE0644, "GeForce 9500 GS" },
{ 0x10DE0645, "GeForce 9500 GS" },
{ 0x10DE0646, "GeForce GT 120" },
{ 0x10DE0647, "GeForce 9600M GT" },
{ 0x10DE0648, "GeForce 9600M GS" },
{ 0x10DE0649, "GeForce 9600M GT" },
{ 0x10DE064A, "GeForce 9700M GT" },
{ 0x10DE064B, "GeForce 9500M G" },
{ 0x10DE064C, "GeForce 9650M GT" },
{ 0x10DE0652, "GeForce GT 130M" },
{ 0x10DE0658, "Quadro FX 380" },
{ 0x10DE0659, "Quadro FX 580" },
{ 0x10DE065A, "Quadro FX 1700M" },
{ 0x10DE065B, "GeForce 9400 GT" },
{ 0x10DE065C, "Quadro FX 770M" },
{ 0x10DE06E0, "GeForce 9300 GE" },
{ 0x10DE06E1, "GeForce 9300 GS" },
{ 0x10DE06E4, "GeForce 8400 GS" },
{ 0x10DE06E5, "GeForce 9300M GS" },
{ 0x10DE06E8, "GeForce 9200M GS" },
{ 0x10DE06E9, "GeForce 9300M GS" },
{ 0x10DE06EA, "Quadro NVS 150M" },
{ 0x10DE06EB, "Quadro NVS 160M" },
{ 0x10DE06EC, "GeForce G 105M" },
{ 0x10DE06EF, "GeForce G 103M" },
{ 0x10DE06F8, "Quadro NVS 420" },
{ 0x10DE06F9, "Quadro FX 370 LP" },
{ 0x10DE06FA, "Quadro NVS 450" },
{ 0x10DE06FD, "Quadro NVS 295" },
{ 0x10DE086A, "GeForce 9400" },
{ 0x10DE0874, "ION 9300M" },
{ 0x10DE086C, "GeForce 9300/nForce 730i" },
{ 0x10DE087D, "ION 9400M" },
{ 0x10DE087E, "ION LE" },
{ 0x10DE0A20, "GeForce GT220" },
{ 0x10DE0A23, "GeForce 210" },
{ 0x10DE0A28, "GeForce GT 230M" },
{ 0x10DE0A29, "GeForce GT 330M" },
{ 0x10DE0A2A, "GeForce GT 230M" },
{ 0x10DE0A34, "GeForce GT 240M" },
{ 0x10DE0A60, "GeForce G210" },
{ 0x10DE0A62, "GeForce 205" },
{ 0x10DE0A63, "GeForce 310" },
{ 0x10DE0A65, "GeForce 210" },
{ 0x10DE0A66, "GeForce 310" },
{ 0x10DE0A74, "GeForce G210M" },
{ 0x10DE0A75, "GeForce G310M" },
{ 0x10DE0A78, "Quadro FX 380 LP" },
{ 0x10DE0CA3, "GeForce GT 240" },
{ 0x10DE0CA8, "GeForce GTS 260M" },
{ 0x10DE0CA9, "GeForce GTS 250M" },
{ 0x10DE0CB1, "GeForce GTS 360M" },
{ 0x10DE0CA3, "GeForce GT240" },
// 06C0 - 06DFF
{ 0x10DE06C0, "GeForce GTX 480" },
{ 0x10DE06C3, "GeForce GTX D12U" },
{ 0x10DE06C4, "GeForce GTX 465" },
{ 0x10DE06CA, "GeForce GTX 480M" },
{ 0x10DE06CD, "GeForce GTX 470" },
{ 0x10DE06D1, "Tesla C2050" },// TODO: sub-device id: 0x0771
{ 0x10DE06D1, "Tesla C2070" },// TODO: sub-device id: 0x0772
{ 0x10DE06D2, "Tesla M2070" },
{ 0x10DE06D8, "Quadro 6000" },
{ 0x10DE06D9, "Quadro 5000" },
{ 0x10DE06DA, "Quadro 5000M" },
{ 0x10DE06DC, "Quadro 6000" },
{ 0x10DE06DE, "Tesla M2050" },// TODO: sub-device id: 0x0846
{ 0x10DE06DE, "Tesla M2070" },// TODO: sub-device id: ?
// 0x10DE06DE also applies to misc S2050, X2070, M2050, M2070
{ 0x10DE06DD, "Quadro 4000" },
// 0DC0 - 0DFF
{ 0x10DE0DC0, "GeForce GT 440" },
{ 0x10DE0DC1, "D12-P1-35" },
{ 0x10DE0DC2, "D12-P1-35" },
{ 0x10DE0DC4, "GeForce GTS 450" },
{ 0x10DE0DC5, "GeForce GTS 450" },
{ 0x10DE0DC6, "GeForce GTS 450" },
{ 0x10DE0DCA, "GF10x" },
{ 0x10DE0DD1, "GeForce GTX 460M" },
{ 0x10DE0DD2, "GeForce GT 445M" },
{ 0x10DE0DD3, "GeForce GT 435M" },
{ 0x10DE0DD8, "Quadro 2000" },
{ 0x10DE0DDE, "GF106-ES" },
{ 0x10DE0DDF, "GF106-INT" },
{ 0x10DE0DE1, "GeForce GT 430" },
{ 0x10DE0DE2, "GeForce GT 420" },
{ 0x10DE0DEB, "GeForce GT 555M" },
{ 0x10DE0DEE, "GeForce GT 415M" },
{ 0x10DE0DF0, "GeForce GT 425M" }, //Azi: ?? GT 450M
{ 0x10DE0DF1, "GeForce GT 420M" },
{ 0x10DE0DF2, "GeForce GT 435M" },
{ 0x10DE0DF3, "GeForce GT 420M" },
{ 0x10DE0DF8, "Quadro 600" },
{ 0x10DE0DFE, "GF108 ES" },
{ 0x10DE0DFF, "GF108 INT" },
// 0E20 - 0E3F
{ 0x10DE0E21, "D12U-25" },
{ 0x10DE0E22, "GeForce GTX 460" },
{ 0x10DE0E23, "GeForce GTX 460 SE" },
{ 0x10DE0E24, "GeForce GTX 460" },
{ 0x10DE0E25, "D12U-50" },
{ 0x10DE0E30, "GeForce GTX 470M" },
{ 0x10DE0E38, "GF104GL" },
{ 0x10DE0E3E, "GF104-ES" },
{ 0x10DE0E3F, "GF104-INT" },
// 0EE0 - 0EFF: none yet
// 0F00 - 0F3F: none yet
// 1040 - 107F: none yet
// 1080 - 109F
{ 0x10DE1080, "GeForce GTX 580" },
{ 0x10DE1081, "D13U" },
{ 0x10DE1082, "D13U" },
{ 0x10DE1083, "D13U" },
{ 0x10DE1098, "D13U" },
{ 0x10DE109A, "N12E-Q5" },
};
static uint16_t swap16(uint16_t x)
{
return (((x & 0x00FF) << 8) | ((x & 0xFF00) >> 8));
}
static uint16_t read16(uint8_t *ptr, uint16_t offset)
{
uint8_t ret[2];
ret[0] = ptr[offset+1];
ret[1] = ptr[offset];
return *((uint16_t*)&ret);
}
#if 0
static uint32_t swap32(uint32_t x)
{
return ((x & 0x000000FF) << 24) | ((x & 0x0000FF00) << 8 ) | ((x & 0x00FF0000) >> 8 ) | ((x & 0xFF000000) >> 24);
}
static uint8_t read8(uint8_t *ptr, uint16_t offset)
{
return ptr[offset];
}
static uint32_t read32(uint8_t *ptr, uint16_t offset)
{
uint8_t ret[4];
ret[0] = ptr[offset+3];
ret[1] = ptr[offset+2];
ret[2] = ptr[offset+1];
ret[3] = ptr[offset];
return *((uint32_t*)&ret);
}
#endif
static int patch_nvidia_rom(uint8_t *rom)
{
if (!rom || (rom[0] != 0x55 && rom[1] != 0xaa)) {
printf("False ROM signature: 0x%02x%02x\n", rom[0], rom[1]);
return PATCH_ROM_FAILED;
}
uint16_t dcbptr = swap16(read16(rom, 0x36));
if(!dcbptr) {
printf("no dcb table found\n");
return PATCH_ROM_FAILED;
}/* else
printf("dcb table at offset 0x%04x\n", dcbptr);
*/
uint8_t *dcbtable = &rom[dcbptr];
uint8_t dcbtable_version = dcbtable[0];
uint8_t headerlength = 0;
uint8_t recordlength = 0;
uint8_t numentries = 0;
if(dcbtable_version >= 0x20) {
uint32_t sig;
if(dcbtable_version >= 0x30) {
headerlength = dcbtable[1];
numentries = dcbtable[2];
recordlength = dcbtable[3];
sig = *(uint32_t *)&dcbtable[6];
} else {
sig = *(uint32_t *)&dcbtable[4];
headerlength = 8;
}
if (sig != 0x4edcbdcb) {
printf("bad display config block signature (0x%8x)\n", sig);
return PATCH_ROM_FAILED;
}
} else if (dcbtable_version >= 0x14) { /* some NV15/16, and NV11+ */
char sig[8] = { 0 };
strncpy(sig, (char *)&dcbtable[-7], 7);
recordlength = 10;
if (strcmp(sig, "DEV_REC")) {
printf("Bad Display Configuration Block signature (%s)\n", sig);
return PATCH_ROM_FAILED;
}
} else {
printf("ERROR: dcbtable_version is 0x%X\n", dcbtable_version);
return PATCH_ROM_FAILED;
}
if(numentries >= MAX_NUM_DCB_ENTRIES)
numentries = MAX_NUM_DCB_ENTRIES;
uint8_t num_outputs = 0, i=0;
struct dcbentry {
uint8_t type;
uint8_t index;
uint8_t *heads;
} entries[numentries];
for (i = 0; i < numentries; i++) {
uint32_t connection;
connection = *(uint32_t *)&dcbtable[headerlength + recordlength * i];
/* Should we allow discontinuous DCBs? Certainly DCB I2C tables can be discontinuous */
if ((connection & 0x0000000f) == 0x0000000f) /* end of records */
continue;
if (connection == 0x00000000) /* seen on an NV11 with DCB v1.5 */
continue;
if ((connection & 0xf) == 0x6) /* we skip type 6 as it doesnt appear on macbook nvcaps */
continue;
entries[num_outputs].type = connection & 0xf;
entries[num_outputs].index = num_outputs;
entries[num_outputs++].heads = (uint8_t*)&(dcbtable[(headerlength + recordlength * i) + 1]);
}
int has_lvds = false;
uint8_t channel1 = 0, channel2 = 0;
for(i=0; i<num_outputs; i++) {
if(entries[i].type == 3) {
has_lvds = true;
//printf("found LVDS\n");
channel1 |= ( 0x1 << entries[i].index);
entries[i].type = TYPE_GROUPED;
}
}
// if we have a LVDS output, we group the rest to the second channel
if(has_lvds) {
for(i=0; i<num_outputs; i++) {
if(entries[i].type == TYPE_GROUPED)
continue;
channel2 |= ( 0x1 << entries[i].index);
entries[i].type = TYPE_GROUPED;
}
} else {
//
int x;
// we loop twice as we need to generate two channels
for(x=0; x<=1; x++) {
for(i=0; i<num_outputs; i++) {
if(entries[i].type == TYPE_GROUPED)
continue;
// if type is TMDS, the prior output is ANALOG
// we always group ANALOG and TMDS
// if there is a TV output after TMDS, we group it to that channel as well
if(i && entries[i].type == 0x2) {
switch (x) {
case 0:
//printf("group channel 1\n");
channel1 |= ( 0x1 << entries[i].index);
entries[i].type = TYPE_GROUPED;
if((entries[i-1].type == 0x0)) {
channel1 |= ( 0x1 << entries[i-1].index);
entries[i-1].type = TYPE_GROUPED;
}
// group TV as well if there is one
if( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) ) {
//printf("group tv1\n");
channel1 |= ( 0x1 << entries[i+1].index);
entries[i+1].type = TYPE_GROUPED;
}
break;
case 1:
//printf("group channel 2 : %d\n", i);
channel2 |= ( 0x1 << entries[i].index);
entries[i].type = TYPE_GROUPED;
if((entries[i-1].type == 0x0)) {
channel2 |= ( 0x1 << entries[i-1].index);
entries[i-1].type = TYPE_GROUPED;
}
// group TV as well if there is one
if( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) ) {
//printf("group tv2\n");
channel2 |= ( 0x1 << entries[i+1].index);
entries[i+1].type = TYPE_GROUPED;
}
break;
}
break;
}
}
}
}
// if we have left ungrouped outputs merge them to the empty channel
uint8_t *togroup;// = (channel1 ? (channel2 ? NULL : &channel2) : &channel1);
togroup = &channel2;
for(i=0; i<num_outputs;i++)
if(entries[i].type != TYPE_GROUPED) {
//printf("%d not grouped\n", i);
if(togroup)
*togroup |= ( 0x1 << entries[i].index);
entries[i].type = TYPE_GROUPED;
}
if(channel1 > channel2) {
uint8_t buff = channel1;
channel1 = channel2;
channel2 = buff;
}
default_NVCAP[6] = channel1;
default_NVCAP[8] = channel2;
// patching HEADS
for(i=0; i<num_outputs;i++) {
if(channel1 & (1 << i))
*entries[i].heads = 1;
else if(channel2 & (1 << i))
*entries[i].heads = 2;
}
return (has_lvds ? PATCH_ROM_SUCCESS_HAS_LVDS : PATCH_ROM_SUCCESS);
}
static char *get_nvidia_model(uint32_t id) {
inti;
for (i=1; i< (sizeof(NVKnownChipsets) / sizeof(NVKnownChipsets[0])); i++) {
if (NVKnownChipsets[i].device == id) {
return NVKnownChipsets[i].name;
}
}
return NVKnownChipsets[0].name;
}
static uint32_t load_nvidia_bios_file(const char *filename, uint8_t *buf, int bufsize)
{
intfd;
intsize;
if ((fd = open_bvdev("bt(0,0)", filename, 0)) < 0) {
return 0;
}
size = file_size(fd);
if (size > bufsize) {
printf("Filesize of %s is bigger than expected! Truncating to 0x%x Bytes!\n", filename, bufsize);
size = bufsize;
}
size = read(fd, (char *)buf, size);
close(fd);
return size > 0 ? size : 0;
}
static int devprop_add_nvidia_template(struct DevPropDevice *device)
{
chartmp[16];
if(!device)
return 0;
if(!DP_ADD_TEMP_VAL(device, nvidia_compatible_0))
return 0;
if(!DP_ADD_TEMP_VAL(device, nvidia_device_type_0))
return 0;
if(!DP_ADD_TEMP_VAL(device, nvidia_name_0))
return 0;
if(!DP_ADD_TEMP_VAL(device, nvidia_compatible_1))
return 0;
if(!DP_ADD_TEMP_VAL(device, nvidia_device_type_1))
return 0;
if(!DP_ADD_TEMP_VAL(device, nvidia_name_1))
return 0;
if(!DP_ADD_TEMP_VAL(device, nvidia_device_type))
return 0;
// Rek : Dont use sprintf return, it does not WORK !! our custom sprintf() always return 0!
// len = sprintf(tmp, "Slot-%x", devices_number);
sprintf(tmp, "Slot-%x",devices_number);
devprop_add_value(device, "AAPL,slot-name", (uint8_t *) tmp, strlen(tmp));
devices_number++;
return 1;
}
int hex2bin(const char *hex, uint8_t *bin, int len)
{
char*p;
inti;
charbuf[3];
if (hex == NULL || bin == NULL || len <= 0 || strlen(hex) != len * 2) {
printf("[ERROR] bin2hex input error\n");
return -1;
}
buf[2] = '\0';
p = (char *) hex;
for (i=0; i<len; i++) {
if (p[0] == '\0' || p[1] == '\0' || !isxdigit(p[0]) || !isxdigit(p[1])) {
printf("[ERROR] bin2hex '%s' syntax error\n", hex);
return -2;
}
buf[0] = *p++;
buf[1] = *p++;
bin[i] = (unsigned char) strtoul(buf, NULL, 16);
}
return 0;
}
unsigned long long mem_detect(volatile uint8_t *regs, uint8_t nvCardType, pci_dt_t *nvda_dev)
{
unsigned long long vram_size = 0;
if (nvCardType < NV_ARCH_50) {
vram_size = REG32(NV04_PFB_FIFO_DATA);
vram_size &= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK;
}
else if (nvCardType < NV_ARCH_C0) {
vram_size = REG32(NV04_PFB_FIFO_DATA);
vram_size |= (vram_size & 0xff) << 32;
vram_size &= 0xffffffff00ll;
}
else { // >= NV_ARCH_C0
vram_size = REG32(NVC0_MEM_CTRLR_RAM_AMOUNT) << 20;
vram_size *= REG32(NVC0_MEM_CTRLR_COUNT);
}
return vram_size;
}
bool setup_nvidia_devprop(pci_dt_t *nvda_dev)
{
struct DevPropDevice*device;
char*devicepath;
option_rom_pci_header_t*rom_pci_header;
volatile uint8_t*regs;
uint8_t*rom;
uint8_t*nvRom;
uint8_tnvCardType;
unsigned long longvideoRam;
uint32_tnvBiosOveride;
uint32_tbar[7];
uint32_tboot_display;
intnvPatch;
intlen;
charbiosVersion[32];
charnvFilename[32];
charkNVCAP[12];
char*model;
const char*value;
booldoit;
devicepath = get_pci_dev_path(nvda_dev);
bar[0] = pci_config_read32(nvda_dev->dev.addr, 0x10 );
regs = (uint8_t *) (bar[0] & ~0x0f);
// get card type
nvCardType = (REG32(0) >> 20) & 0x1ff;
// Amount of VRAM in kilobytes
videoRam = mem_detect(regs, nvCardType, nvda_dev);
model = get_nvidia_model((nvda_dev->vendor_id << 16) | nvda_dev->device_id);
verbose("nVidia %s %dMB NV%02x [%04x:%04x] :: %s\n",
model, (uint32_t)(videoRam / 1024 / 1024),
(REG32(0) >> 20) & 0x1ff, nvda_dev->vendor_id, nvda_dev->device_id,
devicepath);
rom = malloc(NVIDIA_ROM_SIZE);
sprintf(nvFilename, "/Extra/%04x_%04x.rom", (uint16_t)nvda_dev->vendor_id, (uint16_t)nvda_dev->device_id);
if (getBoolForKey(kUseNvidiaROM, &doit, &bootInfo->bootConfig) && doit) {
verbose("Looking for nvidia video bios file %s\n", nvFilename);
nvBiosOveride = load_nvidia_bios_file(nvFilename, rom, NVIDIA_ROM_SIZE);
if (nvBiosOveride > 0) {
verbose("Using nVidia Video BIOS File %s (%d Bytes)\n", nvFilename, nvBiosOveride);
DBG("%s Signature 0x%02x%02x %d bytes\n", nvFilename, rom[0], rom[1], nvBiosOveride);
} else {
printf("ERROR: unable to open nVidia Video BIOS File %s\n", nvFilename);
return false;
}
} else {
// Otherwise read bios from card
nvBiosOveride = 0;
// TODO: we should really check for the signature before copying the rom, i think.
// PRAMIN first
nvRom = (uint8_t*)&regs[NV_PRAMIN_OFFSET];
bcopy((uint32_t *)nvRom, rom, NVIDIA_ROM_SIZE);
// Valid Signature ?
if (rom[0] != 0x55 && rom[1] != 0xaa) {
// PROM next
// Enable PROM access
(REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED;
nvRom = (uint8_t*)&regs[NV_PROM_OFFSET];
bcopy((uint8_t *)nvRom, rom, NVIDIA_ROM_SIZE);
// disable PROM access
(REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED;
// Valid Signature ?
if (rom[0] != 0x55 && rom[1] != 0xaa) {
// 0xC0000 last
bcopy((char *)0xc0000, rom, NVIDIA_ROM_SIZE);
// Valid Signature ?
if (rom[0] != 0x55 && rom[1] != 0xaa) {
printf("ERROR: Unable to locate nVidia Video BIOS\n");
return false;
} else {
DBG("ROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);
}
} else {
DBG("PROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);
}
} else {
DBG("PRAM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);
}
}
if ((nvPatch = patch_nvidia_rom(rom)) == PATCH_ROM_FAILED) {
printf("ERROR: nVidia ROM Patching Failed!\n");
//return false;
}
rom_pci_header = (option_rom_pci_header_t*)(rom + *(uint16_t *)&rom[24]);
// check for 'PCIR' sig
if (rom_pci_header->signature == 0x50434952) {
if (rom_pci_header->device_id != nvda_dev->device_id) {
// Get Model from the OpROM
model = get_nvidia_model((rom_pci_header->vendor_id << 16) | rom_pci_header->device_id);
} else {
printf("nVidia incorrect PCI ROM signature: 0x%x\n", rom_pci_header->signature);
}
}
if (!string) {
string = devprop_create_string();
}
device = devprop_add_device(string, devicepath);
/* FIXME: for primary graphics card only */
boot_display = 1;
devprop_add_value(device, "@0,AAPL,boot-display", (uint8_t*)&boot_display, 4);
if(nvPatch == PATCH_ROM_SUCCESS_HAS_LVDS) {
uint8_t built_in = 0x01;
devprop_add_value(device, "@0,built-in", &built_in, 1);
}
// get bios version
const int MAX_BIOS_VERSION_LENGTH = 32;
char* version_str = (char*)malloc(MAX_BIOS_VERSION_LENGTH);
memset(version_str, 0, MAX_BIOS_VERSION_LENGTH);
int i, version_start;
int crlf_count = 0;
// only search the first 384 bytes
for(i = 0; i < 0x180; i++) {
if(rom[i] == 0x0D && rom[i+1] == 0x0A) {
crlf_count++;
// second 0x0D0A was found, extract bios version
if(crlf_count == 2) {
if(rom[i-1] == 0x20) i--; // strip last " "
for(version_start = i; version_start > (i-MAX_BIOS_VERSION_LENGTH); version_start--) {
// find start
if(rom[version_start] == 0x00) {
version_start++;
// strip "Version "
if(strncmp((const char*)rom+version_start, "Version ", 8) == 0) {
version_start += 8;
}
strncpy(version_str, (const char*)rom+version_start, i-version_start);
break;
}
}
break;
}
}
}
sprintf(biosVersion, "%s", (nvBiosOveride > 0) ? nvFilename : version_str);
sprintf(kNVCAP, "NVCAP_%04x", nvda_dev->device_id);
if (getValueForKey(kNVCAP, &value, &len, &bootInfo->bootConfig) && len == NVCAP_LEN * 2) {
uint8_tnew_NVCAP[NVCAP_LEN];
if (hex2bin(value, new_NVCAP, NVCAP_LEN) == 0) {
verbose("Using user supplied NVCAP for %s :: %s\n", model, devicepath);
memcpy(default_NVCAP, new_NVCAP, NVCAP_LEN);
}
}
#if DEBUG_NVCAP
printf("NVCAP: %02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x\n",
default_NVCAP[0], default_NVCAP[1], default_NVCAP[2], default_NVCAP[3],
default_NVCAP[4], default_NVCAP[5], default_NVCAP[6], default_NVCAP[7],
default_NVCAP[8], default_NVCAP[9], default_NVCAP[10], default_NVCAP[11],
default_NVCAP[12], default_NVCAP[13], default_NVCAP[14], default_NVCAP[15],
default_NVCAP[16], default_NVCAP[17], default_NVCAP[18], default_NVCAP[19]);
#endif
devprop_add_nvidia_template(device);
devprop_add_value(device, "NVCAP", default_NVCAP, NVCAP_LEN);
devprop_add_value(device, "VRAM,totalsize", (uint8_t*)&videoRam, 4);
devprop_add_value(device, "model", (uint8_t*)model, strlen(model) + 1);
devprop_add_value(device, "rom-revision", (uint8_t*)biosVersion, strlen(biosVersion) + 1);
if (getBoolForKey(kVBIOS, &doit, &bootInfo->bootConfig) && doit) {
devprop_add_value(device, "vbios", rom, (nvBiosOveride > 0) ? nvBiosOveride : (rom[2] * 512));
}
stringdata = malloc(sizeof(uint8_t) * string->length);
memcpy(stringdata, (uint8_t*)devprop_generate_string(string), string->length);
stringlength = string->length;
return true;
}
branches/iFabio/Chameleon/i386/modules/GraphicsEnabler/NVIDIAGraphicsEnabler/Makefile
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MODULE_NAME = NVIDIAGraphicsEnabler
MODULE_DESCRIPTION = This module provides
MODULE_AUTHOR =
MODULE_VERSION = "1.0.0"
MODULE_COMPAT_VERSION = "1.0.0"
MODULE_START = $(MODULE_NAME)_start
MODULE_DEPENDENCIES =
DIR = NVIDIAGraphicsEnabler
MODULE_OBJS = nvidia.o NVIDIAGraphicsEnabler.o
include ../MakeInc.dir
branches/iFabio/Chameleon/i386/modules/GraphicsEnabler/IntelGraphicsEnabler/gma.c
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/**
Original patch by nawcom
http://forum.voodooprojects.org/index.php/topic,1029.msg4427.html#msg4427
**/
#include "libsa.h"
#include "saio_internal.h"
#include "bootstruct.h"
#include "pci.h"
#include "platform.h"
#include "device_inject.h"
#include "gma.h"
#ifndef DEBUG_GMA
#define DEBUG_GMA 0
#endif
#if DEBUG_GMA
#define DBG(x...)printf(x)
#else
#define DBG(x...)
#endif
uint8_t GMAX3100_vals[22][4] = {
{ 0x01,0x00,0x00,0x00 },
{ 0x01,0x00,0x00,0x00 },
{ 0x01,0x00,0x00,0x00 },
{ 0x00,0x00,0x00,0x08 },
{ 0x64,0x00,0x00,0x00 },
{ 0x00,0x00,0x00,0x08 },
{ 0x01,0x00,0x00,0x00 },
{ 0x20,0x00,0x00,0x00 },
{ 0x00,0x00,0x00,0x00 },
{ 0x01,0x00,0x00,0x00 },
{ 0x20,0x03,0x00,0x00 },
{ 0x00,0x00,0x00,0x00 },
{ 0x00,0x00,0x00,0x00 },
{ 0x00,0x00,0x00,0x00 },
{ 0x08,0x52,0x00,0x00 },
{ 0x00,0x00,0x00,0x00 },
{ 0x00,0x00,0x00,0x00 },
{ 0x01,0x00,0x00,0x00 },
{ 0x01,0x00,0x00,0x00 },
{ 0x3B,0x00,0x00,0x00 },
{ 0x00,0x00,0x00,0x00 }
};
uint8_t reg_TRUE[] = { 0x01 ,0x00 ,0x00 ,0x00 };
uint8_t reg_FALSE[] = { 0x00,0x00,0x00,0x00 };
static struct gma_gpu_t KnownGPUS[] = {
{ 0x00000000, "Unknown"},
{ 0x808627A2, "Mobile GMA950"},
{ 0x808627AE, "Mobile GMA950"},
{ 0x808627A6, "Mobile GMA950"},
{ 0x80862772, "Desktop GMA950"}, //Azi: never worked with mine.
{ 0x80862776, "Desktop GMA950"},
{ 0x80862A02, "GMAX3100"},
{ 0x80862A03, "GMAX3100"},
{ 0x80862A12, "GMAX3100"},
{ 0x80862A13, "GMAX3100"}
};
char *get_gma_model(uint32_t id) {
int i=0;
for(i = 0; i < (sizeof(KnownGPUS) / sizeof(KnownGPUS[0])); i++) {
if(KnownGPUS[i].device == id)
return KnownGPUS[i].name;
}
return KnownGPUS[0].name;
}
bool setup_gma_devprop(pci_dt_t *gma_dev)
{
//intlen;
char *devicepath;
volatile uint8_t *regs;
uint32_t bar[7];
char *model;
uint8_t BuiltIn = 0x00;
uint8_t ClassFix[4] = { 0x00, 0x00, 0x03, 0x00 };
devicepath = get_pci_dev_path(gma_dev);
bar[0] = pci_config_read32(gma_dev->dev.addr, 0x10);
regs = (uint8_t *) (bar[0] & ~0x0f);
model = get_gma_model((gma_dev->vendor_id << 16) | gma_dev->device_id);
verbose("Intel %s [%04x:%04x] :: %s\n",
model, gma_dev->vendor_id, gma_dev->device_id, devicepath);
if (!string)
string = devprop_create_string();
struct DevPropDevice *device = malloc(sizeof(struct DevPropDevice));
device = devprop_add_device(string, devicepath);
if(!device)
{
printf("Failed initializing dev-prop string dev-entry, press any key...\n");
getchar();
return false;
}
devprop_add_value(device, "model", (uint8_t*)model, (strlen(model) + 1));
devprop_add_value(device, "device_type", (uint8_t*)"display", 8);
if (model == (char *)"Mobile GMA950") {
devprop_add_value(device, "AAPL,HasPanel", reg_TRUE, 4);
devprop_add_value(device, "built-in", &BuiltIn, 1);
devprop_add_value(device, "class-code", ClassFix, 4);
} else if (model == (char *)"Desktop GMA950") {
BuiltIn = 0x01;
devprop_add_value(device, "built-in", &BuiltIn, 1);
} else if (model == (char *)"GMAX3100") {
devprop_add_value(device, "AAPL,HasPanel",GMAX3100_vals[0], 4);
devprop_add_value(device, "AAPL,SelfRefreshSupported",GMAX3100_vals[1], 4);
devprop_add_value(device, "AAPL,aux-power-connected",GMAX3100_vals[2], 4);
devprop_add_value(device, "AAPL,backlight-control",GMAX3100_vals[3], 4);
devprop_add_value(device, "AAPL00,blackscreen-preferences",GMAX3100_vals[4], 4);
devprop_add_value(device, "AAPL01,BacklightIntensity",GMAX3100_vals[5], 4);
devprop_add_value(device, "AAPL01,blackscreen-preferences",GMAX3100_vals[6], 4);
devprop_add_value(device, "AAPL01,DataJustify",GMAX3100_vals[7], 4);
devprop_add_value(device, "AAPL01,Depth",GMAX3100_vals[8], 4);
devprop_add_value(device, "AAPL01,Dither",GMAX3100_vals[9], 4);
devprop_add_value(device, "AAPL01,DualLink",GMAX3100_vals[10], 4);
devprop_add_value(device, "AAPL01,Height",GMAX3100_vals[11], 4);
devprop_add_value(device, "AAPL01,Interlace",GMAX3100_vals[12], 4);
devprop_add_value(device, "AAPL01,Inverter",GMAX3100_vals[13], 4);
devprop_add_value(device, "AAPL01,InverterCurrent",GMAX3100_vals[14], 4);
devprop_add_value(device, "AAPL01,InverterCurrency",GMAX3100_vals[15], 4);
devprop_add_value(device, "AAPL01,LinkFormat",GMAX3100_vals[16], 4);
devprop_add_value(device, "AAPL01,LinkType",GMAX3100_vals[17], 4);
devprop_add_value(device, "AAPL01,Pipe",GMAX3100_vals[18], 4);
devprop_add_value(device, "AAPL01,PixelFormat",GMAX3100_vals[19], 4);
devprop_add_value(device, "AAPL01,Refresh",GMAX3100_vals[20], 4);
devprop_add_value(device, "AAPL01,Stretch",GMAX3100_vals[21], 4);
}
stringdata = malloc(sizeof(uint8_t) * string->length);
if(!stringdata)
{
printf("no stringdata press a key...\n");
getchar();
return false;
}
memcpy(stringdata, (uint8_t*)devprop_generate_string(string), string->length);
stringlength = string->length;
return true;
}
branches/iFabio/Chameleon/i386/modules/GraphicsEnabler/IntelGraphicsEnabler/IntelGraphicsEnabler.c
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/*
* IntelGraphicsEnabler Module ---
* Enables "some" Intel cards to be used out of the box ?? in OS X.
* This was converted from ... // AutoResolution reminder ---
*
*/
#include "saio_internal.h"
#include "bootstruct.h"
#include "pci.h"
#include "gma.h"
#include "modules.h"
#define kGraphicsEnablerKey"GraphicsEnabler"
void GraphicsEnabler_hook(void* arg1, void* arg2, void* arg3, void* arg4);
void IntelGraphicsEnabler_start()
{
register_hook_callback("PCIDevice", &GraphicsEnabler_hook);
}
void GraphicsEnabler_hook(void* arg1, void* arg2, void* arg3, void* arg4)
{
pci_dt_t* current = arg1;
if (current->class_id != PCI_CLASS_DISPLAY_VGA) return;
char *devicepath = get_pci_dev_path(current);
bool do_gfx_devprop = true;
getBoolForKey(kGraphicsEnablerKey, &do_gfx_devprop, &bootInfo->bootConfig);
if (do_gfx_devprop && (current->vendor_id == PCI_VENDOR_ID_INTEL))
{
verbose("Intel VGA Controller [%04x:%04x] :: %s \n",
current->vendor_id, current->device_id, devicepath);
setup_gma_devprop(current);
}
else
verbose("[%04x:%04x] :: %s, is not a Intel VGA Controller.\n",
current->vendor_id, current->device_id, devicepath);
}
branches/iFabio/Chameleon/i386/modules/GraphicsEnabler/IntelGraphicsEnabler/Cconfig
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#
# Chameleon Modules
#
config INTELGRAPHICSENABLER_MODULE
tristate "IntelGraphicsEnabler Module"
default m
---help---
Say Y here if you want to enable the use of this module.
branches/iFabio/Chameleon/i386/modules/GraphicsEnabler/IntelGraphicsEnabler/gma.h
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#ifndef __LIBSAIO_GMA_H
#define __LIBSAIO_GMA_H
bool setup_gma_devprop(pci_dt_t *gma_dev);
struct gma_gpu_t {
unsigned device;
char *name;
};
#define REG8(reg) ((volatile uint8_t *)regs)[(reg)]
#define REG16(reg) ((volatile uint16_t *)regs)[(reg) >> 1]
#define REG32(reg) ((volatile uint32_t *)regs)[(reg) >> 2]
#endif /* !__LIBSAIO_GMA_H */
branches/iFabio/Chameleon/i386/modules/GraphicsEnabler/IntelGraphicsEnabler/Readme.txt
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Module:IntelGraphicsEnabler
Description: Enables "some" ?? Intel cards to be used out of the box ?? in OS X.
This was converted from ...
Dependencies: none
Keys: GraphicsEnabler (enabled by default)
TODO: ---
branches/iFabio/Chameleon/i386/modules/GraphicsEnabler/IntelGraphicsEnabler/Makefile
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MODULE_NAME = IntelGraphicsEnabler
MODULE_DESCRIPTION = This module provides
MODULE_AUTHOR =
MODULE_VERSION = "1.0.0"
MODULE_COMPAT_VERSION = "1.0.0"
MODULE_START = $(MODULE_NAME)_start
MODULE_DEPENDENCIES =
DIR = IntelGraphicsEnabler
MODULE_OBJS = gma.o IntelGraphicsEnabler.o
include ../MakeInc.dir
branches/iFabio/Chameleon/i386/modules/GraphicsEnabler/ATiGraphicsEnabler/ati.h
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/*
* ATI injector
*
* Copyright (C) 2009 Jasmin Fazlic, iNDi, netkas
*
* ATI injector is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* ATI driver and injector is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with ATI injector. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Alternatively you can choose to comply with APSL
*/
#ifndef __LIBSAIO_ATI_H
#define __LIBSAIO_ATI_H
bool setup_ati_devprop(pci_dt_t *ati_dev);
struct ati_chipsets_t {
unsigned device;
char *name;
};
struct ati_data_key {
uint32_t size;
char *name;
uint8_t data[];
};
#define REG8(reg) ((volatile uint8_t *)regs)[(reg)]
#define REG16(reg) ((volatile uint16_t *)regs)[(reg) >> 1]
#define REG32R(reg) ((volatile uint32_t *)regs)[(reg) >> 2]
#define REG32W(reg, val) ((volatile uint32_t *)regs)[(reg) >> 2] = (val)
#endif /* !__LIBSAIO_ATI_H */
branches/iFabio/Chameleon/i386/modules/GraphicsEnabler/ATiGraphicsEnabler/ATiGraphicsEnabler.c
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/*
* ATIGraphicsEnabler Module ---
* Enables many ati "legacy ??" cards to be used out of the box in OS X.
* This was converted from ( < r784) boot2 code to a boot2 module.
*
*/
#include "saio_internal.h"
#include "bootstruct.h"
#include "pci.h"
#include "ati.h"
#include "modules.h"
#define kGraphicsEnablerKey"GraphicsEnabler" // change?
void GraphicsEnabler_hook(void* arg1, void* arg2, void* arg3, void* arg4);
void ATiGraphicsEnabler_start()
{
register_hook_callback("PCIDevice", &GraphicsEnabler_hook);
}
void GraphicsEnabler_hook(void* arg1, void* arg2, void* arg3, void* arg4)
{
pci_dt_t* current = arg1;
if (current->class_id != PCI_CLASS_DISPLAY_VGA) return;
char *devicepath = get_pci_dev_path(current);
bool do_gfx_devprop = true;
getBoolForKey(kGraphicsEnablerKey, &do_gfx_devprop, &bootInfo->bootConfig);
// AMD ?? i don't find any vga 1022 vendor!.. thou ATI isn't used anymore!
if (do_gfx_devprop && (current->vendor_id == PCI_VENDOR_ID_ATI))
{
verbose("ATI VGA Controller [%04x:%04x] :: %s \n",
current->vendor_id, current->device_id, devicepath);
setup_ati_devprop(current);
}
else
verbose("[%04x:%04x] :: %s, is not a AMD/ATI VGA Controller.\n",// amd ??
current->vendor_id, current->device_id, devicepath);
}
branches/iFabio/Chameleon/i386/modules/GraphicsEnabler/ATiGraphicsEnabler/Cconfig
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#
# Chameleon Modules
#
config ATIGRAPHICSENABLER_MODULE
tristate "ATiGraphicsEnabler Module"
default m
---help---
Say Y here if you want to enable the use of this module.
branches/iFabio/Chameleon/i386/modules/GraphicsEnabler/ATiGraphicsEnabler/Readme.txt
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Module:ATiGraphicsEnabler
Description: the GraphicsEnabler ATI code ( < r784) ported to a module.
Support for "legacy" cards...
Based on Meklort's work.
Dependencies: none
Keys: GraphicsEnabler(enabled by default)
UseAtiROM(disabled by default)
TODO:
- naming: ATi or AMD ??
- merge with AMDGraphicsEnabler ??
branches/iFabio/Chameleon/i386/modules/GraphicsEnabler/ATiGraphicsEnabler/Makefile
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MODULE_NAME = ATiGraphicsEnabler
MODULE_DESCRIPTION = This module provides
MODULE_AUTHOR =
MODULE_VERSION = "1.0.0"
MODULE_COMPAT_VERSION = "1.0.0"
MODULE_START = $(MODULE_NAME)_start
MODULE_DEPENDENCIES =
DIR = ATiGraphicsEnabler
MODULE_OBJS = ati.o ATiGraphicsEnabler.o
include ../MakeInc.dir
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/*
* ATI injector
*
* Copyright (C) 2009 Jasmin Fazlic, iNDi, netkas
*
* ATI injector is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* ATI driver and injector is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with ATI injector. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Alternatively you can choose to comply with APSL
*/
#include "libsa.h"
#include "saio_internal.h"
#include "bootstruct.h"
#include "pci.h"
#include "platform.h"
#include "device_inject.h"
#include "ati.h"
#ifndef DEBUG_ATI
#define DEBUG_ATI 0
#endif
#if DEBUG_ATI
#define DBG(x...)printf(x)
#else
#define DBG(x...)
#endif
#define kUseAtiROMKey"UseAtiROM"
#define MAX_NUM_DCB_ENTRIES 16
#define TYPE_GROUPED 0xff
extern uint32_t devices_number;
const char *ati_compatible_0[]= { "@0,compatible", "ATY,%s" };
const char *ati_compatible_1[]= { "@1,compatible", "ATY,%s" };
const char *ati_device_type_0[]= { "@0,device_type", "display" };
const char *ati_device_type_1[]= { "@1,device_type", "display" };
const char *ati_device_type[]= { "device_type", "ATY,%sParent" };
const char *ati_name_0[]= { "@0,name", "ATY,%s" };
const char *ati_name_1[]= { "@1,name", "ATY,%s" };
const char *ati_name[]= { "name", "ATY,%sParent" };
const char *ati_efidisplay_0[]= { "@0,ATY,EFIDisplay", "TMDSB" };
struct ati_data_key ati_connector_type_0= { 0x04, "@0,connector-type", {0x00, 0x04, 0x00, 0x00} };
struct ati_data_key ati_connector_type_1= { 0x04, "@1,connector-type", {0x04, 0x00, 0x00, 0x00} };
struct ati_data_key ati_display_con_fl_type_0= { 0x04, "@0,display-connect-flags", {0x00, 0x00, 0x04, 0x00} };
const char *ati_display_type_0[]= { "@0,display-type", "LCD" };
const char *ati_display_type_1[]= { "@1,display-type", "NONE" };
struct ati_data_key ati_aux_power_conn= { 0x04, "AAPL,aux-power-connected", {0x01, 0x00, 0x00, 0x00} };
struct ati_data_key ati_backlight_ctrl= { 0x04, "AAPL,backlight-control", {0x00, 0x00, 0x00, 0x00} };
struct ati_data_key ati_aapl01_coher= { 0x04, "AAPL01,Coherency", {0x01, 0x00, 0x00, 0x00} };
const char *ati_card_no[]= { "ATY,Card#", "109-B77101-00" };
const char *ati_copyright[]= { "ATY,Copyright", "Copyright AMD Inc. All Rights Reserved. 2005-2009" };
const char *ati_efi_compile_d[]= { "ATY,EFICompileDate", "Jan 26 2009" };
struct ati_data_key ati_efi_disp_conf= { 0x08, "ATY,EFIDispConfig", {0x45, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01} };
struct ati_data_key ati_efi_drv_type= { 0x01, "ATY,EFIDriverType", {0x02} };
struct ati_data_key ati_efi_enbl_mode= { 0x01, "ATY,EFIEnabledMode", {0x01} };
struct ati_data_key ati_efi_init_stat= { 0x04, "ATY,EFIHWInitStatus", {0x00, 0x00, 0x00, 0x00} };
struct ati_data_key ati_efi_orientation= { 0x02, "ATY,EFIOrientation", {0x02, 0x00} };
const char *ati_efi_version[]= { "ATY,EFIVersion", "01.00.318" };
const char *ati_efi_versionB[]= { "ATY,EFIVersionB", "113-SBSJ1G04-00R-02" };
const char *ati_efi_versionE[]= { "ATY,EFIVersionE", "113-B7710A-318" };
struct ati_data_key ati_mclk= { 0x04, "ATY,MCLK", {0x70, 0x2e, 0x11, 0x00} };
struct ati_data_key ati_mem_rev_id= { 0x02, "ATY,MemRevisionID", {0x03, 0x00} };
struct ati_data_key ati_mem_vend_id= { 0x02, "ATY,MemVendorID", {0x02, 0x00} };
const char *ati_mrt[]= { "ATY,MRT", " " };
const char *ati_romno[]= { "ATY,Rom#", "113-B7710C-176" };
struct ati_data_key ati_sclk= { 0x04, "ATY,SCLK", {0x28, 0xdb, 0x0b, 0x00} };
struct ati_data_key ati_vendor_id= { 0x02, "ATY,VendorID", {0x02, 0x10} };
struct ati_data_key ati_platform_info= { 0x80, "ATY,PlatformInfo", {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} };
struct ati_data_key ati_mvad= { 0x40, "MVAD", {0x3f, 0x5c, 0x82, 0x02, 0xff, 0x90, 0x00, 0x54, 0x60, 0x00, 0xac, 0x10, 0xa0, 0x17, 0x00, 0x03, 0xb0, 0x68, 0x00, 0x0a, 0xa0, 0x0a, 0x30, 0x00, 0x20, 0x00, 0x40, 0x06, 0x6e, 0x06, 0x03, 0x00, 0x06, 0x00, 0x40, 0x06, 0x00, 0x0a, 0x10, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x21, 0x00, 0x10, 0x06, 0x92, 0x20, 0x00, 0x03} };
struct ati_data_key ati_saved_config= { 0x100, "saved-config", {0x3f, 0x5c, 0x82, 0x02, 0xff, 0x90, 0x00, 0x54, 0x60, 0x00, 0xac, 0x10, 0xa0, 0x17, 0x00, 0x03, 0xb0, 0x68, 0x00, 0x0a, 0xa0, 0x0a, 0x30, 0x00, 0x20, 0x00, 0x40, 0x06, 0x6e, 0x06, 0x03, 0x00, 0x06, 0x00, 0x40, 0x06, 0x00, 0x0a, 0x10, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x21, 0x00, 0x10, 0x06, 0x92, 0x20, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0xee, 0x02, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x31, 0x30, 0x50, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x32, 0x32, 0x32, 0x01, 0x00, 0x00, 0x00, 0x00, 0x02, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} };
///non 48xx keys
const char *ati_efidisplay_0_n4[]= { "@0,ATY,EFIDisplay", "TMDSA" };
struct ati_data_key ati_connector_type_0_n4= { 0x04, "@0,connector-type", {0x04, 0x00, 0x00, 0x00} };
struct ati_data_key ati_connector_type_1_n4= { 0x04, "@1,connector-type", {0x00, 0x02, 0x00, 0x00} };
struct ati_data_key ati_aapl_emc_disp_list_n4= { 0x40, "AAPL,EMC-Display-List", {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x10, 0x00, 0x00, 0x1b, 0x92, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x10, 0x00, 0x00, 0x1c, 0x92, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x10, 0x00, 0x00, 0x21, 0x92, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} };
struct ati_data_key ati_fb_offset_n4= { 0x08, "ATY,FrameBufferOffset", {0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00} };
struct ati_data_key ati_hwgpio_n4= { 0x04, "ATY,HWGPIO", {0x23, 0xa8, 0x48, 0x00} };
struct ati_data_key ati_iospace_offset_n4= { 0x08, "ATY,IOSpaceOffset", {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00} };
struct ati_data_key ati_mclk_n4= { 0x04, "ATY,MCLK", {0x00, 0x35, 0x0c, 0x00} };
struct ati_data_key ati_sclk_n4= { 0x04, "ATY,SCLK", {0x60, 0xae, 0x0a, 0x00} };
struct ati_data_key ati_refclk_n4= { 0x04, "ATY,RefCLK", {0x8c, 0x0a, 0x00, 0x00} };
struct ati_data_key ati_regspace_offset_n4= { 0x08, "ATY,RegisterSpaceOffset", {0x00, 0x00, 0x00, 0x00, 0x90, 0xa2, 0x00, 0x00} };
struct ati_data_key ati_vram_memsize_0= { 0x08, "@0,VRAM,memsize", {0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00} };
struct ati_data_key ati_vram_memsize_1= { 0x08, "@1,VRAM,memsize", {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} };
struct ati_data_key ati_aapl_blackscr_prefs_0_n4= { 0x04, "AAPL00,blackscreen-preferences", {0x00, 0x00, 0x00, 0x00} };
struct ati_data_key ati_aapl_blackscr_prefs_1_n4= { 0x04, "AAPL01,blackscreen-preferences", {0x00, 0x00, 0x00, 0x00} };
struct ati_data_key ati_swgpio_info_n4= { 0x04, "ATY,SWGPIO Info", {0x00, 0x48, 0xa8, 0x23} };
struct ati_data_key ati_efi_orientation_n4= { 0x01, "ATY,EFIOrientation", {0x08} };
struct ati_data_key ati_mvad_n4= { 0x100, "MVAD", {0x3e, 0x5c, 0x82, 0x00, 0xff, 0x90, 0x00, 0xf6, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x28, 0x3c, 0x80, 0x07, 0x20, 0x08, 0x30, 0x00, 0x20, 0x00, 0xb0, 0x04, 0xd3, 0x04, 0x03, 0x00, 0x06, 0x00, 0xb0, 0x04, 0x80, 0x07, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x90, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x31, 0x30, 0x50, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x32, 0x32, 0x32, 0x01, 0x00, 0x00, 0x00, 0x00, 0x02, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} };
struct ati_data_key ati_saved_config_n4= { 0x100, "saved-config", {0x3e, 0x5c, 0x82, 0x00, 0xff, 0x90, 0x00, 0xf6, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x28, 0x3c, 0x80, 0x07, 0x20, 0x08, 0x30, 0x00, 0x20, 0x00, 0xb0, 0x04, 0xd3, 0x04, 0x03, 0x00, 0x06, 0x00, 0xb0, 0x04, 0x80, 0x07, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x90, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x31, 0x30, 0x50, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x32, 0x32, 0x32, 0x01, 0x00, 0x00, 0x00, 0x00, 0x02, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} };
struct pcir_s {
uint32_t signature;
uint16_t vid;
uint16_t devid;
};
// Known cards as of 2008/08/26
static struct ati_chipsets_t ATIKnownChipsets[] = {
{ 0x00000000, "Unknown" } ,
//{ 0x10027181, "ATI Radeon 1300 Series"} ,
{ 0x10029589, "ATI Radeon 2600 Series"} ,
{ 0x10029588, "ATI Radeon 2600 Series"} ,
{ 0x100294C3, "ATI Radeon 2400 Series"} ,
{ 0x100294C4, "ATI Radeon 2400 Series"} ,
{ 0x100294C6, "ATI Radeon 2400 Series"} ,
{ 0x10029400, "ATI Radeon 2900 Series"} ,
{ 0x10029405, "ATI Radeon 2900GT Series"} ,
{ 0x10029581, "ATI Radeon 2600 Series"} ,
{ 0x10029583, "ATI Radeon 2600 Series"} ,
{ 0x10029586, "ATI Radeon 2600 Series"} ,
{ 0x10029587, "ATI Radeon 2600 Series"} ,
{ 0x100294C9, "ATI Radeon 2400 Series"} ,
{ 0x10029501, "ATI Radeon 3800 Series"} ,
{ 0x10029505, "ATI Radeon 3800 Series"} ,
{ 0x10029515, "ATI Radeon 3800 Series"} ,
{ 0x10029507, "ATI Radeon 3800 Series"} ,
{ 0x10029500, "ATI Radeon 3800 Series"} ,
{ 0x1002950F, "ATI Radeon 3800X2 Series"} ,
{ 0x100295C5, "ATI Radeon 3400 Series"} ,
{ 0x100295C7, "ATI Radeon 3400 Series"} ,
{ 0x100295C0, "ATI Radeon 3400 Series"} ,
{ 0x10029596, "ATI Radeon 3600 Series"} ,
{ 0x10029590, "ATI Radeon 3600 Series"} ,
{ 0x10029599, "ATI Radeon 3600 Series"} ,
{ 0x10029597, "ATI Radeon 3600 Series"} ,
{ 0x10029598, "ATI Radeon 3600 Series"} ,
{ 0x10029442, "ATI Radeon 4850 Series"} ,
{ 0x10029440, "ATI Radeon 4870 Series"} ,
{ 0x1002944C, "ATI Radeon 4830 Series"} ,
{ 0x10029460, "ATI Radeon 4890 Series"} ,
{ 0x10029462, "ATI Radeon 4890 Series"} ,
{ 0x10029441, "ATI Radeon 4870X2 Series"} ,
{ 0x10029443, "ATI Radeon 4850X2 Series"} ,
{ 0x10029444, "ATI Radeon 4800 Series"} ,
{ 0x10029446, "ATI Radeon 4800 Series"} ,
{ 0x1002944E, "ATI Radeon 4730 Series"} ,
{ 0x10029450, "ATI Radeon 4800 Series"} ,
{ 0x10029452, "ATI Radeon 4800 Series"} ,
{ 0x10029456, "ATI Radeon 4800 Series"} ,
{ 0x1002944A, "ATI Radeon 4800 Mobility Series"} ,
{ 0x1002945A, "ATI Radeon 4800 Mobility Series"} ,
{ 0x1002945B, "ATI Radeon 4800 Mobility Series"} ,
{ 0x1002944B, "ATI Radeon 4800 Mobility Series"} ,
{ 0x10029490, "ATI Radeon 4670 Series"} ,
{ 0x10029498, "ATI Radeon 4650 Series"} ,
{ 0x10029490, "ATI Radeon 4600 Series"} ,
{ 0x10029498, "ATI Radeon 4600 Series"} ,
{ 0x1002949E, "ATI Radeon 4600 Series"} ,
{ 0x10029480, "ATI Radeon 4600 Series"} ,
{ 0x10029488, "ATI Radeon 4600 Series"} ,
{ 0x10029540, "ATI Radeon 4500 Series"} ,
{ 0x10029541, "ATI Radeon 4500 Series"} ,
{ 0x1002954E, "ATI Radeon 4500 Series"} ,
{ 0x10029552, "ATI Radeon 4300 Mobility Series"} ,
{ 0x10029553, "ATI Radeon 4500 Mobility Series"} ,
{ 0x1002954F, "ATI Radeon 4300 Series"} ,
{ 0x100294B3, "ATI Radeon 4770 Series"} ,
{ 0x100294B5, "ATI Radeon 4770 Series"} ,
{ 0x100268B8, "ATI Radeon 5700 Series"} ,
{ 0x100268BE, "ATI Radeon 5700 Series"} ,
{ 0x10026898, "ATI Radeon 5800 Series"} ,
{ 0x10026899, "ATI Radeon 5800 Series"}
};
static struct ati_chipsets_t ATIKnownFramebuffers[] = {
{ 0x00000000, "Megalodon" },
//{ 0x10027181, "Caretta" },
{ 0x10029589, "Lamna"} ,
{ 0x10029588, "Lamna"} ,
{ 0x100294C3, "Iago"} ,
{ 0x100294C4, "Iago"} ,
{ 0x100294C6, "Iago"} ,
{ 0x10029400, "Franklin"} ,
{ 0x10029405, "Franklin"} ,
{ 0x10029581, "Hypoprion"} ,
{ 0x10029583, "Hypoprion"} ,
{ 0x10029586, "Hypoprion"} ,
{ 0x10029587, "Hypoprion"} ,
{ 0x100294C9, "Iago"} ,
{ 0x10029501, "Megalodon"} ,
{ 0x10029505, "Megalodon"} ,
{ 0x10029515, "Megalodon"} ,
{ 0x10029507, "Megalodon"} ,
{ 0x10029500, "Megalodon"} ,
{ 0x1002950F, "Triakis"} ,
{ 0x100295C5, "Iago"} ,
{ 0x100295C7, "Iago"} ,
{ 0x100295C0, "Iago"} ,
{ 0x10029596, "Megalodon"} ,
{ 0x10029590, "Megalodon"} ,
{ 0x10029599, "Megalodon"} ,
{ 0x10029597, "Megalodon"} ,
{ 0x10029598, "Megalodon"} ,
{ 0x10029442, "Motmot"} ,
{ 0x10029440, "Motmot"} ,
{ 0x1002944C, "Motmot"} ,
{ 0x10029460, "Motmot"} ,
{ 0x10029462, "Motmot"} ,
{ 0x10029441, "Motmot"} ,
{ 0x10029443, "Motmot"} ,
{ 0x10029444, "Motmot"} ,
{ 0x10029446, "Motmot"} ,
{ 0x1002944E, "Motmot"} ,
{ 0x10029450, "Motmot"} ,
{ 0x10029452, "Motmot"} ,
{ 0x10029456, "Motmot"} ,
{ 0x1002944A, "Motmot"} ,
{ 0x1002945A, "Motmot"} ,
{ 0x1002945B, "Motmot"} ,
{ 0x1002944B, "Motmot"} ,
{ 0x10029490, "Peregrine"} ,
{ 0x10029498, "Peregrine"} ,
{ 0x1002949E, "Peregrine"} ,
{ 0x10029480, "Peregrine"} ,
{ 0x10029488, "Peregrine"} ,
{ 0x10029540, "Peregrine"} ,
{ 0x10029541, "Peregrine"} ,
{ 0x1002954E, "Peregrine"} ,
{ 0x10029552, "Peregrine"} ,
{ 0x10029553, "Peregrine"} ,
{ 0x1002954F, "Peregrine"} ,
{ 0x100294B3, "Peregrine"},
{ 0x100294B5, "Peregrine"},
{ 0x100268B8, "Motmot"},
{ 0x100268BE, "Motmot"},
{ 0x10026898, "Motmot"},
{ 0x10026899, "Motmot"}
};
static uint32_t accessROM(pci_dt_t *ati_dev, unsigned int mode)
{
uint32_tbar[7];
volatile uint32_t*regs;
bar[2] = pci_config_read32(ati_dev->dev.addr, 0x18 );
regs = (uint32_t *) (bar[2] & ~0x0f);
if (mode) {
if (mode != 1) {
return 0xe00002c7;
}
REG32W(0x179c, 0x00080000);
REG32W(0x1798, 0x00080721);
REG32W(0x17a0, 0x00080621);
REG32W(0x1600, 0x14030300);
REG32W(0x1798, 0x21);
REG32W(0x17a0, 0x21);
REG32W(0x179c, 0x00);
REG32W(0x17a0, 0x21);
REG32W(0x1798, 0x21);
REG32W(0x1798, 0x21);
} else {
REG32W(0x1600, 0x14030302);
REG32W(0x1798, 0x21);
REG32W(0x17a0, 0x21);
REG32W(0x179c, 0x00080000);
REG32W(0x17a0, 0x00080621);
REG32W(0x1798, 0x00080721);
REG32W(0x1798, 0x21);
REG32W(0x17a0, 0x21);
REG32W(0x179c, 0x00);
REG32W(0x1604, 0x0400e9fc);
REG32W(0x161c, 0x00);
REG32W(0x1620, 0x9f);
REG32W(0x1618, 0x00040004);
REG32W(0x161c, 0x00);
REG32W(0x1604, 0xe9fc);
REG32W(0x179c, 0x00080000);
REG32W(0x1798, 0x00080721);
REG32W(0x17a0, 0x00080621);
REG32W(0x1798, 0x21);
REG32W(0x17a0, 0x21);
REG32W(0x179c, 0x00);
}
return 0;
}
static uint8_t *readAtomBIOS(pci_dt_t *ati_dev)
{
uint32_tbar[7];
uint32_t*BIOSBase;
uint32_tcounter;
volatile uint32_t*regs;
bar[2] = pci_config_read32(ati_dev->dev.addr, 0x18 );
regs = (volatile uint32_t *) (bar[2] & ~0x0f);
accessROM(ati_dev, 0);
REG32W(0xa8, 0);
REG32R(0xac);
REG32W(0xa8, 0);
REG32R(0xac);
BIOSBase = malloc(0x10000);
REG32W(0xa8, 0);
BIOSBase[0] = REG32R(0xac);
counter = 4;
do {
REG32W(0xa8, counter);
BIOSBase[counter/4] = REG32R(0xac);
counter +=4;
} while (counter != 0x10000);
accessROM((pci_dt_t *)regs, 1);
if (*(uint16_t *)BIOSBase != 0xAA55) {
printf("Wrong BIOS signature: %04x\n", *(uint16_t *)BIOSBase);
return 0;
}
return (uint8_t *)BIOSBase;
}
#define R5XX_CONFIG_MEMSIZE0x00F8 //Azi:---
#define R6XX_CONFIG_MEMSIZE0x5428
uint32_t getvramsizekb(pci_dt_t *ati_dev)
{
uint32_tbar[7];
uint32_tsize;
volatile uint32_t*regs;
bar[2] = pci_config_read32(ati_dev->dev.addr, 0x18 );
regs = (uint32_t *) (bar[2] & ~0x0f);
if (ati_dev->device_id < 0x9400) {
size = (REG32R(R5XX_CONFIG_MEMSIZE)) >> 10;
} else {
size = (REG32R(R6XX_CONFIG_MEMSIZE)) >> 10;
}
return size;
}
#define AVIVO_D1CRTC_CONTROL0x6080
#define AVIVO_CRTC_EN(1<<0)
#define AVIVO_D2CRTC_CONTROL0x6880
static bool radeon_card_posted(pci_dt_t *ati_dev)
{
// if devid matches biosimage(from legacy) devid - posted card, fails with X2/crossfire cards.
/*char *biosimage = 0xC0000;
if ((uint8_t)biosimage[0] == 0x55 && (uint8_t)biosimage[1] == 0xaa)
{
option_rom_pci_header_t *rom_pci_header;
rom_pci_header = (option_rom_pci_header_t*)(biosimage + (uint8_t)biosimage[24] + (uint8_t)biosimage[25]*256);
if (rom_pci_header->signature == 0x52494350)
{
if (rom_pci_header->device_id == ati_dev->device_id)
{
return true;
printf("Card was POSTed\n");
}
}
}
return false;
printf("Card was not POSTed\n");
*/
//fails yet
uint32_tbar[7];
uint32_tval;
volatile uint32_t*regs;
bar[2] = pci_config_read32(ati_dev->dev.addr, 0x18);
regs = (uint32_t *) (bar[2] & ~0x0f);
val = REG32R(AVIVO_D1CRTC_CONTROL) | REG32R(AVIVO_D2CRTC_CONTROL);
if (val & AVIVO_CRTC_EN) {
return true;
} else {
return false;
}
}
static uint32_t load_ati_bios_file(const char *filename, uint8_t *buf, int bufsize)
{
intfd;
intsize;
if ((fd = open_bvdev("bt(0,0)", filename, 0)) < 0) {
return 0;
}
size = file_size(fd);
if (size > bufsize) {
printf("Filesize of %s is bigger than expected! Truncating to 0x%x Bytes!\n", filename, bufsize);
size = bufsize;
}
size = read(fd, (char *)buf, size);
close(fd);
return size > 0 ? size : 0;
}
static char *get_ati_model(uint32_t id)
{
int i;
for (i = 0; i < (sizeof(ATIKnownChipsets) / sizeof(ATIKnownChipsets[0])); i++) {
if (ATIKnownChipsets[i].device == id) {
return ATIKnownChipsets[i].name;
}
}
return ATIKnownChipsets[0].name;
}
static char *get_ati_fb(uint32_t id)
{
inti;
for (i = 0; i < (sizeof(ATIKnownFramebuffers) / sizeof(ATIKnownFramebuffers[0])); i++) {
if (ATIKnownFramebuffers[i].device == id) {
return ATIKnownFramebuffers[i].name;
}
}
return ATIKnownFramebuffers[0].name;
}
static int devprop_add_iopciconfigspace(struct DevPropDevice *device, pci_dt_t *ati_dev)
{
inti;
uint8_t*config_space;
if (!device || !ati_dev) {
return 0;
}
verbose("dumping pci config space, 256 bytes\n");
config_space = malloc(256);
for (i=0; i<=255; i++) {
config_space[i] = pci_config_read8( ati_dev->dev.addr, i);
}
devprop_add_value(device, "ATY,PCIConfigSpace", config_space, 256);
free (config_space);
return 1;
}
static int devprop_add_ati_template_4xxx(struct DevPropDevice *device)
{
if(!device)
return 0;
//if(!DP_ADD_TEMP_VAL(device, ati_compatible_0))
//return 0;
//if(!DP_ADD_TEMP_VAL(device, ati_compatible_1))
//return 0;
if(!DP_ADD_TEMP_VAL(device, ati_device_type_0))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_device_type_1))
return 0;
//if(!DP_ADD_TEMP_VAL(device, ati_device_type))
//return 0;
//if(!DP_ADD_TEMP_VAL(device, ati_name_0))
//return 0;
//if(!DP_ADD_TEMP_VAL(device, ati_name_1))
//return 0;
//if(!DP_ADD_TEMP_VAL(device, ati_name))
//return 0;
if(!DP_ADD_TEMP_VAL(device, ati_efidisplay_0))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_display_type_0))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_display_type_1))
return 0;
//if(!DP_ADD_TEMP_VAL(device, ati_slot_name))
//return 0;
if(!DP_ADD_TEMP_VAL(device, ati_card_no))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_copyright))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_efi_compile_d))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_efi_version))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_efi_versionB))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_efi_versionE))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_mrt))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_romno))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_name_1))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_connector_type_0))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_connector_type_1))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_display_con_fl_type_0))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_aux_power_conn))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_backlight_ctrl))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_aapl01_coher))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_disp_conf))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_drv_type))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_enbl_mode))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_init_stat))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_orientation))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_mclk))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_mem_rev_id))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_mem_vend_id))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_sclk))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_vendor_id))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_platform_info))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_mvad))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_saved_config))
return 0;
return 1;
}
static int devprop_add_ati_template(struct DevPropDevice *device)
{
if(!device)
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_platform_info))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_device_type_0))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_device_type_1))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_efidisplay_0_n4))
return 0;
//if(!DP_ADD_TEMP_VAL(device, ati_slot_name_n4))
//return 0;
if(!DP_ADD_TEMP_VAL(device, ati_card_no))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_copyright))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_efi_compile_d))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_efi_version))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_efi_versionB))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_efi_versionE))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_mrt))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_romno))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_name_1))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_connector_type_0_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_connector_type_1_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_aux_power_conn))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_backlight_ctrl))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_aapl01_coher))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_drv_type))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_enbl_mode))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_mem_rev_id))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_mem_vend_id))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_vendor_id))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_aapl_emc_disp_list_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_fb_offset_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_hwgpio_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_iospace_offset_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_mclk_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_sclk_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_refclk_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_regspace_offset_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_orientation_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_aapl_blackscr_prefs_0_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_aapl_blackscr_prefs_1_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_swgpio_info_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_orientation_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_mvad_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_saved_config_n4))
return 0;
return 1;
}
bool setup_ati_devprop(pci_dt_t *ati_dev)
{
struct DevPropDevice*device;
char*devicepath;
char*model;
char*framebuffer;
char tmp[64];
uint8_t*rom = NULL;
uint32_t rom_size = 0;
option_rom_pci_header_t *rom_pci_header;
uint8_t*bios;
uint32_t bios_size;
uint32_t vram_size;
uint32_t boot_display;
uint8_t&