Chameleon Applications

Chameleon Applications Commit Details

Date:2011-06-07 04:04:42 (3 years 4 months ago)
Author:ErmaC
Commit:312
Parents: 311
Message:Minus update on module folder from azi branch
Changes:
M/branches/iFabio/Chameleon/i386/modules/GraphicsEnabler/NVIDIAGraphicsEnabler/Readme.txt
M/branches/iFabio/Chameleon/i386/modules/GraphicsEnabler/NVIDIAGraphicsEnabler/nvidia.c
M/branches/iFabio/Chameleon/i386/modules/GraphicsEnabler/IntelGraphicsEnabler/Readme.txt
M/branches/iFabio/Chameleon/i386/modules/GraphicsEnabler/NVIDIAGraphicsEnabler/Makefile
M/branches/iFabio/Chameleon/i386/modules/GraphicsEnabler/IntelGraphicsEnabler/Makefile
M/branches/iFabio/Chameleon/i386/modules/GraphicsEnabler/ATiGraphicsEnabler/Makefile
M/branches/iFabio/Chameleon/i386/modules/GraphicsEnabler/ATiGraphicsEnabler/ati.c
M/branches/iFabio/Chameleon/i386/modules/GraphicsEnabler/AMDGraphicsEnabler/Readme.txt
M/branches/iFabio/Chameleon/i386/modules/GraphicsEnabler/AMDGraphicsEnabler/AMDGraphicsEnabler.c
M/branches/iFabio/Chameleon/i386/modules/GraphicsEnabler/AMDGraphicsEnabler/Makefile
M/branches/iFabio/Chameleon/i386/modules/GraphicsEnabler/AMDGraphicsEnabler/ati.c
M/branches/iFabio/Chameleon/i386/modules/GraphicsEnabler/NVIDIAGraphicsEnabler/NVIDIAGraphicsEnabler.c
M/branches/iFabio/Chameleon/i386/modules/GraphicsEnabler/IntelGraphicsEnabler/gma.c
M/branches/iFabio/Chameleon/i386/modules/GraphicsEnabler/AMDGraphicsEnabler/ati_reg.h
M/branches/iFabio/Chameleon/i386/modules/GraphicsEnabler/IntelGraphicsEnabler/IntelGraphicsEnabler.c

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branches/iFabio/Chameleon/i386/modules/GraphicsEnabler/NVIDIAGraphicsEnabler/NVIDIAGraphicsEnabler.c
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/*
* GraphicsEnabler Module
*Enabled many nvidia and ati cards to be used out of the box in
*OS X. This was converted from boot2 code to a boot2 module.
*NVIDIAGraphicsEnabler Module
*Enables many nVidia cards to be used out of the box in OS X.
*This was converted from boot2 code to a boot2 module.
*
*/
#include "nvidia.h"
#include "modules.h"
#define kGraphicsEnablerKey "GraphicsEnabler"
#define kGraphicsEnablerKey"GraphicsEnabler"
void GraphicsEnabler_hook(void* arg1, void* arg2, void* arg3, void* arg4);
branches/iFabio/Chameleon/i386/modules/GraphicsEnabler/NVIDIAGraphicsEnabler/Readme.txt
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Module:GraphicsEnabler
Description: the GraphicsEnabler nVidia code ported to a module.
Based on Meklort's work.
If your card is supported and you find it missing
on this code, please file an issue at:
http://forge.voodooprojects.org/p/chameleon/issues/
Only cards known to work will be added.
Dependencies: none
Keys: GraphicsEnabler(enabled by default)
UseNvidiaROM(disabled by default)
VBIOS...
Keys: GraphicsEnablerYes/No (enabled by default)
Disable GraphicsEnabler patch.
UseNvidiaROMYes/No (disabled by default)
Enable the use of a custom VBIOS ROM image.
VBIOSYes/No (disabled by default)
Adds "vbios" property to ioreg. ??? Azi: confirm
Adaptation of Meklort's work.
TODO: ---
TODO: review "nv_chipsets_t NVKnownChipsets"
branches/iFabio/Chameleon/i386/modules/GraphicsEnabler/NVIDIAGraphicsEnabler/nvidia.c
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/*
* NVidia injector
*NVidia injector
*
* Copyright (C) 2009 Jasmin Fazlic, iNDi
*Copyright (C) 2009Jasmin Fazlic, iNDi
*
* NVidia injector is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*NVidia injector is free software: you can redistribute it and/or modify
*it under the terms of the GNU General Public License as published by
*the Free Software Foundation, either version 3 of the License, or
*(at your option) any later version.
*
* NVidia driver and injector is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*NVidia driver and injector is distributed in the hope that it will be useful,
*but WITHOUT ANY WARRANTY; without even the implied warranty of
*MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
*GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with NVidia injector. If not, see <http://www.gnu.org/licenses/>.
*You should have received a copy of the GNU General Public License
*along with NVidia injector. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Alternatively you can choose to comply with APSL
#include "libsa.h"
#include "saio_internal.h"
#include "bootstruct.h"
#include "pci.h"
#include "platform.h"
#define DBG(x...)
#endif
#define kUseNvidiaROM"UseNvidiaROM"
#define kVBIOS"VBIOS"
#define kUseNvidiaROM"UseNvidiaROM"
#define kVBIOS"VBIOS"
#define NVIDIA_ROM_SIZE 0x10000
#define PATCH_ROM_SUCCESS 1
#define PATCH_ROM_SUCCESS_HAS_LVDS 2
#define PATCH_ROM_FAILED 0
#define MAX_NUM_DCB_ENTRIES 16
#define NVIDIA_ROM_SIZE0x10000
#define PATCH_ROM_SUCCESS1
#define PATCH_ROM_SUCCESS_HAS_LVDS2
#define PATCH_ROM_FAILED0
#define MAX_NUM_DCB_ENTRIES16
#define TYPE_GROUPED0xff
#define TYPE_GROUPED 0xff
extern uint32_t devices_number;
const char *nvidia_compatible_0[]={ "@0,compatible","NVDA,NVMac" };
const char *nvidia_compatible_1[]={ "@1,compatible","NVDA,NVMac" };
const char *nvidia_device_type_0[]={ "@0,device_type","display" };
const char *nvidia_device_type_1[]={ "@1,device_type","display" };
const char *nvidia_device_type[]={ "device_type","NVDA,Parent" };
const char *nvidia_name_0[]={ "@0,name","NVDA,Display-A" };
const char *nvidia_name_1[]={ "@1,name","NVDA,Display-B" };
const char *nvidia_slot_name[]={ "AAPL,slot-name","Slot-1" };
const char *nvidia_compatible_0[]={ "@0,compatible","NVDA,NVMac" };
const char *nvidia_compatible_1[]={ "@1,compatible","NVDA,NVMac" };
const char *nvidia_device_type_0[]={ "@0,device_type", "display" };
const char *nvidia_device_type_1[]={ "@1,device_type", "display" };
const char *nvidia_device_type[]={ "device_type","NVDA,Parent" };
const char *nvidia_name_0[]={ "@0,name","NVDA,Display-A" };
const char *nvidia_name_1[]={ "@1,name","NVDA,Display-B" };
const char *nvidia_slot_name[]={ "AAPL,slot-name", "Slot-1" };
static uint8_t default_NVCAP[]= {
0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0d, 0x00,
#define NVCAP_LEN ( sizeof(default_NVCAP) / sizeof(uint8_t) )
static struct nv_chipsets_t NVKnownChipsets[] = {
//Azi: REVIEW and style
{ 0x00000000, "Unknown" },
{ 0x10DE0040, "GeForce 6800 Ultra" },
{ 0x10DE0041, "GeForce 6800" },
{ 0x10DE0408, "GeForce 9650M GS" },
{ 0x10DE0409, "GeForce 8700M GT" },
{ 0x10DE040A, "Quadro FX 370" },
{ 0x10DE040B, "Quadro NVS 320M" }, //Azi: 320M
{ 0x10DE040B, "Quadro NVS 320M" },
{ 0x10DE040C, "Quadro FX 570M" },
{ 0x10DE040D, "Quadro FX 1600M" },
{ 0x10DE040E, "Quadro FX 570" },
{ 0x10DE0DE2, "GeForce GT 420" },
{ 0x10DE0DEB, "GeForce GT 555M" },
{ 0x10DE0DEE, "GeForce GT 415M" },
{ 0x10DE0DF0, "GeForce GT 425M" }, //Azi: ?? GT 450M
{ 0x10DE0DF0, "GeForce GT 425M" },
{ 0x10DE0DF1, "GeForce GT 420M" },
{ 0x10DE0DF2, "GeForce GT 435M" },
{ 0x10DE0DF3, "GeForce GT 420M" },
static uint16_t read16(uint8_t *ptr, uint16_t offset)
{
uint8_t ret[2];
ret[0] = ptr[offset+1];
ret[1] = ptr[offset];
return *((uint16_t*)&ret);
}
return ((x & 0x000000FF) << 24) | ((x & 0x0000FF00) << 8 ) | ((x & 0x00FF0000) >> 8 ) | ((x & 0xFF000000) >> 24);
}
static uint8_t read8(uint8_t *ptr, uint16_t offset)
static uint8_tread8(uint8_t *ptr, uint16_t offset)
{
return ptr[offset];
}
static uint32_t read32(uint8_t *ptr, uint16_t offset)
{
uint8_t ret[4];
ret[0] = ptr[offset+3];
ret[1] = ptr[offset+2];
ret[2] = ptr[offset+1];
ret[3] = ptr[offset];
return *((uint32_t*)&ret);
}
#endif
}
uint16_t dcbptr = swap16(read16(rom, 0x36));
if(!dcbptr) {
if (!dcbptr) {
printf("no dcb table found\n");
return PATCH_ROM_FAILED;
}/* else
printf("dcb table at offset 0x%04x\n", dcbptr);
*/
uint8_t *dcbtable = &rom[dcbptr];
}
//else
//printf("dcb table at offset 0x%04x\n", dcbptr);
uint8_t *dcbtable = &rom[dcbptr];
uint8_t dcbtable_version = dcbtable[0];
uint8_t headerlength = 0;
uint8_t recordlength = 0;
uint8_t numentries = 0;
uint8_t headerlength = 0;
uint8_t recordlength = 0;
uint8_t numentries = 0;
if(dcbtable_version >= 0x20) {
if (dcbtable_version >= 0x20)
{
uint32_t sig;
if(dcbtable_version >= 0x30) {
if (dcbtable_version >= 0x30)
{
headerlength = dcbtable[1];
numentries = dcbtable[2];
numentries = dcbtable[2];
recordlength = dcbtable[3];
sig = *(uint32_t *)&dcbtable[6];
} else {
}
else
{
sig = *(uint32_t *)&dcbtable[4];
headerlength = 8;
}
if (sig != 0x4edcbdcb) {
if (sig != 0x4edcbdcb)
{
printf("bad display config block signature (0x%8x)\n", sig);
return PATCH_ROM_FAILED;
}
} else if (dcbtable_version >= 0x14) { /* some NV15/16, and NV11+ */
}
else if (dcbtable_version >= 0x14) /* some NV15/16, and NV11+ */
{
char sig[8] = { 0 };
strncpy(sig, (char *)&dcbtable[-7], 7);
recordlength = 10;
if (strcmp(sig, "DEV_REC")) {
if (strcmp(sig, "DEV_REC"))
{
printf("Bad Display Configuration Block signature (%s)\n", sig);
return PATCH_ROM_FAILED;
}
} else {
}
else
{
printf("ERROR: dcbtable_version is 0x%X\n", dcbtable_version);
return PATCH_ROM_FAILED;
}
if(numentries >= MAX_NUM_DCB_ENTRIES)
if (numentries >= MAX_NUM_DCB_ENTRIES)
numentries = MAX_NUM_DCB_ENTRIES;
uint8_t num_outputs = 0, i=0;
struct dcbentry {
uint8_t num_outputs = 0, i = 0;
struct dcbentry
{
uint8_t type;
uint8_t index;
uint8_t *heads;
} entries[numentries];
for (i = 0; i < numentries; i++) {
for (i = 0; i < numentries; i++)
{
uint32_t connection;
connection = *(uint32_t *)&dcbtable[headerlength + recordlength * i];
/* Should we allow discontinuous DCBs? Certainly DCB I2C tables can be discontinuous */
if ((connection & 0x0000000f) == 0x0000000f) /* end of records */
continue;
entries[num_outputs].type = connection & 0xf;
entries[num_outputs].index = num_outputs;
entries[num_outputs++].heads = (uint8_t*)&(dcbtable[(headerlength + recordlength * i) + 1]);
}
int has_lvds = false;
uint8_t channel1 = 0, channel2 = 0;
for(i=0; i<num_outputs; i++) {
if(entries[i].type == 3) {
for (i = 0; i < num_outputs; i++)
{
if (entries[i].type == 3)
{
has_lvds = true;
//printf("found LVDS\n");
channel1 |= ( 0x1 << entries[i].index);
entries[i].type = TYPE_GROUPED;
}
}
// if we have a LVDS output, we group the rest to the second channel
if(has_lvds) {
for(i=0; i<num_outputs; i++) {
if(entries[i].type == TYPE_GROUPED)
if (has_lvds)
{
for (i = 0; i < num_outputs; i++)
{
if (entries[i].type == TYPE_GROUPED)
continue;
channel2 |= ( 0x1 << entries[i].index);
entries[i].type = TYPE_GROUPED;
}
} else {
//
}
else
{
int x;
// we loop twice as we need to generate two channels
for(x=0; x<=1; x++) {
for(i=0; i<num_outputs; i++) {
if(entries[i].type == TYPE_GROUPED)
for (x = 0; x <= 1; x++)
{
for (i=0; i<num_outputs; i++)
{
if (entries[i].type == TYPE_GROUPED)
continue;
// if type is TMDS, the prior output is ANALOG
// we always group ANALOG and TMDS
// if there is a TV output after TMDS, we group it to that channel as well
if(i && entries[i].type == 0x2) {
switch (x) {
if (i && entries[i].type == 0x2)
{
switch (x)
{
case 0:
//printf("group channel 1\n");
channel1 |= ( 0x1 << entries[i].index);
entries[i].type = TYPE_GROUPED;
if((entries[i-1].type == 0x0)) {
if ((entries[i-1].type == 0x0))
{
channel1 |= ( 0x1 << entries[i-1].index);
entries[i-1].type = TYPE_GROUPED;
}
// group TV as well if there is one
if( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) ) {
if ( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) )
{
//printf("group tv1\n");
channel1 |= ( 0x1 << entries[i+1].index);
entries[i+1].type = TYPE_GROUPED;
}
break;
case 1:
//printf("group channel 2 : %d\n", i);
channel2 |= ( 0x1 << entries[i].index);
entries[i].type = TYPE_GROUPED;
if((entries[i-1].type == 0x0)) {
if ((entries[i - 1].type == 0x0))
{
channel2 |= ( 0x1 << entries[i-1].index);
entries[i-1].type = TYPE_GROUPED;
}
// group TV as well if there is one
if( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) ) {
if ( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) )
{
//printf("group tv2\n");
channel2 |= ( 0x1 << entries[i+1].index);
entries[i+1].type = TYPE_GROUPED;
}
break;
}
break;
}
// if we have left ungrouped outputs merge them to the empty channel
uint8_t *togroup;// = (channel1 ? (channel2 ? NULL : &channel2) : &channel1);
togroup = &channel2;
for(i=0; i<num_outputs;i++)
if(entries[i].type != TYPE_GROUPED) {
for (i = 0; i < num_outputs; i++)
{
if (entries[i].type != TYPE_GROUPED)
{
//printf("%d not grouped\n", i);
if(togroup)
if (togroup)
{
*togroup |= ( 0x1 << entries[i].index);
}
entries[i].type = TYPE_GROUPED;
}
}
if(channel1 > channel2) {
if (channel1 > channel2)
{
uint8_t buff = channel1;
channel1 = channel2;
channel2 = buff;
default_NVCAP[8] = channel2;
// patching HEADS
for(i=0; i<num_outputs;i++) {
if(channel1 & (1 << i))
for (i = 0; i < num_outputs; i++)
{
if (channel1 & (1 << i))
{
*entries[i].heads = 1;
}
else if(channel2 & (1 << i))
{
*entries[i].heads = 2;
}
}
return (has_lvds ? PATCH_ROM_SUCCESS_HAS_LVDS : PATCH_ROM_SUCCESS);
}
static char *get_nvidia_model(uint32_t id) {
inti;
for (i=1; i< (sizeof(NVKnownChipsets) / sizeof(NVKnownChipsets[0])); i++) {
if (NVKnownChipsets[i].device == id) {
static char *get_nvidia_model(uint32_t id)
{
int i;
for (i = 1; i < (sizeof(NVKnownChipsets) / sizeof(NVKnownChipsets[0])); i++) {
if (NVKnownChipsets[i].device == id)
{
return NVKnownChipsets[i].name;
}
}
static uint32_t load_nvidia_bios_file(const char *filename, uint8_t *buf, int bufsize)
{
intfd;
intsize;
if ((fd = open_bvdev("bt(0,0)", filename, 0)) < 0) {
int fd;
int size;
if ((fd = open_bvdev("bt(0,0)", filename, 0)) < 0)
{
return 0;
}
size = file_size(fd);
if (size > bufsize) {
printf("Filesize of %s is bigger than expected! Truncating to 0x%x Bytes!\n", filename, bufsize);
if (size > bufsize)
{
printf("Filesize of %s is bigger than expected! Truncating to 0x%x Bytes!\n",
filename, bufsize);
size = bufsize;
}
size = read(fd, (char *)buf, size);
close(fd);
return size > 0 ? size : 0;
}
static int devprop_add_nvidia_template(struct DevPropDevice *device)
{
chartmp[16];
if(!device)
char tmp[16];
if (!device)
return 0;
if(!DP_ADD_TEMP_VAL(device, nvidia_compatible_0))
if (!DP_ADD_TEMP_VAL(device, nvidia_compatible_0))
return 0;
if(!DP_ADD_TEMP_VAL(device, nvidia_device_type_0))
if (!DP_ADD_TEMP_VAL(device, nvidia_device_type_0))
return 0;
if(!DP_ADD_TEMP_VAL(device, nvidia_name_0))
if (!DP_ADD_TEMP_VAL(device, nvidia_name_0))
return 0;
if(!DP_ADD_TEMP_VAL(device, nvidia_compatible_1))
if (!DP_ADD_TEMP_VAL(device, nvidia_compatible_1))
return 0;
if(!DP_ADD_TEMP_VAL(device, nvidia_device_type_1))
if (!DP_ADD_TEMP_VAL(device, nvidia_device_type_1))
return 0;
if(!DP_ADD_TEMP_VAL(device, nvidia_name_1))
if (!DP_ADD_TEMP_VAL(device, nvidia_name_1))
return 0;
if(!DP_ADD_TEMP_VAL(device, nvidia_device_type))
if (!DP_ADD_TEMP_VAL(device, nvidia_device_type))
return 0;
// Rek : Dont use sprintf return, it does not WORK !! our custom sprintf() always return 0!
// len = sprintf(tmp, "Slot-%x", devices_number);
sprintf(tmp, "Slot-%x",devices_number);
devprop_add_value(device, "AAPL,slot-name", (uint8_t *) tmp, strlen(tmp));
devices_number++;
return 1;
}
int hex2bin(const char *hex, uint8_t *bin, int len)
{
char*p;
inti;
inti;
charbuf[3];
if (hex == NULL || bin == NULL || len <= 0 || strlen(hex) != len * 2) {
printf("[ERROR] bin2hex input error\n");
return -1;
}
buf[2] = '\0';
p = (char *) hex;
for (i=0; i<len; i++) {
for (i = 0; i < len; i++)
{
if (p[0] == '\0' || p[1] == '\0' || !isxdigit(p[0]) || !isxdigit(p[1])) {
printf("[ERROR] bin2hex '%s' syntax error\n", hex);
return -2;
unsigned long long mem_detect(volatile uint8_t *regs, uint8_t nvCardType, pci_dt_t *nvda_dev)
{
unsigned long long vram_size = 0;
if (nvCardType < NV_ARCH_50) {
if (nvCardType < NV_ARCH_50)
{
vram_size = REG32(NV04_PFB_FIFO_DATA);
vram_size &= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK;
}
else if (nvCardType < NV_ARCH_C0) {
else if (nvCardType < NV_ARCH_C0)
{
vram_size = REG32(NV04_PFB_FIFO_DATA);
vram_size |= (vram_size & 0xff) << 32;
vram_size &= 0xffffffff00ll;
}
else { // >= NV_ARCH_C0
else // >= NV_ARCH_C0
{
vram_size = REG32(NVC0_MEM_CTRLR_RAM_AMOUNT) << 20;
vram_size *= REG32(NVC0_MEM_CTRLR_COUNT);
}
return vram_size;
}
bool setup_nvidia_devprop(pci_dt_t *nvda_dev)
{
struct DevPropDevice*device;
char*devicepath;
option_rom_pci_header_t*rom_pci_header;
volatile uint8_t*regs;
uint8_t*rom;
uint8_t*nvRom;
uint8_tnvCardType;
unsigned long longvideoRam;
uint32_tnvBiosOveride;
uint32_tbar[7];
uint32_tboot_display;
intnvPatch;
intlen;
charbiosVersion[32];
charnvFilename[32];
charkNVCAP[12];
char*model;
const char*value;
booldoit;
struct DevPropDevice*device;
char*devicepath;
option_rom_pci_header_t *rom_pci_header;
volatile uint8_t*regs;
uint8_t*rom;
uint8_t*nvRom;
uint8_tnvCardType;
unsigned long longvideoRam;
uint32_tnvBiosOveride;
uint32_tbar[7];
uint32_tboot_display;
intnvPatch;
intlen;
charbiosVersion[32];
charnvFilename[32];
charkNVCAP[12];
char*model;
const char*value;
booldoit;
devicepath = get_pci_dev_path(nvda_dev);
bar[0] = pci_config_read32(nvda_dev->dev.addr, 0x10 );
regs = (uint8_t *) (bar[0] & ~0x0f);
// get card type
nvCardType = (REG32(0) >> 20) & 0x1ff;
// Amount of VRAM in kilobytes
videoRam = mem_detect(regs, nvCardType, nvda_dev);
model = get_nvidia_model((nvda_dev->vendor_id << 16) | nvda_dev->device_id);
verbose("nVidia %s %dMB NV%02x [%04x:%04x] :: %s\n",
verbose("nVidia %s %dMB NV%02x [%04x:%04x] :: %s\n",
model, (uint32_t)(videoRam / 1024 / 1024),
(REG32(0) >> 20) & 0x1ff, nvda_dev->vendor_id, nvda_dev->device_id,
devicepath);
rom = malloc(NVIDIA_ROM_SIZE);
sprintf(nvFilename, "/Extra/%04x_%04x.rom", (uint16_t)nvda_dev->vendor_id, (uint16_t)nvda_dev->device_id);
if (getBoolForKey(kUseNvidiaROM, &doit, &bootInfo->bootConfig) && doit) {
sprintf(nvFilename, "/Extra/%04x_%04x.rom", (uint16_t)nvda_dev->vendor_id,
(uint16_t)nvda_dev->device_id);
if (getBoolForKey(kUseNvidiaROM, &doit, &bootInfo->bootConfig) && doit)
{
verbose("Looking for nvidia video bios file %s\n", nvFilename);
nvBiosOveride = load_nvidia_bios_file(nvFilename, rom, NVIDIA_ROM_SIZE);
if (nvBiosOveride > 0) {
if (nvBiosOveride > 0)
{
verbose("Using nVidia Video BIOS File %s (%d Bytes)\n", nvFilename, nvBiosOveride);
DBG("%s Signature 0x%02x%02x %d bytes\n", nvFilename, rom[0], rom[1], nvBiosOveride);
} else {
}
else
{
printf("ERROR: unable to open nVidia Video BIOS File %s\n", nvFilename);
return false;
}
} else {
}
else
{
// Otherwise read bios from card
nvBiosOveride = 0;
// TODO: we should really check for the signature before copying the rom, i think.
// PRAMIN first
nvRom = (uint8_t*)&regs[NV_PRAMIN_OFFSET];
bcopy((uint32_t *)nvRom, rom, NVIDIA_ROM_SIZE);
// Valid Signature ?
if (rom[0] != 0x55 && rom[1] != 0xaa) {
if (rom[0] != 0x55 && rom[1] != 0xaa)
{
// PROM next
// Enable PROM access
(REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED;
nvRom = (uint8_t*)&regs[NV_PROM_OFFSET];
bcopy((uint8_t *)nvRom, rom, NVIDIA_ROM_SIZE);
// disable PROM access
(REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED;
(REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED;
// Valid Signature ?
if (rom[0] != 0x55 && rom[1] != 0xaa) {
if (rom[0] != 0x55 && rom[1] != 0xaa)
{
// 0xC0000 last
bcopy((char *)0xc0000, rom, NVIDIA_ROM_SIZE);
// Valid Signature ?
if (rom[0] != 0x55 && rom[1] != 0xaa) {
if (rom[0] != 0x55 && rom[1] != 0xaa)
{
printf("ERROR: Unable to locate nVidia Video BIOS\n");
return false;
} else {
}
else
{
DBG("ROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);
}
} else {
}
else
{
DBG("PROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);
}
} else {
}
else
{
DBG("PRAM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);
}
}
if ((nvPatch = patch_nvidia_rom(rom)) == PATCH_ROM_FAILED) {
printf("ERROR: nVidia ROM Patching Failed!\n");
//return false;
}
rom_pci_header = (option_rom_pci_header_t*)(rom + *(uint16_t *)&rom[24]);
// check for 'PCIR' sig
if (rom_pci_header->signature == 0x50434952) {
if (rom_pci_header->device_id != nvda_dev->device_id) {
if (rom_pci_header->signature == 0x50434952)
{
if (rom_pci_header->device_id != nvda_dev->device_id)
{
// Get Model from the OpROM
model = get_nvidia_model((rom_pci_header->vendor_id << 16) | rom_pci_header->device_id);
} else {
}
else
{
printf("nVidia incorrect PCI ROM signature: 0x%x\n", rom_pci_header->signature);
}
}
if (!string) {
string = devprop_create_string();
}
device = devprop_add_device(string, devicepath);
/* FIXME: for primary graphics card only */
boot_display = 1;
devprop_add_value(device, "@0,AAPL,boot-display", (uint8_t*)&boot_display, 4);
if(nvPatch == PATCH_ROM_SUCCESS_HAS_LVDS) {
if (nvPatch == PATCH_ROM_SUCCESS_HAS_LVDS) {
uint8_t built_in = 0x01;
devprop_add_value(device, "@0,built-in", &built_in, 1);
}
// get bios version
const int MAX_BIOS_VERSION_LENGTH = 32;
char* version_str = (char*)malloc(MAX_BIOS_VERSION_LENGTH);
memset(version_str, 0, MAX_BIOS_VERSION_LENGTH);
int i, version_start;
int crlf_count = 0;
// only search the first 384 bytes
for(i = 0; i < 0x180; i++) {
if(rom[i] == 0x0D && rom[i+1] == 0x0A) {
for (i = 0; i < 0x180; i++)
{
if (rom[i] == 0x0D && rom[i+1] == 0x0A)
{
crlf_count++;
// second 0x0D0A was found, extract bios version
if(crlf_count == 2) {
if(rom[i-1] == 0x20) i--; // strip last " "
for(version_start = i; version_start > (i-MAX_BIOS_VERSION_LENGTH); version_start--) {
// find start
if(rom[version_start] == 0x00) {
version_start++;
// strip "Version "
if(strncmp((const char*)rom+version_start, "Version ", 8) == 0) {
version_start += 8;
if (crlf_count == 2)
{
if (rom[i-1] == 0x20) i--; // strip last " "
{
for (version_start = i; version_start > (i-MAX_BIOS_VERSION_LENGTH); version_start--)
{
// find start
if (rom[version_start] == 0x00)
{
version_start++;
// strip "Version "
if (strncmp((const char*)rom+version_start, "Version ", 8) == 0)
{
version_start += 8;
}
strncpy(version_str, (const char*)rom+version_start, i-version_start);
break;
}
strncpy(version_str, (const char*)rom+version_start, i-version_start);
break;
}
}
break;
break; //Azi: reminder
}
}
}
sprintf(biosVersion, "%s", (nvBiosOveride > 0) ? nvFilename : version_str);
sprintf(kNVCAP, "NVCAP_%04x", nvda_dev->device_id);
if (getValueForKey(kNVCAP, &value, &len, &bootInfo->bootConfig) && len == NVCAP_LEN * 2) {
uint8_tnew_NVCAP[NVCAP_LEN];
if (hex2bin(value, new_NVCAP, NVCAP_LEN) == 0) {
if (getValueForKey(kNVCAP, &value, &len, &bootInfo->bootConfig) && len == NVCAP_LEN * 2)
{
uint8_t new_NVCAP[NVCAP_LEN];
if (hex2bin(value, new_NVCAP, NVCAP_LEN) == 0)
{
verbose("Using user supplied NVCAP for %s :: %s\n", model, devicepath);
memcpy(default_NVCAP, new_NVCAP, NVCAP_LEN);
}
}
#if DEBUG_NVCAP
printf("NVCAP: %02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x\n",
default_NVCAP[0], default_NVCAP[1], default_NVCAP[2], default_NVCAP[3],
default_NVCAP[4], default_NVCAP[5], default_NVCAP[6], default_NVCAP[7],
default_NVCAP[8], default_NVCAP[9], default_NVCAP[10], default_NVCAP[11],
default_NVCAP[12], default_NVCAP[13], default_NVCAP[14], default_NVCAP[15],
default_NVCAP[16], default_NVCAP[17], default_NVCAP[18], default_NVCAP[19]);
#if DEBUG_NVCAP
printf("NVCAP: %02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x\n",
default_NVCAP[0], default_NVCAP[1], default_NVCAP[2], default_NVCAP[3],
default_NVCAP[4], default_NVCAP[5], default_NVCAP[6], default_NVCAP[7],
default_NVCAP[8], default_NVCAP[9], default_NVCAP[10], default_NVCAP[11],
default_NVCAP[12], default_NVCAP[13], default_NVCAP[14], default_NVCAP[15],
default_NVCAP[16], default_NVCAP[17], default_NVCAP[18], default_NVCAP[19]);
#endif
devprop_add_nvidia_template(device);
devprop_add_value(device, "NVCAP", default_NVCAP, NVCAP_LEN);
devprop_add_value(device, "VRAM,totalsize", (uint8_t*)&videoRam, 4);
devprop_add_value(device, "model", (uint8_t*)model, strlen(model) + 1);
devprop_add_value(device, "rom-revision", (uint8_t*)biosVersion, strlen(biosVersion) + 1);
if (getBoolForKey(kVBIOS, &doit, &bootInfo->bootConfig) && doit) {
if (getBoolForKey(kVBIOS, &doit, &bootInfo->bootConfig) && doit)
{
devprop_add_value(device, "vbios", rom, (nvBiosOveride > 0) ? nvBiosOveride : (rom[2] * 512));
}
stringdata = malloc(sizeof(uint8_t) * string->length);
memcpy(stringdata, (uint8_t*)devprop_generate_string(string), string->length);
stringlength = string->length;
return true;
}
branches/iFabio/Chameleon/i386/modules/GraphicsEnabler/NVIDIAGraphicsEnabler/Makefile
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MODULE_NAME = NVIDIAGraphicsEnabler
MODULE_DESCRIPTION = This module provides
MODULE_AUTHOR =
MODULE_AUTHOR = Chameleon
MODULE_DESCRIPTION = to be added...
MODULE_VERSION = "1.0.0"
MODULE_COMPAT_VERSION = "1.0.0"
MODULE_START = $(MODULE_NAME)_start
MODULE_OBJS = nvidia.o NVIDIAGraphicsEnabler.o
include ../MakeInc.dir
include ../../MakeInc.dir
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/**
Original patch by nawcom
/*
Original patch by Nawcom
http://forum.voodooprojects.org/index.php/topic,1029.msg4427.html#msg4427
**/
*/
#include "libsa.h"
#include "saio_internal.h"
#include "bootstruct.h"
#include "pci.h"
#include "platform.h"
#define DBG(x...)
#endif
uint8_t GMAX3100_vals[22][4] = {
{ 0x01,0x00,0x00,0x00 },
{ 0x01,0x00,0x00,0x00 },
{ 0x3B,0x00,0x00,0x00 },
{ 0x00,0x00,0x00,0x00 }
};
uint8_t reg_TRUE[] = { 0x01 ,0x00 ,0x00 ,0x00 };
uint8_t reg_TRUE[]= { 0x01 ,0x00 ,0x00 ,0x00 };
uint8_t reg_FALSE[] = { 0x00,0x00,0x00,0x00 };
static struct gma_gpu_t KnownGPUS[] = {
{ 0x808627A2, "Mobile GMA950"},
{ 0x808627AE, "Mobile GMA950"},
{ 0x808627A6, "Mobile GMA950"},
{ 0x80862772, "Desktop GMA950"}, //Azi: never worked with mine.
{ 0x8086A011, "Mobile GMA3150"},
{ 0x8086A012, "Mobile GMA3150"},
//Azi: i can get QE/CI but no framebuffer... more testing needed.
{ 0x80862772, "Desktop GMA950"},
{ 0x80862776, "Desktop GMA950"},
{ 0x8086A001, "Mobile GMA3150"},
{ 0x8086A002, "Desktop GMA3150" },
{ 0x80862A02, "GMAX3100"},
{ 0x80862A03, "GMAX3100"},
{ 0x80862A12, "GMAX3100"},
{ 0x80862A13, "GMAX3100"}
{ 0x80862A13, "GMAX3100"},
{ 0x80862A42, "GMAX3100"},
{ 0x80862A43, "GMAX3100"},
};
char *get_gma_model(uint32_t id) {
int i=0;
for(i = 0; i < (sizeof(KnownGPUS) / sizeof(KnownGPUS[0])); i++) {
if(KnownGPUS[i].device == id)
int i = 0;
for (i = 0; i < (sizeof(KnownGPUS) / sizeof(KnownGPUS[0])); i++)
{
if (KnownGPUS[i].device == id)
return KnownGPUS[i].name;
}
return KnownGPUS[0].name;
bool setup_gma_devprop(pci_dt_t *gma_dev)
{
//intlen;
char *devicepath;
volatile uint8_t *regs;
uint32_t bar[7];
char *model;
uint8_t BuiltIn = 0x00;
uint8_t ClassFix[4] = { 0x00, 0x00, 0x03, 0x00 };
char*devicepath;
volatile uint8_t*regs;
uint32_tbar[7];
char*model;
uint8_t BuiltIn =0x00;
uint8_t ClassFix[4] ={ 0x00, 0x00, 0x03, 0x00 };
devicepath = get_pci_dev_path(gma_dev);
bar[0] = pci_config_read32(gma_dev->dev.addr, 0x10);
regs = (uint8_t *) (bar[0] & ~0x0f);
model = get_gma_model((gma_dev->vendor_id << 16) | gma_dev->device_id);
verbose("Intel %s [%04x:%04x] :: %s\n",
model, gma_dev->vendor_id, gma_dev->device_id, devicepath);
if (!string)
string = devprop_create_string();
struct DevPropDevice *device = malloc(sizeof(struct DevPropDevice));
device = devprop_add_device(string, devicepath);
if(!device)
if (!device)
{
printf("Failed initializing dev-prop string dev-entry, press any key...\n");
devprop_add_value(device, "model", (uint8_t*)model, (strlen(model) + 1));
devprop_add_value(device, "device_type", (uint8_t*)"display", 8);
if (model == (char *)"Mobile GMA950") {
if ((model == (char *)"Mobile GMA950")
|| (model == (char *)"Mobile GMA3150"))
{
devprop_add_value(device, "AAPL,HasPanel", reg_TRUE, 4);
devprop_add_value(device, "built-in", &BuiltIn, 1);
devprop_add_value(device, "class-code", ClassFix, 4);
} else if (model == (char *)"Desktop GMA950") {
}
else if ((model == (char *)"Desktop GMA950")
|| (model == (char *)"Desktop GMA3150"))
{
BuiltIn = 0x01;
devprop_add_value(device, "built-in", &BuiltIn, 1);
} else if (model == (char *)"GMAX3100") {
devprop_add_value(device, "AAPL,HasPanel",GMAX3100_vals[0], 4);
devprop_add_value(device, "AAPL,SelfRefreshSupported",GMAX3100_vals[1], 4);
devprop_add_value(device, "AAPL,aux-power-connected",GMAX3100_vals[2], 4);
devprop_add_value(device, "AAPL,backlight-control",GMAX3100_vals[3], 4);
devprop_add_value(device, "AAPL00,blackscreen-preferences",GMAX3100_vals[4], 4);
devprop_add_value(device, "AAPL01,BacklightIntensity",GMAX3100_vals[5], 4);
devprop_add_value(device, "AAPL01,blackscreen-preferences",GMAX3100_vals[6], 4);
devprop_add_value(device, "AAPL01,DataJustify",GMAX3100_vals[7], 4);
devprop_add_value(device, "AAPL01,Depth",GMAX3100_vals[8], 4);
devprop_add_value(device, "AAPL01,Dither",GMAX3100_vals[9], 4);
devprop_add_value(device, "AAPL01,DualLink",GMAX3100_vals[10], 4);
devprop_add_value(device, "AAPL01,Height",GMAX3100_vals[11], 4);
devprop_add_value(device, "AAPL01,Interlace",GMAX3100_vals[12], 4);
devprop_add_value(device, "AAPL01,Inverter",GMAX3100_vals[13], 4);
devprop_add_value(device, "AAPL01,InverterCurrent",GMAX3100_vals[14], 4);
devprop_add_value(device, "AAPL01,InverterCurrency",GMAX3100_vals[15], 4);
devprop_add_value(device, "AAPL01,LinkFormat",GMAX3100_vals[16], 4);
devprop_add_value(device, "AAPL01,LinkType",GMAX3100_vals[17], 4);
devprop_add_value(device, "AAPL01,Pipe",GMAX3100_vals[18], 4);
devprop_add_value(device, "AAPL01,PixelFormat",GMAX3100_vals[19], 4);
devprop_add_value(device, "AAPL01,Refresh",GMAX3100_vals[20], 4);
devprop_add_value(device, "AAPL01,Stretch",GMAX3100_vals[21], 4);
devprop_add_value(device, "class-code", ClassFix, 4);
}
else if (model == (char *)"GMAX3100")
{
devprop_add_value(device, "AAPL,HasPanel",GMAX3100_vals[0], 4);
devprop_add_value(device, "AAPL,SelfRefreshSupported",GMAX3100_vals[1], 4);
devprop_add_value(device, "AAPL,aux-power-connected",GMAX3100_vals[2], 4);
devprop_add_value(device, "AAPL,backlight-control",GMAX3100_vals[3], 4);
devprop_add_value(device, "AAPL00,blackscreen-preferences", GMAX3100_vals[4], 4);
devprop_add_value(device, "AAPL01,BacklightIntensity",GMAX3100_vals[5], 4);
devprop_add_value(device, "AAPL01,blackscreen-preferences", GMAX3100_vals[6], 4);
devprop_add_value(device, "AAPL01,DataJustify",GMAX3100_vals[7], 4);
devprop_add_value(device, "AAPL01,Depth",GMAX3100_vals[8], 4);
devprop_add_value(device, "AAPL01,Dither",GMAX3100_vals[9], 4);
devprop_add_value(device, "AAPL01,DualLink",GMAX3100_vals[10], 4);
devprop_add_value(device, "AAPL01,Height",GMAX3100_vals[11], 4);
devprop_add_value(device, "AAPL01,Interlace",GMAX3100_vals[12], 4);
devprop_add_value(device, "AAPL01,Inverter",GMAX3100_vals[13], 4);
devprop_add_value(device, "AAPL01,InverterCurrent",GMAX3100_vals[14], 4);
devprop_add_value(device, "AAPL01,InverterCurrency",GMAX3100_vals[15], 4);
devprop_add_value(device, "AAPL01,LinkFormat",GMAX3100_vals[16], 4);
devprop_add_value(device, "AAPL01,LinkType",GMAX3100_vals[17], 4);
devprop_add_value(device, "AAPL01,Pipe",GMAX3100_vals[18], 4);
devprop_add_value(device, "AAPL01,PixelFormat",GMAX3100_vals[19], 4);
devprop_add_value(device, "AAPL01,Refresh",GMAX3100_vals[20], 4);
devprop_add_value(device, "AAPL01,Stretch",GMAX3100_vals[21], 4);
devprop_add_value(device, "class-code",ClassFix, 4);
}
stringdata = malloc(sizeof(uint8_t) * string->length);
if(!stringdata)
if (!stringdata)
{
printf("no stringdata press a key...\n");
getchar();
branches/iFabio/Chameleon/i386/modules/GraphicsEnabler/IntelGraphicsEnabler/IntelGraphicsEnabler.c
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/*
* IntelGraphicsEnabler Module ---
* Enables "some" Intel cards to be used out of the box ?? in OS X.
* This was converted from ... // AutoResolution reminder ---
*IntelGraphicsEnabler Module
*Enables a few Intel cards to be used out of the box in OS X.
*
*/
#include "gma.h"
#include "modules.h"
#define kGraphicsEnablerKey "GraphicsEnabler"
#define kGraphicsEnablerKey"GraphicsEnabler"
void GraphicsEnabler_hook(void* arg1, void* arg2, void* arg3, void* arg4);
branches/iFabio/Chameleon/i386/modules/GraphicsEnabler/IntelGraphicsEnabler/Readme.txt
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Module:IntelGraphicsEnabler
Description: Enables "some" ?? Intel cards to be used out of the box ?? in OS X.
This was converted from ...
Description: Enables a few Intel cards to be used out of the box,
mostly mobile ones.
Dependencies: none
Keys: GraphicsEnabler (enabled by default)
Keys: GraphicsEnablerYes/No (enabled by default)
Disable GraphicsEnabler patch.
Adaptation of Meklort's work.
Original patch by Nawcom:
http://forum.voodooprojects.org/index.php/topic,1029.0.html
TODO: ---
TODO: test my GMA desktop again (Azi)
branches/iFabio/Chameleon/i386/modules/GraphicsEnabler/IntelGraphicsEnabler/Makefile
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MODULE_NAME = IntelGraphicsEnabler
MODULE_DESCRIPTION = This module provides
MODULE_AUTHOR =
MODULE_AUTHOR = Chameleon
MODULE_DESCRIPTION = to be added...
MODULE_VERSION = "1.0.0"
MODULE_COMPAT_VERSION = "1.0.0"
MODULE_START = $(MODULE_NAME)_start
MODULE_OBJS = gma.o IntelGraphicsEnabler.o
include ../MakeInc.dir
include ../../MakeInc.dir
branches/iFabio/Chameleon/i386/modules/GraphicsEnabler/ATiGraphicsEnabler/Makefile
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MODULE_NAME = ATiGraphicsEnabler
MODULE_DESCRIPTION = This module provides
MODULE_AUTHOR =
MODULE_AUTHOR = Chameleon
MODULE_DESCRIPTION = to be added...
MODULE_VERSION = "1.0.0"
MODULE_COMPAT_VERSION = "1.0.0"
MODULE_START = $(MODULE_NAME)_start
MODULE_OBJS = ati.o ATiGraphicsEnabler.o
include ../MakeInc.dir
include ../../MakeInc.dir
branches/iFabio/Chameleon/i386/modules/GraphicsEnabler/ATiGraphicsEnabler/ati.c
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devicepath = get_pci_dev_path(ati_dev);
cmd = pci_config_read8(ati_dev->dev.addr, 4);
verbose("old pci command - %x\n", cmd); //Azi: 7
verbose("old pci command - %x\n", cmd);
if (cmd == 0) {
pci_config_write8(ati_dev->dev.addr, 4, 6);
cmd = pci_config_read8(ati_dev->dev.addr, 4);
verbose("new pci command - %x\n", cmd);
}
model = get_ati_model((ati_dev->vendor_id << 16) | ati_dev->device_id); //Azi: Unknown
framebuffer = get_ati_fb((ati_dev->vendor_id << 16) | ati_dev->device_id); //Azi: Megalodon
model = get_ati_model((ati_dev->vendor_id << 16) | ati_dev->device_id);
framebuffer = get_ati_fb((ati_dev->vendor_id << 16) | ati_dev->device_id);
if (!string) {
string = devprop_create_string();
}
} else {
boot_display = 0;
}
verbose("boot display - %x\n", boot_display); //Azi: 1... thus, POSTed!
devprop_add_value(device, "@0,AAPL,boot-display", (uint8_t*)&boot_display, 4); //Azi: Ok!
verbose("boot display - %x\n", boot_display);
devprop_add_value(device, "@0,AAPL,boot-display", (uint8_t*)&boot_display, 4);
if ((framebuffer[0] == 'M' && framebuffer[1] == 'o' && framebuffer[2] == 't') ||
(framebuffer[0] == 'S' && framebuffer[1] == 'h' && framebuffer[2] == 'r') ||
(framebuffer[0] == 'P' && framebuffer[1] == 'e' && framebuffer[2] == 'r')) //faster than strcmp ;)
//Azi: if framebuffer = Motmot or Shrike (none!) or Peregrine
devprop_add_ati_template_4xxx(device); //Azi: 4000 series (or 4800 ??)
devprop_add_ati_template_4xxx(device);
else {
devprop_add_ati_template(device); //Azi: my scene!!!***
devprop_add_ati_template(device);
vram_size = getvramsizekb(ati_dev) * 1024;
if ((vram_size > 0x80000000) || (vram_size == 0)) {
vram_size = 0x10000000;//vram reported wrong, defaulting to 256 mb
}
devprop_add_value(device, "VRAM,totalsize", (uint8_t*)&vram_size, 4); //Azi: 0x20000000
devprop_add_value(device, "VRAM,totalsize", (uint8_t*)&vram_size, 4);
ati_vram_memsize_0.data[6] = (vram_size >> 16) & 0xFF; //4,5 are 0x00 anyway
ati_vram_memsize_0.data[7] = (vram_size >> 24) & 0xFF;
ati_vram_memsize_1.data[6] = (vram_size >> 16) & 0xFF; //4,5 are 0x00 anyway
DP_ADD_TEMP_VAL_DATA(device, ati_vram_memsize_1);
devprop_add_iopciconfigspace(device, ati_dev);
}
devprop_add_value(device, "model", (uint8_t*)model, (strlen(model) + 1)); //Azi: Unknown
devprop_add_value(device, "ATY,DeviceID", (uint8_t*)&ati_dev->device_id, 2); //Azi: Ok! 8171 = (7181)
devprop_add_value(device, "model", (uint8_t*)model, (strlen(model) + 1));
devprop_add_value(device, "ATY,DeviceID", (uint8_t*)&ati_dev->device_id, 2);
//fb setup
sprintf(tmp, "Slot-%x",devices_number);
devprop_add_value(device, "AAPL,slot-name", (uint8_t*)tmp, strlen(tmp) + 1); //Azi: OK! Slot-1
// don't think my card is on slot 1 ??... 0 ??
devprop_add_value(device, "AAPL,slot-name", (uint8_t*)tmp, strlen(tmp) + 1);
devices_number++;
sprintf(tmp, ati_compatible_0[1], framebuffer);
devprop_add_value(device, (char *) ati_compatible_1[0], (uint8_t *)tmp, strlen(tmp) + 1);
sprintf(tmp, ati_device_type[1], framebuffer);
devprop_add_value(device, (char *) ati_device_type[0], (uint8_t *)tmp, strlen(tmp) + 1); //Azi: OK!
devprop_add_value(device, (char *) ati_device_type[0], (uint8_t *)tmp, strlen(tmp) + 1);
sprintf(tmp, ati_name[1], framebuffer);
devprop_add_value(device, (char *) ati_name[0], (uint8_t *)tmp, strlen(tmp) + 1); //Azi: display ??
devprop_add_value(device, (char *) ati_name[0], (uint8_t *)tmp, strlen(tmp) + 1);
sprintf(tmp, ati_name_0[1], framebuffer);
devprop_add_value(device, (char *) ati_name_0[0], (uint8_t *)tmp, strlen(tmp) + 1);
sprintf(tmp, ati_name_1[1], framebuffer);
devprop_add_value(device, (char *) ati_name_1[0], (uint8_t *)tmp, strlen(tmp) + 1);
//Azi: Assemble default path for a custom rom...
sprintf(tmp, "bt(0,0)/Extra/%04x_%04x.rom", (uint16_t)ati_dev->vendor_id, (uint16_t)ati_dev->device_id);
//Azi: if user enabled use of custom rom...
if (getBoolForKey(kUseAtiROMKey, &doit, &bootInfo->bootConfig) && doit) {
verbose("Looking for custom ATI rom %s...\n", tmp);
verbose("looking for ati video bios file %s\n", tmp);
rom = malloc(0x20000);
rom_size = load_ati_bios_file(tmp, rom, 0x20000);
//Azi: if rom exists
if (rom_size > 0)
{
verbose("Using custom rom %s (%d Bytes)\n", tmp, rom_size);
if (rom_size > 0) {
verbose("Using ATI Video BIOS File %s (%d Bytes)\n", tmp, rom_size);
if (rom_size > 0x10000) {
rom_size = 0x10000; // we dont need the rest anyway;
//Azi:verbose("Trimmed %s to %d Bytes\n", tmp, rom_size);
rom_size = 0x10000; //we dont need rest anyway;
}
} else {
printf("ERROR: unable to open ATI Video BIOS File %s\n", tmp);
}
else
{
printf("ERROR: unable to open custom ATI rom %s.\n", tmp);
}
}
if (rom_size == 0) //Azi: rom_size is still 0, user didn't enabled use of custom rom...
{//Azi: if card posted...
if (boot_display) { // no custom rom
bios = NULL; // try to dump from legacy space, otherwise can result in 100% fan speed
//bios = readAtomBIOS(ati_dev); //Azi: Wrong BIOS signature... returns 0 = NULL :-//
}
else
{
if (rom_size == 0) {
if (boot_display) {// no custom rom
bios = NULL;// try to dump from legacy space, otherwise can result in 100% fan speed
} else {
// readAtomBios result in bug on some cards (100% fan speed and black screen),
// not using it for posted card, reading from legacy space instead - Azi: reminder***
// not using it for posted card, reading from legacy space instead
bios = readAtomBIOS(ati_dev);
}
} else {
bios = rom;//going custom rom way
verbose("Using rom %s\n", tmp);
}
else //Azi: rom_size is diff from 0, user enabled use of custom rom...
{
bios = rom; //going custom rom way //Azi: shouldn't this be bios = rom_size??*****
verbose("Using rom %s\n", tmp); //Azi: print just the path
}
if (bios == NULL) //Azi: card was posted (boot_display = 1)
{
if (bios == NULL) {
bios = (uint8_t *)0x000C0000;
toFree = false;
verbose("Card posted, not going to use custom bios?? rom.\n"); //Azi: what file? custom rom??
}
else //Azi: anything but NULL, card wasn't posted (boot_display = 0), bios = readAtomBIOS(ati_dev), bios = rom_size... whatever :P ufff...
{
verbose("Not going to use bios image file\n");
} else {
toFree = true;
}
if (bios[0] == 0x55 && bios[1] == 0xaa) //Azi: check bios for 0xAA55 sig
{
if (bios[0] == 0x55 && bios[1] == 0xaa) {
verbose("Found bios image\n");
bios_size = bios[2] * 512;
rom_pci_header = (option_rom_pci_header_t*)(bios + bios[24] + bios[25]*256);
//Azi: Wrong pci header signature 558a1275 but still works!**** check later...
// ‘rom_header’ is used uninitialized in this function...
//rom_pci_header = (option_rom_pci_header_t *)((uint8_t *)rom_header + rom_header->pci_header_offset);
if (rom_pci_header->signature == 0x52494350) //Azi: ati pci header sig
{
if (rom_pci_header->signature == 0x52494350) {
if (rom_pci_header->device_id != ati_dev->device_id) {
verbose("Bios image (%x) doesnt match card (%x), ignoring\n", rom_pci_header->device_id, ati_dev->device_id);
}
else
{
if (toFree) //Azi: card wasn't posted (boot_display = 0)
} else {
if (toFree)
{
//Azi: mmio, Memory-mapped I/O - Kabyl's smbios patcher stuff reminder.
verbose("Adding binimage to card %x from mmio space with size %x\n", ati_dev->device_id, bios_size);
}
else //Azi: card was posted (boot_display = 1)
{
//Azi: check "legacy space/mmio" stuff again!!!***
} else {
verbose("Adding binimage to card %x from legacy space with size %x\n", ati_dev->device_id, bios_size);
}
//Azi: not all Mac's have this..!!
devprop_add_value(device, "ATY,bin_image", bios, bios_size);
}
}
else
{
// ATY,bin_image is not added... not all Mac's have this..!!
} else {
verbose("Wrong pci header signature %x\n", rom_pci_header->signature);
}
} else {
verbose("Bios image not found at %x, content %x %x\n", bios, bios[0], bios[1]);
}
else
{
verbose("Bios image not found at %x, content %x %x\n", bios, bios[0], bios[1]);
}
if (toFree) //Azi: card wasn't posted (boot_display = 0)
{
if (toFree) {
free(bios);
}
//Azi: see ati.c AMDge; i have no problems here with xcode 4 compilation ???
stringdata = malloc(sizeof(uint8_t) * string->length);
memcpy(stringdata, (uint8_t*)devprop_generate_string(string), string->length);
stringlength = string->length;
branches/iFabio/Chameleon/i386/modules/GraphicsEnabler/AMDGraphicsEnabler/ati_reg.h
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......
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......
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......
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30573053
30583054
......
30673063
30683064
30693065
3070
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31043100
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31863228
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56725664
/*
* Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
* VA Linux Systems Inc., Fremont, California.
* VA Linux Systems Inc., Fremont, California.
*
* All Rights Reserved.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
* NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
* THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
/*
* Authors:
* Kevin E. Martin <martin@xfree86.org>
* Rickard E. Faith <faith@valinux.com>
* Alan Hourihane <alanh@fairlite.demon.co.uk>
* Kevin E. Martin <martin@xfree86.org>
* Rickard E. Faith <faith@valinux.com>
* Alan Hourihane <alanh@fairlite.demon.co.uk>
*
* References:
*
* !!!! FIXME !!!!
* RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical
* Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April
* 1999.
* RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical
* Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April
* 1999.
*
* !!!! FIXME !!!!
* RAGE 128 Software Development Manual (Technical Reference Manual P/N
* SDK-G04000 Rev. 0.01), ATI Technologies: June 1999.
* RAGE 128 Software Development Manual (Technical Reference Manual P/N
* SDK-G04000 Rev. 0.01), ATI Technologies: June 1999.
*
*/
/* !!!! FIXME !!!! NOTE: THIS FILE HAS BEEN CONVERTED FROM r128_reg.h
/* !!!! FIXME !!!!NOTE: THIS FILE HAS BEEN CONVERTED FROM r128_reg.h
* AND CONTAINS REGISTERS AND REGISTER DEFINITIONS THAT ARE NOT CORRECT
* ON THE RADEON. A FULL AUDIT OF THIS CODE IS NEEDED! */
* ON THE RADEON. A FULL AUDIT OF THIS CODE IS NEEDED! */
#ifndef _ATI_REG_H_
#define _ATI_REG_H_
#define ATI_DATATYPE_VQ0
#define ATI_DATATYPE_CI41
#define ATI_DATATYPE_CI82
#define ATI_DATATYPE_ARGB15553
#define ATI_DATATYPE_RGB5654
#define ATI_DATATYPE_RGB8885
#define ATI_DATATYPE_ARGB88886
#define ATI_DATATYPE_RGB3327
#define ATI_DATATYPE_Y88
#define ATI_DATATYPE_RGB89
#define ATI_DATATYPE_CI1610
#define ATI_DATATYPE_VYUY_42211
#define ATI_DATATYPE_YVYU_42212
#define ATI_DATATYPE_AYUV_44414
#define ATI_DATATYPE_ARGB444415
#define ATI_DATATYPE_VQ0
#define ATI_DATATYPE_CI41
#define ATI_DATATYPE_CI82
#define ATI_DATATYPE_ARGB15553
#define ATI_DATATYPE_RGB5654
#define ATI_DATATYPE_RGB8885
#define ATI_DATATYPE_ARGB88886
#define ATI_DATATYPE_RGB3327
#define ATI_DATATYPE_Y88
#define ATI_DATATYPE_RGB89
#define ATI_DATATYPE_CI1610
#define ATI_DATATYPE_VYUY_42211
#define ATI_DATATYPE_YVYU_42212
#define ATI_DATATYPE_AYUV_44414
#define ATI_DATATYPE_ARGB444415
/* Registers for 2D/Video/Overlay */
#define RADEON_ADAPTER_ID 0x0f2c /* PCI */
#define RADEON_AGP_BASE 0x0170
#define RADEON_AGP_CNTL 0x0174
# define RADEON_AGP_APER_SIZE_256MB (0x00 << 0)
# define RADEON_AGP_APER_SIZE_128MB (0x20 << 0)
# define RADEON_AGP_APER_SIZE_64MB (0x30 << 0)
# define RADEON_AGP_APER_SIZE_32MB (0x38 << 0)
# define RADEON_AGP_APER_SIZE_16MB (0x3c << 0)
# define RADEON_AGP_APER_SIZE_8MB (0x3e << 0)
# define RADEON_AGP_APER_SIZE_4MB (0x3f << 0)
# define RADEON_AGP_APER_SIZE_MASK (0x3f << 0)
#define RADEON_STATUS_PCI_CONFIG 0x06
# define RADEON_CAP_LIST 0x100000
#define RADEON_CAPABILITIES_PTR_PCI_CONFIG 0x34 /* offset in PCI config*/
# define RADEON_CAP_PTR_MASK 0xfc /* mask off reserved bits of CAP_PTR */
# define RADEON_CAP_ID_NULL 0x00 /* End of capability list */
# define RADEON_CAP_ID_AGP 0x02 /* AGP capability ID */
# define RADEON_CAP_ID_EXP 0x10 /* PCI Express */
#define RADEON_AGP_COMMAND 0x0f60 /* PCI */
#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config*/
# define RADEON_AGP_ENABLE (1<<8)
#define RADEON_AGP_PLL_CNTL 0x000b /* PLL */
#define RADEON_AGP_STATUS 0x0f5c /* PCI */
# define RADEON_AGP_1X_MODE 0x01
# define RADEON_AGP_2X_MODE 0x02
# define RADEON_AGP_4X_MODE 0x04
# define RADEON_AGP_FW_MODE 0x10
# define RADEON_AGP_MODE_MASK 0x17
# define RADEON_AGPv3_MODE 0x08
# define RADEON_AGPv3_4X_MODE 0x01
# define RADEON_AGPv3_8X_MODE 0x02
#define RADEON_ATTRDR 0x03c1 /* VGA */
#define RADEON_ATTRDW 0x03c0 /* VGA */
#define RADEON_ATTRX 0x03c0 /* VGA */
#define RADEON_AUX_WINDOW_HORZ_CNTL 0x02d8
#define RADEON_AUX_WINDOW_VERT_CNTL 0x02dc
/* Registers for 2D/Video/Overlay */
#define RADEON_ADAPTER_ID0x0f2c/* PCI */
#define RADEON_AGP_BASE0x0170
#define RADEON_AGP_CNTL0x0174
#define RADEON_AGP_APER_SIZE_256MB (0x00 << 0)
#define RADEON_AGP_APER_SIZE_128MB (0x20 << 0)
#define RADEON_AGP_APER_SIZE_64MB (0x30 << 0)
#define RADEON_AGP_APER_SIZE_32MB (0x38 << 0)
#define RADEON_AGP_APER_SIZE_16MB (0x3c << 0)
#define RADEON_AGP_APER_SIZE_8MB (0x3e << 0)
#define RADEON_AGP_APER_SIZE_4MB (0x3f << 0)
#define RADEON_AGP_APER_SIZE_MASK (0x3f << 0)
#define RADEON_STATUS_PCI_CONFIG0x06
#define RADEON_CAP_LIST 0x100000
#define RADEON_CAPABILITIES_PTR_PCI_CONFIG0x34/* offset in PCI config*/
#define RADEON_CAP_PTR_MASK 0xfc/* mask off reserved bits of CAP_PTR */
#define RADEON_CAP_ID_NULL 0x00/* End of capability list */
#define RADEON_CAP_ID_AGP 0x02/* AGP capability ID */
#define RADEON_CAP_ID_EXP 0x10/* PCI Express */
#define RADEON_AGP_COMMAND0x0f60/* PCI */
#define RADEON_AGP_COMMAND_PCI_CONFIG0x0060/* offset in PCI config*/
#define RADEON_AGP_ENABLE (1 << 8)
#define RADEON_AGP_PLL_CNTL0x000b/* PLL */
#define RADEON_AGP_STATUS0x0f5c/* PCI */
#define RADEON_AGP_1X_MODE 0x01
#define RADEON_AGP_2X_MODE 0x02
#define RADEON_AGP_4X_MODE 0x04
#define RADEON_AGP_FW_MODE 0x10
#define RADEON_AGP_MODE_MASK 0x17
#define RADEON_AGPv3_MODE 0x08
#define RADEON_AGPv3_4X_MODE 0x01
#define RADEON_AGPv3_8X_MODE 0x02
#define RADEON_ATTRDR0x03c1/* VGA */
#define RADEON_ATTRDW0x03c0/* VGA */
#define RADEON_ATTRX0x03c0/* VGA */
#define RADEON_AUX_WINDOW_HORZ_CNTL0x02d8
#define RADEON_AUX_WINDOW_VERT_CNTL0x02dc
#define RADEON_BASE_CODE 0x0f0b
#define RADEON_BIOS_0_SCRATCH 0x0010
# define RADEON_FP_PANEL_SCALABLE (1 << 16)
# define RADEON_FP_PANEL_SCALE_EN (1 << 17)
# define RADEON_FP_CHIP_SCALE_EN (1 << 18)
# define RADEON_DRIVER_BRIGHTNESS_EN (1 << 26)
# define RADEON_DISPLAY_ROT_MASK (3 << 28)
# define RADEON_DISPLAY_ROT_00 (0 << 28)
# define RADEON_DISPLAY_ROT_90 (1 << 28)
# define RADEON_DISPLAY_ROT_180 (2 << 28)
# define RADEON_DISPLAY_ROT_270 (3 << 28)
#define RADEON_BIOS_1_SCRATCH 0x0014
#define RADEON_BIOS_2_SCRATCH 0x0018
#define RADEON_BIOS_3_SCRATCH 0x001c
#define RADEON_BIOS_4_SCRATCH 0x0020
# define RADEON_CRT1_ATTACHED_MASK (3 << 0)
# define RADEON_CRT1_ATTACHED_MONO (1 << 0)
# define RADEON_CRT1_ATTACHED_COLOR (2 << 0)
# define RADEON_LCD1_ATTACHED (1 << 2)
# define RADEON_DFP1_ATTACHED (1 << 3)
# define RADEON_TV1_ATTACHED_MASK (3 << 4)
# define RADEON_TV1_ATTACHED_COMP (1 << 4)
# define RADEON_TV1_ATTACHED_SVIDEO (2 << 4)
# define RADEON_CRT2_ATTACHED_MASK (3 << 8)
# define RADEON_CRT2_ATTACHED_MONO (1 << 8)
# define RADEON_CRT2_ATTACHED_COLOR (2 << 8)
# define RADEON_DFP2_ATTACHED (1 << 11)
#define RADEON_BIOS_5_SCRATCH 0x0024
# define RADEON_LCD1_ON (1 << 0)
# define RADEON_CRT1_ON (1 << 1)
# define RADEON_TV1_ON (1 << 2)
# define RADEON_DFP1_ON (1 << 3)
# define RADEON_CRT2_ON (1 << 5)
# define RADEON_CV1_ON (1 << 6)
# define RADEON_DFP2_ON (1 << 7)
# define RADEON_LCD1_CRTC_MASK (1 << 8)
# define RADEON_LCD1_CRTC_SHIFT 8
# define RADEON_CRT1_CRTC_MASK (1 << 9)
# define RADEON_CRT1_CRTC_SHIFT 9
# define RADEON_TV1_CRTC_MASK (1 << 10)
# define RADEON_TV1_CRTC_SHIFT 10
# define RADEON_DFP1_CRTC_MASK (1 << 11)
# define RADEON_DFP1_CRTC_SHIFT 11
# define RADEON_CRT2_CRTC_MASK (1 << 12)
# define RADEON_CRT2_CRTC_SHIFT 12
# define RADEON_CV1_CRTC_MASK (1 << 13)
# define RADEON_CV1_CRTC_SHIFT 13
# define RADEON_DFP2_CRTC_MASK (1 << 14)
# define RADEON_DFP2_CRTC_SHIFT 14
#define RADEON_BIOS_6_SCRATCH 0x0028
# define RADEON_ACC_MODE_CHANGE (1 << 2)
# define RADEON_EXT_DESKTOP_MODE (1 << 3)
# define RADEON_LCD_DPMS_ON (1 << 20)
# define RADEON_CRT_DPMS_ON (1 << 21)
# define RADEON_TV_DPMS_ON (1 << 22)
# define RADEON_DFP_DPMS_ON (1 << 23)
# define RADEON_DPMS_MASK (3 << 24)
# define RADEON_DPMS_ON (0 << 24)
# define RADEON_DPMS_STANDBY (1 << 24)
# define RADEON_DPMS_SUSPEND (2 << 24)
# define RADEON_DPMS_OFF (3 << 24)
# define RADEON_SCREEN_BLANKING (1 << 26)
# define RADEON_DRIVER_CRITICAL (1 << 27)
# define RADEON_DISPLAY_SWITCHING_DIS (1 << 30)
#define RADEON_BIOS_7_SCRATCH 0x002c
# define RADEON_SYS_HOTKEY (1 << 10)
# define RADEON_DRV_LOADED (1 << 12)
#define RADEON_BIOS_ROM 0x0f30 /* PCI */
#define RADEON_BIST 0x0f0f /* PCI */
#define RADEON_BRUSH_DATA0 0x1480
#define RADEON_BRUSH_DATA1 0x1484
#define RADEON_BRUSH_DATA10 0x14a8
#define RADEON_BRUSH_DATA11 0x14ac
#define RADEON_BRUSH_DATA12 0x14b0
#define RADEON_BRUSH_DATA13 0x14b4
#define RADEON_BRUSH_DATA14 0x14b8
#define RADEON_BRUSH_DATA15 0x14bc
#define RADEON_BRUSH_DATA16 0x14c0
#define RADEON_BRUSH_DATA17 0x14c4
#define RADEON_BRUSH_DATA18 0x14c8
#define RADEON_BRUSH_DATA19 0x14cc
#define RADEON_BRUSH_DATA2 0x1488
#define RADEON_BRUSH_DATA20 0x14d0
#define RADEON_BRUSH_DATA21 0x14d4
#define RADEON_BRUSH_DATA22 0x14d8
#define RADEON_BRUSH_DATA23 0x14dc
#define RADEON_BRUSH_DATA24 0x14e0
#define RADEON_BRUSH_DATA25 0x14e4
#define RADEON_BRUSH_DATA26 0x14e8
#define RADEON_BRUSH_DATA27 0x14ec
#define RADEON_BRUSH_DATA28 0x14f0
#define RADEON_BRUSH_DATA29 0x14f4
#define RADEON_BRUSH_DATA3 0x148c
#define RADEON_BRUSH_DATA30 0x14f8
#define RADEON_BRUSH_DATA31 0x14fc
#define RADEON_BRUSH_DATA32 0x1500
#define RADEON_BRUSH_DATA33 0x1504
#define RADEON_BRUSH_DATA34 0x1508
#define RADEON_BRUSH_DATA35 0x150c
#define RADEON_BRUSH_DATA36 0x1510
#define RADEON_BRUSH_DATA37 0x1514
#define RADEON_BRUSH_DATA38 0x1518
#define RADEON_BRUSH_DATA39 0x151c
#define RADEON_BRUSH_DATA4 0x1490
#define RADEON_BRUSH_DATA40 0x1520
#define RADEON_BRUSH_DATA41 0x1524
#define RADEON_BRUSH_DATA42 0x1528
#define RADEON_BRUSH_DATA43 0x152c
#define RADEON_BRUSH_DATA44 0x1530
#define RADEON_BRUSH_DATA45 0x1534
#define RADEON_BRUSH_DATA46 0x1538
#define RADEON_BRUSH_DATA47 0x153c
#define RADEON_BRUSH_DATA48 0x1540
#define RADEON_BRUSH_DATA49 0x1544
#define RADEON_BRUSH_DATA5 0x1494
#define RADEON_BRUSH_DATA50 0x1548
#define RADEON_BRUSH_DATA51 0x154c
#define RADEON_BRUSH_DATA52 0x1550
#define RADEON_BRUSH_DATA53 0x1554
#define RADEON_BRUSH_DATA54 0x1558
#define RADEON_BRUSH_DATA55 0x155c
#define RADEON_BRUSH_DATA56 0x1560
#define RADEON_BRUSH_DATA57 0x1564
#define RADEON_BRUSH_DATA58 0x1568
#define RADEON_BRUSH_DATA59 0x156c
#define RADEON_BRUSH_DATA6 0x1498
#define RADEON_BRUSH_DATA60 0x1570
#define RADEON_BRUSH_DATA61 0x1574
#define RADEON_BRUSH_DATA62 0x1578
#define RADEON_BRUSH_DATA63 0x157c
#define RADEON_BRUSH_DATA7 0x149c
#define RADEON_BRUSH_DATA8 0x14a0
#define RADEON_BRUSH_DATA9 0x14a4
#define RADEON_BRUSH_SCALE 0x1470
#define RADEON_BRUSH_Y_X 0x1474
#define RADEON_BUS_CNTL 0x0030
# define RADEON_BUS_MASTER_DIS (1 << 6)
# define RADEON_BUS_BIOS_DIS_ROM (1 << 12)
# define RADEON_BUS_RD_DISCARD_EN (1 << 24)
# define RADEON_BUS_RD_ABORT_EN (1 << 25)
# define RADEON_BUS_MSTR_DISCONNECT_EN (1 << 28)
# define RADEON_BUS_WRT_BURST (1 << 29)
# define RADEON_BUS_READ_BURST (1 << 30)
#define RADEON_BUS_CNTL1 0x0034
# define RADEON_BUS_WAIT_ON_LOCK_EN (1 << 4)
#define RADEON_BASE_CODE0x0f0b
#define RADEON_BIOS_0_SCRATCH0x0010
#define RADEON_FP_PANEL_SCALABLE (1 << 16)
#define RADEON_FP_PANEL_SCALE_EN (1 << 17)
#define RADEON_FP_CHIP_SCALE_EN (1 << 18)
#define RADEON_DRIVER_BRIGHTNESS_EN (1 << 26)
#define RADEON_DISPLAY_ROT_MASK (3 << 28)
#define RADEON_DISPLAY_ROT_00 (0 << 28)
#define RADEON_DISPLAY_ROT_90 (1 << 28)
#define RADEON_DISPLAY_ROT_180 (2 << 28)
#define RADEON_DISPLAY_ROT_270 (3 << 28)
#define RADEON_BIOS_1_SCRATCH0x0014
#define RADEON_BIOS_2_SCRATCH0x0018
#define RADEON_BIOS_3_SCRATCH0x001c
#define RADEON_BIOS_4_SCRATCH0x0020
#define RADEON_CRT1_ATTACHED_MASK (3 << 0)
#define RADEON_CRT1_ATTACHED_MONO (1 << 0)
#define RADEON_CRT1_ATTACHED_COLOR (2 << 0)
#define RADEON_LCD1_ATTACHED (1 << 2)
#define RADEON_DFP1_ATTACHED (1 << 3)
#define RADEON_TV1_ATTACHED_MASK (3 << 4)
#define RADEON_TV1_ATTACHED_COMP (1 << 4)
#define RADEON_TV1_ATTACHED_SVIDEO (2 << 4)
#define RADEON_CRT2_ATTACHED_MASK (3 << 8)
#define RADEON_CRT2_ATTACHED_MONO (1 << 8)
#define RADEON_CRT2_ATTACHED_COLOR (2 << 8)
#define RADEON_DFP2_ATTACHED (1 << 11)
#define RADEON_BIOS_5_SCRATCH0x0024
#define RADEON_LCD1_ON(1 << 0)
#define RADEON_CRT1_ON(1 << 1)
#define RADEON_TV1_ON(1 << 2)
#define RADEON_DFP1_ON(1 << 3)
#define RADEON_CRT2_ON(1 << 5)
#define RADEON_CV1_ON(1 << 6)
#define RADEON_DFP2_ON(1 << 7)
#define RADEON_LCD1_CRTC_MASK(1 << 8)
#define RADEON_LCD1_CRTC_SHIFT8
#define RADEON_CRT1_CRTC_MASK(1 << 9)
#define RADEON_CRT1_CRTC_SHIFT9
#define RADEON_TV1_CRTC_MASK(1 << 10)
#define RADEON_TV1_CRTC_SHIFT10
#define RADEON_DFP1_CRTC_MASK(1 << 11)
#define RADEON_DFP1_CRTC_SHIFT11
#define RADEON_CRT2_CRTC_MASK(1 << 12)
#define RADEON_CRT2_CRTC_SHIFT12
#define RADEON_CV1_CRTC_MASK(1 << 13)
#define RADEON_CV1_CRTC_SHIFT13
#define RADEON_DFP2_CRTC_MASK(1 << 14)
#define RADEON_DFP2_CRTC_SHIFT14
#define RADEON_BIOS_6_SCRATCH0x0028
#define RADEON_ACC_MODE_CHANGE(1 << 2)
#define RADEON_EXT_DESKTOP_MODE(1 << 3)
#define RADEON_LCD_DPMS_ON(1 << 20)
#define RADEON_CRT_DPMS_ON(1 << 21)
#define RADEON_TV_DPMS_ON(1 << 22)
#define RADEON_DFP_DPMS_ON(1 << 23)
#define RADEON_DPMS_MASK(3 << 24)
#define RADEON_DPMS_ON(0 << 24)
#define RADEON_DPMS_STANDBY(1 << 24)
#define RADEON_DPMS_SUSPEND(2 << 24)
#define RADEON_DPMS_OFF(3 << 24)
#define RADEON_SCREEN_BLANKING(1 << 26)
#define RADEON_DRIVER_CRITICAL(1 << 27)
#define RADEON_DISPLAY_SWITCHING_DI(1 << 30)
#define RADEON_BIOS_7_SCRATCH0x002c
#define RADEON_SYS_HOTKEY(1 << 10)
#define RADEON_DRV_LOADED(1 << 12)
#define RADEON_BIOS_ROM0x0f30/* PCI */
#define RADEON_BIST0x0f0f/* PCI */
#define RADEON_BRUSH_DATA00x1480
#define RADEON_BRUSH_DATA10x1484
#define RADEON_BRUSH_DATA100x14a8
#define RADEON_BRUSH_DATA110x14ac
#define RADEON_BRUSH_DATA120x14b0
#define RADEON_BRUSH_DATA130x14b4
#define RADEON_BRUSH_DATA140x14b8
#define RADEON_BRUSH_DATA150x14bc
#define RADEON_BRUSH_DATA160x14c0
#define RADEON_BRUSH_DATA170x14c4
#define RADEON_BRUSH_DATA180x14c8
#define RADEON_BRUSH_DATA190x14cc
#define RADEON_BRUSH_DATA20x1488
#define RADEON_BRUSH_DATA200x14d0
#define RADEON_BRUSH_DATA210x14d4
#define RADEON_BRUSH_DATA220x14d8
#define RADEON_BRUSH_DATA230x14dc
#define RADEON_BRUSH_DATA240x14e0
#define RADEON_BRUSH_DATA250x14e4
#define RADEON_BRUSH_DATA260x14e8
#define RADEON_BRUSH_DATA270x14ec
#define RADEON_BRUSH_DATA280x14f0
#define RADEON_BRUSH_DATA290x14f4
#define RADEON_BRUSH_DATA30x148c
#define RADEON_BRUSH_DATA300x14f8
#define RADEON_BRUSH_DATA310x14fc
#define RADEON_BRUSH_DATA320x1500
#define RADEON_BRUSH_DATA330x1504
#define RADEON_BRUSH_DATA340x1508
#define RADEON_BRUSH_DATA350x150c
#define RADEON_BRUSH_DATA360x1510
#define RADEON_BRUSH_DATA370x1514
#define RADEON_BRUSH_DATA380x1518
#define RADEON_BRUSH_DATA390x151c
#define RADEON_BRUSH_DATA40x1490
#define RADEON_BRUSH_DATA400x1520
#define RADEON_BRUSH_DATA410x1524
#define RADEON_BRUSH_DATA420x1528
#define RADEON_BRUSH_DATA430x152c
#define RADEON_BRUSH_DATA440x1530
#define RADEON_BRUSH_DATA450x1534
#define RADEON_BRUSH_DATA460x1538
#define RADEON_BRUSH_DATA470x153c
#define RADEON_BRUSH_DATA480x1540
#define RADEON_BRUSH_DATA490x1544
#define RADEON_BRUSH_DATA50x1494
#define RADEON_BRUSH_DATA500x1548
#define RADEON_BRUSH_DATA510x154c
#define RADEON_BRUSH_DATA520x1550
#define RADEON_BRUSH_DATA530x1554
#define RADEON_BRUSH_DATA540x1558
#define RADEON_BRUSH_DATA550x155c
#define RADEON_BRUSH_DATA560x1560
#define RADEON_BRUSH_DATA570x1564
#define RADEON_BRUSH_DATA580x1568
#define RADEON_BRUSH_DATA590x156c
#define RADEON_BRUSH_DATA60x1498
#define RADEON_BRUSH_DATA600x1570
#define RADEON_BRUSH_DATA61␉<