Chameleon Applications

Chameleon Applications Commit Details

Date:2011-07-28 03:09:41 (12 years 9 months ago)
Author:ErmaC
Commit:332
Parents: 331
Message:Sync with Main Trunk 1227
Changes:
M/branches/iFabio/Chameleon/i386/libsaio/cpu.h
M/branches/iFabio/Chameleon/i386/libsaio/ati.c
M/branches/iFabio/Chameleon/i386/modules/GraphicsEnabler/NVIDIAGraphicsEnabler/nvidia.c
M/branches/iFabio/Chameleon/i386/libsaio/stringTable.c
M/branches/iFabio/Chameleon/Makefile
M/branches/iFabio/Chameleon/i386/boot2/drivers.c
M/branches/iFabio/Chameleon/i386/modules/GraphicsEnabler/ATiGraphicsEnabler/ati.c
M/branches/iFabio/Chameleon/i386/boot2/boot.c
M/branches/iFabio/Chameleon/i386/libsaio/cpu.c
M/branches/iFabio/Chameleon/i386/modules/GraphicsEnabler/AMDGraphicsEnabler/ati.c
M/branches/iFabio/Chameleon/i386/libsaio/platform.h
M/branches/iFabio/Chameleon/i386/libsaio/nvidia.c

File differences

branches/iFabio/Chameleon/i386/libsaio/nvidia.c
621621
622622
623623
624
625624
626625
627626
......
629628
630629
631630
632
633631
634632
635633
......
662660
663661
664662
665
666663
667664
668665
......
676673
677674
678675
679
680676
681677
682678
683679
684680
685681
686
687682
688683
689684
......
10861081
10871082
10881083
1089
10901084
10911085
10921086
{␊
␉if (!rom || (rom[0] != 0x55 && rom[1] != 0xaa)) {␊
␉␉printf("False ROM signature: 0x%02x%02x\n", rom[0], rom[1]);␊
␉␉pause();␊
␉␉return PATCH_ROM_FAILED;␊
␉}␊
␉␊
␊
␉if (!dcbptr) {␊
␉␉printf("no dcb table found\n");␊
␉␉pause();␊
␉␉return PATCH_ROM_FAILED;␊
␉}␊
//␉else␊
␉␉if (sig != 0x4edcbdcb)␊
␉␉{␊
␉␉␉printf("Bad display config block signature (0x%8x)\n", sig); //Azi: issue #48␊
␉␉␉pause();␊
␉␉␉return PATCH_ROM_FAILED;␊
␉␉}␊
␉}␊
␉␉if (strcmp(sig, "DEV_REC"))␊
␉␉{␊
␉␉␉printf("Bad Display Configuration Block signature (%s)\n", sig);␊
␉␉␉pause();␊
␉␉␉return PATCH_ROM_FAILED;␊
␉␉}␊
␉}␊
␉else␊
␉{␊
␉␉printf("ERROR: dcbtable_version is 0x%X\n", dcbtable_version);␊
␉␉pause();␊
␉␉return PATCH_ROM_FAILED;␊
␉}␊
␉␊
␉␊
␉if ((nvPatch = patch_nvidia_rom(rom)) == PATCH_ROM_FAILED) {␊
␉␉printf("ERROR: nVidia ROM Patching Failed!\n");␊
␉␉pause();␊
␉␉//return false;␊
␉}␊
␉␊
branches/iFabio/Chameleon/i386/libsaio/ati.c
5050
5151
5252
53
5453
5554
5655
......
8483
8584
8685
87
8886
8987
9088
......
209207
210208
211209
212
210
213211
214212
215213
216
214
217215
218216
219217
......
253251
254252
255253
254
256255
257256
258257
......
346345
347346
348347
348
349349
350350
351351
......
448448
449449
450450
451
451
452
452453
453454
454455
......
12031204
12041205
12051206
1207
1208
1209
1210
1211
12061212
12071213
12081214
␉CHIP_FAMILY_JUNIPER,␊
␉CHIP_FAMILY_CYPRESS,␊
␉CHIP_FAMILY_HEMLOCK,␊
//␉CHIP_FAMILY_GRANVILLE, //Azi:---␊
␉/* Northern Islands */␊
␉CHIP_FAMILY_BARTS,␊
␉CHIP_FAMILY_CAICOS,␊
␉"Juniper",␉// RV840␊
␉"Cypress",␉// RV870␊
␉"Hemlock",␊
//␉"Granville"␉//Azi:---␊
␉/* Northern Islands */␊
␉"Barts",␊
␉"Caicos",␊
␉//Azi: added devices␊
// temporary placement␊
␉// issue #88␊
␉{ 0x6741,␉0x1646103C,␉CHIP_FAMILY_TURKS,/*???*/"AMD Radeon HD 6600M Series",␉␉kNull␉␉},␊
␉{ 0x6741,␉0x1646103C,␉CHIP_FAMILY_TURKS,␉"AMD Radeon HD 6750M",␉␉␉␉kNull␉␉},␊
␉// issue #89␊
␉{ 0x68A8,␉0x050E1025,␉CHIP_FAMILY_CYPRESS,␉"AMD Radeon HD 6850M",␉␉␉␉kUakari␉␉}, //Azi: CHIP_FAMILY_GRANVILLE ??␊
␉// issue #90␊
␉{ 0x68E4,␉0x1c921043,␉CHIP_FAMILY_CEDAR,␉␉"ATI Radeon HD 5470M",␉␉␉␉kEulemur␉},␊
␉{ 0x68E4,␉0x1c921043,␉CHIP_FAMILY_CEDAR,␉"ATI Radeon HD 5470M",␉␉␉␉kEulemur␉},␊
␉// issue #91␊
␉{ 0x68C0,␉0x1594103C,␉CHIP_FAMILY_REDWOOD,␉"AMD Radeon HD 6570M",␉␉␉␉kNull␉␉},␊
␉␊
␉{ 0x944E,␉0x30101787, CHIP_FAMILY_RV770,␉␉"ATI Radeon HD 4810 Series",␉␉kMotmot␉␉},␊
␉{ 0x944E,␉0x31001787, CHIP_FAMILY_RV770,␉␉"ATI Radeon HD 4820",␉␉␉␉kMotmot␉␉},␊
␉␊
␉{ 0x9490,␉0x20031787, CHIP_FAMILY_RV730,␉␉"ATI Radeon HD 4670",␉␉␉␉kFlicker␉},␊
␉{ 0x9490,␉0x30501787, CHIP_FAMILY_RV730,␉␉"ATI Radeon HD 4710",␉␉␉␉kNull␉␉},␊
␉{ 0x9490,␉0x4710174B, CHIP_FAMILY_RV730,␉␉"ATI Radeon HD 4710",␉␉␉␉kNull␉␉},␊
␉{ 0x9490,␉0x300017AF, CHIP_FAMILY_RV730,␉␉"ATI Radeon HD 4710",␉␉␉␉kNull␉␉},␊
␉{ 0x9552,␉0x3000174B, CHIP_FAMILY_RV710,␉␉"ATI Radeon HD 4300/4500 Series",␉kNull␉␉},␊
␉{ 0x9552,␉0x30001787, CHIP_FAMILY_RV710,␉␉"ATI Radeon HD 4300/4500 Series",␉kNull␉␉},␊
␉{ 0x9552,␉0x300017AF, CHIP_FAMILY_RV710,␉␉"ATI Radeon HD 4300/4500 Series",␉kNull␉␉},␊
␉{ 0x9552,␉0x04341028, CHIP_FAMILY_RV710,␉␉"ATI Mobility Radeon 4330",␉␉␉kShrike␉␉},␊
␉␊
␉{ 0x9581,␉0x95811002, CHIP_FAMILY_RV630,␉␉"ATI Radeon HD 3600 Series",␉␉kNull␉␉},␊
␉{ 0x9581,␉0x3000148C, CHIP_FAMILY_RV630,␉␉"ATI Radeon HD 3600 Series",␉␉kNull␉␉},␊
␉{ 0x68F9,␉0x5470174B, CHIP_FAMILY_CEDAR,␉␉"ATI Radeon HD 5470",␉␉␉␉kNull␉␉},␊
␉{ 0x68F9,␉0x5490174B, CHIP_FAMILY_CEDAR,␉␉"ATI Radeon HD 5490",␉␉␉␉kNull␉␉},␊
␉{ 0x68F9,␉0x5530174B, CHIP_FAMILY_CEDAR,␉␉"ATI Radeon HD 5530",␉␉␉␉kNull␉␉},␊
{ 0x68F9, 0x20091787, CHIP_FAMILY_CEDAR, "ATI Radeon HD 5450", kEulemur },␊
␉{ 0x68F9,␉0x20091787, CHIP_FAMILY_CEDAR,␉␉"ATI Radeon HD 5450",␉␉␉␉kEulemur␉},␊
␉{ 0x68F9,␉0x22911787, CHIP_FAMILY_CEDAR,␉␉"ATI Radeon HD 5450",␉␉␉␉kEulemur␉},␊
␉␊
␉/* Northen Islands */␊
␉{ 0x6718,␉0x0B001002,␉CHIP_FAMILY_CAYMAN,␉␉"AMD Radeon HD 6970",␉␉␉␉kNull␉␉},␊
␉␉␉␉card->ports = card_configs[i].ports;␊
␉}␊
␉␊
␉//Azi: http://forum.voodooprojects.org/index.php/topic,1959.msg10402.html#msg10402␊
␉// get around this...␊
␉if (pci_dev->device_id == 0x9552 && pci_dev->subsys_id.subsys_id == 0x04341028 )␊
␉␉card->ports = 2;␊
␉␊
␉sprintf(name, "ATY,%s", card->cfg_name);␊
␉aty_name.type = kStr;␊
␉aty_name.size = strlen(name) + 1;␊
branches/iFabio/Chameleon/i386/libsaio/cpu.c
8383
8484
8585
86
8687
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
87195
88196
89197
......
110218
111219
112220
113
221
114222
115
223
224
225
226
227
116228
117229
230
231
118232
119233
120234
121235
122236
123237
124
125
238
239
126240
127241
128242
......
136250
137251
138252
139
253
140254
141255
142256
143
257
258
144259
145260
146261
147
262
263
264
265
266
267
268
269
148270
149271
150272
......
171293
172294
173295
174
175
176
177
178
179
296
297
298
299
300
301
180302
181303
182304
......
213335
214336
215337
216
338
217339
218340
219341
......
227349
228350
229351
230
231
232
352
353
354
233355
234
235
236
356
357
358
237359
238
239
240
241
242
243
244
360
361
362
363
364
365
366
245367
246
247
368
248369
249370
250
371
251372
252373
253374
......
292413
293414
294415
295
296
416
417
297418
298
419
299420
300
301
421
422
302423
303424
304425
305
426
306427
307428
308429
......
329450
330451
331452
332
333
334
335
336
337
338
339
340
341
342
343
344
345
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
346485
347
348
349
350
351
352
353
354
355
356
357
358
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
359502
360
361
362
363
364
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
365531
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
385551
386
552
387553
388554
return retval;␊
}␊
␊
#if 0␊
/*␊
* DFE: Measures the Max Performance Frequency in Hz (64-bit)␊
*/␊
static uint64_t measure_mperf_frequency(void)␊
{␊
uint64_t mperfStart;␊
uint64_t mperfEnd;␊
uint64_t mperfDelta = 0xffffffffffffffffULL;␊
unsigned long pollCount;␊
uint64_t retval = 0;␊
int i;␊
␊
/* Time how many MPERF ticks elapse in 30 msec using the 8254 PIT␊
* counter 2. We run this loop 3 times to make sure the cache␊
* is hot and we take the minimum delta from all of the runs.␊
* That is to say that we're biased towards measuring the minimum␊
* number of MPERF ticks that occur while waiting for the timer to␊
* expire.␊
*/␊
for(i = 0; i < 10; ++i)␊
{␊
enable_PIT2();␊
set_PIT2_mode0(CALIBRATE_LATCH);␊
mperfStart = rdmsr64(MSR_AMD_MPERF);␊
pollCount = poll_PIT2_gate();␊
mperfEnd = rdmsr64(MSR_AMD_MPERF);␊
/* The poll loop must have run at least a few times for accuracy */␊
if(pollCount <= 1)␊
continue;␊
/* The MPERF must increment at LEAST once every millisecond. We␊
* should have waited exactly 30 msec so the MPERF delta should␊
* be >= 30. Anything less and the processor is way too slow.␊
*/␊
if((mperfEnd - mperfStart) <= CALIBRATE_TIME_MSEC)␊
continue;␊
// tscDelta = MIN(tscDelta, (tscEnd - tscStart))␊
if( (mperfEnd - mperfStart) < mperfDelta )␊
mperfDelta = mperfEnd - mperfStart;␊
}␊
/* mperfDelta is now the least number of MPERF ticks the processor made in␊
* a timespan of 0.03 s (e.g. 30 milliseconds)␊
*/␊
␊
if(mperfDelta > (1ULL<<32))␊
retval = 0;␊
else␊
{␊
retval = mperfDelta * 1000 / 30;␊
}␊
disable_PIT2();␊
return retval;␊
}␊
#endif␊
/*␊
* Measures the Actual Performance Frequency in Hz (64-bit)␊
*/␊
static uint64_t measure_aperf_frequency(void)␊
{␊
uint64_t aperfStart;␊
uint64_t aperfEnd;␊
uint64_t aperfDelta = 0xffffffffffffffffULL;␊
unsigned long pollCount;␊
uint64_t retval = 0;␊
int i;␊
␊
/* Time how many APERF ticks elapse in 30 msec using the 8254 PIT␊
* counter 2. We run this loop 3 times to make sure the cache␊
* is hot and we take the minimum delta from all of the runs.␊
* That is to say that we're biased towards measuring the minimum␊
* number of APERF ticks that occur while waiting for the timer to␊
* expire. ␊
*/␊
for(i = 0; i < 10; ++i)␊
{␊
enable_PIT2();␊
set_PIT2_mode0(CALIBRATE_LATCH);␊
aperfStart = rdmsr64(MSR_AMD_APERF);␊
pollCount = poll_PIT2_gate();␊
aperfEnd = rdmsr64(MSR_AMD_APERF);␊
/* The poll loop must have run at least a few times for accuracy */␊
if(pollCount <= 1)␊
continue;␊
/* The TSC must increment at LEAST once every millisecond. We␊
* should have waited exactly 30 msec so the APERF delta should␊
* be >= 30. Anything less and the processor is way too slow.␊
*/␊
if((aperfEnd - aperfStart) <= CALIBRATE_TIME_MSEC)␊
continue;␊
// tscDelta = MIN(tscDelta, (tscEnd - tscStart))␊
if( (aperfEnd - aperfStart) < aperfDelta )␊
aperfDelta = aperfEnd - aperfStart;␊
}␊
/* mperfDelta is now the least number of MPERF ticks the processor made in␊
* a timespan of 0.03 s (e.g. 30 milliseconds)␊
*/␊
␊
if(aperfDelta > (1ULL<<32))␊
retval = 0;␊
else␊
{␊
retval = aperfDelta * 1000 / 30;␊
}␊
disable_PIT2();␊
return retval;␊
}␊
␊
␊
/*␊
* Calculates the FSB and CPU frequencies using specific MSRs for each CPU␊
* - multi. is read from a specific MSR. In the case of Intel, there is:␊
* a max multi. (used to calculate the FSB freq.),␊
␉do_cpuid(0x00000001, p->CPU.CPUID[CPUID_1]);␊
␉do_cpuid(0x00000002, p->CPU.CPUID[CPUID_2]);␊
␉do_cpuid(0x00000003, p->CPU.CPUID[CPUID_3]);␊
␉do_cpuid2(0x00000004, 0, p->CPU.CPUID[CPUID_4]);␊
do_cpuid2(0x00000004, 0, p->CPU.CPUID[CPUID_4]);␊
␉do_cpuid(0x80000000, p->CPU.CPUID[CPUID_80]);␊
␉if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 1) {␊
if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 8) {␊
do_cpuid(0x80000008, p->CPU.CPUID[CPUID_88]);␊
do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊
␉}␊
else if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 1) {␊
␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊
␉}␊
␊
␊
#if DEBUG_CPU␊
␉{␊
␉␉int␉␉i;␊
␉␉printf("CPUID Raw Values:\n");␊
␉␉for (i=0; i<CPUID_MAX; i++) {␊
␉␉␉printf("%02d: %08x-%08x-%08x-%08x\n", i,␊
␉␉␉␉p->CPU.CPUID[i][0], p->CPU.CPUID[i][1],␊
␉␉␉␉p->CPU.CPUID[i][2], p->CPU.CPUID[i][3]);␊
p->CPU.CPUID[i][0], p->CPU.CPUID[i][1],␊
p->CPU.CPUID[i][2], p->CPU.CPUID[i][3]);␊
␉␉}␊
␉}␊
#endif␊
␉␊
p->CPU.Model += (p->CPU.ExtModel << 4);␊
␊
if (p->CPU.Vendor == 0x756E6547 /* Intel */ && ␊
if (p->CPU.Vendor == CPUID_VENDOR_INTEL && ␊
p->CPU.Family == 0x06 && ␊
p->CPU.Model >= CPUID_MODEL_NEHALEM && ␊
p->CPU.Model != CPUID_MODEL_ATOM // MSR is *NOT* available on the Intel Atom CPU␊
){␊
)␊
{␊
msr = rdmsr64(MSR_CORE_THREAD_COUNT);␉␉␉␉␉␉␉␉␉// Undocumented MSR in Nehalem and newer CPUs␊
p->CPU.NoCores␉␉= bitfield((uint32_t)msr, 31, 16);␉␉␉␉␉// Using undocumented MSR to get actual values␊
p->CPU.NoThreads␉= bitfield((uint32_t)msr, 15, 0);␉␉␉␉␉// Using undocumented MSR to get actual values␊
␉} else {␊
␉}␊
else if (p->CPU.Vendor == CPUID_VENDOR_AMD)␊
{␊
p->CPU.NoThreads␉= bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␊
p->CPU.NoCores␉␉= bitfield(p->CPU.CPUID[CPUID_88][2], 7, 0) + 1;␊
}␊
else␊
{␊
p->CPU.NoThreads␉= bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␉␉// Use previous method for Cores and Threads␊
p->CPU.NoCores␉␉= bitfield(p->CPU.CPUID[CPUID_4][0], 31, 26) + 1;␊
␉}␊
␉␉strlcpy(p->CPU.BrandString,␉s, sizeof(p->CPU.BrandString));␊
␉␉␊
␉␉if (!strncmp(p->CPU.BrandString, CPU_STRING_UNKNOWN, MIN(sizeof(p->CPU.BrandString), strlen(CPU_STRING_UNKNOWN) + 1))) {␊
␉␉␉ /*␊
␉␉␉ * This string means we have a firmware-programmable brand string,␊
␉␉␉ * and the firmware couldn't figure out what sort of CPU we have.␊
␉␉␉ */␊
␉␉␉ p->CPU.BrandString[0] = '\0';␊
␉␉ }␊
/*␊
* This string means we have a firmware-programmable brand string,␊
* and the firmware couldn't figure out what sort of CPU we have.␊
*/␊
p->CPU.BrandString[0] = '\0';␊
}␊
␉}␊
␉␊
␉/* setup features */␊
␉fsbFrequency = 0;␊
␉cpuFrequency = 0;␊
␊
␉if ((p->CPU.Vendor == 0x756E6547 /* Intel */) && ((p->CPU.Family == 0x06) || (p->CPU.Family == 0x0f))) {␊
␉if ((p->CPU.Vendor == CPUID_VENDOR_INTEL) && ((p->CPU.Family == 0x06) || (p->CPU.Family == 0x0f))) {␊
␉␉int intelCPU = p->CPU.Model;␊
␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) || (p->CPU.Family == 0x0f && p->CPU.Model >= 0x03)) {␊
␉␉␉/* Nehalem CPU model */␊
p->CPU.Model == CPU_MODEL_SANDY ||␊
p->CPU.Model == CPU_MODEL_SANDY_XEON)) {␊
␉␉␉␉msr = rdmsr64(MSR_PLATFORM_INFO);␊
␉␉␉␉DBG("msr(%d): platform_info %08x\n", __LINE__, msr & 0xffffffff);␊
␉␉␉␉bus_ratio_max = (msr >> 8) & 0xff;␊
␉␉␉␉bus_ratio_min = (msr >> 40) & 0xff; //valv: not sure about this one (Remarq.1)␊
DBG("msr(%d): platform_info %08x\n", __LINE__, bitfield(msr, 31, 0));␊
bus_ratio_max = bitfield(msr, 14, 8);␊
bus_ratio_min = bitfield(msr, 46, 40); //valv: not sure about this one (Remarq.1)␊
␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊
␉␉␉␉DBG("msr(%d): flex_ratio %08x\n", __LINE__, msr & 0xffffffff);␊
␉␉␉␉if ((msr >> 16) & 0x01) {␊
␉␉␉␉␉flex_ratio = (msr >> 8) & 0xff;␊
DBG("msr(%d): flex_ratio %08x\n", __LINE__, bitfield(msr, 31, 0));␊
if (bitfield(msr, 16, 16)) {␊
flex_ratio = bitfield(msr, 14, 8);␊
␉␉␉␉␉/* bcc9: at least on the gigabyte h67ma-ud2h,␊
␉␉␉␉␉ where the cpu multipler can't be changed to␊
␉␉␉␉␉ allow overclocking, the flex_ratio msr has unexpected (to OSX)␊
␉␉␉␉␉ contents. These contents cause mach_kernel to␊
␉␉␉␉␉ fail to compute the bus ratio correctly, instead␊
␉␉␉␉␉ causing the system to crash since tscGranularity␊
␉␉␉␉␉ is inadvertently set to 0.␊
␉␉␉␉␉*/␊
where the cpu multipler can't be changed to␊
allow overclocking, the flex_ratio msr has unexpected (to OSX)␊
contents. These contents cause mach_kernel to␊
fail to compute the bus ratio correctly, instead␊
causing the system to crash since tscGranularity␊
is inadvertently set to 0.␊
*/␊
␉␉␉␉␉if (flex_ratio == 0) {␊
␉␉␉␉␉␉/* Clear bit 16 (evidently the␊
␉␉␉␉␉␉ presence bit) */␊
␉␉␉␉␉␉/* Clear bit 16 (evidently the presence bit) */␊
␉␉␉␉␉␉wrmsr64(MSR_FLEX_RATIO, (msr & 0xFFFFFFFFFFFEFFFFULL));␊
␉␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊
␉␉␉␉␉␉verbose("Unusable flex ratio detected. Patched MSR now %08x\n", msr & 0xffffffff);␊
verbose("Unusable flex ratio detected. Patched MSR now %08x\n", bitfield(msr, 31, 0));␊
␉␉␉␉␉} else {␊
␉␉␉␉␉␉if (bus_ratio_max > flex_ratio) {␊
␉␉␉␉␉␉␉bus_ratio_max = flex_ratio;␊
␉␉␉␉currcoef = bus_ratio_max;␊
␉␉␉} else {␊
␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_STATUS);␊
␉␉␉␉DBG("msr(%d): ia32_perf_stat 0x%08x\n", __LINE__, msr & 0xffffffff);␊
␉␉␉␉currcoef = (msr >> 8) & 0x1f;␊
DBG("msr(%d): ia32_perf_stat 0x%08x\n", __LINE__, bitfield(msr, 31, 0));␊
currcoef = bitfield(msr, 12, 8);␊
␉␉␉␉/* Non-integer bus ratio for the max-multi*/␊
␉␉␉␉maxdiv = (msr >> 46) & 0x01;␊
maxdiv = bitfield(msr, 46, 46);␊
␉␉␉␉/* Non-integer bus ratio for the current-multi (undocumented)*/␊
␉␉␉␉currdiv = (msr >> 14) & 0x01;␊
␊
currdiv = bitfield(msr, 14, 14);␊
␊
␉␉␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0e) || (p->CPU.Family == 0x0f)) // This will always be model >= 3␊
␉␉␉␉{␊
␉␉␉␉␉/* On these models, maxcoef defines TSC freq */␊
␉␉␉␉␉maxcoef = (msr >> 40) & 0x1f;␊
maxcoef = bitfield(msr, 44, 40);␊
␉␉␉␉} else {␊
␉␉␉␉␉/* On lower models, currcoef defines TSC freq */␊
␉␉␉␉␉/* XXX */␊
␉␉␉p->CPU.Features |= CPU_FEATURE_MOBILE;␊
␉␉}␊
␉}␊
#if 0␊
␉else if((p->CPU.Vendor == 0x68747541 /* AMD */) && (p->CPU.Family == 0x0f)) {␊
␉␉if(p->CPU.ExtFamily == 0x00 /* K8 */) {␊
␉␉␉msr = rdmsr64(K8_FIDVID_STATUS);␊
␉␉␉currcoef = (msr & 0x3f) / 2 + 4;␊
␉␉␉currdiv = (msr & 0x01) * 2;␊
␉␉} else if(p->CPU.ExtFamily >= 0x01 /* K10+ */) {␊
␉␉␉msr = rdmsr64(K10_COFVID_STATUS);␊
␉␉␉if(p->CPU.ExtFamily == 0x01 /* K10 */)␊
␉␉␉␉currcoef = (msr & 0x3f) + 0x10;␊
␉␉␉else /* K11+ */␊
␉␉␉␉currcoef = (msr & 0x3f) + 0x08;␊
␉␉␉currdiv = (2 << ((msr >> 6) & 0x07));␊
␉␉}␊
␉else if((p->CPU.Vendor == CPUID_VENDOR_AMD) && (p->CPU.Family == 0x0f))␊
{␊
switch(p->CPU.ExtFamily)␊
{␊
case 0x00: /* K8 */␊
msr = rdmsr64(K8_FIDVID_STATUS);␊
maxcoef = bitfield(msr, 21, 16) / 2 + 4;␊
currcoef = bitfield(msr, 5, 0) / 2 + 4;␊
break;␊
␊
case 0x01: /* K10 */␊
msr = rdmsr64(K10_COFVID_STATUS);␊
do_cpuid2(0x00000006, 0, p->CPU.CPUID[CPUID_6]);␊
if(bitfield(p->CPU.CPUID[CPUID_6][2], 0, 0) == 1) // EffFreq: effective frequency interface␊
{␊
//uint64_t mperf = measure_mperf_frequency();␊
uint64_t aperf = measure_aperf_frequency();␊
cpuFrequency = aperf;␊
}␊
// NOTE: tsc runs at the maccoeff (non turbo)␊
// *not* at the turbo frequency.␊
maxcoef = bitfield(msr, 54, 49) / 2 + 4;␊
currcoef = bitfield(msr, 5, 0) + 0x10;␊
currdiv = 2 << bitfield(msr, 8, 6);␊
␊
break;␊
␊
case 0x05: /* K14 */␊
msr = rdmsr64(K10_COFVID_STATUS);␊
currcoef = (bitfield(msr, 54, 49) + 0x10) << 2;␊
currdiv = (bitfield(msr, 8, 4) + 1) << 2;␊
currdiv += bitfield(msr, 3, 0);␊
␊
␉␉if (currcoef) {␊
␉␉␉if (currdiv) {␊
␉␉␉␉fsbFrequency = ((tscFrequency * currdiv) / currcoef);␊
␉␉␉␉DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);␊
␉␉␉} else {␊
␉␉␉␉fsbFrequency = (tscFrequency / currcoef);␊
␉␉␉␉DBG("%d\n", currcoef);␊
␉␉␉}␊
␉␉␉fsbFrequency = (tscFrequency / currcoef);␊
␉␉␉cpuFrequency = tscFrequency;␊
␉␉}␊
␉}␊
break;␊
␊
case 0x02: /* K11 */␊
// not implimented␊
break;␊
}␊
␊
if (maxcoef)␊
{␊
if (currdiv)␊
{␊
if(!currcoef) currcoef = maxcoef;␊
if(!cpuFrequency)␊
fsbFrequency = ((tscFrequency * currdiv) / currcoef);␊
else ␊
fsbFrequency = ((cpuFrequency * currdiv) / currcoef);␊
␊
␉if (!fsbFrequency) {␊
␉␉fsbFrequency = (DEFAULT_FSB * 1000);␊
␉␉cpuFrequency = tscFrequency;␊
␉␉DBG("0 ! using the default value for FSB !\n");␊
␉}␊
DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);␊
} else {␊
if(!cpuFrequency)␊
fsbFrequency = (tscFrequency / maxcoef);␊
else ␊
fsbFrequency = (cpuFrequency / maxcoef);␊
DBG("%d\n", currcoef);␊
}␊
}␊
else if (currcoef)␊
{␊
if (currdiv)␊
{␊
fsbFrequency = ((tscFrequency * currdiv) / currcoef);␊
DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);␊
} else {␊
fsbFrequency = (tscFrequency / currcoef);␊
DBG("%d\n", currcoef);␊
}␊
}␊
if(!cpuFrequency) cpuFrequency = tscFrequency;␊
}␊
#if 0␊
if (!fsbFrequency) {␊
fsbFrequency = (DEFAULT_FSB * 1000);␊
cpuFrequency = tscFrequency;␊
DBG("0 ! using the default value for FSB !\n");␊
}␊
#endif␊
␊
␉p->CPU.MaxCoef = maxcoef;␊
␉p->CPU.MaxDiv = maxdiv;␊
␉p->CPU.CurrCoef = currcoef;␊
␉p->CPU.CurrDiv = currdiv;␊
␉p->CPU.TSCFrequency = tscFrequency;␊
␉p->CPU.FSBFrequency = fsbFrequency;␊
␉p->CPU.CPUFrequency = cpuFrequency;␊
␊
␉DBG("CPU: Brand String: %s\n",␉␉␉␉p->CPU.BrandString);␊
␉DBG("CPU: Vendor/Family/ExtFamily: 0x%x/0x%x/0x%x\n",␉p->CPU.Vendor, p->CPU.Family, p->CPU.ExtFamily);␊
␉DBG("CPU: Model/ExtModel/Stepping: 0x%x/0x%x/0x%x\n",␉p->CPU.Model, p->CPU.ExtModel, p->CPU.Stepping);␊
␉DBG("CPU: MaxCoef/CurrCoef: 0x%x/0x%x\n",␉␉p->CPU.MaxCoef, p->CPU.CurrCoef);␊
␉DBG("CPU: MaxDiv/CurrDiv: 0x%x/0x%x\n",␉␉p->CPU.MaxDiv, p->CPU.CurrDiv);␊
␉DBG("CPU: TSCFreq: %dMHz\n",␉␉␉p->CPU.TSCFrequency / 1000000);␊
␉DBG("CPU: FSBFreq: %dMHz\n",␉␉␉p->CPU.FSBFrequency / 1000000);␊
␉DBG("CPU: CPUFreq: %dMHz\n",␉␉␉p->CPU.CPUFrequency / 1000000);␊
␉DBG("CPU: NoCores/NoThreads: %d/%d\n",␉␉␉p->CPU.NoCores, p->CPU.NoThreads);␊
␉DBG("CPU: Features: 0x%08x\n",␉␉␉p->CPU.Features);␊
␊
p->CPU.MaxCoef = maxcoef;␊
p->CPU.MaxDiv = maxdiv;␊
p->CPU.CurrCoef = currcoef;␊
p->CPU.CurrDiv = currdiv;␊
p->CPU.TSCFrequency = tscFrequency;␊
p->CPU.FSBFrequency = fsbFrequency;␊
p->CPU.CPUFrequency = cpuFrequency;␊
␊
DBG("CPU: Brand String: %s\n",␉␉␉␉p->CPU.BrandString);␊
DBG("CPU: Vendor/Family/ExtFamily: 0x%x/0x%x/0x%x\n",␉p->CPU.Vendor, p->CPU.Family, p->CPU.ExtFamily);␊
DBG("CPU: Model/ExtModel/Stepping: 0x%x/0x%x/0x%x\n",␉p->CPU.Model, p->CPU.ExtModel, p->CPU.Stepping);␊
DBG("CPU: MaxCoef/CurrCoef: 0x%x/0x%x\n",␉␉p->CPU.MaxCoef, p->CPU.CurrCoef);␊
DBG("CPU: MaxDiv/CurrDiv: 0x%x/0x%x\n",␉␉p->CPU.MaxDiv, p->CPU.CurrDiv);␊
DBG("CPU: TSCFreq: %dMHz\n",␉␉␉p->CPU.TSCFrequency / 1000000);␊
DBG("CPU: FSBFreq: %dMHz\n",␉␉␉p->CPU.FSBFrequency / 1000000);␊
DBG("CPU: CPUFreq: %dMHz\n",␉␉␉p->CPU.CPUFrequency / 1000000);␊
DBG("CPU: NoCores/NoThreads: %d/%d\n",␉␉␉p->CPU.NoCores, p->CPU.NoThreads);␊
DBG("CPU: Features: 0x%08x\n",␉␉␉p->CPU.Features);␊
#if DEBUG_CPU␊
␉pause();␊
pause();␊
#endif␊
}␊
branches/iFabio/Chameleon/i386/libsaio/platform.h
1313
1414
1515
16
17
18
19
1620
1721
1822
1923
2024
2125
22
23
24
26
27
28
29
30
2531
2632
2733
extern void scan_platform(void);␊
extern void dumpPhysAddr(const char * title, void * a, int len);␊
␊
/* CPUID Vendor */␊
#define CPUID_VENDOR_INTEL 0x756E6547␊
#define CPUID_VENDOR_AMD 0x68747541␊
␊
/* CPUID index into cpuid_raw */␊
#define CPUID_0␉␉␉␉0␊
#define CPUID_1␉␉␉␉1␊
#define CPUID_2␉␉␉␉2␊
#define CPUID_3␉␉␉␉3␊
#define CPUID_4␉␉␉␉4␊
#define CPUID_80␉␉␉5␊
#define CPUID_81␉␉␉6␊
#define CPUID_MAX␉␉␉7␊
#define CPUID_6␉␉␉␉5␊
#define CPUID_80␉␉␉6␊
#define CPUID_81␉␉␉7␊
#define CPUID_88␉␉␉8␊
#define CPUID_MAX␉␉␉9␊
␊
#define CPU_MODEL_YONAH␉␉␉0x0E␉␉␉// Sossaman, Yonah␊
#define CPU_MODEL_MEROM␉␉␉0x0F␉␉␉// Allendale, Conroe, Kentsfield, Woodcrest, Clovertown, Tigerton, Merom␊
branches/iFabio/Chameleon/i386/libsaio/cpu.h
1616
1717
1818
19
19
2020
2121
2222
......
2828
2929
3030
31
32
33
3134
3235
3336
␊
#define CPU_STRING_UNKNOWN␉␉"Unknown CPU Type"␊
␊
#define␉MSR_IA32_PERF_STATUS␉0x198␊
#define␉MSR_IA32_PERF_STATUS␉0x00000198␊
#define MSR_IA32_PERF_CONTROL␉0x199␊
#define MSR_IA32_EXT_CONFIG␉0x00EE␊
#define MSR_FLEX_RATIO␉␉0x194␊
#define K8_FIDVID_STATUS␉0xC0010042␊
#define K10_COFVID_STATUS␉0xC0010071␊
␊
#define MSR_AMD_MPERF 0x000000E7␊
#define MSR_AMD_APERF 0x000000E8␊
␊
#define DEFAULT_FSB␉␉100000 /* for now, hardcoding 100MHz for old CPUs */␊
␊
// DFE: This constant comes from older xnu:␊
branches/iFabio/Chameleon/i386/libsaio/stringTable.c
650650
651651
652652
653
653
654654
655655
656656
␉␉"bt(0,0)/Extra/org.chameleon.Boot.plist",␊
␉␉␊
␉␉"rd(0,0)/Extra/com.apple.Boot.plist", /* DEPRECIATED */␊
␉␉"/Extra/com.apple.Boot.plist" /* DEPRECIATED */␊
␉␉"/Extra/com.apple.Boot.plist", /* DEPRECIATED */␊
␉␉"bt(0,0)/Extra/com.apple.Boot.plist", /* DEPRECIATED */␊
␉};␊
␊
branches/iFabio/Chameleon/i386/boot2/drivers.c
746746
747747
748748
749
750
749
750
751
752
751753
752
754
753755
754756
755757
756
757758
758759
759760
␊
if (length == -1) return -1;␊
␊
#if 0 /** remove this check. **/ ␊
if (strcmp(XMLCastString(XMLGetProperty(moduleDict, kPropOSBundleRequired)), "Safe Boot") == 0)␊
␊
if (!(gBootMode & kBootModeSafe) &&␊
XMLGetProperty(moduleDict, kPropOSBundleRequired) && ␊
strcmp(XMLCastString(XMLGetProperty(moduleDict, kPropOSBundleRequired)), "Safe Boot") == 0)␊
{␊
// Don't load Safe Boot kexts. NOTE: -x should be check too.␊
// Don't load Safe Boot kexts if -x not specified.␊
XMLFreeTag(moduleDict);␊
return -2;␊
}␊
#endif ␊
␊
tmpModule = malloc(sizeof(Module));␊
if (tmpModule == 0)␊
branches/iFabio/Chameleon/i386/boot2/boot.c
607607
608608
609609
610
610
611611
612
613
614
615
616
617
618
612
613
614
619615
620616
621617
622
623
618
619
620
621
622
623
624
624625
625
626626
627627
628628
629629
630630
631
631
632
632633
633634
634
635
636
635637
636638
637639
638640
639641
640642
641
643
644
642645
643646
644647
645
648
649
646650
647651
648652
......
679683
680684
681685
682
686
683687
684688
685689
bootFile = bootInfo->bootFile;␊
␊
// Try to load kernel image from alternate locations on boot helper partitions.␊
sprintf(bootFileSpec, "com.apple.boot.P/%s", bootFile);␊
sprintf(bootFileSpec, "com.apple.boot.P%s", bootFile);␊
ret = GetFileInfo(NULL, bootFileSpec, &flags, &time); ␊
␉ ␉ if (ret == -1)␊
␉ ␉ {␊
sprintf(bootFileSpec, "com.apple.boot.R/%s", bootFile);␊
ret = GetFileInfo(NULL, bootFileSpec, &flags, &time); ␊
if (ret == -1)␊
{␊
sprintf(bootFileSpec, "com.apple.boot.S/%s", bootFile);␊
if (ret == -1)␊
{␊
sprintf(bootFileSpec, "com.apple.boot.R%s", bootFile);␊
ret = GetFileInfo(NULL, bootFileSpec, &flags, &time); ␊
if (ret == -1)␊
{␊
// No alternate location found, using the original kernel image path.␊
strcpy(bootFileSpec, bootFile);␊
sprintf(bootFileSpec, "com.apple.boot.S%s", bootFile);␊
ret = GetFileInfo(NULL, bootFileSpec, &flags, &time); ␊
if (ret == -1)␊
{␊
// No alternate location found, using the original kernel image path.␊
strcpy(bootFileSpec, bootFile);␊
}␊
}␊
}␊
}␊
␊
if (checkOSVersion("10.7"))␊
{␊
//Lion, dont load kernel if haz cache␊
if (!trycache) {␊
if (!trycache) ␊
{␊
␉␉verbose("Loading kernel %s\n", bootFileSpec);␊
␉␉ret = LoadThinFatFile(bootFileSpec, &binary);␊
␉␉if (ret <= 0 && archCpuType == CPU_TYPE_X86_64) {␊
␉␉if (ret <= 0 && archCpuType == CPU_TYPE_X86_64) ␊
{␊
␉␉␉archCpuType = CPU_TYPE_I386;␊
␉␉␉ret = LoadThinFatFile(bootFileSpec, &binary);␉␉␉␉␊
␉␉}␊
␉␉ } ␊
␉␉␉␉else ret = 1;␊
} ␊
␉␉␉else {␊
␉␉␉else ␊
{␊
//Snow Leopard or older␊
verbose("Loading kernel %s\n", bootFileSpec);␊
ret = LoadThinFatFile(bootFileSpec, &binary);␊
if (ret <= 0 && archCpuType == CPU_TYPE_X86_64) {␊
if (ret <= 0 && archCpuType == CPU_TYPE_X86_64) ␊
{␊
archCpuType = CPU_TYPE_I386;␊
ret = LoadThinFatFile(bootFileSpec, &binary);␉␉␉␉␊
}␊
}␊
␉␊
if ((gBootFileType == kNetworkDeviceType) && gUnloadPXEOnExit) {␊
␉nbpUnloadBaseCode();␊
␉␉nbpUnloadBaseCode();␊
}␊
}␊
␊
branches/iFabio/Chameleon/i386/modules/GraphicsEnabler/NVIDIAGraphicsEnabler/nvidia.c
11
2
2
33
4
4
55
6
7
8
9
6
7
8
9
1010
11
12
13
14
11
12
13
14
1515
16
17
16
17
1818
1919
2020
2121
22
23
22
23
2424
2525
2626
......
4848
4949
5050
51
52
51
52
53
5354
5455
5556
......
7172
7273
7374
74
75
76
77
78
75
76
77
78
79
80
7981
80
81
82
83
8482
8583
86
87
88
89
90
91
92
93
94
84
85
86
87
88
89
90
91
9592
9693
9794
......
110107
111108
112109
113
110
114111
115112
116113
......
840837
841838
842839
840
843841
844842
843
845844
846845
847846
......
851850
852851
853852
854
853
855854
856855
857856
......
859858
860859
861860
861
862862
863863
864864
865865
866
866867
867868
868869
......
875876
876877
877878
878
879
880
879881
880882
881
882
883
884
883
884
885
886
887
885888
886
887
888
889
890
891
889892
890
893
894
891895
892896
893
897
898
894899
895
900
896901
902
897903
898
904
905
906
899907
900908
901909
902
903
904
910
911
912
913
905914
906915
907
916
917
918
908919
909920
910921
911922
912
923
924
925
913926
914927
915928
916
929
930
931
917932
918933
919934
920935
921
936
922937
923938
924
925
939
940
941
942
926943
927944
928945
929946
930947
931
948
949
932950
933951
952
934953
935954
936955
......
942961
943962
944963
945
946964
947965
948966
949967
950968
951
952
969
970
971
972
953973
954974
955975
956976
957977
958978
979
959980
960
961
962
981
982
983
984
985
963986
987
964988
965989
966990
967
968
991
992
993
969994
970995
971
972
973
996
997
998
999
1000
9741001
9751002
9761003
9771004
978
979
1005
1006
1007
1008
9801009
9811010
9821011
9831012
984
1013
1014
1015
9851016
9861017
9871018
9881019
989
1020
1021
9901022
9911023
9921024
9931025
9941026
1027
9951028
9961029
9971030
9981031
999
1032
1033
1034
10001035
10011036
10021037
10031038
1004
1039
1040
10051041
10061042
10071043
10081044
10091045
1010
10111046
10121047
10131048
......
10181053
10191054
10201055
1021
1022
1056
1057
1058
1059
1060
10231061
1024
1062
1063
10251064
1065
10261066
10271067
1068
10281069
1029
1070
1071
10301072
10311073
10321074
......
10361078
10371079
10381080
1039
1040
1081
1082
1083
1084
10411085
1086
10421087
1088
10431089
1090
10441091
1045
10461092
10471093
10481094
1049
1050
1051
1052
1053
1095
1096
1097
1098
1099
1100
1101
10541102
10551103
10561104
......
10591107
10601108
10611109
1062
1063
1064
1065
1110
1111
1112
1113
1114
10661115
10671116
1117
10681118
1069
1070
1119
1120
1121
1122
1123
10711124
10721125
10731126
10741127
1128
10751129
10761130
10771131
10781132
10791133
1080
1081
1082
1134
1135
1136
10831137
1084
1085
1138
1139
10861140
1087
1141
10881142
1089
1143
10901144
1091
1145
10921146
1093
1147
10941148
1095
1149
10961150
1097
1151
10981152
1153
10991154
11001155
11011156
11021157
11031158
1104
1159
11051160
11061161
11071162
11081163
11091164
11101165
1111
1166
11121167
11131168
11141169
......
11181173
11191174
11201175
1121
1176
1177
1178
11221179
11231180
11241181
......
11341191
11351192
11361193
1137
1194
1195
11381196
11391197
11401198
1141
1199
1200
11421201
11431202
11441203
11451204
1146
1205
1206
11471207
11481208
11491209
1150
1210
11511211
11521212
11531213
11541214
11551215
1156
1216
11571217
11581218
11591219
......
11621222
11631223
11641224
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
11861245
11871246
11881247
11891248
11901249
11911250
1192
1251
11931252
11941253
11951254
11961255
1197
1256
11981257
11991258
12001259
1201
1260
12021261
1203
1204
1262
1263
1264
1265
1266
12051267
12061268
1207
1269
1270
1271
12081272
12091273
1210
1274
1275
1276
12111277
12121278
12131279
1214
1280
1281
1282
12151283
12161284
1217
1285
12181286
1219
1287
12201288
12211289
12221290
12231291
12241292
1225
1293
1294
12261295
12271296
12281297
1229
1298
12301299
12311300
12321301
12331302
1234
1235
1303
1304
12361305
1237
1306
1307
12381308
12391309
12401310
12411311
1242
1312
1313
12431314
12441315
1245
1316
1317
1318
12461319
12471320
1248
1321
1322
1323
12491324
12501325
1251
1326
1327
1328
12521329
12531330
12541331
1255
1332
12561333
12571334
12581335
12591336
1260
1337
12611338
1262
1339
12631340
1264
1265
1341
1342
1343
1344
12661345
12671346
1268
1347
1348
1349
12691350
12701351
12711352
1272
1353
12731354
12741355
12751356
12761357
1277
1358
12781359
12791360
12801361
1281
1282
1362
1363
12831364
12841365
12851366
......
12871368
12881369
12891370
1371
12901372
1373
12911374
12921375
1376
12931377
1294
1295
1378
1379
1380
1381
12961382
12971383
1298
1299
1300
1384
1385
1386
1387
1388
1389
13011390
1302
1391
1392
13031393
13041394
13051395
1306
1396
1397
13071398
13081399
13091400
......
13171408
13181409
13191410
1320
13211411
1322
1323
1324
1325
1412
1413
1414
1415
1416
1417
1418
13261419
13271420
13281421
13291422
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
13741459
13751460
13761461
......
13781463
13791464
13801465
1381
1382
1466
1467
13831468
13841469
13851470
1386
1387
1471
1472
13881473
13891474
1390
1475
1476
13911477
13921478
1393
1479
13941480
13951481
13961482
1397
1483
13981484
13991485
/*␊
* NVidia injector␊
*␉NVidia injector␊
*␊
* Copyright (C) 2009 Jasmin Fazlic, iNDi␊
*␉Copyright (C) 2009␉Jasmin Fazlic, iNDi␊
*␊
* NVidia injector is free software: you can redistribute it and/or modify␊
* it under the terms of the GNU General Public License as published by␊
* the Free Software Foundation, either version 3 of the License, or␊
* (at your option) any later version.␊
*␉NVidia injector is free software: you can redistribute it and/or modify␊
*␉it under the terms of the GNU General Public License as published by␊
*␉the Free Software Foundation, either version 3 of the License, or␊
*␉(at your option) any later version.␊
*␊
* NVidia driver and injector is distributed in the hope that it will be useful,␊
* but WITHOUT ANY WARRANTY; without even the implied warranty of␊
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the␊
* GNU General Public License for more details.␊
*␉NVidia driver and injector is distributed in the hope that it will be useful,␊
*␉but WITHOUT ANY WARRANTY; without even the implied warranty of␊
*␉MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the␊
*␉GNU General Public License for more details.␊
*␊
* You should have received a copy of the GNU General Public License␊
* along with NVidia injector. If not, see <http://www.gnu.org/licenses/>.␊
*␉You should have received a copy of the GNU General Public License␊
*␉along with NVidia injector.␉ If not, see <http://www.gnu.org/licenses/>.␊
*/ ␊
/*␊
* Alternatively you can choose to comply with APSL␊
*/␊
␊
␊
␊
␊
/*␊
* DCB-Table parsing is based on software (nouveau driver) originally distributed under following license:␊
*␊
* SOFTWARE.␊
*/␊
␊
#include "libsaio.h"␊
#include "boot.h"␊
//#include "boot.h"␊
#include "libsa.h"␊
#include "saio_internal.h"␊
#include "bootstruct.h"␊
#include "pci.h"␊
#include "platform.h"␊
#define kDcfg0␉␉␉␉␉␉"display_0"␊
#define kDcfg1␉␉␉␉␉␉"display_1"␊
␊
#define NVIDIA_ROM_SIZE 0x10000␊
#define PATCH_ROM_SUCCESS 1␊
#define PATCH_ROM_SUCCESS_HAS_LVDS 2␊
#define PATCH_ROM_FAILED 0␊
#define MAX_NUM_DCB_ENTRIES 16␊
#define NVIDIA_ROM_SIZE␉␉␉␉0x10000␊
#define PATCH_ROM_SUCCESS␉␉␉1␊
#define PATCH_ROM_SUCCESS_HAS_LVDS␉2␊
#define PATCH_ROM_FAILED␉␉␉0␊
#define MAX_NUM_DCB_ENTRIES␉␉␉16␊
#define TYPE_GROUPED␉␉␉␉0xff␊
␊
␊
␊
#define TYPE_GROUPED 0xff␊
␊
extern uint32_t devices_number;␊
␊
const char *nvidia_compatible_0[]␉=␉{ "@0,compatible",␉"NVDA,NVMac" };␊
const char *nvidia_compatible_1[]␉=␉{ "@1,compatible",␉"NVDA,NVMac" };␊
const char *nvidia_device_type_0[]␉=␉{ "@0,device_type",␉"display" };␊
const char *nvidia_device_type_1[]␉=␉{ "@1,device_type",␉"display" };␊
const char *nvidia_device_type[]␉=␉{ "device_type",␉"NVDA,Parent" };␊
const char *nvidia_name_0[]␉␉=␉{ "@0,name",␉␉"NVDA,Display-A" };␊
const char *nvidia_name_1[]␉␉=␉{ "@1,name",␉␉"NVDA,Display-B" };␊
const char *nvidia_slot_name[]␉␉=␉{ "AAPL,slot-name",␉"Slot-1" };␊
//const char *nvidia_display_cfg_0[] = { "@0,display-cfg␊
const char *nvidia_compatible_0[]␉=␉{ "@0,compatible",␉"NVDA,NVMac"␉ };␊
const char *nvidia_compatible_1[]␉=␉{ "@1,compatible",␉"NVDA,NVMac"␉ };␊
const char *nvidia_device_type_0[]␉=␉{ "@0,device_type", "display"␉␉ };␊
const char *nvidia_device_type_1[]␉=␉{ "@1,device_type", "display"␉␉ };␊
const char *nvidia_device_type[]␉=␉{ "device_type",␉"NVDA,Parent"␉ };␊
const char *nvidia_name_0[]␉␉␉=␉{ "@0,name",␉␉"NVDA,Display-A" };␊
const char *nvidia_name_1[]␉␉␉=␉{ "@1,name",␉␉"NVDA,Display-B" };␊
const char *nvidia_slot_name[]␉␉=␉{ "AAPL,slot-name", "Slot-1"␉␉ };␊
␊
static uint8_t default_NVCAP[]= {␊
␉0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0d, 0x00,␊
static struct nv_chipsets_t NVKnownChipsets[] = {␊
␉{ 0x00000000, "Unknown" },␊
// temporary placement␊
␉{ 0x10DE0DF4, "GeForce GT 450M" }, // mine + issue #99␊
␉{ 0x10DE0DF4, "GeForce GT 450M" }, //Azi + issue #99␊
␉{ 0x10DE1251, "GeForce GTX 560M" }, // Asus G74SX␊
//========================================␊
␉// 0040 - 004F␉␊
static uint16_t read16(uint8_t *ptr, uint16_t offset)␊
{␊
␉uint8_t ret[2];␊
␉␊
␉ret[0] = ptr[offset+1];␊
␉ret[1] = ptr[offset];␊
␉␊
␉return *((uint16_t*)&ret);␊
}␊
␊
␉return ((x & 0x000000FF) << 24) | ((x & 0x0000FF00) << 8 ) | ((x & 0x00FF0000) >> 8 ) | ((x & 0xFF000000) >> 24);␊
}␊
␊
static uint8_t read8(uint8_t *ptr, uint16_t offset)␊
static uint8_t␉read8(uint8_t *ptr, uint16_t offset)␊
{ ␊
␉return ptr[offset];␊
}␊
static uint32_t read32(uint8_t *ptr, uint16_t offset)␊
{␊
␉uint8_t ret[4];␊
␉␊
␉ret[0] = ptr[offset+3];␊
␉ret[1] = ptr[offset+2];␊
␉ret[2] = ptr[offset+1];␊
␉ret[3] = ptr[offset];␊
␉␊
␉return *((uint32_t*)&ret);␊
}␊
#endif␊
␉}␊
␉␊
␉uint16_t dcbptr = swap16(read16(rom, 0x36));␊
␉if(!dcbptr) {␊
␉␊
␉if (!dcbptr) {␊
␉␉printf("no dcb table found\n");␊
␉␉return PATCH_ROM_FAILED;␊
␉}/* else␊
␉ printf("dcb table at offset 0x%04x\n", dcbptr);␊
␉ */␊
␉uint8_t *dcbtable = &rom[dcbptr];␊
␉}␊
//␉else␊
//␉␉printf("dcb table at offset 0x%04x\n", dcbptr);␊
␉ ␊
␉uint8_t *dcbtable␉␉ = &rom[dcbptr];␊
␉uint8_t dcbtable_version = dcbtable[0];␊
␉uint8_t headerlength = 0;␊
␉uint8_t recordlength = 0;␊
␉uint8_t numentries = 0;␊
␉uint8_t headerlength␉ = 0;␊
␉uint8_t numentries␉␉ = 0;␊
␉uint8_t recordlength␉ = 0;␊
␉␊
␉if(dcbtable_version >= 0x20) {␊
␉if (dcbtable_version >= 0x20)␊
␉{␊
␉␉uint32_t sig;␊
␉␉␊
␉␉if(dcbtable_version >= 0x30) {␊
␉␉if (dcbtable_version >= 0x30)␊
␉␉{␊
␉␉␉headerlength = dcbtable[1];␊
␉␉␉numentries = dcbtable[2];␊
␉␉␉numentries␉ = dcbtable[2];␊
␉␉␉recordlength = dcbtable[3];␊
␉␉␉␊
␉␉␉sig = *(uint32_t *)&dcbtable[6];␊
␉␉} else {␊
␉␉}␊
␉␉else␊
␉␉{␊
␉␉␉sig = *(uint32_t *)&dcbtable[4];␊
␉␉␉headerlength = 8;␊
␉␉}␊
␉␉if (sig != 0x4edcbdcb) {␊
␉␉␉//Azi: match this with one below and add line number ?␊
␉␉␉printf("Bad display config block signature (0x%8x)\n", sig);␊
␉␉␊
␉␉if (sig != 0x4edcbdcb)␊
␉␉{␊
␉␉␉printf("Bad display config block signature (0x%8x)\n", sig); //Azi: issue #48␊
␉␉␉return PATCH_ROM_FAILED;␊
␉␉}␊
␉} else if (dcbtable_version >= 0x14) { /* some NV15/16, and NV11+ */␊
␉}␊
␉else if (dcbtable_version >= 0x14) /* some NV15/16, and NV11+ */␊
␉{␊
␉␉char sig[8] = { 0 };␊
␉␉␊
␉␉strncpy(sig, (char *)&dcbtable[-7], 7);␊
␉␉recordlength = 10;␊
␉␉if (strcmp(sig, "DEV_REC")) {␊
␉␉␊
␉␉if (strcmp(sig, "DEV_REC"))␊
␉␉{␊
␉␉␉printf("Bad Display Configuration Block signature (%s)\n", sig);␊
␉␉␉return PATCH_ROM_FAILED;␊
␉␉}␊
␉} else {␊
␉}␊
␉else␊
␉{␊
␉␉printf("ERROR: dcbtable_version is 0x%X\n", dcbtable_version);␊
␉␉return PATCH_ROM_FAILED;␊
␉}␊
␉␊
␉if(numentries >= MAX_NUM_DCB_ENTRIES)␊
␉if (numentries >= MAX_NUM_DCB_ENTRIES)␊
␉␉numentries = MAX_NUM_DCB_ENTRIES;␊
␉␊
␉uint8_t num_outputs = 0, i=0;␊
␉struct dcbentry {␊
␉uint8_t num_outputs = 0, i = 0;␊
␉␊
␉struct dcbentry␊
␉{␊
␉␉uint8_t type;␊
␉␉uint8_t index;␊
␉␉uint8_t *heads;␊
␉} entries[numentries];␊
␉␊
␉for (i = 0; i < numentries; i++) {␊
␉for (i = 0; i < numentries; i++)␊
␉{␊
␉␉uint32_t connection;␊
␉␉connection = *(uint32_t *)&dcbtable[headerlength + recordlength * i];␊
␉␉␊
␉␉/* Should we allow discontinuous DCBs? Certainly DCB I2C tables can be discontinuous */␊
␉␉if ((connection & 0x0000000f) == 0x0000000f) /* end of records */ ␊
␉␉␉continue;␊
␉␉entries[num_outputs].type = connection & 0xf;␊
␉␉entries[num_outputs].index = num_outputs;␊
␉␉entries[num_outputs++].heads = (uint8_t*)&(dcbtable[(headerlength + recordlength * i) + 1]);␊
␊
␉}␊
␉␊
␉int has_lvds = false;␊
␉uint8_t channel1 = 0, channel2 = 0;␊
␉␊
␉for(i=0; i<num_outputs; i++) {␊
␉␉if(entries[i].type == 3) {␊
␉for (i = 0; i < num_outputs; i++)␊
␉{␊
␉␉if (entries[i].type == 3)␊
␉␉{␊
␉␉␉has_lvds = true;␊
␉␉␉//printf("found LVDS\n");␊
␉␉␉channel1 |= ( 0x1 << entries[i].index);␊
␉␉␉entries[i].type = TYPE_GROUPED;␊
␉␉}␊
␉}␊
␉␊
␉// if we have a LVDS output, we group the rest to the second channel␊
␉if(has_lvds) {␊
␉␉for(i=0; i<num_outputs; i++) {␊
␉␉␉if(entries[i].type == TYPE_GROUPED)␊
␉if (has_lvds)␊
␉{␊
␉␉for (i = 0; i < num_outputs; i++)␊
␉␉{␊
␉␉␉if (entries[i].type == TYPE_GROUPED)␊
␉␉␉␉continue;␊
␉␉␉␊
␉␉␉channel2 |= ( 0x1 << entries[i].index);␊
␉␉␉entries[i].type = TYPE_GROUPED;␊
␉␉}␊
␉} else {␊
␉␉//␊
␉}␊
␉else␊
␉{␊
␉␉int x;␊
␉␉// we loop twice as we need to generate two channels␊
␉␉for(x=0; x<=1; x++) {␊
␉␉␉for(i=0; i<num_outputs; i++) {␊
␉␉␉␉if(entries[i].type == TYPE_GROUPED)␊
␉␉for (x = 0; x <= 1; x++)␊
␉␉{␊
␉␉␉for (i=0; i<num_outputs; i++)␊
␉␉␉{␊
␉␉␉␉if (entries[i].type == TYPE_GROUPED)␊
␉␉␉␉␉continue;␊
␉␉␉␉// if type is TMDS, the prior output is ANALOG␊
␉␉␉␉// we always group ANALOG and TMDS␊
␉␉␉␉// if there is a TV output after TMDS, we group it to that channel as well␊
␉␉␉␉if(i && entries[i].type == 0x2) {␊
␉␉␉␉␉switch (x) {␊
␉␉␉␉if (i && entries[i].type == 0x2)␊
␉␉␉␉{␊
␉␉␉␉␉switch (x)␊
␉␉␉␉␉{␊
␉␉␉␉␉␉case 0:␊
␉␉␉␉␉␉␉//printf("group channel 1\n");␊
␉␉␉␉␉␉␉channel1 |= ( 0x1 << entries[i].index);␊
␉␉␉␉␉␉␉entries[i].type = TYPE_GROUPED;␊
␉␉␉␉␉␉␉if((entries[i-1].type == 0x0)) {␊
␉␉␉␉␉␉␉␊
␉␉␉␉␉␉␉if ((entries[i-1].type == 0x0))␊
␉␉␉␉␉␉␉{␊
␉␉␉␉␉␉␉␉channel1 |= ( 0x1 << entries[i-1].index);␊
␉␉␉␉␉␉␉␉entries[i-1].type = TYPE_GROUPED;␊
␉␉␉␉␉␉␉}␊
␉␉␉␉␉␉␉// group TV as well if there is one␊
␉␉␉␉␉␉␉if( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) ) {␊
␉␉␉␉␉␉␉if ( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) )␊
␉␉␉␉␉␉␉{␊
␉␉␉␉␉␉␉␉//␉printf("group tv1\n");␊
␉␉␉␉␉␉␉␉channel1 |= ( 0x1 << entries[i+1].index);␊
␉␉␉␉␉␉␉␉entries[i+1].type = TYPE_GROUPED;␊
␉␉␉␉␉␉␉}␊
␉␉␉␉␉␉␉break;␊
␉␉␉␉␉␉␊
␉␉␉␉␉␉case 1:␊
␉␉␉␉␉␉␉//printf("group channel 2 : %d\n", i);␊
␉␉␉␉␉␉␉channel2 |= ( 0x1 << entries[i].index);␊
␉␉␉␉␉␉␉entries[i].type = TYPE_GROUPED;␊
␉␉␉␉␉␉␉if((entries[i-1].type == 0x0)) {␊
␉␉␉␉␉␉␉␊
␉␉␉␉␉␉␉if ((entries[i - 1].type == 0x0))␊
␉␉␉␉␉␉␉{␊
␉␉␉␉␉␉␉␉channel2 |= ( 0x1 << entries[i-1].index);␊
␉␉␉␉␉␉␉␉entries[i-1].type = TYPE_GROUPED;␊
␉␉␉␉␉␉␉}␊
␉␉␉␉␉␉␉// group TV as well if there is one␊
␉␉␉␉␉␉␉if( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) ) {␊
␉␉␉␉␉␉␉if ( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) )␊
␉␉␉␉␉␉␉{␊
␉␉␉␉␉␉␉␉//␉printf("group tv2\n");␊
␉␉␉␉␉␉␉␉channel2 |= ( 0x1 << entries[i+1].index);␊
␉␉␉␉␉␉␉␉entries[i+1].type = TYPE_GROUPED;␊
␉␉␉␉␉␉␉}␊
␉␉␉␉␉␉␉break;␊
␉␉␉␉␉␉␉␊
␉␉␉␉␉}␊
␉␉␉␉␉break;␊
␉␉␉␉}␊
␉// if we have left ungrouped outputs merge them to the empty channel␊
␉uint8_t *togroup;// = (channel1 ? (channel2 ? NULL : &channel2) : &channel1);␊
␉togroup = &channel2;␊
␉for(i=0; i<num_outputs;i++)␊
␉␉if(entries[i].type != TYPE_GROUPED) {␊
␉␊
␉for (i = 0; i < num_outputs; i++)␊
␉{␊
␉␉if (entries[i].type != TYPE_GROUPED)␊
␉␉{␊
␉␉␉//printf("%d not grouped\n", i);␊
␉␉␉if(togroup)␊
␉␉␉if (togroup)␊
␉␉␉{␊
␉␉␉␉*togroup |= ( 0x1 << entries[i].index);␊
␉␉␉}␊
␉␉␉entries[i].type = TYPE_GROUPED;␊
␉␉}␊
␉}␊
␉␊
␉if(channel1 > channel2) {␊
␉if (channel1 > channel2)␊
␉{␊
␉␉uint8_t buff = channel1;␊
␉␉channel1 = channel2;␊
␉␉channel2 = buff;␊
␉default_NVCAP[8] = channel2;␊
␉␊
␉// patching HEADS␊
␉for(i=0; i<num_outputs;i++) {␊
␉␉if(channel1 & (1 << i))␊
␉for (i = 0; i < num_outputs; i++)␊
␉{␊
␉␉if (channel1 & (1 << i))␊
␉␉{␊
␉␉␉*entries[i].heads = 1;␊
␉␉}␊
␉␉else if(channel2 & (1 << i))␊
␉␉{␊
␉␉␉*entries[i].heads = 2;␊
␉␉}␊
␉}␊
␉␊
␉return (has_lvds ? PATCH_ROM_SUCCESS_HAS_LVDS : PATCH_ROM_SUCCESS);␊
}␊
␊
static char *get_nvidia_model(uint32_t id) {␊
␉int␉i;␊
␊
␉for (i=1; i< (sizeof(NVKnownChipsets) / sizeof(NVKnownChipsets[0])); i++) {␊
␉␉if (NVKnownChipsets[i].device == id) {␊
static char *get_nvidia_model(uint32_t id)␊
{␊
␉int i;␊
␉␊
␉for (i = 1; i < (sizeof(NVKnownChipsets) / sizeof(NVKnownChipsets[0])); i++) {␊
␉␉if (NVKnownChipsets[i].device == id)␊
␉␉{␊
␉␉␉return NVKnownChipsets[i].name;␊
␉␉}␊
␉}␊
␊
static uint32_t load_nvidia_bios_file(const char *filename, uint8_t *buf, int bufsize)␊
{␊
␉int␉fd;␊
␉int␉size;␊
␊
␉if ((fd = open_bvdev("bt(0,0)", filename, 0)) < 0) {␊
␉int fd;␊
␉int size;␊
␉␊
␉if ((fd = open_bvdev("bt(0,0)", filename, 0)) < 0)␊
␉{␊
␉␉return 0;␊
␉}␊
␉␊
␉size = file_size(fd);␊
␉if (size > bufsize) {␊
␉␉printf("Filesize of %s is bigger than expected! Truncating to 0x%x Bytes!\n", filename, bufsize);␊
␉␊
␉if (size > bufsize)␊
␉{␊
␉␉printf("Filesize of %s is bigger than expected! Truncating to 0x%x Bytes!\n",␊
␉␉␉␉filename, bufsize);␊
␉␉size = bufsize;␊
␉}␊
␉size = read(fd, (char *)buf, size);␊
␉close(fd);␊
␉␊
␉return size > 0 ? size : 0;␊
}␊
␊
static int devprop_add_nvidia_template(struct DevPropDevice *device)␊
{␊
␉char␉tmp[16]; ␊
␊
␉if(!device)␊
␉char tmp[16];␊
␉␊
␉if (!device)␊
␉␉return 0;␊
␊
␉if(!DP_ADD_TEMP_VAL(device, nvidia_compatible_0))␊
␉␊
␉if (!DP_ADD_TEMP_VAL(device, nvidia_compatible_0))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL(device, nvidia_device_type_0))␊
␉if (!DP_ADD_TEMP_VAL(device, nvidia_device_type_0))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL(device, nvidia_name_0))␊
␉if (!DP_ADD_TEMP_VAL(device, nvidia_name_0))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL(device, nvidia_compatible_1))␊
␉if (!DP_ADD_TEMP_VAL(device, nvidia_compatible_1))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL(device, nvidia_device_type_1))␊
␉if (!DP_ADD_TEMP_VAL(device, nvidia_device_type_1))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL(device, nvidia_name_1))␊
␉if (!DP_ADD_TEMP_VAL(device, nvidia_name_1))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL(device, nvidia_device_type))␊
␉if (!DP_ADD_TEMP_VAL(device, nvidia_device_type))␊
␉␉return 0;␊
␉␊
␉// Rek : Dont use sprintf return, it does not WORK !! our custom sprintf() always return 0!␊
␉// len = sprintf(tmp, "Slot-%x", devices_number);␊
␉sprintf(tmp, "Slot-%x",devices_number);␊
␉devprop_add_value(device, "AAPL,slot-name", (uint8_t *) tmp, strlen(tmp));␊
␉devices_number++;␊
␊
␉␊
␉return 1;␊
}␊
␊
int hex2bin(const char *hex, uint8_t *bin, int len)␊
{␊
␉char␉*p;␊
␉int␉i;␊
␉int␉␉i;␊
␉char␉buf[3];␊
␉␊
␉if (hex == NULL || bin == NULL || len <= 0 || strlen(hex) != len * 2) {␊
␉␊
␉buf[2] = '\0';␊
␉p = (char *) hex;␊
␉for (i=0; i<len; i++) {␊
␉␊
␉for (i = 0; i < len; i++)␊
␉{␊
␉␉if (p[0] == '\0' || p[1] == '\0' || !isxdigit(p[0]) || !isxdigit(p[1])) {␊
␉␉␉printf("[ERROR] bin2hex '%s' syntax error\n", hex);␊
␉␉␉return -2;␊
{␊
␉unsigned long long vram_size = 0;␊
␉␊
␉if (nvCardType < NV_ARCH_50) {␊
␉if (nvCardType < NV_ARCH_50)␊
␉{␊
␉␉vram_size = REG32(NV04_PFB_FIFO_DATA);␊
␉␉vram_size &= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK;␊
␉}␊
␉else if (nvCardType < NV_ARCH_C0) {␊
␉else if (nvCardType < NV_ARCH_C0)␊
␉{␊
␉␉vram_size = REG32(NV04_PFB_FIFO_DATA);␊
␉␉vram_size |= (vram_size & 0xff) << 32;␊
␉␉vram_size &= 0xffffffff00ll;␊
␉}␊
␉else { // >= NV_ARCH_C0␊
␉else // >= NV_ARCH_C0␊
␉{␊
␉␉vram_size = REG32(NVC0_MEM_CTRLR_RAM_AMOUNT) << 20;␊
␉␉vram_size *= REG32(NVC0_MEM_CTRLR_COUNT);␊
␉}␊
␊
␉␊
␉// Workaround for GT 420/430 & 9600M GT␊
␉switch (nvda_dev->device_id)␊
␉{␊
␉␉case 0x0DE1: vram_size = 1024*1024*1024; break; // GT 430␊
␉␉case 0x0DE2: vram_size = 1024*1024*1024; break; // GT 420␊
␉␉case 0x0649: vram_size = 512*1024*1024; break; // 9600M GT␊
␉␉case 0x0649: vram_size = 512*1024*1024; break;␉// 9600M GT␊
␉␉default: break;␊
␉}␊
␉␊
␊
bool setup_nvidia_devprop(pci_dt_t *nvda_dev)␊
{␊
␉struct DevPropDevice␉␉*device;␊
␉char␉␉␉␉␉␉*devicepath;␊
␉option_rom_pci_header_t␉␉*rom_pci_header;␉␊
␉volatile uint8_t␉*regs;␊
␉uint8_t␉␉␉␉*rom;␊
␉uint8_t␉␉␉␉*nvRom;␊
␉uint8_t␉␉␉␉nvCardType;␊
␉unsigned long long␉videoRam;␊
␉uint32_t␉␉␉nvBiosOveride;␊
␉uint32_t␉␉␉bar[7];␊
␉uint32_t␉␉␉boot_display;␊
␉int␉␉␉␉␉nvPatch;␊
␉int␉␉␉␉␉len;␊
␉char␉␉␉␉biosVersion[32];␊
␉char␉␉␉␉nvFilename[32];␊
␉char␉␉␉␉kNVCAP[12];␊
␉char␉␉␉␉*model;␊
␉const char␉␉␉*value;␊
␉bool␉␉␉␉doit;␊
␊
␊
␉struct DevPropDevice␉*device;␊
␉char␉␉␉␉␉*devicepath;␊
␉option_rom_pci_header_t *rom_pci_header;␊
␉volatile uint8_t␉␉*regs;␊
␉uint8_t␉␉␉␉␉*rom;␊
␉uint8_t␉␉␉␉␉*nvRom;␊
␉uint8_t␉␉␉␉␉nvCardType;␊
␉unsigned long long␉␉videoRam;␊
␉uint32_t␉␉␉␉nvBiosOveride;␊
␉uint32_t␉␉␉␉bar[7];␊
␉uint32_t␉␉␉␉boot_display;␊
␉int␉␉␉␉␉␉nvPatch;␊
␉int␉␉␉␉␉␉len;␊
␉char␉␉␉␉␉biosVersion[32];␊
␉char␉␉␉␉␉nvFilename[32];␊
␉char␉␉␉␉␉kNVCAP[12];␊
␉char␉␉␉␉␉*model;␊
␉const char␉␉␉␉*value;␊
␉bool␉␉␉␉␉doit;␊
␉␊
␉devicepath = get_pci_dev_path(nvda_dev);␊
␉bar[0] = pci_config_read32(nvda_dev->dev.addr, 0x10 );␊
␉regs = (uint8_t *) (bar[0] & ~0x0f);␊
␉␊
␉// get card type␊
␉nvCardType = (REG32(0) >> 20) & 0x1ff;␊
␊
␉␊
␉// Amount of VRAM in kilobytes␊
␉videoRam = mem_detect(regs, nvCardType, nvda_dev);␊
␉model = get_nvidia_model((nvda_dev->vendor_id << 16) | nvda_dev->device_id);␊
␉␊
␉verbose("nVidia %s %dMB NV%02x [%04x:%04x] :: %s\n", ␊
␉verbose("nVidia %s %dMB NV%02x [%04x:%04x] :: %s\n",␊
␉␉␉model, (uint32_t)(videoRam / 1024 / 1024),␊
␉␉␉(REG32(0) >> 20) & 0x1ff, nvda_dev->vendor_id, nvda_dev->device_id,␊
␉␉␉devicepath);␊
␊
␉␊
␉rom = malloc(NVIDIA_ROM_SIZE);␊
␉sprintf(nvFilename, "/Extra/%04x_%04x.rom", (uint16_t)nvda_dev->vendor_id, (uint16_t)nvda_dev->device_id);␊
␉if (getBoolForKey(kUseNvidiaROM, &doit, &bootInfo->chameleonConfig) && doit) {␊
␉sprintf(nvFilename, "/Extra/%04x_%04x.rom", (uint16_t)nvda_dev->vendor_id,␊
␉␉␉(uint16_t)nvda_dev->device_id);␊
␉␊
␉if (getBoolForKey(kUseNvidiaROM, &doit, &bootInfo->chameleonConfig) && doit)␊
␉{␊
␉␉verbose("Looking for nvidia video bios file %s\n", nvFilename);␊
␉␉nvBiosOveride = load_nvidia_bios_file(nvFilename, rom, NVIDIA_ROM_SIZE);␊
␉␉if (nvBiosOveride > 0) {␊
␉␉␊
␉␉if (nvBiosOveride > 0)␊
␉␉{␊
␉␉␉verbose("Using nVidia Video BIOS File %s (%d Bytes)\n", nvFilename, nvBiosOveride);␊
␉␉␉DBG("%s Signature 0x%02x%02x %d bytes\n", nvFilename, rom[0], rom[1], nvBiosOveride);␊
␉␉} else {␊
␉␉}␊
␉␉else␊
␉␉{␊
␉␉␉printf("ERROR: unable to open nVidia Video BIOS File %s\n", nvFilename);␊
␉␉␉return false;␊
␉␉}␊
␉} else {␊
␉}␊
␉else␊
␉{␊
␉␉// Otherwise read bios from card␊
␉␉nvBiosOveride = 0;␊
␊
␉␉␊
␉␉// TODO: we should really check for the signature before copying the rom, i think.␊
␊
␉␉␊
␉␉// PRAMIN first␊
␉␉nvRom = (uint8_t*)&regs[NV_PRAMIN_OFFSET];␊
␉␉bcopy((uint32_t *)nvRom, rom, NVIDIA_ROM_SIZE);␊
␉␉␊
␉␉// Valid Signature ?␊
␉␉if (rom[0] != 0x55 && rom[1] != 0xaa) {␊
␉␉if (rom[0] != 0x55 && rom[1] != 0xaa)␊
␉␉{␊
␉␉␉// PROM next␊
␉␉␉// Enable PROM access␊
␉␉␉(REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED;␊
␊
␉␉␉␊
␉␉␉nvRom = (uint8_t*)&regs[NV_PROM_OFFSET];␊
␉␉␉bcopy((uint8_t *)nvRom, rom, NVIDIA_ROM_SIZE);␊
␉␉␉␊
␉␉␉// disable PROM access␊
␉␉␉(REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED;␉␊
␊
␉␉␉(REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED;␊
␉␉␉␊
␉␉␉// Valid Signature ?␊
␉␉␉if (rom[0] != 0x55 && rom[1] != 0xaa) {␊
␉␉␉if (rom[0] != 0x55 && rom[1] != 0xaa)␊
␉␉␉{␊
␉␉␉␉// 0xC0000 last␊
␉␉␉␉bcopy((char *)0xc0000, rom, NVIDIA_ROM_SIZE);␊
␉␉␉␉␊
␉␉␉␉// Valid Signature ?␊
␉␉␉␉if (rom[0] != 0x55 && rom[1] != 0xaa) {␊
␉␉␉␉if (rom[0] != 0x55 && rom[1] != 0xaa)␊
␉␉␉␉{␊
␉␉␉␉␉printf("ERROR: Unable to locate nVidia Video BIOS\n");␊
␉␉␉␉␉return false;␊
␉␉␉␉} else {␊
␉␉␉␉}␊
␉␉␉␉else␊
␉␉␉␉{␊
␉␉␉␉␉DBG("ROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);␊
␉␉␉␉}␊
␉␉␉} else {␊
␉␉␉}␊
␉␉␉else␊
␉␉␉{␊
␉␉␉␉DBG("PROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);␊
␉␉␉}␊
␉␉} else {␊
␉␉}␊
␉␉else␊
␉␉{␊
␉␉␉DBG("PRAM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);␊
␉␉}␊
␉}␊
␊
␉␊
␉if ((nvPatch = patch_nvidia_rom(rom)) == PATCH_ROM_FAILED) {␊
␉␉printf("ERROR: nVidia ROM Patching Failed!\n");␊
␉␉//return false;␊
␉}␊
␊
␉␊
␉rom_pci_header = (option_rom_pci_header_t*)(rom + *(uint16_t *)&rom[24]);␊
␊
␉␊
␉// check for 'PCIR' sig␊
␉if (rom_pci_header->signature == 0x50434952) {␊
␉␉if (rom_pci_header->device_id != nvda_dev->device_id) {␊
␉if (rom_pci_header->signature == 0x50434952)␊
␉{␊
␉␉if (rom_pci_header->device_id != nvda_dev->device_id)␊
␉␉{␊
␉␉␉// Get Model from the OpROM␊
␉␉␉model = get_nvidia_model((rom_pci_header->vendor_id << 16) | rom_pci_header->device_id);␊
␉␉} else {␊
␉␉}␊
␉␉else␊
␉␉{␊
␉␉␉printf("nVidia incorrect PCI ROM signature: 0x%x\n", rom_pci_header->signature);␊
␉␉}␊
␉}␊
␊
␉␊
␉if (!string) {␊
␉␉string = devprop_create_string();␊
␉}␊
␉device = devprop_add_device(string, devicepath);␊
␊
␉␊
␉/* FIXME: for primary graphics card only */␊
␉boot_display = 1;␊
␉devprop_add_value(device, "@0,AAPL,boot-display", (uint8_t*)&boot_display, 4);␊
␊
␉if(nvPatch == PATCH_ROM_SUCCESS_HAS_LVDS) {␊
␉␊
␉if (nvPatch == PATCH_ROM_SUCCESS_HAS_LVDS) {␊
␉␉uint8_t built_in = 0x01;␊
␉␉devprop_add_value(device, "@0,built-in", &built_in, 1);␊
␉}␊
␉// get bios version␊
␉const int MAX_BIOS_VERSION_LENGTH = 32;␊
␉char* version_str = (char*)malloc(MAX_BIOS_VERSION_LENGTH);␊
␉␊
␉memset(version_str, 0, MAX_BIOS_VERSION_LENGTH);␊
␉␊
␉int i, version_start;␊
␉int crlf_count = 0;␊
␉␊
␉// only search the first 384 bytes␊
␉for(i = 0; i < 0x180; i++) {␊
␉␉if(rom[i] == 0x0D && rom[i+1] == 0x0A) {␊
␉for (i = 0; i < 0x180; i++)␊
␉{␊
␉␉if (rom[i] == 0x0D && rom[i+1] == 0x0A)␊
␉␉{␊
␉␉␉crlf_count++;␊
␉␉␉// second 0x0D0A was found, extract bios version␊
␉␉␉if(crlf_count == 2) {␊
␉␉␉␉if(rom[i-1] == 0x20) i--; // strip last " "␊
␉␉␉␉for(version_start = i; version_start > (i-MAX_BIOS_VERSION_LENGTH); version_start--) {␊
␉␉␉if (crlf_count == 2)␊
␉␉␉{␊
␉␉␉␉if (rom[i-1] == 0x20) i--; // strip last " "␊
␉␉␉␉␊
␉␉␉␉for (version_start = i; version_start > (i-MAX_BIOS_VERSION_LENGTH); version_start--)␊
␉␉␉␉{␊
␉␉␉␉␉// find start␊
␉␉␉␉␉if(rom[version_start] == 0x00) {␊
␉␉␉␉␉if (rom[version_start] == 0x00)␊
␉␉␉␉␉{␊
␉␉␉␉␉␉version_start++;␊
␉␉␉␉␉␉␊
␉␉␉␉␉␉// strip "Version "␊
␉␉␉␉␉␉if(strncmp((const char*)rom+version_start, "Version ", 8) == 0) {␊
␉␉␉␉␉␉if (strncmp((const char*)rom+version_start, "Version ", 8) == 0)␊
␉␉␉␉␉␉{␊
␉␉␉␉␉␉␉version_start += 8;␊
␉␉␉␉␉␉}␊
␉␉␉␉␉␉␊
␉}␊
␉␊
␉sprintf(biosVersion, "%s", (nvBiosOveride > 0) ? nvFilename : version_str);␊
␊
␉sprintf(kNVCAP, "NVCAP_%04x", nvda_dev->device_id);␊
␉if (getValueForKey(kNVCAP, &value, &len, &bootInfo->chameleonConfig) && len == NVCAP_LEN * 2) {␊
␉␉uint8_t␉new_NVCAP[NVCAP_LEN];␊
␊
␉␉if (hex2bin(value, new_NVCAP, NVCAP_LEN) == 0) {␊
␉␊
␉if (getValueForKey(kNVCAP, &value, &len, &bootInfo->chameleonConfig) && len == NVCAP_LEN * 2)␊
␉{␊
␉␉uint8_t new_NVCAP[NVCAP_LEN];␊
␉␉␊
␉␉if (hex2bin(value, new_NVCAP, NVCAP_LEN) == 0)␊
␉␉{␊
␉␉␉verbose("Using user supplied NVCAP for %s :: %s\n", model, devicepath);␊
␉␉␉memcpy(default_NVCAP, new_NVCAP, NVCAP_LEN);␊
␉␉}␊
␉}␊
␊
if (getValueForKey(kDcfg0, &value, &len, &bootInfo->chameleonConfig) && len == DCFG0_LEN * 2){␊
␊
uint8_t new_dcfg0[DCFG0_LEN];␊
␊
if (hex2bin(value, new_dcfg0, DCFG0_LEN) == 0)␊
{␊
␊
memcpy(default_dcfg_0, new_dcfg0, DCFG0_LEN);␊
␊
verbose("Using user supplied @0,display-cfg\n");␊
printf("@0,display-cfg: %02x%02x%02x%02x\n",␊
default_dcfg_0[0], default_dcfg_0[1], default_dcfg_0[2], default_dcfg_0[3]); ␊
␊
␊
}␊
}␊
␊
␊
if (getValueForKey(kDcfg1, &value, &len, &bootInfo->chameleonConfig) && len == DCFG1_LEN * 2){␊
␊
uint8_t new_dcfg1[DCFG1_LEN];␊
␊
if (hex2bin(value, new_dcfg1, DCFG1_LEN) == 0)␊
{␊
memcpy(default_dcfg_1, new_dcfg1, DCFG1_LEN);␊
␊
verbose("Using user supplied @1,display-cfg\n");␊
printf("@1,display-cfg: %02x%02x%02x%02x\n",␊
default_dcfg_1[0], default_dcfg_1[1], default_dcfg_1[2], default_dcfg_1[3]);␊
␊
}␊
␊
}␊
␊
␊
␊
#if DEBUG_NVCAP␊
printf("NVCAP: %02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x\n",␊
␉␉default_NVCAP[0], default_NVCAP[1], default_NVCAP[2], default_NVCAP[3],␊
␉␉default_NVCAP[4], default_NVCAP[5], default_NVCAP[6], default_NVCAP[7],␊
␉␉default_NVCAP[8], default_NVCAP[9], default_NVCAP[10], default_NVCAP[11],␊
␉␉default_NVCAP[12], default_NVCAP[13], default_NVCAP[14], default_NVCAP[15],␊
␉␉default_NVCAP[16], default_NVCAP[17], default_NVCAP[18], default_NVCAP[19]);␊
␉␊
␉if (getValueForKey(kDcfg0, &value, &len, &bootInfo->chameleonConfig) && len == DCFG0_LEN * 2)␊
␉{␊
␉␉uint8_t new_dcfg0[DCFG0_LEN];␊
␉␉␊
␉␉if (hex2bin(value, new_dcfg0, DCFG0_LEN) == 0)␊
␉␉{␊
␉␉␉memcpy(default_dcfg_0, new_dcfg0, DCFG0_LEN);␊
␉␉␉␊
␉␉␉verbose("Using user supplied @0,display-cfg\n");␊
␉␉␉printf("@0,display-cfg: %02x%02x%02x%02x\n",␊
␉␉␉␉ default_dcfg_0[0], default_dcfg_0[1], default_dcfg_0[2], default_dcfg_0[3]);␊
␉␉}␊
␉}␊
␉␊
␉if (getValueForKey(kDcfg1, &value, &len, &bootInfo->chameleonConfig) && len == DCFG1_LEN * 2)␊
␉{␊
␉␉uint8_t new_dcfg1[DCFG1_LEN];␊
␉␉␊
␉␉if (hex2bin(value, new_dcfg1, DCFG1_LEN) == 0)␊
␉␉{␊
␉␉␉memcpy(default_dcfg_1, new_dcfg1, DCFG1_LEN);␊
␉␉␉␊
␉␉␉verbose("Using user supplied @1,display-cfg\n");␊
␉␉␉printf("@1,display-cfg: %02x%02x%02x%02x\n",␊
␉␉␉␉ default_dcfg_1[0], default_dcfg_1[1], default_dcfg_1[2], default_dcfg_1[3]);␊
␉␉}␊
␉}␊
␉␊
#if DEBUG_NVCAP␊
␉printf("NVCAP: %02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x\n",␊
␉default_NVCAP[0], default_NVCAP[1], default_NVCAP[2], default_NVCAP[3],␊
␉default_NVCAP[4], default_NVCAP[5], default_NVCAP[6], default_NVCAP[7],␊
␉default_NVCAP[8], default_NVCAP[9], default_NVCAP[10], default_NVCAP[11],␊
␉default_NVCAP[12], default_NVCAP[13], default_NVCAP[14], default_NVCAP[15],␊
␉default_NVCAP[16], default_NVCAP[17], default_NVCAP[18], default_NVCAP[19]);␊
#endif␊
␉␊
␉devprop_add_nvidia_template(device);␊
␉devprop_add_value(device, "VRAM,totalsize", (uint8_t*)&videoRam, 4);␊
␉devprop_add_value(device, "model", (uint8_t*)model, strlen(model) + 1);␊
␉devprop_add_value(device, "rom-revision", (uint8_t*)biosVersion, strlen(biosVersion) + 1);␊
devprop_add_value(device, "@0,display-cfg", default_dcfg_0, DCFG0_LEN);␊
devprop_add_value(device, "@1,display-cfg", default_dcfg_1, DCFG1_LEN);␊
␉devprop_add_value(device, "@0,display-cfg", default_dcfg_0, DCFG0_LEN);␊
␉devprop_add_value(device, "@1,display-cfg", default_dcfg_1, DCFG1_LEN);␊
␉␊
␉//add HDMI Audio back to nvidia␊
␉//http://forge.voodooprojects.org/p/chameleon/issues/67/␊
// uint8_t connector_type_1[]= {0x00, 0x08, 0x00, 0x00};␊
// devprop_add_value(device, "@1,connector-type",connector_type_1, 4);␊
//␉uint8_t connector_type_1[]= {0x00, 0x08, 0x00, 0x00};␊
//␉devprop_add_value(device, "@1,connector-type",connector_type_1, 4);␊
␉//end Nvidia HDMI Audio␊
␉␊
␉if (getBoolForKey(kVBIOS, &doit, &bootInfo->chameleonConfig) && doit) {␊
␉if (getBoolForKey(kVBIOS, &doit, &bootInfo->chameleonConfig) && doit)␊
␉{␊
␉␉devprop_add_value(device, "vbios", rom, (nvBiosOveride > 0) ? nvBiosOveride : (rom[2] * 512));␊
␉}␊
␊
␉␊
␉stringdata = malloc(sizeof(uint8_t) * string->length);␊
␉memcpy(stringdata, (uint8_t*)devprop_generate_string(string), string->length);␊
␉stringlength = string->length;␊
␊
␉␊
␉return true;␊
}␊
branches/iFabio/Chameleon/i386/modules/GraphicsEnabler/ATiGraphicsEnabler/ati.c
2222
2323
2424
25
2625
2726
2827
......
164163
165164
166165
167
166
168167
169168
170169
......
229228
230229
231230
232
231
233232
234233
235234
␊
#include "libsa.h"␊
#include "saio_internal.h"␊
␊
#include "bootstruct.h"␊
#include "pci.h"␊
#include "platform.h"␊
␉{ 0x10029490, "ATI Radeon 4600 Series"} ,␊
␉{ 0x10029498, "ATI Radeon 4600 Series"} ,␊
␉{ 0x1002949E, "ATI Radeon 4600 Series"} ,␊
␉{ 0x10029480, "ATI Radeon 4600 Series"} ,␊
␉{ 0x10029480, "ATI Radeon HD 4650M"␉}, // akbar␊
␉{ 0x10029488, "ATI Radeon 4600 Series"} ,␊
␉{ 0x10029540, "ATI Radeon 4500 Series"} ,␊
␉{ 0x10029541, "ATI Radeon 4500 Series"} ,␊
{ 0x10029490, "Peregrine"} ,␊
{ 0x10029498, "Peregrine"} ,␊
{ 0x1002949E, "Peregrine"} ,␊
{ 0x10029480, "Peregrine"} ,␊
{ 0x10029480, "Shrike"␉␉}, // akbar␊
{ 0x10029488, "Peregrine"} ,␊
{ 0x10029540, "Peregrine"} ,␊
{ 0x10029541, "Peregrine"} ,␊
branches/iFabio/Chameleon/i386/modules/GraphicsEnabler/AMDGraphicsEnabler/ati.c
4646
4747
4848
49
49
5050
5151
5252
......
5555
5656
5757
58
58
5959
6060
6161
6262
63
63
64
65
66
6467
6568
6669
......
8992
9093
9194
92
95
9396
9497
9598
9699
97100
101
102
98103
99104
100105
101106
102
103
107
108
104109
105110
106111
......
213218
214219
215220
221
222
216223
217
224
225
226
218227
219
228
220229
221
230
222231
223
232
224233
225234
226235
......
453462
454463
455464
465
466
456467
457468
458469
459470
460471
461
472
462473
463474
464475
......
534545
535546
536547
537
548
538549
539550
540551
541552
542553
543554
544
555
545556
546557
547558
......
10001011
10011012
10021013
1003
1014
10041015
10051016
10061017
␉CHIP_FAMILY_RS880,␊
␉/* R700 */␊
␉CHIP_FAMILY_RV770,␊
␉CHIP_FAMILY_RV730,␊
␉CHIP_FAMILY_RV730, // review - rv730 is not an HD chipset - see read_disabled_vbios␊
␉CHIP_FAMILY_RV710,␊
␉CHIP_FAMILY_RV740,␊
␉/* Evergreen */␊
␉CHIP_FAMILY_JUNIPER,␊
␉CHIP_FAMILY_CYPRESS,␊
␉CHIP_FAMILY_HEMLOCK,␊
//␉CHIP_FAMILY_GRANVILLE, //Azi: improvising ?? a bit here...␊
//␉CHIP_FAMILY_GRANVILLE, //Azi:---␊
␉/* Northern Islands */␊
␉CHIP_FAMILY_BARTS,␊
␉CHIP_FAMILY_CAICOS,␊
␉CHIP_FAMILY_CAYMAN,␊
␉CHIP_FAMILY_TURKS,␊
␉CHIP_FAMILY_TURKS, // just 6758 & 6759 dev ids - review***␊
␉// mobility␊
␉CHIP_FAMILY_M96,␊
␉//---␊
␉CHIP_FAMILY_LAST␊
} chip_family_t;␊
␊
␉"Juniper",␉// RV840␊
␉"Cypress",␉// RV870␊
␉"Hemlock",␊
//␉"Granville"␉//Azi: improvising ?? a bit here...␊
//␉"Granville"␉//Azi:---␊
␉/* Northern Islands */␊
␉"Barts",␊
␉"Caicos",␊
␉"Cayman",␊
␉"Turks",␊
␉// mobility␊
␉"M96",␊
␉""␊
};␊
␊
typedef struct {␊
␉const char␉␉␉␉*name;␊
␉uint8_t␉␉␉␉␉ports;␊
␉const char␉␉*name;␊
␉uint8_t␉␉␉ports;␊
} card_config_t;␊
␊
static card_config_t card_configs[] = {␊
static radeon_card_info_t radeon_cards[] = {␊
␉//Azi: added devices␊
// temporary placement␊
␉// Akbar␊
␉{ 0x9480,␉0x3629103C,␉CHIP_FAMILY_M96/*RV730*/,"ATI Radeon HD 4650M",␉␉␉␉kShrike␉␉}, // hp OK␊
␉// issue #88␊
␉{ 0x6741,␉0x1646103C,␉CHIP_FAMILY_TURKS,/*???*/"AMD Radeon HD 6600M Series",␉␉kNull␉␉},␊
␉{ 0x6741,␉0x1646103C,␉CHIP_FAMILY_TURKS,/*??*/"AMD Radeon HD 6750M",␉␉␉␉kNull␉␉}, // - review turks␊
␉// issue #121␊
␉{ 0x6741,␉0x050E1025,␉CHIP_FAMILY_TURKS,/*??*/"AMD Radeon HD 6650M",␉␉␉␉kNull␉␉}, // acer - review turks␊
␉// issue #89␊
␉{ 0x68A8,␉0x050E1025,␉CHIP_FAMILY_CYPRESS,␉"AMD Radeon HD 6850M",␉␉␉␉kUakari␉␉}, //Azi: CHIP_FAMILY_GRANVILLE ??␊
␉{ 0x68A8,␉0x050E1025,␉CHIP_FAMILY_CYPRESS,␉"AMD Radeon HD 6850M",␉␉␉␉kUakari␉␉}, //Azi: CHIP_FAMILY_GRANVILLE ?? review␊
␉// issue #90␊
␉{ 0x68E4,␉0x1c921043,␉CHIP_FAMILY_CEDAR,␉␉"ATI Radeon HD 5470M",␉␉␉␉kEulemur␉},␊
␉{ 0x68E4,␉0x1c921043,␉CHIP_FAMILY_CEDAR,␉␉"ATI Radeon HD 5470M",␉␉␉␉kEulemur␉}, // asus - confirm model, chipset␊
␉// issue #91␊
␉{ 0x68C0,␉0x1594103C,␉CHIP_FAMILY_REDWOOD,␉"AMD Radeon HD 6570M",␉␉␉␉kNull␉␉},␊
␉{ 0x68C0,␉0x1594103C,␉CHIP_FAMILY_REDWOOD,␉"AMD Radeon HD 6570M",␉␉␉␉kNull␉␉}, // confirm model, chipset␊
␉␊
␉//==================================//================================//============================//␊
␉␊
␉{ 0x68F9,␉0x5470174B, CHIP_FAMILY_CEDAR,␉␉"ATI Radeon HD 5470",␉␉␉␉kNull␉␉},␊
␉{ 0x68F9,␉0x5490174B, CHIP_FAMILY_CEDAR,␉␉"ATI Radeon HD 5490",␉␉␉␉kNull␉␉},␊
␉{ 0x68F9,␉0x5530174B, CHIP_FAMILY_CEDAR,␉␉"ATI Radeon HD 5530",␉␉␉␉kNull␉␉},␊
␉{ 0x68F9, 0x20091787, CHIP_FAMILY_CEDAR, "ATI Radeon HD 5450", kEulemur }, // issue 119␊
␉{ 0x68F9, 0x22911787, CHIP_FAMILY_CEDAR, "ATI Radeon HD 5450", kEulemur }, // HIS␊
␉␊
␉/* Northen Islands */␊
␉{ 0x6718,␉0x0B001002,␉CHIP_FAMILY_CAYMAN,␉␉"AMD Radeon HD 6970",␉␉␉␉kNull␉␉},␊
␉{ 0x6718,␉0x31301682,␉CHIP_FAMILY_CAYMAN,␉␉"AMD Radeon HD 6970",␉␉␉␉kNull␉␉},␊
␉{ 0x6718,␉0x67181002,␉CHIP_FAMILY_CAYMAN,␉␉"AMD Radeon HD 6970",␉␉␉␉kNull␉␉},␊
␊
␉␊
␉{ 0x6738,␉0x67381002,␉CHIP_FAMILY_BARTS,␉␉"AMD Radeon HD 6870",␉␉␉␉kDuckweed␉},␊
␉{ 0x6739,␉0x67391002,␉CHIP_FAMILY_BARTS,␉␉"AMD Radeon HD 6850",␉␉␉␉kDuckweed␉},␊
␉{ 0x6739,␉0x21F81458,␉CHIP_FAMILY_BARTS,␉␉"AMD Radeon HD 6850",␉␉␉␉kDuckweed␉},␊
␉␊
␉/* Northen Islands */␊
␉{ 0x6718,␉0x00000000,␉CHIP_FAMILY_CAYMAN,␉␉"AMD Radeon HD 6970 Series",␉␉kNull␉␉},␊
␊
␉␊
␉{ 0x6738,␉0x00000000,␉CHIP_FAMILY_BARTS,␉␉"AMD Radeon HD 6870 Series",␉␉kDuckweed␉},␊
␉{ 0x6739,␉0x00000000,␉CHIP_FAMILY_BARTS,␉␉"AMD Radeon HD 6850 Series",␉␉kDuckweed␉},␊
␉{ 0x673E,␉0x00000000,␉CHIP_FAMILY_BARTS,␉␉"AMD Radeon HD 6790 Series",␉␉kNull␉␉},␊
␉␊
␉{ 0x6758,␉0x00000000,␉CHIP_FAMILY_TURKS,␉␉"AMD Radeon HD 6670 Series",␉␉kNull␉␉},␊
␉{ 0x6759,␉0x00000000,␉CHIP_FAMILY_TURKS,␉␉"AMD Radeon HD 6500 Series",␉␉kNull␉␉},␊
␊
␉␊
␉{ 0x6770,␉0x00000000,␉CHIP_FAMILY_CAICOS,␉␉"AMD Radeon HD 6400 Series",␉␉kNull␉␉},␊
␉{ 0x6779,␉0x00000000,␉CHIP_FAMILY_CAICOS,␉␉"AMD Radeon HD 6450 Series",␉␉kNull␉␉},␊
␉␊
␉␉RegWrite32(AVIVO_D2VGA_CONTROL, (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | AVIVO_DVGA_CONTROL_TIMING_SELECT)));␊
␉␉RegWrite32(AVIVO_VGA_RENDER_CONTROL, (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));␊
␉␉␊
␉␉if (chip_family == CHIP_FAMILY_RV730)␊
␉␉if (chip_family == CHIP_FAMILY_RV730) // hum... akbar****␊
␉␉{␊
␉␉␉cg_spll_func_cntl = RegRead32(R600_CG_SPLL_FUNC_CNTL);␊
␉␉␉␊
branches/iFabio/Chameleon/Makefile
103103
104104
105105
106
107
106108
107109
108110
......
116118
117119
118120
121
122
123
119124
120125
121126
␉@mkdir -p ${IMGROOT}/Extra/modules␉␉␉␉␊
␉@echo "\t[MKDIR] ${IMGROOT}/Extra/Themes/Default"␊
␉@mkdir -p ${IMGROOT}/Extra/Themes/Default␉␉␉␉␊
␉@echo "\t[MKDIR] ${IMGROOT}/usr/bin"␊
␉@mkdir -p ${IMGROOT}/usr/bin␊
␉@if [ -e "$(IMGSKELROOT)" ]; then␉␉␉␉\␊
␉␉@echo "\t[CP] ${IMGROOTSKEL} ${IMGROOT}"␉␉\␊
␉␉@cp -R -f "${IMGSKELROOT}"/* "${IMGROOT}";␉␉\␊
␉@cp -f ${SYMROOT}/i386/boot0md ${IMGROOT}/usr/standalone/i386␊
␉@cp -f ${SYMROOT}/i386/boot1h ${IMGROOT}/usr/standalone/i386␊
␉@cp -f ${SYMROOT}/i386/boot1f32 ${IMGROOT}/usr/standalone/i386␊
␉@cp -f ${SYMROOT}/i386/fdisk440 ${IMGROOT}/usr/bin␊
␉@cp -f ${SYMROOT}/i386/bdmesg ${IMGROOT}/usr/bin ␊
␊
␉@echo "\t[HDIUTIL] ${ISOIMAGE}"␊
␉@hdiutil makehybrid -iso -joliet -hfs -hfs-volume-name \␊
␉␉${CDLABEL} -eltorito-boot ${CDBOOT} -no-emul-boot -ov -o \␊

Archive Download the corresponding diff file

Revision: 332