Chameleon Applications

Chameleon Applications Svn Source Tree

Root/branches/trunk/i386/libsaio/usb.c

Source at commit 173 created 13 years 6 months ago.
By ifabio, upload my branch. Add Blackosx background & icon Merged all the scrax's change
1/*␊
2 * usb.c␊
3 * ␊
4 *␊
5 * Created by mackerintel on 12/20/08.␊
6 * Copyright 2008 mackerintel. All rights reserved.␊
7 *␊
8 */␊
9␊
10#include "libsaio.h"␊
11#include "boot.h"␊
12#include "bootstruct.h"␊
13#include "pci.h"␊
14␊
15#ifndef DEBUG_USB␊
16#define DEBUG_USB 0␊
17#endif␊
18␊
19#if DEBUG_USB␊
20#define DBG(x...)␉printf(x)␊
21#else␊
22#define DBG(x...)␊
23#endif␊
24␊
25␊
26struct pciList␊
27{␊
28␉pci_dt_t* pciDev;␊
29␉struct pciList* next;␊
30};␊
31␊
32struct pciList* usbList = NULL;␊
33␊
34int legacy_off (pci_dt_t *pci_dev);␊
35int ehci_acquire (pci_dt_t *pci_dev);␊
36int uhci_reset (pci_dt_t *pci_dev);␊
37␊
38// Add usb device to the list␊
39void notify_usb_dev(pci_dt_t *pci_dev)␊
40{␊
41␉␊
42␉struct pciList* current = usbList;␊
43␉if(!usbList)␊
44␉{␊
45␉␉usbList = (struct pciList*)malloc(sizeof(struct pciList));␊
46␉␉usbList->next = NULL;␊
47␉␉usbList->pciDev = pci_dev;␊
48␉␉␊
49␉}␊
50␉else␊
51␉{␊
52␉␉while(current != NULL && current->next != NULL)␊
53␉␉{␊
54␉␉␉current = current->next;␊
55␉␉}␊
56␉␉current->next = (struct pciList*)malloc(sizeof(struct pciList));␊
57␉␉current = current->next;␊
58␉␉␊
59␉␉current->pciDev = pci_dev;␊
60␉␉current->next = NULL;␊
61␉}␊
62}␊
63␊
64// Loop through the list and call the apropriate patch function␊
65int usb_loop()␊
66{␊
67␉int retVal = 1;␊
68␉bool fix_ehci, fix_uhci, fix_usb, fix_legacy;␊
69␉fix_ehci = fix_uhci = fix_usb = fix_legacy = false;␊
70␉␊
71␉if (getBoolForKey(kUSBBusFix, &fix_usb, &bootInfo->bootConfig))␊
72␉{␊
73␉␉fix_ehci = fix_uhci = fix_legacy = fix_usb;␉// Disable all if none set␊
74␉}␊
75␉else ␊
76␉{␊
77␉␉getBoolForKey(kEHCIacquire, &fix_ehci, &bootInfo->bootConfig);␊
78␉␉getBoolForKey(kUHCIreset, &fix_uhci, &bootInfo->bootConfig);␊
79␉␉getBoolForKey(kLegacyOff, &fix_legacy, &bootInfo->bootConfig);␊
80␉}␊
81␉␊
82␉struct pciList* current = usbList;␊
83␉␊
84␉while(current)␊
85␉{␊
86␉␉switch (pci_config_read8(current->pciDev->dev.addr, PCI_CLASS_PROG))␊
87␉␉{␊
88␉␉␉// EHCI␊
89␉␉␉case 0x20:␊
90␉␉ ␉if(fix_ehci) retVal &= ehci_acquire(current->pciDev);␊
91␉␉ ␉if(fix_legacy) retVal &= legacy_off(current->pciDev);␊
92␉␉␉␉␊
93␉␉␉␉break;␊
94␉␉␉␉␊
95␉␉␉// UHCI␊
96␉␉␉case 0x00:␊
97␉␉␉␉if (fix_uhci) retVal &= uhci_reset(current->pciDev);␊
98␊
99␉␉␉␉break;␊
100␉␉}␊
101␉␉␊
102␉␉current = current->next;␊
103␉}␊
104␉return retVal;␊
105}␊
106␊
107int legacy_off (pci_dt_t *pci_dev)␊
108{␊
109␉// Set usb legacy off modification by Signal64␊
110␉// NOTE: This *must* be called after the last file is loaded from the drive in the event that we are booting form usb.␊
111␉// NOTE2: This should be called after any getc() call. (aka, after the Wait=y keyworkd is used)␊
112␉// AKA: Make this run immediatly before the kernel is called␊
113␉uint32_t␉capaddr, opaddr; ␉␉␊
114␉uint8_t␉␉eecp;␉␉␉␊
115␉uint32_t␉usbcmd, usbsts, usbintr;␉␉␉␊
116␉uint32_t␉usblegsup, usblegctlsts;␉␉␊
117␉␊
118␉int isOSowned;␊
119␉int isBIOSowned;␊
120␉␊
121␉verbose("Setting Legacy USB Off on controller [%04x:%04x] at %02x:%2x.%x\n", ␊
122␉␉␉pci_dev->vendor_id, pci_dev->device_id,␊
123␉␉␉pci_dev->dev.bits.bus, pci_dev->dev.bits.dev, pci_dev->dev.bits.func);␊
124␉␊
125␉␊
126␉// capaddr = Capability Registers = dev.addr + offset stored in dev.addr + 0x10 (USBBASE)␊
127␉capaddr = pci_config_read32(pci_dev->dev.addr, 0x10);␉␊
128␉␊
129␉// opaddr = Operational Registers = capaddr + offset (8bit CAPLENGTH in Capability Registers + offset 0)␊
130␉opaddr = capaddr + *((unsigned char*)(capaddr)); ␉␉␊
131␉␊
132␉// eecp = EHCI Extended Capabilities offset = capaddr HCCPARAMS bits 15:8␊
133␉eecp=*((unsigned char*)(capaddr + 9));␊
134␉␊
135␉DBG("capaddr=%x opaddr=%x eecp=%x\n", capaddr, opaddr, eecp);␊
136␉␊
137␉usbcmd = *((unsigned int*)(opaddr));␉␉␉// Command Register␊
138␉usbsts = *((unsigned int*)(opaddr + 4));␉␉// Status Register␊
139␉usbintr = *((unsigned int*)(opaddr + 8));␉␉// Interrupt Enable Register␊
140␉␊
141␉DBG("usbcmd=%08x usbsts=%08x usbintr=%08x\n", usbcmd, usbsts, usbintr);␊
142␉␊
143␉// read PCI Config 32bit USBLEGSUP (eecp+0) ␊
144␉usblegsup = pci_config_read32(pci_dev->dev.addr, eecp);␊
145␉␊
146␉// informational only␊
147␉isBIOSowned = !!((usblegsup) & (1 << (16)));␊
148␉isOSowned = !!((usblegsup) & (1 << (24)));␊
149␉␊
150␉// read PCI Config 32bit USBLEGCTLSTS (eecp+4) ␊
151␉usblegctlsts = pci_config_read32(pci_dev->dev.addr, eecp + 4);␊
152␉␊
153␉DBG("usblegsup=%08x isOSowned=%d isBIOSowned=%d usblegctlsts=%08x\n", usblegsup, isOSowned, isBIOSowned, usblegctlsts);␊
154␉␊
155␉// Reset registers to Legacy OFF␊
156␉DBG("Clearing USBLEGCTLSTS\n");␊
157␉pci_config_write32(pci_dev->dev.addr, eecp + 4, 0);␉//usblegctlsts␊
158␉␊
159␉// if delay value is in milliseconds it doesn't appear to work. ␊
160␉// setting value to anything up to 65535 does not add the expected delay here.␊
161␉delay(100);␊
162␉␊
163␉usbcmd = *((unsigned int*)(opaddr));␊
164␉usbsts = *((unsigned int*)(opaddr + 4));␊
165␉usbintr = *((unsigned int*)(opaddr + 8));␊
166␉␊
167␉DBG("usbcmd=%08x usbsts=%08x usbintr=%08x\n", usbcmd, usbsts, usbintr);␊
168␉␊
169␉DBG("Clearing Registers\n");␊
170␉␊
171␉// clear registers to default␊
172␉usbcmd = (usbcmd & 0xffffff00);␊
173␉*((unsigned int*)(opaddr)) = usbcmd;␊
174␉*((unsigned int*)(opaddr + 8)) = 0;␉␉␉␉␉//usbintr - clear interrupt registers␊
175␉*((unsigned int*)(opaddr + 4)) = 0x1000;␉␉␉//usbsts - clear status registers ␉␊
176␉pci_config_write32(pci_dev->dev.addr, eecp, 1);␉␉//usblegsup␊
177␉␊
178␉// get the results␊
179␉usbcmd = *((unsigned int*)(opaddr));␊
180␉usbsts = *((unsigned int*)(opaddr + 4));␊
181␉usbintr = *((unsigned int*)(opaddr + 8));␊
182␉␊
183␉DBG("usbcmd=%08x usbsts=%08x usbintr=%08x\n", usbcmd, usbsts, usbintr);␊
184␉␊
185␉// read 32bit USBLEGSUP (eecp+0) ␊
186␉usblegsup = pci_config_read32(pci_dev->dev.addr, eecp);␊
187␉␊
188␉// informational only␊
189␉isBIOSowned = !!((usblegsup) & (1 << (16)));␊
190␉isOSowned = !!((usblegsup) & (1 << (24)));␊
191␉␊
192␉// read 32bit USBLEGCTLSTS (eecp+4) ␊
193␉usblegctlsts = pci_config_read32(pci_dev->dev.addr, eecp + 4);␊
194␉␊
195␉DBG("usblegsup=%08x isOSowned=%d isBIOSowned=%d usblegctlsts=%08x\n", usblegsup, isOSowned, isBIOSowned, usblegctlsts);␊
196␉␊
197␉verbose("Legacy USB Off Done\n");␉␊
198␉return 1;␊
199}␊
200␊
201int ehci_acquire (pci_dt_t *pci_dev)␊
202{␊
203␉int␉␉j, k;␊
204␉uint32_t␉base;␊
205␉uint8_t␉␉eecp;␊
206␉uint8_t␉␉legacy[8];␊
207␉bool␉␉isOwnershipConflict;␉␊
208␉bool␉␉alwaysHardBIOSReset;␊
209␊
210␉alwaysHardBIOSReset = false;␉␊
211␉if (!getBoolForKey(kEHCIhard, &alwaysHardBIOSReset, &bootInfo->bootConfig)) {␊
212␉␉alwaysHardBIOSReset = true;␊
213␉}␊
214␊
215␉pci_config_write16(pci_dev->dev.addr, 0x04, 0x0002);␊
216␉base = pci_config_read32(pci_dev->dev.addr, 0x10);␊
217␊
218␉verbose("EHCI controller [%04x:%04x] at %02x:%2x.%x DMA @%x\n", ␊
219␉␉pci_dev->vendor_id, pci_dev->device_id,␊
220␉␉pci_dev->dev.bits.bus, pci_dev->dev.bits.dev, pci_dev->dev.bits.func, ␊
221␉␉base);␊
222␊
223␉if (*((unsigned char*)base) < 0xc)␊
224␉{␊
225␉␉DBG("Config space too small: no legacy implementation\n");␊
226␉␉return 1;␊
227␉}␊
228␉eecp = *((unsigned char*)(base + 9));␊
229␉if (!eecp) {␊
230␉␉DBG("No extended capabilities: no legacy implementation\n");␊
231␉␉return 1;␊
232␉}␊
233␊
234␉DBG("eecp=%x\n",eecp);␊
235␊
236␉// bad way to do it␊
237␉// pci_conf_write(pci_dev->dev.addr, eecp, 4, 0x01000001);␊
238␉for (j = 0; j < 8; j++) {␊
239␉␉legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j);␊
240␉␉DBG("%02x ", legacy[j]);␊
241␉}␊
242␉DBG("\n");␊
243␊
244␉//Real Job: based on orByte's AppleUSBEHCI.cpp␊
245␉//We try soft reset first - some systems hang on reboot with hard reset␊
246␉// Definitely needed during reboot on 10.4.6␊
247␊
248␉isOwnershipConflict = ((legacy[3] & 1 != 0) && (legacy[2] & 1 != 0));␊
249␉if (!alwaysHardBIOSReset && isOwnershipConflict) {␊
250␉␉DBG("EHCI - Ownership conflict - attempting soft reset ...\n");␊
251␉␉DBG("EHCI - toggle OS Ownership to 0\n");␊
252␉␉pci_config_write8(pci_dev->dev.addr, eecp + 3, 0);␊
253␉␉for (k = 0; k < 25; k++) {␊
254␉␉␉for (j = 0; j < 8; j++) {␊
255␉␉␉␉legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j);␊
256␉␉␉}␊
257␉␉␉if (legacy[3] == 0) {␊
258␉␉␉␉break;␊
259␉␉␉}␊
260␉␉␉delay(10);␊
261␉␉}␊
262␉}␉␊
263␊
264␉DBG("Found USBLEGSUP_ID - value %x:%x - writing OSOwned\n", legacy[3],legacy[2]);␊
265␉pci_config_write8(pci_dev->dev.addr, eecp + 3, 1);␊
266␊
267␉// wait for kEHCI_USBLEGSUP_BIOSOwned bit to clear␊
268␉for (k = 0; k < 25; k++) {␊
269␉␉for (j = 0;j < 8; j++) {␊
270␉␉␉legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j);␊
271␉␉}␊
272␉␉DBG ("%x:%x,",legacy[3],legacy[2]);␊
273␉␉if (legacy[2] == 0) {␊
274␉␉␉break;␊
275␉␉}␊
276␉␉delay(10);␊
277␉}␊
278␊
279␉for (j = 0;j < 8; j++) {␊
280␉␉legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j);␊
281␉}␊
282␉isOwnershipConflict = ((legacy[2]) != 0);␊
283␉if (isOwnershipConflict) {␊
284␉␉// Soft reset has failed. Assume SMI being ignored␊
285␉␉// Hard reset␊
286␉␉// Force Clear BIOS BIT␊
287␉␉DBG("EHCI - Ownership conflict - attempting hard reset ...\n");␉␉␉␊
288␉␉DBG ("%x:%x\n",legacy[3],legacy[2]);␊
289␉␉DBG("EHCI - Force BIOS Ownership to 0\n");␊
290␊
291␉␉pci_config_write8(pci_dev->dev.addr, eecp + 2, 0);␊
292␉␉for (k = 0; k < 25; k++) {␊
293␉␉␉for (j = 0; j < 8; j++) {␊
294␉␉␉␉legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j);␊
295␉␉␉}␊
296␉␉␉DBG ("%x:%x,",legacy[3],legacy[2]);␊
297␊
298␉␉␉if ((legacy[2]) == 0) {␊
299␉␉␉␉break;␊
300␉␉␉}␊
301␉␉␉delay(10);␉␊
302␉␉}␉␉␊
303␉␉// Disable further SMI events␊
304␉␉for (j = 4; j < 8; j++) {␊
305␉␉␉pci_config_write8(pci_dev->dev.addr, eecp + j, 0);␊
306␉␉}␊
307␉}␊
308␊
309␉for (j = 0; j < 8; j++) {␊
310␉␉legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j);␊
311␉}␊
312␊
313␉DBG ("%x:%x\n",legacy[3],legacy[2]);␊
314␊
315␉// Final Ownership Resolution Check...␊
316␉if (legacy[2] & 1) {␉␉␉␉␉␊
317␉␉DBG("EHCI controller unable to take control from BIOS\n");␊
318␉␉return 0;␊
319␉}␊
320␊
321␉DBG("EHCI Acquire OS Ownership done\n");␉␊
322␉return 1;␊
323}␊
324␊
325int uhci_reset (pci_dt_t *pci_dev)␊
326{␊
327␉uint32_t base, port_base;␊
328␉␊
329␉base = pci_config_read32(pci_dev->dev.addr, 0x20);␊
330␉port_base = (base >> 5) & 0x07ff;␊
331␊
332␉verbose("UHCI controller [%04x:%04x] at %02x:%2x.%x base %x(%x)\n", ␊
333␉␉pci_dev->vendor_id, pci_dev->device_id,␊
334␉␉pci_dev->dev.bits.bus, pci_dev->dev.bits.dev, pci_dev->dev.bits.func, ␊
335␉␉port_base, base);␊
336␉␊
337␉pci_config_write16(pci_dev->dev.addr, 0xc0, 0x8f00);␊
338␊
339␉outw (port_base, 0x0002);␊
340␉delay(10);␊
341␉outw (port_base+4,0);␊
342␉delay(10);␊
343␉outw (port_base,0);␊
344␉return 1;␊
345}␊
346

Archive Download this file

Revision: 173