Root/
| Source at commit 214 created 13 years 5 months ago. By ifabio, update to chameleon trunk 630, and now the pakage folder is the same as blackosx branch, also add Icon "building" into buildpkg script, and add mint theme info into the English localizable.strings. | |
|---|---|
| 1 | /*␊ |
| 2 | * ␊ |
| 3 | */␊ |
| 4 | ␊ |
| 5 | #include "libsaio.h"␊ |
| 6 | #include "pci.h"␊ |
| 7 | #include "hpet.h"␊ |
| 8 | ␊ |
| 9 | #ifndef DEBUG_HPET␊ |
| 10 | #define DEBUG_HPET 0␊ |
| 11 | #endif␊ |
| 12 | ␊ |
| 13 | #if DEBUG_HPET␊ |
| 14 | #define DBG(x...) printf(x)␊ |
| 15 | #else␊ |
| 16 | #define DBG(x...)␊ |
| 17 | #endif␊ |
| 18 | ␊ |
| 19 | static struct lpc_controller_t lpc_controllers[] = {␊ |
| 20 | ␊ |
| 21 | ␉// Default unknown chipset␊ |
| 22 | ␉{ 0, 0, "" },␊ |
| 23 | ␊ |
| 24 | ␉// Intel␊ |
| 25 | ␉{ 0x8086, 0x24dc, "ICH5" },␊ |
| 26 | ␉{ 0x8086, 0x2640, "ICH6" },␊ |
| 27 | ␉{ 0x8086, 0x2641, "ICH6M" },␊ |
| 28 | ␊ |
| 29 | ␉{ 0x8086, 0x27b0, "ICH7 DH" },␊ |
| 30 | ␉{ 0x8086, 0x27b8, "ICH7" },␊ |
| 31 | ␉{ 0x8086, 0x27b9, "ICH7M" },␊ |
| 32 | ␉{ 0x8086, 0x27bd, "ICH7M DH" },␊ |
| 33 | ␊ |
| 34 | ␉{ 0x8086, 0x2810, "ICH8R" },␊ |
| 35 | ␉{ 0x8086, 0x2811, "ICH8M-E" },␊ |
| 36 | ␉{ 0x8086, 0x2812, "ICH8DH" },␊ |
| 37 | ␉{ 0x8086, 0x2814, "ICH8DO" },␊ |
| 38 | ␉{ 0x8086, 0x2815, "ICH8M" },␊ |
| 39 | ␊ |
| 40 | ␉{ 0x8086, 0x2912, "ICH9DH" },␊ |
| 41 | ␉{ 0x8086, 0x2914, "ICH9DO" },␊ |
| 42 | ␉{ 0x8086, 0x2916, "ICH9R" },␊ |
| 43 | ␉{ 0x8086, 0x2917, "ICH9M-E" },␊ |
| 44 | ␉{ 0x8086, 0x2918, "ICH9" },␊ |
| 45 | ␉{ 0x8086, 0x2919, "ICH9M" },␊ |
| 46 | ␊ |
| 47 | ␉{ 0x8086, 0x3a14, "ICH10DO" },␊ |
| 48 | ␉{ 0x8086, 0x3a16, "ICH10R" },␊ |
| 49 | ␉{ 0x8086, 0x3a18, "ICH10" },␊ |
| 50 | ␉{ 0x8086, 0x3a1a, "ICH10D" },␊ |
| 51 | ␊ |
| 52 | };␊ |
| 53 | ␊ |
| 54 | void force_enable_hpet(pci_dt_t *lpc_dev)␊ |
| 55 | {␊ |
| 56 | ␉int i;␊ |
| 57 | ␉uint32_t␉val, hpet_address = 0xFED00000;␊ |
| 58 | ␉void␉␉*rcba;␊ |
| 59 | ␊ |
| 60 | ␉/* LPC on Intel ICH is always (?) at 00:1f.0 */␊ |
| 61 | ␉for(i = 1; i < sizeof(lpc_controllers) / sizeof(lpc_controllers[0]); i++)␊ |
| 62 | ␉␉if ((lpc_controllers[i].vendor == lpc_dev->vendor_id) ␊ |
| 63 | ␉␉␉&& (lpc_controllers[i].device == lpc_dev->device_id))␊ |
| 64 | ␉␉{␊ |
| 65 | ␉␉␉rcba = (void *)(pci_config_read32(lpc_dev->dev.addr, 0xF0) & 0xFFFFC000);␊ |
| 66 | ␊ |
| 67 | ␉␉␉DBG("Intel(R) %s LPC Interface [%04x:%04x], MMIO @ 0x%lx\n", ␊ |
| 68 | ␉␉␉␉lpc_controllers[i].name, lpc_dev->vendor_id, lpc_dev->device_id, rcba);␊ |
| 69 | ␊ |
| 70 | ␉␉␉if (rcba == 0)␊ |
| 71 | ␉␉␉␉printf(" RCBA disabled; cannot force enable HPET\n");␊ |
| 72 | ␉␉␉else␊ |
| 73 | ␉␉␉{␊ |
| 74 | ␉␉␉␉val = REG32(rcba, 0x3404);␊ |
| 75 | ␉␉␉␉if (val & 0x80)␊ |
| 76 | ␉␉␉␉{␊ |
| 77 | ␉␉␉␉␉// HPET is enabled in HPTC. Just not reported by BIOS␊ |
| 78 | ␉␉␉␉␉DBG(" HPET is enabled in HPTC, just not reported by BIOS\n");␊ |
| 79 | ␉␉␉␉␉hpet_address |= (val & 3) << 12 ;␊ |
| 80 | ␉␉␉␉␉DBG(" HPET MMIO @ 0x%lx\n", hpet_address);␊ |
| 81 | ␉␉␉␉}␊ |
| 82 | ␉␉␉␉else␊ |
| 83 | ␉␉␉␉{␊ |
| 84 | ␉␉␉␉␉// HPET disabled in HPTC. Trying to enable␊ |
| 85 | ␉␉␉␉␉DBG(" HPET is disabled in HPTC, trying to enable\n");␉␉␉␉␉␉␉␉␉␊ |
| 86 | ␉␉␉␉␉REG32(rcba, 0x3404) = val | 0x80;␊ |
| 87 | ␉␉␉␉␉hpet_address |= (val & 3) << 12 ;␊ |
| 88 | ␉␉␉␉␉DBG(" Force enabled HPET, MMIO @ 0x%lx\n", hpet_address);␊ |
| 89 | ␉␉␉␉}␊ |
| 90 | ␊ |
| 91 | ␉␉␉␉// verify if the job is done␊ |
| 92 | ␉␉␉␉val = REG32(rcba, 0x3404);␊ |
| 93 | ␉␉␉␉if (!(val & 0x80))␊ |
| 94 | ␉␉␉␉␉printf(" Failed to force enable HPET\n");␊ |
| 95 | ␉␉␉}␊ |
| 96 | ␉␉␉break;␊ |
| 97 | ␉␉}␊ |
| 98 | ␊ |
| 99 | #if DEBUG_HPET␊ |
| 100 | ␉printf("Press [Enter] to continue...\n");␊ |
| 101 | ␉getc();␊ |
| 102 | #endif␊ |
| 103 | }␊ |
| 104 | |
