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Root/branches/iFabio/Chameleon/i386/libsaio/nvidia.c

Source at commit 298 created 12 years 10 months ago.
By ifabio, Latest trunk. Also add the Azi modules (Nvidia,AMD,ATI,Intel), added strings into localizable.strings. preparing the "make dmg".
1/*␊
2 * NVidia injector␊
3 *␊
4 * Copyright (C) 2009 Jasmin Fazlic, iNDi␊
5 *␊
6 * NVidia injector is free software: you can redistribute it and/or modify␊
7 * it under the terms of the GNU General Public License as published by␊
8 * the Free Software Foundation, either version 3 of the License, or␊
9 * (at your option) any later version.␊
10 *␊
11 * NVidia driver and injector is distributed in the hope that it will be useful,␊
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of␊
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the␊
14 * GNU General Public License for more details.␊
15 *␊
16 * You should have received a copy of the GNU General Public License␊
17 * along with NVidia injector. If not, see <http://www.gnu.org/licenses/>.␊
18 */ ␊
19/*␊
20 * Alternatively you can choose to comply with APSL␊
21 */␊
22␊
23␊
24/*␊
25 * DCB-Table parsing is based on software (nouveau driver) originally distributed under following license:␊
26 *␊
27 *␊
28 * Copyright 2005-2006 Erik Waling␊
29 * Copyright 2006 Stephane Marchesin␊
30 * Copyright 2007-2009 Stuart Bennett␊
31 *␊
32 * Permission is hereby granted, free of charge, to any person obtaining a␊
33 * copy of this software and associated documentation files (the "Software"),␊
34 * to deal in the Software without restriction, including without limitation␊
35 * the rights to use, copy, modify, merge, publish, distribute, sublicense,␊
36 * and/or sell copies of the Software, and to permit persons to whom the␊
37 * Software is furnished to do so, subject to the following conditions:␊
38 *␊
39 * The above copyright notice and this permission notice shall be included in␊
40 * all copies or substantial portions of the Software.␊
41 *␊
42 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR␊
43 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,␊
44 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL␊
45 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,␊
46 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF␊
47 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE␊
48 * SOFTWARE.␊
49 */␊
50␊
51#include "libsaio.h"␊
52#include "boot.h"␊
53#include "bootstruct.h"␊
54#include "pci.h"␊
55#include "platform.h"␊
56#include "device_inject.h"␊
57#include "nvidia.h"␊
58␊
59#ifndef DEBUG_NVIDIA␊
60#define DEBUG_NVIDIA 0␊
61#endif␊
62␊
63#if DEBUG_NVIDIA␊
64#define DBG(x...)␉printf(x)␊
65#else␊
66#define DBG(x...)␊
67#endif␊
68␊
69#define NVIDIA_ROM_SIZE 0x20000␊
70#define PATCH_ROM_SUCCESS 1␊
71#define PATCH_ROM_SUCCESS_HAS_LVDS 2␊
72#define PATCH_ROM_FAILED 0␊
73#define MAX_NUM_DCB_ENTRIES 16␊
74␊
75#define TYPE_GROUPED 0xff␊
76␊
77extern uint32_t devices_number;␊
78␊
79const char *nvidia_compatible_0[]␉=␉{ "@0,compatible",␉"NVDA,NVMac" };␊
80const char *nvidia_compatible_1[]␉=␉{ "@1,compatible",␉"NVDA,NVMac" };␊
81const char *nvidia_device_type_0[]␉=␉{ "@0,device_type",␉"display" };␊
82const char *nvidia_device_type_1[]␉=␉{ "@1,device_type",␉"display" };␊
83const char *nvidia_device_type[]␉=␉{ "device_type",␉"NVDA,Parent" };␊
84const char *nvidia_name_0[]␉␉=␉{ "@0,name",␉␉"NVDA,Display-A" };␊
85const char *nvidia_name_1[]␉␉=␉{ "@1,name",␉␉"NVDA,Display-B" };␊
86const char *nvidia_slot_name[]␉␉=␉{ "AAPL,slot-name",␉"Slot-1" };␊
87␊
88static uint8_t default_dcfg_0[]␉␉=␉{0xff, 0xff, 0xff, 0xff};␊
89static uint8_t default_dcfg_1[]␉␉=␉{0xff, 0xff, 0xff, 0xff};␊
90uint8_t connector_type_1[] ␉␉=␉{0x00, 0x08, 0x00, 0x00};␊
91␊
92static uint8_t default_NVCAP[]␉␉=␉{␊
93␉0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0d, 0x00,␊
94␉0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a,␊
95␉0x00, 0x00, 0x00, 0x00␊
96};␊
97␊
98static uint8_t default_NVPM[]= {␊
99 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,␊
100 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,␊
101 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,␊
102 0x00, 0x00, 0x00, 0x00␊
103};␊
104␊
105#define DCFG0_LEN ( sizeof(default_dcfg_0) / sizeof(uint8_t) )␊
106#define DCFG1_LEN ( sizeof(default_dcfg_1) / sizeof(uint8_t) )␊
107#define NVCAP_LEN ( sizeof(default_NVCAP) / sizeof(uint8_t) )␊
108␊
109static struct nv_chipsets_t NVKnownChipsets[] = {␊
110␉{ 0x00000000, "Unknown" },␊
111␉{ 0x10DE0040, "GeForce 6800 Ultra" },␊
112␉{ 0x10DE0041, "GeForce 6800" },␊
113␉{ 0x10DE0042, "GeForce 6800 LE" },␊
114␉{ 0x10DE0043, "GeForce 6800 XE" },␊
115␉{ 0x10DE0044, "GeForce 6800 XT" },␊
116␉{ 0x10DE0045, "GeForce 6800 GT" },␊
117␉{ 0x10DE0046, "GeForce 6800 GT" },␊
118␉{ 0x10DE0047, "GeForce 6800 GS" },␊
119␉{ 0x10DE0048, "GeForce 6800 XT" },␊
120␉{ 0x10DE004D, "Quadro FX 3400" },␊
121␉{ 0x10DE004E, "Quadro FX 4000" },␊
122␉{ 0x10DE0090, "GeForce 7800 GTX" },␊
123␉{ 0x10DE0091, "GeForce 7800 GTX" },␊
124␉{ 0x10DE0092, "GeForce 7800 GT" },␊
125␉{ 0x10DE0093, "GeForce 7800 GS" },␊
126␉{ 0x10DE0095, "GeForce 7800 SLI" },␊
127␉{ 0x10DE0098, "GeForce Go 7800" },␊
128␉{ 0x10DE0099, "GeForce Go 7800 GTX" },␊
129␉{ 0x10DE009D, "Quadro FX 4500" },␊
130␉{ 0x10DE00C0, "GeForce 6800 GS" },␊
131␉{ 0x10DE00C1, "GeForce 6800" },␊
132␉{ 0x10DE00C2, "GeForce 6800 LE" },␊
133␉{ 0x10DE00C3, "GeForce 6800 XT" },␊
134␉{ 0x10DE00C8, "GeForce Go 6800" },␊
135␉{ 0x10DE00C9, "GeForce Go 6800 Ultra" },␊
136␉{ 0x10DE00CC, "Quadro FX Go1400" },␊
137␉{ 0x10DE00CD, "Quadro FX 3450/4000 SDI" },␊
138␉{ 0x10DE00CE, "Quadro FX 1400" },␊
139␉{ 0x10DE00F1, "GeForce 6600 GT" },␊
140␉{ 0x10DE00F2, "GeForce 6600" },␊
141␉{ 0x10DE00F3, "GeForce 6200" },␊
142␉{ 0x10DE00F4, "GeForce 6600 LE" },␊
143␉{ 0x10DE00F5, "GeForce 7800 GS" },␊
144␉{ 0x10DE00F6, "GeForce 6800 GS/XT" },␊
145␉{ 0x10DE00F8, "Quadro FX 3400/4400" },␊
146␉{ 0x10DE00F9, "GeForce 6800 Series GPU" },␊
147␉{ 0x10DE0140, "GeForce 6600 GT" },␊
148␉{ 0x10DE0141, "GeForce 6600" },␊
149␉{ 0x10DE0142, "GeForce 6600 LE" },␊
150␉{ 0x10DE0143, "GeForce 6600 VE" },␊
151␉{ 0x10DE0144, "GeForce Go 6600" },␊
152␉{ 0x10DE0145, "GeForce 6610 XL" },␊
153␉{ 0x10DE0146, "GeForce Go 6600 TE/6200 TE" },␊
154␉{ 0x10DE0147, "GeForce 6700 XL" },␊
155␉{ 0x10DE0148, "GeForce Go 6600" },␊
156␉{ 0x10DE0149, "GeForce Go 6600 GT" },␊
157␉{ 0x10DE014A, "Quadro NVS 440" },␊
158␉{ 0x10DE014C, "Quadro FX 550" },␊
159␉{ 0x10DE014D, "Quadro FX 550" },␊
160␉{ 0x10DE014E, "Quadro FX 540" },␊
161␉{ 0x10DE014F, "GeForce 6200" },␊
162␉{ 0x10DE0160, "GeForce 6500" },␊
163␉{ 0x10DE0161, "GeForce 6200 TurboCache(TM)" },␊
164␉{ 0x10DE0162, "GeForce 6200SE TurboCache(TM)" },␊
165␉{ 0x10DE0163, "GeForce 6200 LE" },␊
166␉{ 0x10DE0164, "GeForce Go 6200" },␊
167␉{ 0x10DE0165, "Quadro NVS 285" },␊
168␉{ 0x10DE0166, "GeForce Go 6400" },␊
169␉{ 0x10DE0167, "GeForce Go 6200" },␊
170␉{ 0x10DE0168, "GeForce Go 6400" },␊
171␉{ 0x10DE0169, "GeForce 6250" },␊
172␉{ 0x10DE016A, "GeForce 7100 GS" },␊
173␉{ 0x10DE0191, "GeForce 8800 GTX" },␊
174␉{ 0x10DE0193, "GeForce 8800 GTS" },␊
175␉{ 0x10DE0194, "GeForce 8800 Ultra" },␊
176␉{ 0x10DE0197, "Tesla C870" },␊
177␉{ 0x10DE019D, "Quadro FX 5600" },␊
178␉{ 0x10DE019E, "Quadro FX 4600" },␊
179␉{ 0x10DE01D0, "GeForce 7350 LE" },␊
180␉{ 0x10DE01D1, "GeForce 7300 LE" },␊
181␉{ 0x10DE01D2, "GeForce 7550 LE" },␊
182␉{ 0x10DE01D3, "GeForce 7300 SE/7200 GS" },␊
183␉{ 0x10DE01D6, "GeForce Go 7200" },␊
184␉{ 0x10DE01D7, "GeForce Go 7300" },␊
185␉{ 0x10DE01D8, "GeForce Go 7400" },␊
186␉{ 0x10DE01D9, "GeForce Go 7400 GS" },␊
187␉{ 0x10DE01DA, "Quadro NVS 110M" },␊
188␉{ 0x10DE01DB, "Quadro NVS 120M" },␊
189␉{ 0x10DE01DC, "Quadro FX 350M" },␊
190␉{ 0x10DE01DD, "GeForce 7500 LE" },␊
191␉{ 0x10DE01DE, "Quadro FX 350" },␊
192␉{ 0x10DE01DF, "GeForce 7300 GS" },␊
193␉{ 0x10DE0211, "GeForce 6800" },␊
194␉{ 0x10DE0212, "GeForce 6800 LE" },␊
195␉{ 0x10DE0215, "GeForce 6800 GT" },␊
196␉{ 0x10DE0218, "GeForce 6800 XT" },␊
197␉{ 0x10DE0221, "GeForce 6200" },␊
198␉{ 0x10DE0222, "GeForce 6200 A-LE" },␊
199␉{ 0x10DE0240, "GeForce 6150" },␊
200␉{ 0x10DE0241, "GeForce 6150 LE" },␊
201␉{ 0x10DE0242, "GeForce 6100" },␊
202␉{ 0x10DE0244, "GeForce Go 6150" },␊
203␉{ 0x10DE0245, "Quadro NVS 210S / GeForce 6150LE" },␊
204␉{ 0x10DE0247, "GeForce Go 6100" },␊
205␉{ 0x10DE0290, "GeForce 7900 GTX" },␊
206␉{ 0x10DE0291, "GeForce 7900 GT/GTO" },␊
207␉{ 0x10DE0292, "GeForce 7900 GS" },␊
208␉{ 0x10DE0293, "GeForce 7950 GX2" },␊
209␉{ 0x10DE0294, "GeForce 7950 GX2" },␊
210␉{ 0x10DE0295, "GeForce 7950 GT" },␊
211␉{ 0x10DE0298, "GeForce Go 7900 GS" },␊
212␉{ 0x10DE0299, "GeForce Go 7900 GTX" },␊
213␉{ 0x10DE029A, "Quadro FX 2500M" },␊
214␉{ 0x10DE029B, "Quadro FX 1500M" },␊
215␉{ 0x10DE029C, "Quadro FX 5500" },␊
216␉{ 0x10DE029D, "Quadro FX 3500" },␊
217␉{ 0x10DE029E, "Quadro FX 1500" },␊
218␉{ 0x10DE029F, "Quadro FX 4500 X2" },␊
219␉{ 0x10DE02E0, "GeForce 7600 GT" },␊
220␉{ 0x10DE02E1, "GeForce 7600 GS" },␊
221␉{ 0x10DE02E2, "GeForce 7300 GT" },␊
222␉{ 0x10DE02E3, "GeForce 7900 GS" },␊
223␉{ 0x10DE02E4, "GeForce 7950 GT" },␊
224␉{ 0x10DE0301, "GeForce FX 5800 Ultra" },␊
225␉{ 0x10DE0302, "GeForce FX 5800" },␊
226␉{ 0x10DE0308, "Quadro FX 2000" },␊
227␉{ 0x10DE0309, "Quadro FX 1000" },␊
228␉{ 0x10DE0311, "GeForce FX 5600 Ultra" },␊
229␉{ 0x10DE0312, "GeForce FX 5600" },␊
230␉{ 0x10DE0314, "GeForce FX 5600XT" },␊
231␉{ 0x10DE031A, "GeForce FX Go5600" },␊
232␉{ 0x10DE031B, "GeForce FX Go5650" },␊
233␉{ 0x10DE031C, "Quadro FX Go700" },␊
234␉{ 0x10DE0324, "GeForce FX Go5200" },␊
235␉{ 0x10DE0325, "GeForce FX Go5250" },␊
236␉{ 0x10DE0326, "GeForce FX 5500" },␊
237␉{ 0x10DE0328, "GeForce FX Go5200 32M/64M" },␊
238␉{ 0x10DE032A, "Quadro NVS 55/280 PCI" },␊
239␉{ 0x10DE032B, "Quadro FX 500/600 PCI" },␊
240␉{ 0x10DE032C, "GeForce FX Go53xx Series" },␊
241␉{ 0x10DE032D, "GeForce FX Go5100" },␊
242␉{ 0x10DE0330, "GeForce FX 5900 Ultra" },␊
243␉{ 0x10DE0331, "GeForce FX 5900" },␊
244␉{ 0x10DE0332, "GeForce FX 5900XT" },␊
245␉{ 0x10DE0333, "GeForce FX 5950 Ultra" },␊
246␉{ 0x10DE0334, "GeForce FX 5900ZT" },␊
247␉{ 0x10DE0338, "Quadro FX 3000" },␊
248␉{ 0x10DE033F, "Quadro FX 700" },␊
249␉{ 0x10DE0341, "GeForce FX 5700 Ultra" },␊
250␉{ 0x10DE0342, "GeForce FX 5700" },␊
251␉{ 0x10DE0343, "GeForce FX 5700LE" },␊
252␉{ 0x10DE0344, "GeForce FX 5700VE" },␊
253␉{ 0x10DE0347, "GeForce FX Go5700" },␊
254␉{ 0x10DE0348, "GeForce FX Go5700" },␊
255␉{ 0x10DE034C, "Quadro FX Go1000" },␊
256␉{ 0x10DE034E, "Quadro FX 1100" },␊
257␉{ 0x10DE038B, "GeForce 7650 GS" },␊
258␉{ 0x10DE0390, "GeForce 7650 GS" },␊
259␉{ 0x10DE0391, "GeForce 7600 GT" },␊
260␉{ 0x10DE0392, "GeForce 7600 GS" },␊
261␉{ 0x10DE0393, "GeForce 7300 GT" },␊
262␉{ 0x10DE0394, "GeForce 7600 LE" },␊
263␉{ 0x10DE0395, "GeForce 7300 GT" },␊
264␉{ 0x10DE0397, "GeForce Go 7700" },␊
265␉{ 0x10DE0398, "GeForce Go 7600" },␊
266␉{ 0x10DE0399, "GeForce Go 7600 GT"},␊
267␉{ 0x10DE039A, "Quadro NVS 300M" },␊
268␉{ 0x10DE039B, "GeForce Go 7900 SE" },␊
269␉{ 0x10DE039C, "Quadro FX 550M" },␊
270␉{ 0x10DE039E, "Quadro FX 560" },␊
271␉{ 0x10DE03D0, "GeForce 6150SE nForce 430" },␊
272␉{ 0x10DE03D1, "GeForce 6100 nForce 405" },␊
273␉{ 0x10DE03D2, "GeForce 6100 nForce 400" },␊
274␉{ 0x10DE03D5, "GeForce 6100 nForce 420" },␊
275␉{ 0x10DE03D6, "GeForce 7025 / nForce 630a" },␊
276␉{ 0x10DE0400, "GeForce 8600 GTS" },␊
277␉{ 0x10DE0401, "GeForce 8600 GT" },␊
278␉{ 0x10DE0402, "GeForce 8600 GT" },␊
279␉{ 0x10DE0403, "GeForce 8600 GS" },␊
280␉{ 0x10DE0404, "GeForce 8400 GS" },␊
281␉{ 0x10DE0405, "GeForce 9500M GS" },␊
282␉{ 0x10DE0406, "GeForce 8300 GS" },␊
283␉{ 0x10DE0407, "GeForce 8600M GT" },␊
284␉{ 0x10DE0408, "GeForce 9650M GS" },␊
285␉{ 0x10DE0409, "GeForce 8700M GT" },␊
286␉{ 0x10DE040A, "Quadro FX 370" },␊
287␉{ 0x10DE040B, "Quadro NVS 320M" },␊
288␉{ 0x10DE040C, "Quadro FX 570M" },␊
289␉{ 0x10DE040D, "Quadro FX 1600M" },␊
290␉{ 0x10DE040E, "Quadro FX 570" },␊
291␉{ 0x10DE040F, "Quadro FX 1700" },␊
292␉{ 0x10DE0410, "GeForce GT 330" },␊
293␉{ 0x10DE0420, "GeForce 8400 SE" },␊
294␉{ 0x10DE0421, "GeForce 8500 GT" },␊
295␉{ 0x10DE0422, "GeForce 8400 GS" },␊
296␉{ 0x10DE0423, "GeForce 8300 GS" },␊
297␉{ 0x10DE0424, "GeForce 8400 GS" },␊
298␉{ 0x10DE0425, "GeForce 8600M GS" },␊
299␉{ 0x10DE0426, "GeForce 8400M GT" },␊
300␉{ 0x10DE0427, "GeForce 8400M GS" },␊
301␉{ 0x10DE0428, "GeForce 8400M G" },␊
302␉{ 0x10DE0429, "Quadro NVS 140M" },␊
303␉{ 0x10DE042A, "Quadro NVS 130M" },␊
304␉{ 0x10DE042B, "Quadro NVS 135M" },␊
305␉{ 0x10DE042C, "GeForce 9400 GT" },␊
306␉{ 0x10DE042D, "Quadro FX 360M" },␊
307␉{ 0x10DE042E, "GeForce 9300M G" },␊
308␉{ 0x10DE042F, "Quadro NVS 290" },␊
309␉{ 0x10DE053A, "GeForce 7050 PV / nForce 630a" },␊
310␉{ 0x10DE053B, "GeForce 7050 PV / nForce 630a" },␊
311␉{ 0x10DE053E, "GeForce 7025 / nForce 630a" },␊
312␉{ 0x10DE05E0, "GeForce GTX 295" },␊
313␉{ 0x10DE05E1, "GeForce GTX 280" },␊
314␉{ 0x10DE05E2, "GeForce GTX 260" },␊
315␉{ 0x10DE05E3, "GeForce GTX 285" },␊
316␉{ 0x10DE05E6, "GeForce GTX 275" },␊
317␉{ 0x10DE05EA, "GeForce GTX 260" },␊
318␉{ 0x10DE05EB, "GeForce GTX 295" },␊
319␉{ 0x10DE05ED, "Quadroplex 2200 D2" },␊
320␉{ 0x10DE05F8, "Quadroplex 2200 S4" },␊
321␉{ 0x10DE05F9, "Quadro CX" },␊
322␉{ 0x10DE05FD, "Quadro FX 5800" },␊
323␉{ 0x10DE05FE, "Quadro FX 4800" },␊
324␉{ 0x10DE05FF, "Quadro FX 3800" },␊
325␉{ 0x10DE0600, "GeForce 8800 GTS 512" },␊
326␉{ 0x10DE0601, "GeForce 9800 GT" },␊
327␉{ 0x10DE0602, "GeForce 8800 GT" },␊
328␉{ 0x10DE0603, "GeForce GT 230" },␊
329␉{ 0x10DE0604, "GeForce 9800 GX2" },␊
330␉{ 0x10DE0605, "GeForce 9800 GT" },␊
331␉{ 0x10DE0606, "GeForce 8800 GS" },␊
332␉{ 0x10DE0607, "GeForce GTS 240" },␊
333␉{ 0x10DE0608, "GeForce 9800M GTX" },␊
334␉{ 0x10DE0609, "GeForce 8800M GTS" },␊
335␉{ 0x10DE060A, "GeForce GTX 280M" },␊
336␉{ 0x10DE060B, "GeForce 9800M GT" },␊
337␉{ 0x10DE060C, "GeForce 8800M GTX" },␊
338␉{ 0x10DE060D, "GeForce 8800 GS" },␊
339␉{ 0x10DE060F, "GeForce GTX 285M" },␊
340␉{ 0x10DE0610, "GeForce 9600 GSO" },␊
341␉{ 0x10DE0611, "GeForce 8800 GT" },␊
342␉{ 0x10DE0612, "GeForce 9800 GTX" },␊
343␉{ 0x10DE0613, "GeForce 9800 GTX+" },␊
344␉{ 0x10DE0614, "GeForce 9800 GT" },␊
345␉{ 0x10DE0615, "GeForce GTS 250" },␊
346␉{ 0x10DE0617, "GeForce 9800M GTX" },␊
347␉{ 0x10DE0618, "GeForce GTX 260M" },␊
348␉{ 0x10DE0619, "Quadro FX 4700 X2" },␊
349␉{ 0x10DE061A, "Quadro FX 3700" },␊
350␉{ 0x10DE061B, "Quadro VX 200" },␊
351␉{ 0x10DE061C, "Quadro FX 3600M" },␊
352␉{ 0x10DE061D, "Quadro FX 2800M" },␊
353␉{ 0x10DE061F, "Quadro FX 3800M" },␊
354␉{ 0x10DE0622, "GeForce 9600 GT" },␊
355␉{ 0x10DE0623, "GeForce 9600 GS" },␊
356␉{ 0x10DE0625, "GeForce 9600 GSO 512"},␊
357␉{ 0x10DE0626, "GeForce GT 130" },␊
358␉{ 0x10DE0627, "GeForce GT 140" },␊
359␉{ 0x10DE0628, "GeForce 9800M GTS" },␊
360␉{ 0x10DE062A, "GeForce 9700M GTS" },␊
361␉{ 0x10DE062C, "GeForce 9800M GTS" },␊
362␉{ 0x10DE062D, "GeForce 9600 GT" },␊
363␉{ 0x10DE062E, "GeForce 9600 GT" },␊
364␉{ 0x10DE0631, "GeForce GTS 160M" },␊
365␉{ 0x10DE0632, "GeForce GTS 150M" },␊
366␉{ 0x10DE0635, "GeForce 9600 GSO" },␊
367␉{ 0x10DE0637, "GeForce 9600 GT" },␊
368␉{ 0x10DE0638, "Quadro FX 1800" },␊
369␉{ 0x10DE063A, "Quadro FX 2700M" },␊
370␉{ 0x10DE0640, "GeForce 9500 GT" },␊
371␉{ 0x10DE0641, "GeForce 9400 GT" },␊
372␉{ 0x10DE0642, "GeForce 8400 GS" },␊
373␉{ 0x10DE0643, "GeForce 9500 GT" },␊
374␉{ 0x10DE0644, "GeForce 9500 GS" },␊
375␉{ 0x10DE0645, "GeForce 9500 GS" },␊
376␉{ 0x10DE0646, "GeForce GT 120" },␊
377␉{ 0x10DE0647, "GeForce 9600M GT" },␊
378␉{ 0x10DE0648, "GeForce 9600M GS" },␊
379␉{ 0x10DE0649, "GeForce 9600M GT" },␊
380␉{ 0x10DE064A, "GeForce 9700M GT" },␊
381␉{ 0x10DE064B, "GeForce 9500M G" },␊
382␉{ 0x10DE064C, "GeForce 9650M GT" },␊
383␉{ 0x10DE0651, "GeForce G 110M" },␊
384␉{ 0x10DE0652, "GeForce GT 130M" },␊
385␉{ 0x10DE0653, "GeForce GT 120M" },␊
386␉{ 0x10DE0654, "GeForce GT 220M" },␊
387␉{ 0x10DE0656, "GeForce 9650 S" },␊
388␉{ 0x10DE0658, "Quadro FX 380" },␊
389␉{ 0x10DE0659, "Quadro FX 580" },␊
390␉{ 0x10DE065A, "Quadro FX 1700M" },␊
391␉{ 0x10DE065B, "GeForce 9400 GT" },␊
392␉{ 0x10DE065C, "Quadro FX 770M" },␊
393␉{ 0x10DE065F, "GeForce G210" },␊
394␉{ 0x10DE06C0, "GeForce GTX 480" },␊
395␉{ 0x10DE06C3, "GeForce GTX D12U" },␊
396␉{ 0x10DE06C4, "GeForce GTX 465" },␊
397␉{ 0x10DE06CA, "GeForce GTX 480M" },␊
398␉{ 0x10DE06CD, "GeForce GTX 470" },␊
399␉{ 0x10DE06D1, "Tesla C2050" },␊
400␉{ 0x10DE06D1, "Tesla C2070" },␊
401␉{ 0x10DE06D2, "Tesla M2070" },␊
402␉{ 0x10DE06D8, "Quadro 6000" },␊
403␉{ 0x10DE06D9, "Quadro 5000" },␊
404␉{ 0x10DE06DA, "Quadro 5000M" },␊
405␉{ 0x10DE06DC, "Quadro 6000" },␊
406␉{ 0x10DE06DE, "Tesla M2050" },␊
407␉{ 0x10DE06DE, "Tesla M2070" },␊
408␉{ 0x10DE06DD, "Quadro 4000" },␊
409␉{ 0x10DE06DE, "Tesla M2050" },␊
410␉{ 0x10DE06DE, "Tesla M2070" },␊
411␉{ 0x10DE06DF, "Tesla M2070-Q" },␊
412␉{ 0x10DE06E0, "GeForce 9300 GE" },␊
413␉{ 0x10DE06E1, "GeForce 9300 GS" },␊
414␉{ 0x10DE06E2, "GeForce 8400" },␊
415␉{ 0x10DE06E3, "GeForce 8400 SE" },␊
416␉{ 0x10DE06E4, "GeForce 8400 GS" },␊
417␉{ 0x10DE06E5, "GeForce 9300M GS" },␊
418␉{ 0x10DE06E6, "GeForce G100" },␊
419␉{ 0x10DE06E7, "GeForce 9300 SE" },␊
420␉{ 0x10DE06E8, "GeForce 9200M GS" },␊
421␉{ 0x10DE06E9, "GeForce 9300M GS" },␊
422␉{ 0x10DE06EA, "Quadro NVS 150M" },␊
423␉{ 0x10DE06EB, "Quadro NVS 160M" },␊
424␉{ 0x10DE06EC, "GeForce G 105M" },␊
425␉{ 0x10DE06EF, "GeForce G 103M" },␊
426␉{ 0x10DE06F8, "Quadro NVS 420" },␊
427␉{ 0x10DE06F9, "Quadro FX 370 LP" },␊
428␉{ 0x10DE06FA, "Quadro NVS 450" },␊
429␉{ 0x10DE06FB, "Quadro FX 370M" },␊
430␉{ 0x10DE06FD, "Quadro NVS 295" },␊
431␉{ 0x10DE07E0, "GeForce 7150 / nForce 630i" },␊
432␉{ 0x10DE07E1, "GeForce 7100 / nForce 630i" },␊
433␉{ 0x10DE07E2, "GeForce 7050 / nForce 630i" },␊
434␉{ 0x10DE07E3, "GeForce 7050 / nForce 610i" },␊
435␉{ 0x10DE07E5, "GeForce 7050 / nForce 620i" },␊
436␉{ 0x10DE0844, "GeForce 9100M G" },␊
437␉{ 0x10DE0845, "GeForce 8200M G" },␊
438␉{ 0x10DE0846, "GeForce 9200" },␊
439␉{ 0x10DE0847, "GeForce 9100" },␊
440␉{ 0x10DE0848, "GeForce 8300" },␊
441␉{ 0x10DE0849, "GeForce 8200" },␊
442␉{ 0x10DE084A, "nForce 730a" },␊
443␉{ 0x10DE084B, "GeForce 9200" },␊
444␉{ 0x10DE084C, "nForce 980a/780a SLI" },␊
445␉{ 0x10DE084D, "nForce 750a SLI" },␊
446␉{ 0x10DE084F, "GeForce 8100 / nForce 720a" },␊
447␉{ 0x10DE0860, "GeForce 9400" },␊
448␉{ 0x10DE0861, "GeForce 9400" },␊
449␉{ 0x10DE0862, "GeForce 9400M G" },␊
450␉{ 0x10DE0863, "GeForce 9400M" },␊
451␉{ 0x10DE0864, "GeForce 9300" },␊
452␉{ 0x10DE0865, "ION" },␊
453␉{ 0x10DE0866, "GeForce 9400M G" },␊
454␉{ 0x10DE0867, "GeForce 9400" },␊
455␉{ 0x10DE0868, "nForce 760i SLI" },␊
456␉{ 0x10DE086A, "GeForce 9400" },␊
457␉{ 0x10DE086C, "GeForce 9300 / nForce 730i" },␊
458␉{ 0x10DE086D, "GeForce 9200" },␊
459␉{ 0x10DE086E, "GeForce 9100M G" },␊
460␉{ 0x10DE086F, "GeForce 8200M G" },␊
461␉{ 0x10DE0870, "GeForce 9400M" },␊
462␉{ 0x10DE0871, "GeForce 9200" },␊
463␉{ 0x10DE0872, "GeForce G102M" },␊
464␉{ 0x10DE0873, "GeForce G102M" },␊
465␉{ 0x10DE0874, "ION 9300M" },␊
466␉{ 0x10DE0876, "ION" },␊
467␉{ 0x10DE087A, "GeForce 9400" },␊
468␉{ 0x10DE087D, "ION 9400M" },␊
469␉{ 0x10DE087E, "ION LE" },␊
470␉{ 0x10DE087F, "ION LE" },␊
471␉{ 0x10DE0A20, "GeForce GT220" },␊
472␉{ 0x10DE0A22, "GeForce 315" },␊
473␉{ 0x10DE0A23, "GeForce 210" },␊
474␉{ 0x10DE0A28, "GeForce GT 230M" },␊
475␉{ 0x10DE0A29, "GeForce GT 330M" },␊
476␉{ 0x10DE0A2A, "GeForce GT 230M" },␊
477␉{ 0x10DE0A2B, "GeForce GT 330M" },␊
478␉{ 0x10DE0A2C, "NVS 5100M" },␊
479␉{ 0x10DE0A2D, "GeForce GT 320M" },␊
480␉{ 0x10DE0A34, "GeForce GT 240M" },␊
481␉{ 0x10DE0A35, "GeForce GT 325M" },␊
482␉{ 0x10DE0A3C, "Quadro FX 880M" },␊
483␉{ 0x10DE0A60, "GeForce G210" },␊
484␉{ 0x10DE0A62, "GeForce 205" },␊
485␉{ 0x10DE0A63, "GeForce 310" },␊
486␉{ 0x10DE0A64, "ION" },␊
487␉{ 0x10DE0A65, "GeForce 210" },␊
488␉{ 0x10DE0A66, "GeForce 310" },␊
489␉{ 0x10DE0A67, "GeForce 315" },␊
490␉{ 0x10DE0A68, "GeForce G105M" },␊
491␉{ 0x10DE0A69, "GeForce G105M" },␊
492␉{ 0x10DE0A6A, "NVS 2100M" },␊
493␉{ 0x10DE0A6C, "NVS 3100M" },␊
494␉{ 0x10DE0A6E, "GeForce 305M" },␊
495␉{ 0x10DE0A6F, "ION" },␊
496␉{ 0x10DE0A70, "GeForce 310M" },␊
497␉{ 0x10DE0A71, "GeForce 305M" },␊
498␉{ 0x10DE0A72, "GeForce 310M" },␊
499␉{ 0x10DE0A73, "GeForce 305M" },␊
500␉{ 0x10DE0A74, "GeForce G210M" },␊
501␉{ 0x10DE0A75, "GeForce G310M" },␊
502␉{ 0x10DE0A78, "Quadro FX 380 LP" },␊
503␉{ 0x10DE0A7C, "Quadro FX 380M" },␊
504␉{ 0x10DE0CA0, "GeForce GT 330 " },␊
505␉{ 0x10DE0CA2, "GeForce GT 320" },␊
506␉{ 0x10DE0CA3, "GeForce GT 240" },␊
507␉{ 0x10DE0CA4, "GeForce GT 340" },␊
508␉{ 0x10DE0CA7, "GeForce GT 330" },␊
509␉{ 0x10DE0CA8, "GeForce GTS 260M" },␊
510␉{ 0x10DE0CA9, "GeForce GTS 250M" },␊
511␉{ 0x10DE0CAC, "GeForce 315" },␊
512␉{ 0x10DE0CAF, "GeForce GT 335M" },␊
513␉{ 0x10DE0CB0, "GeForce GTS 350M" },␊
514␉{ 0x10DE0CB1, "GeForce GTS 360M" },␊
515␉{ 0x10DE0CBC, "Quadro FX 1800M" },␊
516␉{ 0x10DE0DC0, "GeForce GT 440" },␊
517␉{ 0x10DE0DC1, "D12-P1-35" },␊
518␉{ 0x10DE0DC2, "D12-P1-35" },␊
519␉{ 0x10DE0DC4, "GeForce GTS 450" },␊
520␉{ 0x10DE0DC5, "GeForce GTS 450" },␊
521␉{ 0x10DE0DC6, "GeForce GTS 450" },␊
522␉{ 0x10DE0DCA, "GF10x" },␊
523␉{ 0x10DE0DCD, "GeForce GT 555M" },␊
524␉{ 0x10DE0DCE, "GeForce GT 555M" },␊
525␉{ 0x10DE0DD1, "GeForce GTX 460M" },␊
526␉{ 0x10DE0DD2, "GeForce GT 445M" },␊
527␉{ 0x10DE0DD3, "GeForce GT 435M" },␊
528␉{ 0x10DE0DD6, "GeForce GT 550M" },␊
529␉{ 0x10DE0DD8, "Quadro 2000" },␊
530␉{ 0x10DE0DDA, "Quadro 2000M" },␊
531␉{ 0x10DE0DDE, "GF106-ES" },␊
532␉{ 0x10DE0DDF, "GF106-INT" },␊
533␉{ 0x10DE0DE0, "GeForce GT 440" },␊
534␉{ 0x10DE0DE1, "GeForce GT 430" },␊
535␉{ 0x10DE0DE2, "GeForce GT 420" },␊
536␉{ 0x10DE0DE5, "GeForce GT 530" },␊
537␉{ 0x10DE0DEB, "GeForce GT 555M" },␊
538␉{ 0x10DE0DEC, "GeForce GT 525M" },␊
539␉{ 0x10DE0DED, "GeForce GT 520M" },␊
540␉{ 0x10DE0DEE, "GeForce GT 415M" },␊
541␉{ 0x10DE0DF0, "GeForce GT 425M" },␊
542␉{ 0x10DE0DF1, "GeForce GT 420M" },␊
543␉{ 0x10DE0DF2, "GeForce GT 435M" },␊
544␉{ 0x10DE0DF3, "GeForce GT 420M" },␊
545␉{ 0x10DE0DF4, "GeForce GT 540M" },␊
546␉{ 0x10DE0DF5, "GeForce GT 525M" },␊
547␉{ 0x10DE0DF6, "GeForce GT 550M" },␊
548␉{ 0x10DE0DF7, "GeForce GT 520M" },␊
549␉{ 0x10DE0DF8, "Quadro 600" },␊
550␉{ 0x10DE0DFA, "Quadro 1000M" },␊
551␉{ 0x10DE0DFE, "GF108 ES" },␊
552␉{ 0x10DE0DFF, "GF108 INT" },␊
553␉{ 0x10DE0E21, "D12U-25" },␊
554␉{ 0x10DE0E22, "GeForce GTX 460" },␊
555␉{ 0x10DE0E23, "GeForce GTX 460 SE" },␊
556␉{ 0x10DE0E24, "GeForce GTX 460" },␊
557␉{ 0x10DE0E25, "D12U-50" },␊
558␉{ 0x10DE0E30, "GeForce GTX 470M" },␊
559␉{ 0x10DE0E31, "GeForce GTX 485M" },␊
560␉{ 0x10DE0E38, "GF104GL" },␊
561␉{ 0x10DE0E3A, "Quadro 3000M" },␊
562␉{ 0x10DE0E3B, "Quadro 4000M" },␊
563␉{ 0x10DE0E3E, "GF104-ES" },␊
564␉{ 0x10DE0E3F, "GF104-INT" },␊
565␉{ 0x10DE1050, "GeForce GT 520M" },␊
566␉{ 0x10DE1054, "GeForce GT 410M" },␊
567␉{ 0x10DE1056, "NVS 4200M" },␊
568␉{ 0x10DE1057, "NVS 4200M" },␊
569␉{ 0x10DE107F, "NVIDIA GF119-ES" },␊
570␉{ 0x10DE1080, "GeForce GTX 580" },␊
571␉{ 0x10DE1081, "GeForce GTX 570" },␊
572␉{ 0x10DE1082, "D13U" },␊
573␉{ 0x10DE1083, "D13U" },␊
574␉{ 0x10DE1086, "GeForce GTX 570" },␊
575␉{ 0x10DE1088, "GeForce GTX 590" },␊
576␉{ 0x10DE1098, "D13U" },␊
577␉{ 0x10DE109A, "Quadro 5010M / N12E-Q5" },␊
578␉{ 0x10DE1200, "GeForce GTX 560 Ti" },␊
579␉{ 0x10DE1244, "GeForce GTX 550 Ti" },␊
580␉{ 0x10DE1245, "GeForce GTS 450" },␊
581␉{ 0x10DE1251, "N12E-GS-A1" },␊
582␉{ 0x10DE10C3, "GeForce 8400 GS" }␊
583};␊
584␊
585static uint16_t swap16(uint16_t x)␊
586{␊
587␉return (((x & 0x00FF) << 8) | ((x & 0xFF00) >> 8));␊
588}␊
589␊
590static uint16_t read16(uint8_t *ptr, uint16_t offset)␊
591{␊
592␉uint8_t ret[2];␊
593␉ret[0] = ptr[offset+1];␊
594␉ret[1] = ptr[offset];␊
595␉return *((uint16_t*)&ret);␊
596}␊
597␊
598#if 0␊
599static uint32_t swap32(uint32_t x)␊
600{␊
601␉return ((x & 0x000000FF) << 24) | ((x & 0x0000FF00) << 8 ) | ((x & 0x00FF0000) >> 8 ) | ((x & 0xFF000000) >> 24);␊
602}␊
603␊
604static uint8_t read8(uint8_t *ptr, uint16_t offset)␊
605{ ␊
606␉return ptr[offset];␊
607}␊
608␊
609static uint32_t read32(uint8_t *ptr, uint16_t offset)␊
610{␊
611␉uint8_t ret[4];␊
612␉ret[0] = ptr[offset+3];␊
613␉ret[1] = ptr[offset+2];␊
614␉ret[2] = ptr[offset+1];␊
615␉ret[3] = ptr[offset];␊
616␉return *((uint32_t*)&ret);␊
617}␊
618#endif␊
619␊
620static int patch_nvidia_rom(uint8_t *rom)␊
621{␊
622␉if (!rom || (rom[0] != 0x55 && rom[1] != 0xaa)) {␊
623␉␉printf("False ROM signature: 0x%02x%02x\n", rom[0], rom[1]);␊
624␉␉return PATCH_ROM_FAILED;␊
625␉}␊
626␉␊
627␉uint16_t dcbptr = swap16(read16(rom, 0x36));␊
628␉if(!dcbptr) {␊
629␉␉printf("no dcb table found\n");␊
630␉␉return PATCH_ROM_FAILED;␊
631␉}/* else␊
632␉ printf("dcb table at offset 0x%04x\n", dcbptr);␊
633␉ */␊
634␉uint8_t *dcbtable = &rom[dcbptr];␊
635␉uint8_t dcbtable_version = dcbtable[0];␊
636␉uint8_t headerlength = 0;␊
637␉uint8_t recordlength = 0;␊
638␉uint8_t numentries = 0;␊
639␉␊
640␉if(dcbtable_version >= 0x20) {␊
641␉␉uint32_t sig;␊
642␉␉␊
643␉␉if(dcbtable_version >= 0x30) {␊
644␉␉␉headerlength = dcbtable[1];␊
645␉␉␉numentries = dcbtable[2];␊
646␉␉␉recordlength = dcbtable[3];␊
647␉␉␉sig = *(uint32_t *)&dcbtable[6];␊
648␉␉} else {␊
649␉␉␉sig = *(uint32_t *)&dcbtable[4];␊
650␉␉␉headerlength = 8;␊
651␉␉}␊
652␉␉if (sig != 0x4edcbdcb) {␊
653␉␉␉printf("bad display config block signature (0x%8x)\n", sig);␊
654␉␉␉return PATCH_ROM_FAILED;␊
655␉␉}␊
656␉} else if (dcbtable_version >= 0x14) { /* some NV15/16, and NV11+ */␊
657␉␉char sig[8] = { 0 };␊
658␉␉␊
659␉␉strncpy(sig, (char *)&dcbtable[-7], 7);␊
660␉␉recordlength = 10;␊
661␉␉if (strcmp(sig, "DEV_REC")) {␊
662␉␉␉printf("Bad Display Configuration Block signature (%s)\n", sig);␊
663␉␉␉return PATCH_ROM_FAILED;␊
664␉␉}␊
665␉} else {␊
666␉␉printf("ERROR: dcbtable_version is 0x%X\n", dcbtable_version);␊
667␉␉return PATCH_ROM_FAILED;␊
668␉}␊
669␉␊
670␉if(numentries >= MAX_NUM_DCB_ENTRIES)␊
671␉␉numentries = MAX_NUM_DCB_ENTRIES;␊
672␉␊
673␉uint8_t num_outputs = 0, i=0;␊
674␉struct dcbentry {␊
675␉␉uint8_t type;␊
676␉␉uint8_t index;␊
677␉␉uint8_t *heads;␊
678␉} entries[numentries];␊
679␉␊
680␉for (i = 0; i < numentries; i++) {␊
681␉␉uint32_t connection;␊
682␉␉connection = *(uint32_t *)&dcbtable[headerlength + recordlength * i];␊
683␉␉/* Should we allow discontinuous DCBs? Certainly DCB I2C tables can be discontinuous */␊
684␉␉if ((connection & 0x0000000f) == 0x0000000f) /* end of records */ ␊
685␉␉␉continue;␊
686␉␉if (connection == 0x00000000) /* seen on an NV11 with DCB v1.5 */ ␊
687␉␉␉continue;␊
688␉␉if ((connection & 0xf) == 0x6) /* we skip type 6 as it doesnt appear on macbook nvcaps */␊
689␉␉␉continue;␊
690␉␉␊
691␉␉entries[num_outputs].type = connection & 0xf;␊
692␉␉entries[num_outputs].index = num_outputs;␊
693␉␉entries[num_outputs++].heads = (uint8_t*)&(dcbtable[(headerlength + recordlength * i) + 1]);␊
694␊
695␉}␊
696␉␊
697␉int has_lvds = false;␊
698␉uint8_t channel1 = 0, channel2 = 0;␊
699␉␊
700␉for(i=0; i<num_outputs; i++) {␊
701␉␉if(entries[i].type == 3) {␊
702␉␉␉has_lvds = true;␊
703␉␉␉//printf("found LVDS\n");␊
704␉␉␉channel1 |= ( 0x1 << entries[i].index);␊
705␉␉␉entries[i].type = TYPE_GROUPED;␊
706␉␉}␊
707␉}␊
708␉// if we have a LVDS output, we group the rest to the second channel␊
709␉if(has_lvds) {␊
710␉␉for(i=0; i<num_outputs; i++) {␊
711␉␉␉if(entries[i].type == TYPE_GROUPED)␊
712␉␉␉␉continue;␊
713␉␉␉channel2 |= ( 0x1 << entries[i].index);␊
714␉␉␉entries[i].type = TYPE_GROUPED;␊
715␉␉}␊
716␉} else {␊
717␉␉//␊
718␉␉int x;␊
719␉␉// we loop twice as we need to generate two channels␊
720␉␉for(x=0; x<=1; x++) {␊
721␉␉␉for(i=0; i<num_outputs; i++) {␊
722␉␉␉␉if(entries[i].type == TYPE_GROUPED)␊
723␉␉␉␉␉continue;␊
724␉␉␉␉// if type is TMDS, the prior output is ANALOG␊
725␉␉␉␉// we always group ANALOG and TMDS␊
726␉␉␉␉// if there is a TV output after TMDS, we group it to that channel as well␊
727␉␉␉␉if(i && entries[i].type == 0x2) {␊
728␉␉␉␉␉switch (x) {␊
729␉␉␉␉␉␉case 0:␊
730␉␉␉␉␉␉␉//printf("group channel 1\n");␊
731␉␉␉␉␉␉␉channel1 |= ( 0x1 << entries[i].index);␊
732␉␉␉␉␉␉␉entries[i].type = TYPE_GROUPED;␊
733␉␉␉␉␉␉␉if((entries[i-1].type == 0x0)) {␊
734␉␉␉␉␉␉␉␉channel1 |= ( 0x1 << entries[i-1].index);␊
735␉␉␉␉␉␉␉␉entries[i-1].type = TYPE_GROUPED;␊
736␉␉␉␉␉␉␉}␊
737␉␉␉␉␉␉␉// group TV as well if there is one␊
738␉␉␉␉␉␉␉if( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) ) {␊
739␉␉␉␉␉␉␉␉//␉printf("group tv1\n");␊
740␉␉␉␉␉␉␉␉channel1 |= ( 0x1 << entries[i+1].index);␊
741␉␉␉␉␉␉␉␉entries[i+1].type = TYPE_GROUPED;␊
742␉␉␉␉␉␉␉}␊
743␉␉␉␉␉␉␉break;␊
744␉␉␉␉␉␉case 1:␊
745␉␉␉␉␉␉␉//printf("group channel 2 : %d\n", i);␊
746␉␉␉␉␉␉␉channel2 |= ( 0x1 << entries[i].index);␊
747␉␉␉␉␉␉␉entries[i].type = TYPE_GROUPED;␊
748␉␉␉␉␉␉␉if((entries[i-1].type == 0x0)) {␊
749␉␉␉␉␉␉␉␉channel2 |= ( 0x1 << entries[i-1].index);␊
750␉␉␉␉␉␉␉␉entries[i-1].type = TYPE_GROUPED;␊
751␉␉␉␉␉␉␉}␊
752␉␉␉␉␉␉␉// group TV as well if there is one␊
753␉␉␉␉␉␉␉if( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) ) {␊
754␉␉␉␉␉␉␉␉//␉printf("group tv2\n");␊
755␉␉␉␉␉␉␉␉channel2 |= ( 0x1 << entries[i+1].index);␊
756␉␉␉␉␉␉␉␉entries[i+1].type = TYPE_GROUPED;␊
757␉␉␉␉␉␉␉}␊
758␉␉␉␉␉␉␉break;␊
759␉␉␉␉␉␉␉␊
760␉␉␉␉␉}␊
761␉␉␉␉␉break;␊
762␉␉␉␉}␊
763␉␉␉}␊
764␉␉}␊
765␉}␊
766␉␊
767␉// if we have left ungrouped outputs merge them to the empty channel␊
768␉uint8_t *togroup;// = (channel1 ? (channel2 ? NULL : &channel2) : &channel1);␊
769␉togroup = &channel2;␊
770␉for(i=0; i<num_outputs;i++)␊
771␉␉if(entries[i].type != TYPE_GROUPED) {␊
772␉␉␉//printf("%d not grouped\n", i);␊
773␉␉␉if(togroup)␊
774␉␉␉␉*togroup |= ( 0x1 << entries[i].index);␊
775␉␉␉entries[i].type = TYPE_GROUPED;␊
776␉␉}␊
777␉␊
778␉if(channel1 > channel2) {␊
779␉␉uint8_t buff = channel1;␊
780␉␉channel1 = channel2;␊
781␉␉channel2 = buff;␊
782␉}␊
783␉␊
784␉default_NVCAP[6] = channel1;␊
785␉default_NVCAP[8] = channel2;␊
786␉␊
787␉// patching HEADS␊
788␉for(i=0; i<num_outputs;i++) {␊
789␉␉if(channel1 & (1 << i))␊
790␉␉␉*entries[i].heads = 1;␊
791␉␉else if(channel2 & (1 << i))␊
792␉␉␉*entries[i].heads = 2;␊
793␉}␊
794␉␊
795␉return (has_lvds ? PATCH_ROM_SUCCESS_HAS_LVDS : PATCH_ROM_SUCCESS);␊
796}␊
797␊
798static char *get_nvidia_model(uint32_t id) {␊
799␉int␉i;␊
800␊
801␉for (i=1; i< (sizeof(NVKnownChipsets) / sizeof(NVKnownChipsets[0])); i++) {␊
802␉␉if (NVKnownChipsets[i].device == id) {␊
803␉␉␉return NVKnownChipsets[i].name;␊
804␉␉}␊
805␉}␊
806␉return NVKnownChipsets[0].name;␊
807}␊
808␊
809static uint32_t load_nvidia_bios_file(const char *filename, uint8_t *buf, int bufsize)␊
810{␊
811␉int␉fd;␊
812␉int␉size;␊
813␊
814␉if ((fd = open_bvdev("bt(0,0)", filename, 0)) < 0) {␊
815␉␉return 0;␊
816␉}␊
817␉size = file_size(fd);␊
818␉if (size > bufsize) {␊
819␉␉printf("Filesize of %s is bigger than expected! Truncating to 0x%x Bytes!\n", filename, bufsize);␊
820␉␉size = bufsize;␊
821␉}␊
822␉size = read(fd, (char *)buf, size);␊
823␉close(fd);␊
824␉return size > 0 ? size : 0;␊
825}␊
826␊
827static int devprop_add_nvidia_template(struct DevPropDevice *device)␊
828{␊
829␉char␉tmp[16]; ␊
830␊
831␉if(!device)␊
832␉␉return 0;␊
833␊
834␉if(!DP_ADD_TEMP_VAL(device, nvidia_compatible_0))␊
835␉␉return 0;␊
836␉if(!DP_ADD_TEMP_VAL(device, nvidia_device_type_0))␊
837␉␉return 0;␊
838␉if(!DP_ADD_TEMP_VAL(device, nvidia_name_0))␊
839␉␉return 0;␊
840␉if(!DP_ADD_TEMP_VAL(device, nvidia_compatible_1))␊
841␉␉return 0;␊
842␉if(!DP_ADD_TEMP_VAL(device, nvidia_device_type_1))␊
843␉␉return 0;␊
844␉if(!DP_ADD_TEMP_VAL(device, nvidia_name_1))␊
845␉␉return 0;␊
846␉if(!DP_ADD_TEMP_VAL(device, nvidia_device_type))␊
847␉␉return 0;␊
848␉// Rek : Dont use sprintf return, it does not WORK !! our custom sprintf() always return 0!␊
849␉// len = sprintf(tmp, "Slot-%x", devices_number);␊
850␉sprintf(tmp, "Slot-%x",devices_number);␊
851␉devprop_add_value(device, "AAPL,slot-name", (uint8_t *) tmp, strlen(tmp));␊
852␉devices_number++;␊
853␊
854␉return 1;␊
855}␊
856␊
857int hex2bin(const char *hex, uint8_t *bin, int len)␊
858{␊
859␉char␉*p;␊
860␉int␉i;␊
861␉char␉buf[3];␊
862␊
863␉if (hex == NULL || bin == NULL || len <= 0 || strlen(hex) != len * 2) {␊
864␉␉printf("[ERROR] bin2hex input error\n");␊
865␉␉return -1;␊
866␉}␊
867␊
868␉buf[2] = '\0';␊
869␉p = (char *) hex;␊
870␉for (i=0; i<len; i++) {␊
871␉␉if (p[0] == '\0' || p[1] == '\0' || !isxdigit(p[0]) || !isxdigit(p[1])) {␊
872␉␉␉printf("[ERROR] bin2hex '%s' syntax error\n", hex);␊
873␉␉␉return -2;␊
874␉␉}␊
875␉␉buf[0] = *p++;␊
876␉␉buf[1] = *p++;␊
877␉␉bin[i] = (unsigned char) strtoul(buf, NULL, 16);␊
878␉}␊
879␉return 0;␊
880}␊
881␊
882unsigned long long mem_detect(volatile uint8_t *regs, uint8_t nvCardType, pci_dt_t *nvda_dev)␊
883{␊
884␉unsigned long long vram_size = 0;␊
885␊
886␉if (nvCardType < NV_ARCH_50) {␊
887␉␉vram_size = REG32(NV04_PFB_FIFO_DATA);␊
888␉␉vram_size &= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK;␊
889␉}␊
890␉else if (nvCardType < NV_ARCH_C0) {␊
891␉␉vram_size = REG32(NV04_PFB_FIFO_DATA);␊
892␉␉vram_size |= (vram_size & 0xff) << 32;␊
893␉␉vram_size &= 0xffffffff00ll;␊
894␉}␊
895␉else { // >= NV_ARCH_C0␊
896␉␉vram_size = REG32(NVC0_MEM_CTRLR_RAM_AMOUNT) << 20;␊
897␉␉vram_size *= REG32(NVC0_MEM_CTRLR_COUNT);␊
898␉}␊
899␊
900␉return vram_size;␊
901}␊
902␊
903bool setup_nvidia_devprop(pci_dt_t *nvda_dev)␊
904{␊
905␉struct DevPropDevice␉␉*device;␊
906␉char␉␉␉␉␉␉*devicepath;␊
907␉option_rom_pci_header_t␉␉*rom_pci_header;␉␊
908␉volatile uint8_t␉*regs;␊
909␉uint8_t␉␉␉␉*rom;␊
910␉uint8_t␉␉␉␉*nvRom;␊
911␉uint8_t␉␉␉␉nvCardType;␊
912␉unsigned long long␉videoRam;␊
913␉uint32_t␉␉␉nvBiosOveride;␊
914␉uint32_t␉␉␉bar[7];␊
915␉uint32_t␉␉␉boot_display;␊
916␉int␉␉␉␉␉nvPatch;␊
917␉int␉␉␉␉␉len;␊
918␉char␉␉␉␉biosVersion[32];␊
919␉char␉␉␉␉nvFilename[32];␊
920␉char␉␉␉␉kNVCAP[12];␊
921␉char␉␉␉␉*model;␊
922␉const char␉␉␉*value;␊
923␉bool␉␉␉␉doit;␊
924␊
925␉devicepath = get_pci_dev_path(nvda_dev);␊
926␉bar[0] = pci_config_read32(nvda_dev->dev.addr, 0x10 );␊
927␉regs = (uint8_t *) (bar[0] & ~0x0f);␊
928␊
929␉// get card type␊
930␉nvCardType = (REG32(0) >> 20) & 0x1ff;␊
931␊
932␉// Amount of VRAM in kilobytes␊
933␉videoRam = mem_detect(regs, nvCardType, nvda_dev);␊
934␉model = get_nvidia_model((nvda_dev->vendor_id << 16) | nvda_dev->device_id);␊
935␉␊
936␉verbose("nVidia %s %dMB NV%02x [%04x:%04x] :: %s\n", ␊
937␉␉␉model, (uint32_t)(videoRam / 1024 / 1024),␊
938␉␉␉(REG32(0) >> 20) & 0x1ff, nvda_dev->vendor_id, nvda_dev->device_id,␊
939␉␉␉devicepath);␊
940␊
941␉rom = malloc(NVIDIA_ROM_SIZE);␊
942␉sprintf(nvFilename, "/Extra/%04x_%04x.rom", (uint16_t)nvda_dev->vendor_id, (uint16_t)nvda_dev->device_id);␊
943␉if (getBoolForKey(kUseNvidiaROM, &doit, &bootInfo->bootConfig) && doit) {␊
944␉␉verbose("Looking for nvidia video bios file %s\n", nvFilename);␊
945␉␉nvBiosOveride = load_nvidia_bios_file(nvFilename, rom, NVIDIA_ROM_SIZE);␊
946␉␉if (nvBiosOveride > 0) {␊
947␉␉␉verbose("Using nVidia Video BIOS File %s (%d Bytes)\n", nvFilename, nvBiosOveride);␊
948␉␉␉DBG("%s Signature 0x%02x%02x %d bytes\n", nvFilename, rom[0], rom[1], nvBiosOveride);␊
949␉␉} else {␊
950␉␉␉printf("ERROR: unable to open nVidia Video BIOS File %s\n", nvFilename);␊
951␉␉␉return false;␊
952␉␉}␊
953␉} else {␊
954␉␉// Otherwise read bios from card␊
955␉␉nvBiosOveride = 0;␊
956␊
957␉␉// TODO: we should really check for the signature before copying the rom, i think.␊
958␊
959␉␉// PRAMIN first␊
960␉␉nvRom = (uint8_t*)&regs[NV_PRAMIN_OFFSET];␊
961␉␉bcopy((uint32_t *)nvRom, rom, NVIDIA_ROM_SIZE);␊
962␉␉␊
963␉␉// Valid Signature ?␊
964␉␉if (rom[0] != 0x55 && rom[1] != 0xaa) {␊
965␉␉␉// PROM next␊
966␉␉␉// Enable PROM access␊
967␉␉␉(REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED;␊
968␊
969␉␉␉nvRom = (uint8_t*)&regs[NV_PROM_OFFSET];␊
970␉␉␉bcopy((uint8_t *)nvRom, rom, NVIDIA_ROM_SIZE);␊
971␉␉␉␊
972␉␉␉// disable PROM access␊
973␉␉␉(REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED;␉␊
974␊
975␉␉␉// Valid Signature ?␊
976␉␉␉if (rom[0] != 0x55 && rom[1] != 0xaa) {␊
977␉␉␉␉// 0xC0000 last␊
978␉␉␉␉bcopy((char *)0xc0000, rom, NVIDIA_ROM_SIZE);␊
979␉␉␉␉␊
980␉␉␉␉// Valid Signature ?␊
981␉␉␉␉if (rom[0] != 0x55 && rom[1] != 0xaa) {␊
982␉␉␉␉␉printf("ERROR: Unable to locate nVidia Video BIOS\n");␊
983␉␉␉␉␉return false;␊
984␉␉␉␉} else {␊
985␉␉␉␉␉DBG("ROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);␊
986␉␉␉␉}␊
987␉␉␉} else {␊
988␉␉␉␉DBG("PROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);␊
989␉␉␉}␊
990␉␉} else {␊
991␉␉␉DBG("PRAM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);␊
992␉␉}␊
993␉}␊
994␊
995␉if ((nvPatch = patch_nvidia_rom(rom)) == PATCH_ROM_FAILED) {␊
996␉␉printf("ERROR: nVidia ROM Patching Failed!\n");␊
997␉␉//return false;␊
998␉}␊
999␊
1000␉rom_pci_header = (option_rom_pci_header_t*)(rom + *(uint16_t *)&rom[24]);␊
1001␊
1002␉// check for 'PCIR' sig␊
1003␉if (rom_pci_header->signature == 0x50434952) {␊
1004␉␉if (rom_pci_header->device_id != nvda_dev->device_id) {␊
1005␉␉␉// Get Model from the OpROM␊
1006␉␉␉model = get_nvidia_model((rom_pci_header->vendor_id << 16) | rom_pci_header->device_id);␊
1007␉␉} else {␊
1008␉␉␉printf("nVidia incorrect PCI ROM signature: 0x%x\n", rom_pci_header->signature);␊
1009␉␉}␊
1010␉}␊
1011␊
1012␉if (!string) {␊
1013␉␉string = devprop_create_string();␊
1014␉}␊
1015␉device = devprop_add_device(string, devicepath);␊
1016␊
1017␉/* FIXME: for primary graphics card only */␊
1018␉boot_display = 1;␊
1019␉devprop_add_value(device, "@0,AAPL,boot-display", (uint8_t*)&boot_display, 4);␊
1020␊
1021␉if(nvPatch == PATCH_ROM_SUCCESS_HAS_LVDS) {␊
1022␉␉uint8_t built_in = 0x01;␊
1023␉␉devprop_add_value(device, "@0,built-in", &built_in, 1);␊
1024␉}␊
1025␉␊
1026␉// get bios version␊
1027␉const int MAX_BIOS_VERSION_LENGTH = 32;␊
1028␉char* version_str = (char*)malloc(MAX_BIOS_VERSION_LENGTH);␊
1029␉memset(version_str, 0, MAX_BIOS_VERSION_LENGTH);␊
1030␉int i, version_start;␊
1031␉int crlf_count = 0;␊
1032␉// only search the first 384 bytes␊
1033␉for(i = 0; i < 0x180; i++) {␊
1034␉␉if(rom[i] == 0x0D && rom[i+1] == 0x0A) {␊
1035␉␉␉crlf_count++;␊
1036␉␉␉// second 0x0D0A was found, extract bios version␊
1037␉␉␉if(crlf_count == 2) {␊
1038␉␉␉␉if(rom[i-1] == 0x20) i--; // strip last " "␊
1039␉␉␉␉for(version_start = i; version_start > (i-MAX_BIOS_VERSION_LENGTH); version_start--) {␊
1040␉␉␉␉␉// find start␊
1041␉␉␉␉␉if(rom[version_start] == 0x00) {␊
1042␉␉␉␉␉␉version_start++;␊
1043␉␉␉␉␉␉␊
1044␉␉␉␉␉␉// strip "Version "␊
1045␉␉␉␉␉␉if(strncmp((const char*)rom+version_start, "Version ", 8) == 0) {␊
1046␉␉␉␉␉␉␉version_start += 8;␊
1047␉␉␉␉␉␉}␊
1048␉␉␉␉␉␉␊
1049␉␉␉␉␉␉strncpy(version_str, (const char*)rom+version_start, i-version_start);␊
1050␉␉␉␉␉␉break;␊
1051␉␉␉␉␉}␊
1052␉␉␉␉}␊
1053␉␉␉␉break;␊
1054␉␉␉}␊
1055␉␉}␊
1056␉}␊
1057␉␊
1058␉sprintf(biosVersion, "%s", (nvBiosOveride > 0) ? nvFilename : version_str);␊
1059␊
1060␉sprintf(kNVCAP, "NVCAP_%04x", nvda_dev->device_id);␊
1061␉if (getValueForKey(kNVCAP, &value, &len, &bootInfo->bootConfig) && len == NVCAP_LEN * 2) {␊
1062␉␉uint8_t␉new_NVCAP[NVCAP_LEN];␊
1063␊
1064␉␉if (hex2bin(value, new_NVCAP, NVCAP_LEN) == 0) {␊
1065␉␉␉verbose("Using user supplied NVCAP for %s :: %s\n", model, devicepath);␊
1066␉␉␉memcpy(default_NVCAP, new_NVCAP, NVCAP_LEN);␊
1067␉␉}␊
1068␉}␊
1069␊
1070#if DEBUG_NVCAP␊
1071 printf("NVCAP: %02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x\n",␊
1072␉␉default_NVCAP[0], default_NVCAP[1], default_NVCAP[2], default_NVCAP[3],␊
1073␉␉default_NVCAP[4], default_NVCAP[5], default_NVCAP[6], default_NVCAP[7],␊
1074␉␉default_NVCAP[8], default_NVCAP[9], default_NVCAP[10], default_NVCAP[11],␊
1075␉␉default_NVCAP[12], default_NVCAP[13], default_NVCAP[14], default_NVCAP[15],␊
1076␉␉default_NVCAP[16], default_NVCAP[17], default_NVCAP[18], default_NVCAP[19]);␊
1077#endif␊
1078␊
1079␉devprop_add_nvidia_template(device);␊
1080␉devprop_add_value(device, "NVCAP", default_NVCAP, NVCAP_LEN);␊
1081␉devprop_add_value(device, "VRAM,totalsize", (uint8_t*)&videoRam, 4);␊
1082␉devprop_add_value(device, "model", (uint8_t*)model, strlen(model) + 1);␊
1083␉devprop_add_value(device, "rom-revision", (uint8_t*)biosVersion, strlen(biosVersion) + 1);␊
1084␉devprop_add_value(device, "@1,connector-type", connector_type_1, 4);␊
1085␉devprop_add_value(device, "@0,display-cfg", default_dcfg_0, DCFG0_LEN);␊
1086␉devprop_add_value(device, "@1,display-cfg", default_dcfg_1, DCFG1_LEN);␊
1087␉devprop_add_value(device, "NVPM", default_NVPM, 28);␊
1088␉if (getBoolForKey(kVBIOS, &doit, &bootInfo->bootConfig) && doit) {␊
1089␉␉devprop_add_value(device, "vbios", rom, (nvBiosOveride > 0) ? nvBiosOveride : (rom[2] * 512));␊
1090␉}␊
1091␊
1092␉stringdata = malloc(sizeof(uint8_t) * string->length);␊
1093␉memcpy(stringdata, (uint8_t*)devprop_generate_string(string), string->length);␊
1094␉stringlength = string->length;␊
1095␊
1096␉return true;␊
1097}␊
1098

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