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Root/branches/iFabio/Chameleon/i386/libsaio/nvidia.c

Source at commit 325 created 12 years 9 months ago.
By ifabio, Update to C2RC5 r.1164. Some change into makefile and buildpkg script thanks to meklort for the tips.
1/*␊
2 *␉NVidia injector␊
3 *␊
4 *␉Copyright (C) 2009␉Jasmin Fazlic, iNDi␊
5 *␊
6 *␉NVidia injector is free software: you can redistribute it and/or modify␊
7 *␉it under the terms of the GNU General Public License as published by␊
8 *␉the Free Software Foundation, either version 3 of the License, or␊
9 *␉(at your option) any later version.␊
10 *␊
11 *␉NVidia driver and injector is distributed in the hope that it will be useful,␊
12 *␉but WITHOUT ANY WARRANTY; without even the implied warranty of␊
13 *␉MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the␊
14 *␉GNU General Public License for more details.␊
15 *␊
16 *␉You should have received a copy of the GNU General Public License␊
17 *␉along with NVidia injector.␉ If not, see <http://www.gnu.org/licenses/>.␊
18 */ ␊
19/*␊
20 * Alternatively you can choose to comply with APSL␊
21 */␊
22␊
23␊
24/*␊
25 * DCB-Table parsing is based on software (nouveau driver) originally distributed under following license:␊
26 *␊
27 *␊
28 * Copyright 2005-2006 Erik Waling␊
29 * Copyright 2006 Stephane Marchesin␊
30 * Copyright 2007-2009 Stuart Bennett␊
31 *␊
32 * Permission is hereby granted, free of charge, to any person obtaining a␊
33 * copy of this software and associated documentation files (the "Software"),␊
34 * to deal in the Software without restriction, including without limitation␊
35 * the rights to use, copy, modify, merge, publish, distribute, sublicense,␊
36 * and/or sell copies of the Software, and to permit persons to whom the␊
37 * Software is furnished to do so, subject to the following conditions:␊
38 *␊
39 * The above copyright notice and this permission notice shall be included in␊
40 * all copies or substantial portions of the Software.␊
41 *␊
42 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR␊
43 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,␊
44 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL␊
45 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,␊
46 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF␊
47 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE␊
48 * SOFTWARE.␊
49 */␊
50␊
51#include "boot.h"␊
52#include "bootstruct.h"␊
53#include "pci.h"␊
54#include "platform.h"␊
55#include "device_inject.h"␊
56#include "nvidia.h"␊
57␊
58#ifndef DEBUG_NVIDIA␊
59#define DEBUG_NVIDIA 0␊
60#endif␊
61␊
62#if DEBUG_NVIDIA␊
63#define DBG(x...)␉printf(x)␊
64#else␊
65#define DBG(x...)␊
66#endif␊
67␊
68#define NVIDIA_ROM_SIZE␉␉␉␉0x10000␊
69#define PATCH_ROM_SUCCESS␉␉␉1␊
70#define PATCH_ROM_SUCCESS_HAS_LVDS␉2␊
71#define PATCH_ROM_FAILED␉␉␉0␊
72#define MAX_NUM_DCB_ENTRIES␉␉␉16␊
73#define TYPE_GROUPED␉␉␉␉0xff␊
74␊
75extern uint32_t devices_number;␊
76␊
77const char *nvidia_compatible_0[]␉=␉{ "@0,compatible",␉"NVDA,NVMac"␉ };␊
78const char *nvidia_compatible_1[]␉=␉{ "@1,compatible",␉"NVDA,NVMac"␉ };␊
79const char *nvidia_device_type_0[]␉=␉{ "@0,device_type", "display"␉␉ };␊
80const char *nvidia_device_type_1[]␉=␉{ "@1,device_type", "display"␉␉ };␊
81const char *nvidia_device_type[]␉=␉{ "device_type",␉"NVDA,Parent"␉ };␊
82const char *nvidia_name_0[]␉␉␉=␉{ "@0,name",␉␉"NVDA,Display-A" };␊
83const char *nvidia_name_1[]␉␉␉=␉{ "@1,name",␉␉"NVDA,Display-B" };␊
84const char *nvidia_slot_name[]␉␉=␉{ "AAPL,slot-name", "Slot-1"␉␉ };␊
85␊
86static uint8_t default_NVCAP[]= {␊
87␉0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0d, 0x00,␊
88␉0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a,␊
89␉0x00, 0x00, 0x00, 0x00␊
90};␊
91␊
92#define NVCAP_LEN ( sizeof(default_NVCAP) / sizeof(uint8_t) )␊
93␊
94static uint8_t default_dcfg_0[]␉␉=␉{0xff, 0xff, 0xff, 0xff};␊
95static uint8_t default_dcfg_1[]␉␉=␉{0xff, 0xff, 0xff, 0xff};␊
96␊
97#define DCFG0_LEN ( sizeof(default_dcfg_0) / sizeof(uint8_t) )␊
98#define DCFG1_LEN ( sizeof(default_dcfg_1) / sizeof(uint8_t) )␊
99␊
100static struct nv_chipsets_t NVKnownChipsets[] = {␊
101␉{ 0x00000000, "Unknown" },␊
102// temporary placement␊
103␉{ 0x10DE0DF4, "GeForce GT 450M" }, //Azi + issue #99␊
104␉{ 0x10DE1251, "GeForce GTX 560M" }, // Asus G74SX␊
105//========================================␊
106␉// 0040 - 004F␉␊
107␉{ 0x10DE0040, "GeForce 6800 Ultra" },␊
108␉{ 0x10DE0041, "GeForce 6800" },␊
109␉{ 0x10DE0042, "GeForce 6800 LE" },␊
110␉{ 0x10DE0043, "GeForce 6800 XE" },␊
111␉{ 0x10DE0044, "GeForce 6800 XT" },␊
112␉{ 0x10DE0045, "GeForce 6800 GT" },␊
113␉{ 0x10DE0046, "GeForce 6800 GT" },␊
114␉{ 0x10DE0047, "GeForce 6800 GS" },␊
115␉{ 0x10DE0048, "GeForce 6800 XT" },␊
116␉{ 0x10DE004D, "Quadro FX 3400" },␊
117␉{ 0x10DE004E, "Quadro FX 4000" },␊
118␉{ 0x10DE0090, "GeForce 7800 GTX" },␊
119␉{ 0x10DE0091, "GeForce 7800 GTX" },␊
120␉{ 0x10DE0092, "GeForce 7800 GT" },␊
121␉{ 0x10DE0093, "GeForce 7800 GS" },␊
122␉{ 0x10DE0095, "GeForce 7800 SLI" },␊
123␉{ 0x10DE0098, "GeForce Go 7800" },␊
124␉{ 0x10DE0099, "GeForce Go 7800 GTX" },␊
125␉{ 0x10DE009D, "Quadro FX 4500" },␊
126␉{ 0x10DE00C0, "GeForce 6800 GS" },␊
127␉{ 0x10DE00C1, "GeForce 6800" },␊
128␉{ 0x10DE00C2, "GeForce 6800 LE" },␊
129␉{ 0x10DE00C3, "GeForce 6800 XT" },␊
130␉{ 0x10DE00C8, "GeForce Go 6800" },␊
131␉{ 0x10DE00C9, "GeForce Go 6800 Ultra" },␊
132␉{ 0x10DE00CC, "Quadro FX Go1400" },␊
133␉{ 0x10DE00CD, "Quadro FX 3450/4000 SDI" },␊
134␉{ 0x10DE00CE, "Quadro FX 1400" },␊
135␉{ 0x10DE00F1, "GeForce 6600 GT" },␊
136␉{ 0x10DE00F2, "GeForce 6600" },␊
137␉{ 0x10DE00F3, "GeForce 6200" },␊
138␉{ 0x10DE00F4, "GeForce 6600 LE" },␊
139␉{ 0x10DE00F5, "GeForce 7800 GS" },␊
140␉{ 0x10DE00F6, "GeForce 6800 GS/XT" },␊
141␉{ 0x10DE00F8, "Quadro FX 3400/4400" },␊
142␉{ 0x10DE00F9, "GeForce 6800 Series GPU" },␊
143␉{ 0x10DE0140, "GeForce 6600 GT" },␊
144␉{ 0x10DE0141, "GeForce 6600" },␊
145␉{ 0x10DE0142, "GeForce 6600 LE" },␊
146␉{ 0x10DE0143, "GeForce 6600 VE" },␊
147␉{ 0x10DE0144, "GeForce Go 6600" },␊
148␉{ 0x10DE0145, "GeForce 6610 XL" },␊
149␉{ 0x10DE0146, "GeForce Go 6600 TE/6200 TE" },␊
150␉{ 0x10DE0147, "GeForce 6700 XL" },␊
151␉{ 0x10DE0148, "GeForce Go 6600" },␊
152␉{ 0x10DE0149, "GeForce Go 6600 GT" },␊
153␉{ 0x10DE014A, "Quadro NVS 440" },␊
154␉{ 0x10DE014C, "Quadro FX 550" },␊
155␉{ 0x10DE014D, "Quadro FX 550" },␊
156␉{ 0x10DE014E, "Quadro FX 540" },␊
157␉{ 0x10DE014F, "GeForce 6200" },␊
158␉{ 0x10DE0160, "GeForce 6500" },␊
159␉{ 0x10DE0161, "GeForce 6200 TurboCache(TM)" },␊
160␉{ 0x10DE0162, "GeForce 6200SE TurboCache(TM)" },␊
161␉{ 0x10DE0163, "GeForce 6200 LE" },␊
162␉{ 0x10DE0164, "GeForce Go 6200" },␊
163␉{ 0x10DE0165, "Quadro NVS 285" },␊
164␉{ 0x10DE0166, "GeForce Go 6400" },␊
165␉{ 0x10DE0167, "GeForce Go 6200" },␊
166␉{ 0x10DE0168, "GeForce Go 6400" },␊
167␉{ 0x10DE0169, "GeForce 6250" },␊
168␉{ 0x10DE016A, "GeForce 7100 GS" },␊
169␉{ 0x10DE0191, "GeForce 8800 GTX" },␊
170␉{ 0x10DE0193, "GeForce 8800 GTS" },␊
171␉{ 0x10DE0194, "GeForce 8800 Ultra" },␊
172␉{ 0x10DE0197, "Tesla C870" },␊
173␉{ 0x10DE019D, "Quadro FX 5600" },␊
174␉{ 0x10DE019E, "Quadro FX 4600" },␊
175␉{ 0x10DE01D0, "GeForce 7350 LE" },␊
176␉{ 0x10DE01D1, "GeForce 7300 LE" },␊
177␉{ 0x10DE01D2, "GeForce 7550 LE" },␊
178␉{ 0x10DE01D3, "GeForce 7300 SE/7200 GS" },␊
179␉{ 0x10DE01D6, "GeForce Go 7200" },␊
180␉{ 0x10DE01D7, "GeForce Go 7300" },␊
181␉{ 0x10DE01D8, "GeForce Go 7400" },␊
182␉{ 0x10DE01D9, "GeForce Go 7400 GS" },␊
183␉{ 0x10DE01DA, "Quadro NVS 110M" },␊
184␉{ 0x10DE01DB, "Quadro NVS 120M" },␊
185␉{ 0x10DE01DC, "Quadro FX 350M" },␊
186␉{ 0x10DE01DD, "GeForce 7500 LE" },␊
187␉{ 0x10DE01DE, "Quadro FX 350" },␊
188␉{ 0x10DE01DF, "GeForce 7300 GS" },␊
189␉{ 0x10DE0211, "GeForce 6800" },␊
190␉{ 0x10DE0212, "GeForce 6800 LE" },␊
191␉{ 0x10DE0215, "GeForce 6800 GT" },␊
192␉{ 0x10DE0218, "GeForce 6800 XT" },␊
193␉{ 0x10DE0221, "GeForce 6200" },␊
194␉{ 0x10DE0222, "GeForce 6200 A-LE" },␊
195␉{ 0x10DE0240, "GeForce 6150" },␊
196␉{ 0x10DE0241, "GeForce 6150 LE" },␊
197␉{ 0x10DE0242, "GeForce 6100" },␊
198␉{ 0x10DE0244, "GeForce Go 6150" },␊
199␉{ 0x10DE0245, "Quadro NVS 210S / GeForce 6150LE" },␊
200␉{ 0x10DE0247, "GeForce Go 6100" },␊
201␉{ 0x10DE0290, "GeForce 7900 GTX" },␊
202␉{ 0x10DE0291, "GeForce 7900 GT/GTO" },␊
203␉{ 0x10DE0292, "GeForce 7900 GS" },␊
204␉{ 0x10DE0293, "GeForce 7950 GX2" },␊
205␉{ 0x10DE0294, "GeForce 7950 GX2" },␊
206␉{ 0x10DE0295, "GeForce 7950 GT" },␊
207␉{ 0x10DE0298, "GeForce Go 7900 GS" },␊
208␉{ 0x10DE0299, "GeForce Go 7900 GTX" },␊
209␉{ 0x10DE029A, "Quadro FX 2500M" },␊
210␉{ 0x10DE029B, "Quadro FX 1500M" },␊
211␉{ 0x10DE029C, "Quadro FX 5500" },␊
212␉{ 0x10DE029D, "Quadro FX 3500" },␊
213␉{ 0x10DE029E, "Quadro FX 1500" },␊
214␉{ 0x10DE029F, "Quadro FX 4500 X2" },␊
215␉{ 0x10DE02E0, "GeForce 7600 GT" },␊
216␉{ 0x10DE02E1, "GeForce 7600 GS" },␊
217␉{ 0x10DE02E2, "GeForce 7300 GT" },␊
218␉{ 0x10DE02E3, "GeForce 7900 GS" },␊
219␉{ 0x10DE02E4, "GeForce 7950 GT" },␊
220␉{ 0x10DE0301, "GeForce FX 5800 Ultra" },␊
221␉{ 0x10DE0302, "GeForce FX 5800" },␊
222␉{ 0x10DE0308, "Quadro FX 2000" },␊
223␉{ 0x10DE0309, "Quadro FX 1000" },␊
224␉{ 0x10DE0311, "GeForce FX 5600 Ultra" },␊
225␉{ 0x10DE0312, "GeForce FX 5600" },␊
226␉{ 0x10DE0314, "GeForce FX 5600XT" },␊
227␉{ 0x10DE031A, "GeForce FX Go5600" },␊
228␉{ 0x10DE031B, "GeForce FX Go5650" },␊
229␉{ 0x10DE031C, "Quadro FX Go700" },␊
230␉{ 0x10DE0324, "GeForce FX Go5200" },␊
231␉{ 0x10DE0325, "GeForce FX Go5250" },␊
232␉{ 0x10DE0326, "GeForce FX 5500" },␊
233␉{ 0x10DE0328, "GeForce FX Go5200 32M/64M" },␊
234␉{ 0x10DE032A, "Quadro NVS 55/280 PCI" },␊
235␉{ 0x10DE032B, "Quadro FX 500/600 PCI" },␊
236␉{ 0x10DE032C, "GeForce FX Go53xx Series" },␊
237␉{ 0x10DE032D, "GeForce FX Go5100" },␊
238␉{ 0x10DE0330, "GeForce FX 5900 Ultra" },␊
239␉{ 0x10DE0331, "GeForce FX 5900" },␊
240␉{ 0x10DE0332, "GeForce FX 5900XT" },␊
241␉{ 0x10DE0333, "GeForce FX 5950 Ultra" },␊
242␉{ 0x10DE0334, "GeForce FX 5900ZT" },␊
243␉{ 0x10DE0338, "Quadro FX 3000" },␊
244␉{ 0x10DE033F, "Quadro FX 700" },␊
245␉{ 0x10DE0341, "GeForce FX 5700 Ultra" },␊
246␉{ 0x10DE0342, "GeForce FX 5700" },␊
247␉{ 0x10DE0343, "GeForce FX 5700LE" },␊
248␉{ 0x10DE0344, "GeForce FX 5700VE" },␊
249␉{ 0x10DE0347, "GeForce FX Go5700" },␊
250␉{ 0x10DE0348, "GeForce FX Go5700" },␊
251␉{ 0x10DE034C, "Quadro FX Go1000" },␊
252␉{ 0x10DE034E, "Quadro FX 1100" },␊
253␉{ 0x10DE038B, "GeForce 7650 GS" },␊
254␉{ 0x10DE0390, "GeForce 7650 GS" },␊
255␉{ 0x10DE0391, "GeForce 7600 GT" },␊
256␉{ 0x10DE0392, "GeForce 7600 GS" },␊
257␉{ 0x10DE0393, "GeForce 7300 GT" },␊
258␉{ 0x10DE0394, "GeForce 7600 LE" },␊
259␉{ 0x10DE0395, "GeForce 7300 GT" },␊
260␉{ 0x10DE0397, "GeForce Go 7700" },␊
261␉{ 0x10DE0398, "GeForce Go 7600" },␊
262␉{ 0x10DE0399, "GeForce Go 7600 GT"},␊
263␉{ 0x10DE039A, "Quadro NVS 300M" },␊
264␉{ 0x10DE039B, "GeForce Go 7900 SE" },␊
265␉{ 0x10DE039C, "Quadro FX 550M" },␊
266␉{ 0x10DE039E, "Quadro FX 560" },␊
267␉{ 0x10DE03D0, "GeForce 6150SE nForce 430" },␊
268␉{ 0x10DE03D1, "GeForce 6100 nForce 405" },␊
269␉{ 0x10DE03D2, "GeForce 6100 nForce 400" },␊
270␉{ 0x10DE03D5, "GeForce 6100 nForce 420" },␊
271␉{ 0x10DE03D6, "GeForce 7025 / nForce 630a" },␊
272␉{ 0x10DE0400, "GeForce 8600 GTS" },␊
273␉{ 0x10DE0401, "GeForce 8600 GT" },␊
274␉{ 0x10DE0402, "GeForce 8600 GT" },␊
275␉{ 0x10DE0403, "GeForce 8600 GS" },␊
276␉{ 0x10DE0404, "GeForce 8400 GS" },␊
277␉{ 0x10DE0405, "GeForce 9500M GS" },␊
278␉{ 0x10DE0406, "GeForce 8300 GS" },␊
279␉{ 0x10DE0407, "GeForce 8600M GT" },␊
280␉{ 0x10DE0408, "GeForce 9650M GS" },␊
281␉{ 0x10DE0409, "GeForce 8700M GT" },␊
282␉{ 0x10DE040A, "Quadro FX 370" },␊
283␉{ 0x10DE040B, "Quadro NVS 320M" },␊
284␉{ 0x10DE040C, "Quadro FX 570M" },␊
285␉{ 0x10DE040D, "Quadro FX 1600M" },␊
286␉{ 0x10DE040E, "Quadro FX 570" },␊
287␉{ 0x10DE040F, "Quadro FX 1700" },␊
288␉{ 0x10DE0410, "GeForce GT 330" },␊
289␉{ 0x10DE0420, "GeForce 8400 SE" },␊
290␉{ 0x10DE0421, "GeForce 8500 GT" },␊
291␉{ 0x10DE0422, "GeForce 8400 GS" },␊
292␉{ 0x10DE0423, "GeForce 8300 GS" },␊
293␉{ 0x10DE0424, "GeForce 8400 GS" },␊
294␉{ 0x10DE0425, "GeForce 8600M GS" },␊
295␉{ 0x10DE0426, "GeForce 8400M GT" },␊
296␉{ 0x10DE0427, "GeForce 8400M GS" },␊
297␉{ 0x10DE0428, "GeForce 8400M G" },␊
298␉{ 0x10DE0429, "Quadro NVS 140M" },␊
299␉{ 0x10DE042A, "Quadro NVS 130M" },␊
300␉{ 0x10DE042B, "Quadro NVS 135M" },␊
301␉{ 0x10DE042C, "GeForce 9400 GT" },␊
302␉{ 0x10DE042D, "Quadro FX 360M" },␊
303␉{ 0x10DE042E, "GeForce 9300M G" },␊
304␉{ 0x10DE042F, "Quadro NVS 290" },␊
305␉{ 0x10DE053A, "GeForce 7050 PV / nForce 630a" },␊
306␉{ 0x10DE053B, "GeForce 7050 PV / nForce 630a" },␊
307␉{ 0x10DE053E, "GeForce 7025 / nForce 630a" },␊
308␉{ 0x10DE05E0, "GeForce GTX 295" },␊
309␉{ 0x10DE05E1, "GeForce GTX 280" },␊
310␉{ 0x10DE05E2, "GeForce GTX 260" },␊
311␉{ 0x10DE05E3, "GeForce GTX 285" },␊
312␉{ 0x10DE05E6, "GeForce GTX 275" },␊
313␉{ 0x10DE05EA, "GeForce GTX 260" },␊
314␉{ 0x10DE05EB, "GeForce GTX 295" },␊
315␉{ 0x10DE05ED, "Quadroplex 2200 D2" },␊
316␉{ 0x10DE05F8, "Quadroplex 2200 S4" },␊
317␉{ 0x10DE05F9, "Quadro CX" },␊
318␉{ 0x10DE05FD, "Quadro FX 5800" },␊
319␉{ 0x10DE05FE, "Quadro FX 4800" },␊
320␉{ 0x10DE05FF, "Quadro FX 3800" },␊
321␉{ 0x10DE0600, "GeForce 8800 GTS 512" },␊
322␉{ 0x10DE0601, "GeForce 9800 GT" },␊
323␉{ 0x10DE0602, "GeForce 8800 GT" },␊
324␉{ 0x10DE0603, "GeForce GT 230" },␊
325␉{ 0x10DE0604, "GeForce 9800 GX2" },␊
326␉{ 0x10DE0605, "GeForce 9800 GT" },␊
327␉{ 0x10DE0606, "GeForce 8800 GS" },␊
328␉{ 0x10DE0607, "GeForce GTS 240" },␊
329␉{ 0x10DE0608, "GeForce 9800M GTX" },␊
330␉{ 0x10DE0609, "GeForce 8800M GTS" },␊
331␉{ 0x10DE060A, "GeForce GTX 280M" },␊
332␉{ 0x10DE060B, "GeForce 9800M GT" },␊
333␉{ 0x10DE060C, "GeForce 8800M GTX" },␊
334␉{ 0x10DE060D, "GeForce 8800 GS" },␊
335␉{ 0x10DE060F, "GeForce GTX 285M" },␊
336␉{ 0x10DE0610, "GeForce 9600 GSO" },␊
337␉{ 0x10DE0611, "GeForce 8800 GT" },␊
338␉{ 0x10DE0612, "GeForce 9800 GTX" },␊
339␉{ 0x10DE0613, "GeForce 9800 GTX+" },␊
340␉{ 0x10DE0614, "GeForce 9800 GT" },␊
341␉{ 0x10DE0615, "GeForce GTS 250" },␊
342␉{ 0x10DE0617, "GeForce 9800M GTX" },␊
343␉{ 0x10DE0618, "GeForce GTX 260M" },␊
344␉{ 0x10DE0619, "Quadro FX 4700 X2" },␊
345␉{ 0x10DE061A, "Quadro FX 3700" },␊
346␉{ 0x10DE061B, "Quadro VX 200" },␊
347␉{ 0x10DE061C, "Quadro FX 3600M" },␊
348␉{ 0x10DE061D, "Quadro FX 2800M" },␊
349␉{ 0x10DE061F, "Quadro FX 3800M" },␊
350␉{ 0x10DE0622, "GeForce 9600 GT" },␊
351␉{ 0x10DE0623, "GeForce 9600 GS" },␊
352␉{ 0x10DE0625, "GeForce 9600 GSO 512"},␊
353␉{ 0x10DE0626, "GeForce GT 130" },␊
354␉{ 0x10DE0627, "GeForce GT 140" },␊
355␉{ 0x10DE0628, "GeForce 9800M GTS" },␊
356␉{ 0x10DE062A, "GeForce 9700M GTS" },␊
357␉{ 0x10DE062C, "GeForce 9800M GTS" },␊
358␉{ 0x10DE062D, "GeForce 9600 GT" },␊
359␉{ 0x10DE062E, "GeForce 9600 GT" },␊
360␉{ 0x10DE0631, "GeForce GTS 160M" },␊
361␉{ 0x10DE0632, "GeForce GTS 150M" },␊
362␉{ 0x10DE0635, "GeForce 9600 GSO" },␊
363␉{ 0x10DE0637, "GeForce 9600 GT" },␊
364␉{ 0x10DE0638, "Quadro FX 1800" },␊
365␉{ 0x10DE063A, "Quadro FX 2700M" },␊
366␉{ 0x10DE0640, "GeForce 9500 GT" },␊
367␉{ 0x10DE0641, "GeForce 9400 GT" },␊
368␉{ 0x10DE0642, "GeForce 8400 GS" },␊
369␉{ 0x10DE0643, "GeForce 9500 GT" },␊
370␉{ 0x10DE0644, "GeForce 9500 GS" },␊
371␉{ 0x10DE0645, "GeForce 9500 GS" },␊
372␉{ 0x10DE0646, "GeForce GT 120" },␊
373␉{ 0x10DE0647, "GeForce 9600M GT" },␊
374␉{ 0x10DE0648, "GeForce 9600M GS" },␊
375␉{ 0x10DE0649, "GeForce 9600M GT" },␊
376␉{ 0x10DE064A, "GeForce 9700M GT" },␊
377␉{ 0x10DE064B, "GeForce 9500M G" },␊
378␉{ 0x10DE064C, "GeForce 9650M GT" },␊
379␉{ 0x10DE0651, "GeForce G 110M" },␊
380␉{ 0x10DE0652, "GeForce GT 130M" },␊
381␉{ 0x10DE0653, "GeForce GT 120M" },␊
382␉{ 0x10DE0654, "GeForce GT 220M" },␊
383␉{ 0x10DE0656, "GeForce 9650 S" },␊
384␉{ 0x10DE0658, "Quadro FX 380" },␊
385␉{ 0x10DE0659, "Quadro FX 580" },␊
386␉{ 0x10DE065A, "Quadro FX 1700M" },␊
387␉{ 0x10DE065B, "GeForce 9400 GT" },␊
388␉{ 0x10DE065C, "Quadro FX 770M" },␊
389␉{ 0x10DE065F, "GeForce G210" },␊
390␉{ 0x10DE06C0, "GeForce GTX 480" },␊
391␉{ 0x10DE06C3, "GeForce GTX D12U" },␊
392␉{ 0x10DE06C4, "GeForce GTX 465" },␊
393␉{ 0x10DE06CA, "GeForce GTX 480M" },␊
394␉{ 0x10DE06CD, "GeForce GTX 470" },␊
395␉{ 0x10DE06D1, "Tesla C2050" },␊
396␉{ 0x10DE06D1, "Tesla C2070" },␊
397␉{ 0x10DE06D2, "Tesla M2070" },␊
398␉{ 0x10DE06D8, "Quadro 6000" },␊
399␉{ 0x10DE06D9, "Quadro 5000" },␊
400␉{ 0x10DE06DA, "Quadro 5000M" },␊
401␉{ 0x10DE06DC, "Quadro 6000" },␊
402␉{ 0x10DE06DE, "Tesla M2050" },␊
403␉{ 0x10DE06DE, "Tesla M2070" },␊
404␉{ 0x10DE06DD, "Quadro 4000" },␊
405␉{ 0x10DE06DE, "Tesla M2050" },␊
406␉{ 0x10DE06DE, "Tesla M2070" },␊
407␉{ 0x10DE06DF, "Tesla M2070-Q" },␊
408␉{ 0x10DE06E0, "GeForce 9300 GE" },␊
409␉{ 0x10DE06E1, "GeForce 9300 GS" },␊
410␉{ 0x10DE06E2, "GeForce 8400" },␊
411␉{ 0x10DE06E3, "GeForce 8400 SE" },␊
412␉{ 0x10DE06E4, "GeForce 8400 GS" },␊
413␉{ 0x10DE06E5, "GeForce 9300M GS" },␊
414␉{ 0x10DE06E6, "GeForce G100" },␊
415␉{ 0x10DE06E7, "GeForce 9300 SE" },␊
416␉{ 0x10DE06E8, "GeForce 9200M GS" },␊
417␉{ 0x10DE06E9, "GeForce 9300M GS" },␊
418␉{ 0x10DE06EA, "Quadro NVS 150M" },␊
419␉{ 0x10DE06EB, "Quadro NVS 160M" },␊
420␉{ 0x10DE06EC, "GeForce G 105M" },␊
421␉{ 0x10DE06EF, "GeForce G 103M" },␊
422␉{ 0x10DE06F8, "Quadro NVS 420" },␊
423␉{ 0x10DE06F9, "Quadro FX 370 LP" },␊
424␉{ 0x10DE06FA, "Quadro NVS 450" },␊
425␉{ 0x10DE06FB, "Quadro FX 370M" },␊
426␉{ 0x10DE06FD, "Quadro NVS 295" },␊
427␉{ 0x10DE07E0, "GeForce 7150 / nForce 630i" },␊
428␉{ 0x10DE07E1, "GeForce 7100 / nForce 630i" },␊
429␉{ 0x10DE07E2, "GeForce 7050 / nForce 630i" },␊
430␉{ 0x10DE07E3, "GeForce 7050 / nForce 610i" },␊
431␉{ 0x10DE07E5, "GeForce 7050 / nForce 620i" },␊
432␉{ 0x10DE0844, "GeForce 9100M G" },␊
433␉{ 0x10DE0845, "GeForce 8200M G" },␊
434␉{ 0x10DE0846, "GeForce 9200" },␊
435␉{ 0x10DE0847, "GeForce 9100" },␊
436␉{ 0x10DE0848, "GeForce 8300" },␊
437␉{ 0x10DE0849, "GeForce 8200" },␊
438␉{ 0x10DE084A, "nForce 730a" },␊
439␉{ 0x10DE084B, "GeForce 9200" },␊
440␉{ 0x10DE084C, "nForce 980a/780a SLI" },␊
441␉{ 0x10DE084D, "nForce 750a SLI" },␊
442␉{ 0x10DE084F, "GeForce 8100 / nForce 720a" },␊
443␉{ 0x10DE0860, "GeForce 9400" },␊
444␉{ 0x10DE0861, "GeForce 9400" },␊
445␉{ 0x10DE0862, "GeForce 9400M G" },␊
446␉{ 0x10DE0863, "GeForce 9400M" },␊
447␉{ 0x10DE0864, "GeForce 9300" },␊
448␉{ 0x10DE0865, "ION" },␊
449␉{ 0x10DE0866, "GeForce 9400M G" },␊
450␉{ 0x10DE0867, "GeForce 9400" },␊
451␉{ 0x10DE0868, "nForce 760i SLI" },␊
452␉{ 0x10DE086A, "GeForce 9400" },␊
453␉{ 0x10DE086C, "GeForce 9300 / nForce 730i" },␊
454␉{ 0x10DE086D, "GeForce 9200" },␊
455␉{ 0x10DE086E, "GeForce 9100M G" },␊
456␉{ 0x10DE086F, "GeForce 8200M G" },␊
457␉{ 0x10DE0870, "GeForce 9400M" },␊
458␉{ 0x10DE0871, "GeForce 9200" },␊
459␉{ 0x10DE0872, "GeForce G102M" },␊
460␉{ 0x10DE0873, "GeForce G102M" },␊
461␉{ 0x10DE0874, "ION 9300M" },␊
462␉{ 0x10DE0876, "ION" },␊
463␉{ 0x10DE087A, "GeForce 9400" },␊
464␉{ 0x10DE087D, "ION 9400M" },␊
465␉{ 0x10DE087E, "ION LE" },␊
466␉{ 0x10DE087F, "ION LE" },␊
467␉{ 0x10DE0A20, "GeForce GT220" },␊
468␉{ 0x10DE0A22, "GeForce 315" },␊
469␉{ 0x10DE0A23, "GeForce 210" },␊
470␉{ 0x10DE0A28, "GeForce GT 230M" },␊
471␉{ 0x10DE0A29, "GeForce GT 330M" },␊
472␉{ 0x10DE0A2A, "GeForce GT 230M" },␊
473␉{ 0x10DE0A2B, "GeForce GT 330M" },␊
474␉{ 0x10DE0A2C, "NVS 5100M" },␊
475␉{ 0x10DE0A2D, "GeForce GT 320M" },␊
476␉{ 0x10DE0A34, "GeForce GT 240M" },␊
477␉{ 0x10DE0A35, "GeForce GT 325M" },␊
478␉{ 0x10DE0A3C, "Quadro FX 880M" },␊
479␉{ 0x10DE0A60, "GeForce G210" },␊
480␉{ 0x10DE0A62, "GeForce 205" },␊
481␉{ 0x10DE0A63, "GeForce 310" },␊
482␉{ 0x10DE0A64, "ION" },␊
483␉{ 0x10DE0A65, "GeForce 210" },␊
484␉{ 0x10DE0A66, "GeForce 310" },␊
485␉{ 0x10DE0A67, "GeForce 315" },␊
486␉{ 0x10DE0A68, "GeForce G105M" },␊
487␉{ 0x10DE0A69, "GeForce G105M" },␊
488␉{ 0x10DE0A6A, "NVS 2100M" },␊
489␉{ 0x10DE0A6C, "NVS 3100M" },␊
490␉{ 0x10DE0A6E, "GeForce 305M" },␊
491␉{ 0x10DE0A6F, "ION" },␊
492␉{ 0x10DE0A70, "GeForce 310M" },␊
493␉{ 0x10DE0A71, "GeForce 305M" },␊
494␉{ 0x10DE0A72, "GeForce 310M" },␊
495␉{ 0x10DE0A73, "GeForce 305M" },␊
496␉{ 0x10DE0A74, "GeForce G210M" },␊
497␉{ 0x10DE0A75, "GeForce G310M" },␊
498␉{ 0x10DE0A78, "Quadro FX 380 LP" },␊
499␉{ 0x10DE0A7C, "Quadro FX 380M" },␊
500␉{ 0x10DE0CA0, "GeForce GT 330 " },␊
501␉{ 0x10DE0CA2, "GeForce GT 320" },␊
502␉{ 0x10DE0CA3, "GeForce GT 240" },␊
503␉{ 0x10DE0CA4, "GeForce GT 340" },␊
504␉{ 0x10DE0CA7, "GeForce GT 330" },␊
505␉{ 0x10DE0CA8, "GeForce GTS 260M" },␊
506␉{ 0x10DE0CA9, "GeForce GTS 250M" },␊
507␉{ 0x10DE0CAC, "GeForce 315" },␊
508␉{ 0x10DE0CAF, "GeForce GT 335M" },␊
509␉{ 0x10DE0CB0, "GeForce GTS 350M" },␊
510␉{ 0x10DE0CB1, "GeForce GTS 360M" },␊
511␉{ 0x10DE0CBC, "Quadro FX 1800M" },␊
512␉{ 0x10DE0DC0, "GeForce GT 440" },␊
513␉{ 0x10DE0DC1, "D12-P1-35" },␊
514␉{ 0x10DE0DC2, "D12-P1-35" },␊
515␉{ 0x10DE0DC4, "GeForce GTS 450" },␊
516␉{ 0x10DE0DC5, "GeForce GTS 450" },␊
517␉{ 0x10DE0DC6, "GeForce GTS 450" },␊
518␉{ 0x10DE0DCA, "GF10x" },␊
519␉{ 0x10DE0DCD, "GeForce GT 555M" },␊
520␉{ 0x10DE0DCE, "GeForce GT 555M" },␊
521␉{ 0x10DE0DD1, "GeForce GTX 460M" },␊
522␉{ 0x10DE0DD2, "GeForce GT 445M" },␊
523␉{ 0x10DE0DD3, "GeForce GT 435M" },␊
524␉{ 0x10DE0DD6, "GeForce GT 550M" },␊
525␉{ 0x10DE0DD8, "Quadro 2000" },␊
526␉{ 0x10DE0DDA, "Quadro 2000M" },␊
527␉{ 0x10DE0DDE, "GF106-ES" },␊
528␉{ 0x10DE0DDF, "GF106-INT" },␊
529␉{ 0x10DE0DE0, "GeForce GT 440" },␊
530␉{ 0x10DE0DE1, "GeForce GT 430" },␊
531␉{ 0x10DE0DE2, "GeForce GT 420" },␊
532␉{ 0x10DE0DE5, "GeForce GT 530" },␊
533␉{ 0x10DE0DEB, "GeForce GT 555M" },␊
534␉{ 0x10DE0DEC, "GeForce GT 525M" },␊
535␉{ 0x10DE0DED, "GeForce GT 520M" },␊
536␉{ 0x10DE0DEE, "GeForce GT 415M" },␊
537␉{ 0x10DE0DF0, "GeForce GT 425M" },␊
538␉{ 0x10DE0DF1, "GeForce GT 420M" },␊
539␉{ 0x10DE0DF2, "GeForce GT 435M" },␊
540␉{ 0x10DE0DF3, "GeForce GT 420M" },␊
541␉{ 0x10DE0DF4, "GeForce GT 540M" },␊
542␉{ 0x10DE0DF5, "GeForce GT 525M" },␊
543␉{ 0x10DE0DF6, "GeForce GT 550M" },␊
544␉{ 0x10DE0DF7, "GeForce GT 520M" },␊
545␉{ 0x10DE0DF8, "Quadro 600" },␊
546␉{ 0x10DE0DFA, "Quadro 1000M" },␊
547␉{ 0x10DE0DFE, "GF108 ES" },␊
548␉{ 0x10DE0DFF, "GF108 INT" },␊
549␉{ 0x10DE0E21, "D12U-25" },␊
550␉{ 0x10DE0E22, "GeForce GTX 460" },␊
551␉{ 0x10DE0E23, "GeForce GTX 460 SE" },␊
552␉{ 0x10DE0E24, "GeForce GTX 460" },␊
553␉{ 0x10DE0E25, "D12U-50" },␊
554␉{ 0x10DE0E30, "GeForce GTX 470M" },␊
555␉{ 0x10DE0E31, "GeForce GTX 485M" },␊
556␉{ 0x10DE0E38, "GF104GL" },␊
557␉{ 0x10DE0E3A, "Quadro 3000M" },␊
558␉{ 0x10DE0E3B, "Quadro 4000M" },␊
559␉{ 0x10DE0E3E, "GF104-ES" },␊
560␉{ 0x10DE0E3F, "GF104-INT" },␊
561␉{ 0x10DE1050, "GeForce GT 520M" },␊
562␉{ 0x10DE1054, "GeForce GT 410M" },␊
563␉{ 0x10DE1056, "NVS 4200M" },␊
564␉{ 0x10DE1057, "NVS 4200M" },␊
565␉{ 0x10DE107F, "NVIDIA GF119-ES" },␊
566␉{ 0x10DE1080, "GeForce GTX 580" },␊
567␉{ 0x10DE1081, "GeForce GTX 570" },␊
568␉{ 0x10DE1082, "GeForce GTX 560 Ti" },␊
569␉{ 0x10DE1083, "D13U" },␊
570␉{ 0x10DE1086, "GeForce GTX 570" },␊
571␉{ 0x10DE1088, "GeForce GTX 590" },␊
572␉{ 0x10DE1098, "D13U" },␊
573␉{ 0x10DE109A, "Quadro 5010M / N12E-Q5" },␊
574␉{ 0x10DE10C3, "GeForce 8400 GS" },␊
575␉{ 0x10DE1200, "GeForce GTX 560 Ti" },␊
576␉{ 0x10DE1244, "GeForce GTX 550 Ti" },␊
577␉{ 0x10DE1245, "GeForce GTS 450" },␊
578␉{ 0x10DE1251, "N12E-GS-A1" },␊
579};␊
580␊
581static uint16_t swap16(uint16_t x)␊
582{␊
583␉return (((x & 0x00FF) << 8) | ((x & 0xFF00) >> 8));␊
584}␊
585␊
586static uint16_t read16(uint8_t *ptr, uint16_t offset)␊
587{␊
588␉uint8_t ret[2];␊
589␊
590␉ret[0] = ptr[offset+1];␊
591␉ret[1] = ptr[offset];␊
592␊
593␉return *((uint16_t*)&ret);␊
594}␊
595␊
596#if 0␊
597static uint32_t swap32(uint32_t x)␊
598{␊
599␉return ((x & 0x000000FF) << 24) | ((x & 0x0000FF00) << 8 ) | ((x & 0x00FF0000) >> 8 ) | ((x & 0xFF000000) >> 24);␊
600}␊
601␊
602static uint8_t␉read8(uint8_t *ptr, uint16_t offset)␊
603{ ␊
604␉return ptr[offset];␊
605}␊
606␊
607static uint32_t read32(uint8_t *ptr, uint16_t offset)␊
608{␊
609␉uint8_t ret[4];␊
610␊
611␉ret[0] = ptr[offset+3];␊
612␉ret[1] = ptr[offset+2];␊
613␉ret[2] = ptr[offset+1];␊
614␉ret[3] = ptr[offset];␊
615␊
616␉return *((uint32_t*)&ret);␊
617}␊
618#endif␊
619␊
620static int patch_nvidia_rom(uint8_t *rom)␊
621{␊
622␉if (!rom || (rom[0] != 0x55 && rom[1] != 0xaa)) {␊
623␉␉printf("False ROM signature: 0x%02x%02x\n", rom[0], rom[1]);␊
624␉␉pause();␊
625␉␉return PATCH_ROM_FAILED;␊
626␉}␊
627␉␊
628␉uint16_t dcbptr = swap16(read16(rom, 0x36));␊
629␊
630␉if (!dcbptr) {␊
631␉␉printf("no dcb table found\n");␊
632␉␉pause();␊
633␉␉return PATCH_ROM_FAILED;␊
634␉}␊
635//␉else␊
636//␉␉printf("dcb table at offset 0x%04x\n", dcbptr);␊
637␉ ␊
638␉uint8_t *dcbtable␉␉ = &rom[dcbptr];␊
639␉uint8_t dcbtable_version = dcbtable[0];␊
640␉uint8_t headerlength␉ = 0;␊
641␉uint8_t numentries␉␉ = 0;␊
642␉uint8_t recordlength␉ = 0;␊
643␉␊
644␉if (dcbtable_version >= 0x20)␊
645␉{␊
646␉␉uint32_t sig;␊
647␉␉␊
648␉␉if (dcbtable_version >= 0x30)␊
649␉␉{␊
650␉␉␉headerlength = dcbtable[1];␊
651␉␉␉numentries␉ = dcbtable[2];␊
652␉␉␉recordlength = dcbtable[3];␊
653␊
654␉␉␉sig = *(uint32_t *)&dcbtable[6];␊
655␉␉}␊
656␉␉else␊
657␉␉{␊
658␉␉␉sig = *(uint32_t *)&dcbtable[4];␊
659␉␉␉headerlength = 8;␊
660␉␉}␊
661␉␉␊
662␉␉if (sig != 0x4edcbdcb)␊
663␉␉{␊
664␉␉␉printf("Bad display config block signature (0x%8x)\n", sig); //Azi: issue #48␊
665␉␉␉pause();␊
666␉␉␉return PATCH_ROM_FAILED;␊
667␉␉}␊
668␉}␊
669␉else if (dcbtable_version >= 0x14) /* some NV15/16, and NV11+ */␊
670␉{␊
671␉␉char sig[8] = { 0 };␊
672␉␉␊
673␉␉strncpy(sig, (char *)&dcbtable[-7], 7);␊
674␉␉recordlength = 10;␊
675␉␉␊
676␉␉if (strcmp(sig, "DEV_REC"))␊
677␉␉{␊
678␉␉␉printf("Bad Display Configuration Block signature (%s)\n", sig);␊
679␉␉␉pause();␊
680␉␉␉return PATCH_ROM_FAILED;␊
681␉␉}␊
682␉}␊
683␉else␊
684␉{␊
685␉␉printf("ERROR: dcbtable_version is 0x%X\n", dcbtable_version);␊
686␉␉pause();␊
687␉␉return PATCH_ROM_FAILED;␊
688␉}␊
689␉␊
690␉if (numentries >= MAX_NUM_DCB_ENTRIES)␊
691␉␉numentries = MAX_NUM_DCB_ENTRIES;␊
692␉␊
693␉uint8_t num_outputs = 0, i = 0;␊
694␉␊
695␉struct dcbentry␊
696␉{␊
697␉␉uint8_t type;␊
698␉␉uint8_t index;␊
699␉␉uint8_t *heads;␊
700␉} entries[numentries];␊
701␉␊
702␉for (i = 0; i < numentries; i++)␊
703␉{␊
704␉␉uint32_t connection;␊
705␉␉connection = *(uint32_t *)&dcbtable[headerlength + recordlength * i];␊
706␊
707␉␉/* Should we allow discontinuous DCBs? Certainly DCB I2C tables can be discontinuous */␊
708␉␉if ((connection & 0x0000000f) == 0x0000000f) /* end of records */ ␊
709␉␉␉continue;␊
710␉␉if (connection == 0x00000000) /* seen on an NV11 with DCB v1.5 */ ␊
711␉␉␉continue;␊
712␉␉if ((connection & 0xf) == 0x6) /* we skip type 6 as it doesnt appear on macbook nvcaps */␊
713␉␉␉continue;␊
714␉␉␊
715␉␉entries[num_outputs].type = connection & 0xf;␊
716␉␉entries[num_outputs].index = num_outputs;␊
717␉␉entries[num_outputs++].heads = (uint8_t*)&(dcbtable[(headerlength + recordlength * i) + 1]);␊
718␉}␊
719␉␊
720␉int has_lvds = false;␊
721␉uint8_t channel1 = 0, channel2 = 0;␊
722␉␊
723␉for (i = 0; i < num_outputs; i++)␊
724␉{␊
725␉␉if (entries[i].type == 3)␊
726␉␉{␊
727␉␉␉has_lvds = true;␊
728␉␉␉//printf("found LVDS\n");␊
729␉␉␉channel1 |= ( 0x1 << entries[i].index);␊
730␉␉␉entries[i].type = TYPE_GROUPED;␊
731␉␉}␊
732␉}␊
733␉␊
734␉// if we have a LVDS output, we group the rest to the second channel␊
735␉if (has_lvds)␊
736␉{␊
737␉␉for (i = 0; i < num_outputs; i++)␊
738␉␉{␊
739␉␉␉if (entries[i].type == TYPE_GROUPED)␊
740␉␉␉␉continue;␊
741␉␉␉␊
742␉␉␉channel2 |= ( 0x1 << entries[i].index);␊
743␉␉␉entries[i].type = TYPE_GROUPED;␊
744␉␉}␊
745␉}␊
746␉else␊
747␉{␊
748␉␉int x;␊
749␉␉// we loop twice as we need to generate two channels␊
750␉␉for (x = 0; x <= 1; x++)␊
751␉␉{␊
752␉␉␉for (i=0; i<num_outputs; i++)␊
753␉␉␉{␊
754␉␉␉␉if (entries[i].type == TYPE_GROUPED)␊
755␉␉␉␉␉continue;␊
756␉␉␉␉// if type is TMDS, the prior output is ANALOG␊
757␉␉␉␉// we always group ANALOG and TMDS␊
758␉␉␉␉// if there is a TV output after TMDS, we group it to that channel as well␊
759␉␉␉␉if (i && entries[i].type == 0x2)␊
760␉␉␉␉{␊
761␉␉␉␉␉switch (x)␊
762␉␉␉␉␉{␊
763␉␉␉␉␉␉case 0:␊
764␉␉␉␉␉␉␉//printf("group channel 1\n");␊
765␉␉␉␉␉␉␉channel1 |= ( 0x1 << entries[i].index);␊
766␉␉␉␉␉␉␉entries[i].type = TYPE_GROUPED;␊
767␉␉␉␉␉␉␉␊
768␉␉␉␉␉␉␉if ((entries[i-1].type == 0x0))␊
769␉␉␉␉␉␉␉{␊
770␉␉␉␉␉␉␉␉channel1 |= ( 0x1 << entries[i-1].index);␊
771␉␉␉␉␉␉␉␉entries[i-1].type = TYPE_GROUPED;␊
772␉␉␉␉␉␉␉}␊
773␉␉␉␉␉␉␉// group TV as well if there is one␊
774␉␉␉␉␉␉␉if ( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) )␊
775␉␉␉␉␉␉␉{␊
776␉␉␉␉␉␉␉␉//␉printf("group tv1\n");␊
777␉␉␉␉␉␉␉␉channel1 |= ( 0x1 << entries[i+1].index);␊
778␉␉␉␉␉␉␉␉entries[i+1].type = TYPE_GROUPED;␊
779␉␉␉␉␉␉␉}␊
780␉␉␉␉␉␉␉break;␊
781␉␉␉␉␉␉␊
782␉␉␉␉␉␉case 1:␊
783␉␉␉␉␉␉␉//printf("group channel 2 : %d\n", i);␊
784␉␉␉␉␉␉␉channel2 |= ( 0x1 << entries[i].index);␊
785␉␉␉␉␉␉␉entries[i].type = TYPE_GROUPED;␊
786␉␉␉␉␉␉␉␊
787␉␉␉␉␉␉␉if ((entries[i - 1].type == 0x0))␊
788␉␉␉␉␉␉␉{␊
789␉␉␉␉␉␉␉␉channel2 |= ( 0x1 << entries[i-1].index);␊
790␉␉␉␉␉␉␉␉entries[i-1].type = TYPE_GROUPED;␊
791␉␉␉␉␉␉␉}␊
792␉␉␉␉␉␉␉// group TV as well if there is one␊
793␉␉␉␉␉␉␉if ( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) )␊
794␉␉␉␉␉␉␉{␊
795␉␉␉␉␉␉␉␉//␉printf("group tv2\n");␊
796␉␉␉␉␉␉␉␉channel2 |= ( 0x1 << entries[i+1].index);␊
797␉␉␉␉␉␉␉␉entries[i+1].type = TYPE_GROUPED;␊
798␉␉␉␉␉␉␉}␊
799␉␉␉␉␉␉␉break;␊
800␉␉␉␉␉}␊
801␉␉␉␉␉break;␊
802␉␉␉␉}␊
803␉␉␉}␊
804␉␉}␊
805␉}␊
806␉␊
807␉// if we have left ungrouped outputs merge them to the empty channel␊
808␉uint8_t *togroup;// = (channel1 ? (channel2 ? NULL : &channel2) : &channel1);␊
809␉togroup = &channel2;␊
810␉␊
811␉for (i = 0; i < num_outputs; i++)␊
812␉{␊
813␉␉if (entries[i].type != TYPE_GROUPED)␊
814␉␉{␊
815␉␉␉//printf("%d not grouped\n", i);␊
816␉␉␉if (togroup)␊
817␉␉␉{␊
818␉␉␉␉*togroup |= ( 0x1 << entries[i].index);␊
819␉␉␉}␊
820␉␉␉entries[i].type = TYPE_GROUPED;␊
821␉␉}␊
822␉}␊
823␉␊
824␉if (channel1 > channel2)␊
825␉{␊
826␉␉uint8_t buff = channel1;␊
827␉␉channel1 = channel2;␊
828␉␉channel2 = buff;␊
829␉}␊
830␉␊
831␉default_NVCAP[6] = channel1;␊
832␉default_NVCAP[8] = channel2;␊
833␉␊
834␉// patching HEADS␊
835␉for (i = 0; i < num_outputs; i++)␊
836␉{␊
837␉␉if (channel1 & (1 << i))␊
838␉␉{␊
839␉␉␉*entries[i].heads = 1;␊
840␉␉}␊
841␉␉else if(channel2 & (1 << i))␊
842␉␉{␊
843␉␉␉*entries[i].heads = 2;␊
844␉␉}␊
845␉}␊
846␉return (has_lvds ? PATCH_ROM_SUCCESS_HAS_LVDS : PATCH_ROM_SUCCESS);␊
847}␊
848␊
849static char *get_nvidia_model(uint32_t id)␊
850{␊
851␉int i;␊
852␉␊
853␉for (i = 1; i < (sizeof(NVKnownChipsets) / sizeof(NVKnownChipsets[0])); i++) {␊
854␉␉if (NVKnownChipsets[i].device == id)␊
855␉␉{␊
856␉␉␉return NVKnownChipsets[i].name;␊
857␉␉}␊
858␉}␊
859␉return NVKnownChipsets[0].name;␊
860}␊
861␊
862static uint32_t load_nvidia_bios_file(const char *filename, uint8_t *buf, int bufsize)␊
863{␊
864␉int fd;␊
865␉int size;␊
866␉␊
867␉if ((fd = open_bvdev("bt(0,0)", filename, 0)) < 0)␊
868␉{␊
869␉␉return 0;␊
870␉}␊
871␉␊
872␉size = file_size(fd);␊
873␉␊
874␉if (size > bufsize)␊
875␉{␊
876␉␉printf("Filesize of %s is bigger than expected! Truncating to 0x%x Bytes!\n",␊
877␉␉␉␉filename, bufsize);␊
878␉␉size = bufsize;␊
879␉}␊
880␉size = read(fd, (char *)buf, size);␊
881␉close(fd);␊
882␉␊
883␉return size > 0 ? size : 0;␊
884}␊
885␊
886static int devprop_add_nvidia_template(struct DevPropDevice *device)␊
887{␊
888␉char tmp[16];␊
889␉␊
890␉if (!device)␊
891␉␉return 0;␊
892␉␊
893␉if (!DP_ADD_TEMP_VAL(device, nvidia_compatible_0))␊
894␉␉return 0;␊
895␉if (!DP_ADD_TEMP_VAL(device, nvidia_device_type_0))␊
896␉␉return 0;␊
897␉if (!DP_ADD_TEMP_VAL(device, nvidia_name_0))␊
898␉␉return 0;␊
899␉if (!DP_ADD_TEMP_VAL(device, nvidia_compatible_1))␊
900␉␉return 0;␊
901␉if (!DP_ADD_TEMP_VAL(device, nvidia_device_type_1))␊
902␉␉return 0;␊
903␉if (!DP_ADD_TEMP_VAL(device, nvidia_name_1))␊
904␉␉return 0;␊
905␉if (!DP_ADD_TEMP_VAL(device, nvidia_device_type))␊
906␉␉return 0;␊
907␉␊
908␉// Rek : Dont use sprintf return, it does not WORK !! our custom sprintf() always return 0!␊
909␉// len = sprintf(tmp, "Slot-%x", devices_number);␊
910␉sprintf(tmp, "Slot-%x",devices_number);␊
911␉devprop_add_value(device, "AAPL,slot-name", (uint8_t *) tmp, strlen(tmp));␊
912␉devices_number++;␊
913␉␊
914␉return 1;␊
915}␊
916␊
917int hex2bin(const char *hex, uint8_t *bin, int len)␊
918{␊
919␉char␉*p;␊
920␉int␉␉i;␊
921␉char␉buf[3];␊
922␉␊
923␉if (hex == NULL || bin == NULL || len <= 0 || strlen(hex) != len * 2) {␊
924␉␉printf("[ERROR] bin2hex input error\n");␊
925␉␉return -1;␊
926␉}␊
927␉␊
928␉buf[2] = '\0';␊
929␉p = (char *) hex;␊
930␉␊
931␉for (i = 0; i < len; i++)␊
932␉{␊
933␉␉if (p[0] == '\0' || p[1] == '\0' || !isxdigit(p[0]) || !isxdigit(p[1])) {␊
934␉␉␉printf("[ERROR] bin2hex '%s' syntax error\n", hex);␊
935␉␉␉return -2;␊
936␉␉}␊
937␉␉buf[0] = *p++;␊
938␉␉buf[1] = *p++;␊
939␉␉bin[i] = (unsigned char) strtoul(buf, NULL, 16);␊
940␉}␊
941␉return 0;␊
942}␊
943␊
944unsigned long long mem_detect(volatile uint8_t *regs, uint8_t nvCardType, pci_dt_t *nvda_dev)␊
945{␊
946␉unsigned long long vram_size = 0;␊
947␉␊
948␉if (nvCardType < NV_ARCH_50)␊
949␉{␊
950␉␉vram_size = REG32(NV04_PFB_FIFO_DATA);␊
951␉␉vram_size &= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK;␊
952␉}␊
953␉else if (nvCardType < NV_ARCH_C0)␊
954␉{␊
955␉␉vram_size = REG32(NV04_PFB_FIFO_DATA);␊
956␉␉vram_size |= (vram_size & 0xff) << 32;␊
957␉␉vram_size &= 0xffffffff00ll;␊
958␉}␊
959␉else // >= NV_ARCH_C0␊
960␉{␊
961␉␉vram_size = REG32(NVC0_MEM_CTRLR_RAM_AMOUNT) << 20;␊
962␉␉vram_size *= REG32(NVC0_MEM_CTRLR_COUNT);␊
963␉}␊
964␉␊
965␉// Workaround for GT 420/430 & 9600M GT␊
966␉switch (nvda_dev->device_id)␊
967␉{␊
968␉␉case 0x0DE1: vram_size = 1024*1024*1024; break; // GT 430␊
969␉␉case 0x0DE2: vram_size = 1024*1024*1024; break; // GT 420␊
970␉␉case 0x0649: vram_size = 512*1024*1024; break;␉// 9600M GT␊
971␉␉default: break;␊
972␉}␊
973␉␊
974␉return vram_size;␊
975}␊
976␊
977bool setup_nvidia_devprop(pci_dt_t *nvda_dev)␊
978{␊
979␉struct DevPropDevice␉*device;␊
980␉char␉␉␉␉␉*devicepath;␊
981␉option_rom_pci_header_t *rom_pci_header;␊
982␉volatile uint8_t␉␉*regs;␊
983␉uint8_t␉␉␉␉␉*rom;␊
984␉uint8_t␉␉␉␉␉*nvRom;␊
985␉uint8_t␉␉␉␉␉nvCardType;␊
986␉unsigned long long␉␉videoRam;␊
987␉uint32_t␉␉␉␉nvBiosOveride;␊
988␉uint32_t␉␉␉␉bar[7];␊
989␉uint32_t␉␉␉␉boot_display;␊
990␉int␉␉␉␉␉␉nvPatch;␊
991␉int␉␉␉␉␉␉len;␊
992␉char␉␉␉␉␉biosVersion[32];␊
993␉char␉␉␉␉␉nvFilename[32];␊
994␉char␉␉␉␉␉kNVCAP[12];␊
995␉char␉␉␉␉␉*model;␊
996␉const char␉␉␉␉*value;␊
997␉bool␉␉␉␉␉doit;␊
998␉␊
999␉devicepath = get_pci_dev_path(nvda_dev);␊
1000␉bar[0] = pci_config_read32(nvda_dev->dev.addr, 0x10 );␊
1001␉regs = (uint8_t *) (bar[0] & ~0x0f);␊
1002␉␊
1003␉// get card type␊
1004␉nvCardType = (REG32(0) >> 20) & 0x1ff;␊
1005␉␊
1006␉// Amount of VRAM in kilobytes␊
1007␉videoRam = mem_detect(regs, nvCardType, nvda_dev);␊
1008␉model = get_nvidia_model((nvda_dev->vendor_id << 16) | nvda_dev->device_id);␊
1009␉␊
1010␉verbose("nVidia %s %dMB NV%02x [%04x:%04x] :: %s\n",␊
1011␉␉␉model, (uint32_t)(videoRam / 1024 / 1024),␊
1012␉␉␉(REG32(0) >> 20) & 0x1ff, nvda_dev->vendor_id, nvda_dev->device_id,␊
1013␉␉␉devicepath);␊
1014␉␊
1015␉rom = malloc(NVIDIA_ROM_SIZE);␊
1016␉sprintf(nvFilename, "/Extra/%04x_%04x.rom", (uint16_t)nvda_dev->vendor_id,␊
1017␉␉␉(uint16_t)nvda_dev->device_id);␊
1018␉␊
1019␉if (getBoolForKey(kUseNvidiaROM, &doit, &bootInfo->chameleonConfig) && doit)␊
1020␉{␊
1021␉␉verbose("Looking for nvidia video bios file %s\n", nvFilename);␊
1022␉␉nvBiosOveride = load_nvidia_bios_file(nvFilename, rom, NVIDIA_ROM_SIZE);␊
1023␉␉␊
1024␉␉if (nvBiosOveride > 0)␊
1025␉␉{␊
1026␉␉␉verbose("Using nVidia Video BIOS File %s (%d Bytes)\n", nvFilename, nvBiosOveride);␊
1027␉␉␉DBG("%s Signature 0x%02x%02x %d bytes\n", nvFilename, rom[0], rom[1], nvBiosOveride);␊
1028␉␉}␊
1029␉␉else␊
1030␉␉{␊
1031␉␉␉printf("ERROR: unable to open nVidia Video BIOS File %s\n", nvFilename);␊
1032␉␉␉return false;␊
1033␉␉}␊
1034␉}␊
1035␉else␊
1036␉{␊
1037␉␉// Otherwise read bios from card␊
1038␉␉nvBiosOveride = 0;␊
1039␉␉␊
1040␉␉// TODO: we should really check for the signature before copying the rom, i think.␊
1041␉␉␊
1042␉␉// PRAMIN first␊
1043␉␉nvRom = (uint8_t*)&regs[NV_PRAMIN_OFFSET];␊
1044␉␉bcopy((uint32_t *)nvRom, rom, NVIDIA_ROM_SIZE);␊
1045␉␉␊
1046␉␉// Valid Signature ?␊
1047␉␉if (rom[0] != 0x55 && rom[1] != 0xaa)␊
1048␉␉{␊
1049␉␉␉// PROM next␊
1050␉␉␉// Enable PROM access␊
1051␉␉␉(REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED;␊
1052␉␉␉␊
1053␉␉␉nvRom = (uint8_t*)&regs[NV_PROM_OFFSET];␊
1054␉␉␉bcopy((uint8_t *)nvRom, rom, NVIDIA_ROM_SIZE);␊
1055␉␉␉␊
1056␉␉␉// disable PROM access␊
1057␉␉␉(REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED;␊
1058␉␉␉␊
1059␉␉␉// Valid Signature ?␊
1060␉␉␉if (rom[0] != 0x55 && rom[1] != 0xaa)␊
1061␉␉␉{␊
1062␉␉␉␉// 0xC0000 last␊
1063␉␉␉␉bcopy((char *)0xc0000, rom, NVIDIA_ROM_SIZE);␊
1064␉␉␉␉␊
1065␉␉␉␉// Valid Signature ?␊
1066␉␉␉␉if (rom[0] != 0x55 && rom[1] != 0xaa)␊
1067␉␉␉␉{␊
1068␉␉␉␉␉printf("ERROR: Unable to locate nVidia Video BIOS\n");␊
1069␉␉␉␉␉return false;␊
1070␉␉␉␉}␊
1071␉␉␉␉else␊
1072␉␉␉␉{␊
1073␉␉␉␉␉DBG("ROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);␊
1074␉␉␉␉}␊
1075␉␉␉}␊
1076␉␉␉else␊
1077␉␉␉{␊
1078␉␉␉␉DBG("PROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);␊
1079␉␉␉}␊
1080␉␉}␊
1081␉␉else␊
1082␉␉{␊
1083␉␉␉DBG("PRAM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);␊
1084␉␉}␊
1085␉}␊
1086␉␊
1087␉if ((nvPatch = patch_nvidia_rom(rom)) == PATCH_ROM_FAILED) {␊
1088␉␉printf("ERROR: nVidia ROM Patching Failed!\n");␊
1089␉␉pause();␊
1090␉␉//return false;␊
1091␉}␊
1092␉␊
1093␉rom_pci_header = (option_rom_pci_header_t*)(rom + *(uint16_t *)&rom[24]);␊
1094␉␊
1095␉// check for 'PCIR' sig␊
1096␉if (rom_pci_header->signature == 0x50434952)␊
1097␉{␊
1098␉␉if (rom_pci_header->device_id != nvda_dev->device_id)␊
1099␉␉{␊
1100␉␉␉// Get Model from the OpROM␊
1101␉␉␉model = get_nvidia_model((rom_pci_header->vendor_id << 16) | rom_pci_header->device_id);␊
1102␉␉}␊
1103␉␉else␊
1104␉␉{␊
1105␉␉␉printf("nVidia incorrect PCI ROM signature: 0x%x\n", rom_pci_header->signature);␊
1106␉␉}␊
1107␉}␊
1108␉␊
1109␉if (!string) {␊
1110␉␉string = devprop_create_string();␊
1111␉}␊
1112␉device = devprop_add_device(string, devicepath);␊
1113␉␊
1114␉/* FIXME: for primary graphics card only */␊
1115␉boot_display = 1;␊
1116␉devprop_add_value(device, "@0,AAPL,boot-display", (uint8_t*)&boot_display, 4);␊
1117␉␊
1118␉if (nvPatch == PATCH_ROM_SUCCESS_HAS_LVDS) {␊
1119␉␉uint8_t built_in = 0x01;␊
1120␉␉devprop_add_value(device, "@0,built-in", &built_in, 1);␊
1121␉}␊
1122␉␊
1123␉// get bios version␊
1124␉const int MAX_BIOS_VERSION_LENGTH = 32;␊
1125␉char* version_str = (char*)malloc(MAX_BIOS_VERSION_LENGTH);␊
1126␉␊
1127␉memset(version_str, 0, MAX_BIOS_VERSION_LENGTH);␊
1128␉␊
1129␉int i, version_start;␊
1130␉int crlf_count = 0;␊
1131␉␊
1132␉// only search the first 384 bytes␊
1133␉for (i = 0; i < 0x180; i++)␊
1134␉{␊
1135␉␉if (rom[i] == 0x0D && rom[i+1] == 0x0A)␊
1136␉␉{␊
1137␉␉␉crlf_count++;␊
1138␉␉␉// second 0x0D0A was found, extract bios version␊
1139␉␉␉if (crlf_count == 2)␊
1140␉␉␉{␊
1141␉␉␉␉if (rom[i-1] == 0x20) i--; // strip last " "␊
1142␉␉␉␉␊
1143␉␉␉␉for (version_start = i; version_start > (i-MAX_BIOS_VERSION_LENGTH); version_start--)␊
1144␉␉␉␉{␊
1145␉␉␉␉␉// find start␊
1146␉␉␉␉␉if (rom[version_start] == 0x00)␊
1147␉␉␉␉␉{␊
1148␉␉␉␉␉␉version_start++;␊
1149␉␉␉␉␉␉␊
1150␉␉␉␉␉␉// strip "Version "␊
1151␉␉␉␉␉␉if (strncmp((const char*)rom+version_start, "Version ", 8) == 0)␊
1152␉␉␉␉␉␉{␊
1153␉␉␉␉␉␉␉version_start += 8;␊
1154␉␉␉␉␉␉}␊
1155␉␉␉␉␉␉␊
1156␉␉␉␉␉␉strncpy(version_str, (const char*)rom+version_start, i-version_start);␊
1157␉␉␉␉␉␉break;␊
1158␉␉␉␉␉}␊
1159␉␉␉␉}␊
1160␉␉␉␉break;␊
1161␉␉␉}␊
1162␉␉}␊
1163␉}␊
1164␉␊
1165␉sprintf(biosVersion, "%s", (nvBiosOveride > 0) ? nvFilename : version_str);␊
1166␉sprintf(kNVCAP, "NVCAP_%04x", nvda_dev->device_id);␊
1167␉␊
1168␉if (getValueForKey(kNVCAP, &value, &len, &bootInfo->chameleonConfig) && len == NVCAP_LEN * 2)␊
1169␉{␊
1170␉␉uint8_t new_NVCAP[NVCAP_LEN];␊
1171␉␉␊
1172␉␉if (hex2bin(value, new_NVCAP, NVCAP_LEN) == 0)␊
1173␉␉{␊
1174␉␉␉verbose("Using user supplied NVCAP for %s :: %s\n", model, devicepath);␊
1175␉␉␉memcpy(default_NVCAP, new_NVCAP, NVCAP_LEN);␊
1176␉␉}␊
1177␉}␊
1178␉␊
1179␉if (getValueForKey(kDcfg0, &value, &len, &bootInfo->chameleonConfig) && len == DCFG0_LEN * 2)␊
1180␉{␊
1181␉␉uint8_t new_dcfg0[DCFG0_LEN];␊
1182␉␉␊
1183␉␉if (hex2bin(value, new_dcfg0, DCFG0_LEN) == 0)␊
1184␉␉{␊
1185␉␉␉memcpy(default_dcfg_0, new_dcfg0, DCFG0_LEN);␊
1186␉␉␉␊
1187␉␉␉verbose("Using user supplied @0,display-cfg\n");␊
1188␉␉␉printf("@0,display-cfg: %02x%02x%02x%02x\n",␊
1189␉␉␉␉ default_dcfg_0[0], default_dcfg_0[1], default_dcfg_0[2], default_dcfg_0[3]);␊
1190␉␉}␊
1191␉}␊
1192␉␊
1193␉if (getValueForKey(kDcfg1, &value, &len, &bootInfo->chameleonConfig) && len == DCFG1_LEN * 2)␊
1194␉{␊
1195␉␉uint8_t new_dcfg1[DCFG1_LEN];␊
1196␉␉␊
1197␉␉if (hex2bin(value, new_dcfg1, DCFG1_LEN) == 0)␊
1198␉␉{␊
1199␉␉␉memcpy(default_dcfg_1, new_dcfg1, DCFG1_LEN);␊
1200␉␉␉␊
1201␉␉␉verbose("Using user supplied @1,display-cfg\n");␊
1202␉␉␉printf("@1,display-cfg: %02x%02x%02x%02x\n",␊
1203␉␉␉␉ default_dcfg_1[0], default_dcfg_1[1], default_dcfg_1[2], default_dcfg_1[3]);␊
1204␉␉}␊
1205␉}␊
1206␉␊
1207#if DEBUG_NVCAP␊
1208␉printf("NVCAP: %02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x\n",␊
1209␉default_NVCAP[0], default_NVCAP[1], default_NVCAP[2], default_NVCAP[3],␊
1210␉default_NVCAP[4], default_NVCAP[5], default_NVCAP[6], default_NVCAP[7],␊
1211␉default_NVCAP[8], default_NVCAP[9], default_NVCAP[10], default_NVCAP[11],␊
1212␉default_NVCAP[12], default_NVCAP[13], default_NVCAP[14], default_NVCAP[15],␊
1213␉default_NVCAP[16], default_NVCAP[17], default_NVCAP[18], default_NVCAP[19]);␊
1214#endif␊
1215␉␊
1216␉devprop_add_nvidia_template(device);␊
1217␉devprop_add_value(device, "NVCAP", default_NVCAP, NVCAP_LEN);␊
1218␉devprop_add_value(device, "VRAM,totalsize", (uint8_t*)&videoRam, 4);␊
1219␉devprop_add_value(device, "model", (uint8_t*)model, strlen(model) + 1);␊
1220␉devprop_add_value(device, "rom-revision", (uint8_t*)biosVersion, strlen(biosVersion) + 1);␊
1221␉devprop_add_value(device, "@0,display-cfg", default_dcfg_0, DCFG0_LEN);␊
1222␉devprop_add_value(device, "@1,display-cfg", default_dcfg_1, DCFG1_LEN);␊
1223␉␊
1224␉//add HDMI Audio back to nvidia␊
1225␉//http://forge.voodooprojects.org/p/chameleon/issues/67/␊
1226//␉uint8_t connector_type_1[]= {0x00, 0x08, 0x00, 0x00};␊
1227//␉devprop_add_value(device, "@1,connector-type",connector_type_1, 4);␊
1228␉//end Nvidia HDMI Audio␊
1229␉␊
1230␉if (getBoolForKey(kVBIOS, &doit, &bootInfo->chameleonConfig) && doit)␊
1231␉{␊
1232␉␉devprop_add_value(device, "vbios", rom, (nvBiosOveride > 0) ? nvBiosOveride : (rom[2] * 512));␊
1233␉}␊
1234␉␊
1235␉stringdata = malloc(sizeof(uint8_t) * string->length);␊
1236␉memcpy(stringdata, (uint8_t*)devprop_generate_string(string), string->length);␊
1237␉stringlength = string->length;␊
1238␉␊
1239␉return true;␊
1240}␊
1241

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