| 1 | #ifndef SDHCI_H␊ |
| 2 | #include "License.h"␊ |
| 3 | ␊ |
| 4 | /*Controller registers*/␊ |
| 5 | #define SDHCI_DMA_ADDRESS␉0x00␊ |
| 6 | ␊ |
| 7 | #define SDHCI_BLOCK_SIZE␉0x04␊ |
| 8 | #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))␊ |
| 9 | ␊ |
| 10 | #define SDHCI_BLOCK_COUNT␉0x06␊ |
| 11 | ␊ |
| 12 | #define SDHCI_ARGUMENT␉␉0x08␊ |
| 13 | ␊ |
| 14 | #define SDHCI_TRANSFER_MODE␉0x0C␊ |
| 15 | #define SDHCI_TRNS_DMA␉␉0x01␊ |
| 16 | #define SDHCI_TRNS_BLK_CNT_EN␉0x02␊ |
| 17 | #define SDHCI_TRNS_ACMD12␉0x04␊ |
| 18 | #define SDHCI_TRNS_READ␉0x10␊ |
| 19 | #define SDHCI_TRNS_MULTI␉0x20␊ |
| 20 | ␊ |
| 21 | #define SDHCI_COMMAND␉␉0x0E␊ |
| 22 | #define SDHCI_CMD_RESP_MASK␉0x03␊ |
| 23 | #define SDHCI_CMD_CRC␉␉0x08␊ |
| 24 | #define SDHCI_CMD_INDEX␉0x10␊ |
| 25 | #define SDHCI_CMD_DATA␉␉0x20␊ |
| 26 | ␊ |
| 27 | #define SDHCI_CMD_RESP_NONE␉0x00␊ |
| 28 | #define SDHCI_CMD_RESP_LONG␉0x01␊ |
| 29 | #define SDHCI_CMD_RESP_SHORT␉0x02␊ |
| 30 | #define SDHCI_CMD_RESP_SHORT_BUSY 0x03␊ |
| 31 | ␊ |
| 32 | #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))␊ |
| 33 | ␊ |
| 34 | #define SDHCI_RESPONSE␉␉0x10␊ |
| 35 | ␊ |
| 36 | #define SDHCI_BUFFER␉␉0x20␊ |
| 37 | ␊ |
| 38 | #define SDHCI_PRESENT_STATE␉0x24␊ |
| 39 | #define SDHCI_CMD_INHIBIT␉0x00000001␊ |
| 40 | #define SDHCI_DATA_INHIBIT␉0x00000002␊ |
| 41 | #define SDHCI_DOING_WRITE␉0x00000100␊ |
| 42 | #define SDHCI_DOING_READ␉0x00000200␊ |
| 43 | #define SDHCI_SPACE_AVAILABLE␉0x00000400␊ |
| 44 | #define SDHCI_DATA_AVAILABLE␉0x00000800␊ |
| 45 | #define SDHCI_CARD_PRESENT␉0x00010000␊ |
| 46 | #define SDHCI_WRITE_PROTECT␉0x00080000␊ |
| 47 | ␊ |
| 48 | #define SDHCI_HOST_CONTROL ␉0x28␊ |
| 49 | #define SDHCI_CTRL_LED␉␉0x01␊ |
| 50 | #define SDHCI_CTRL_4BITBUS␉0x02␊ |
| 51 | #define SDHCI_CTRL_HISPD␉0x04␊ |
| 52 | #define SDHCI_CTRL_DMA_MASK␉0x18␊ |
| 53 | #define SDHCI_CTRL_SDMA␉0x00␊ |
| 54 | #define SDHCI_CTRL_ADMA1␉0x08␊ |
| 55 | #define SDHCI_CTRL_ADMA32␉0x10␊ |
| 56 | #define SDHCI_CTRL_ADMA64␉0x18␊ |
| 57 | ␊ |
| 58 | #define SDHCI_POWER_CONTROL␉0x29␊ |
| 59 | #define SDHCI_POWER_ON␉␉0x01␊ |
| 60 | #define SDHCI_POWER_180␉0x0A␊ |
| 61 | #define SDHCI_POWER_300␉0x0C␊ |
| 62 | #define SDHCI_POWER_330␉0x0E␊ |
| 63 | ␊ |
| 64 | #define SDHCI_BLOCK_GAP_CONTROL␉0x2A␊ |
| 65 | ␊ |
| 66 | #define SDHCI_WAKE_UP_CONTROL␉0x2B␊ |
| 67 | ␊ |
| 68 | #define SDHCI_CLOCK_CONTROL␉0x2C␊ |
| 69 | #define SDHCI_DIVIDER_SHIFT␉8␊ |
| 70 | #define SDHCI_CLOCK_CARD_EN␉0x0004␊ |
| 71 | #define SDHCI_CLOCK_INT_STABLE␉0x0002␊ |
| 72 | #define SDHCI_CLOCK_INT_EN␉0x0001␊ |
| 73 | ␊ |
| 74 | #define SDHCI_TIMEOUT_CONTROL␉0x2E␊ |
| 75 | ␊ |
| 76 | #define SDHCI_SOFTWARE_RESET␉0x2F␊ |
| 77 | #define SDHCI_RESET_ALL␉0x01␊ |
| 78 | #define SDHCI_RESET_CMD␉0x02␊ |
| 79 | #define SDHCI_RESET_DATA␉0x04␊ |
| 80 | ␊ |
| 81 | #define SDHCI_INT_STATUS␉0x30␊ |
| 82 | #define SDHCI_INT_ENABLE␉0x34␊ |
| 83 | #define SDHCI_SIGNAL_ENABLE␉0x38␊ |
| 84 | #define SDHCI_INT_RESPONSE␉0x00000001␊ |
| 85 | #define SDHCI_INT_DATA_END␉0x00000002␊ |
| 86 | #define SDHCI_INT_DMA_END␉0x00000008␊ |
| 87 | #define SDHCI_INT_SPACE_AVAIL␉0x00000010␊ |
| 88 | #define SDHCI_INT_DATA_AVAIL␉0x00000020␊ |
| 89 | #define SDHCI_INT_CARD_INSERT␉0x00000040␊ |
| 90 | #define SDHCI_INT_CARD_REMOVE␉0x00000080␊ |
| 91 | #define SDHCI_INT_CARD_INT␉0x00000100␊ |
| 92 | #define SDHCI_INT_ERROR␉0x00008000␊ |
| 93 | #define SDHCI_INT_TIMEOUT␉0x00010000␊ |
| 94 | #define SDHCI_INT_CRC␉␉0x00020000␊ |
| 95 | #define SDHCI_INT_END_BIT␉0x00040000␊ |
| 96 | #define SDHCI_INT_INDEX␉0x00080000␊ |
| 97 | #define SDHCI_INT_DATA_TIMEOUT␉0x00100000␊ |
| 98 | #define SDHCI_INT_DATA_CRC␉0x00200000␊ |
| 99 | #define SDHCI_INT_DATA_END_BIT␉0x00400000␊ |
| 100 | #define SDHCI_INT_BUS_POWER␉0x00800000␊ |
| 101 | #define SDHCI_INT_ACMD12ERR␉0x01000000␊ |
| 102 | #define SDHCI_INT_ADMA_ERROR␉0x02000000␊ |
| 103 | ␊ |
| 104 | #define SDHCI_INT_NORMAL_MASK␉0x00007FFF␊ |
| 105 | #define SDHCI_INT_ERROR_MASK␉0xFFFF8000␊ |
| 106 | ␊ |
| 107 | #define SDHCI_INT_CMD_MASK␉(SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \␊ |
| 108 | ␉␉SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)␊ |
| 109 | #define SDHCI_INT_DATA_MASK␉(SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \␊ |
| 110 | ␉␉SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \␊ |
| 111 | ␉␉SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \␊ |
| 112 | ␉␉SDHCI_INT_DATA_END_BIT)␊ |
| 113 | ␊ |
| 114 | #define SDHCI_ACMD12_ERR␉0x3C␊ |
| 115 | ␊ |
| 116 | /* 3E-3F reserved */␊ |
| 117 | ␊ |
| 118 | #define SDHCI_CAPABILITIES␉0x40␊ |
| 119 | #define SDHCI_TIMEOUT_CLK_MASK␉0x0000003F␊ |
| 120 | #define SDHCI_TIMEOUT_CLK_SHIFT 0␊ |
| 121 | #define SDHCI_TIMEOUT_CLK_UNIT␉0x00000080␊ |
| 122 | #define SDHCI_CLOCK_BASE_MASK␉0x00003F00␊ |
| 123 | #define SDHCI_CLOCK_BASE_SHIFT␉8␊ |
| 124 | #define SDHCI_MAX_BLOCK_MASK␉0x00030000␊ |
| 125 | #define SDHCI_MAX_BLOCK_SHIFT 16␊ |
| 126 | #define SDHCI_CAN_DO_ADMA2␉0x00080000␊ |
| 127 | #define SDHCI_CAN_DO_ADMA1␉0x00100000␊ |
| 128 | #define SDHCI_CAN_DO_HISPD␉0x00200000␊ |
| 129 | #define SDHCI_CAN_DO_DMA␉0x00400000␊ |
| 130 | #define SDHCI_CAN_VDD_330␉0x01000000␊ |
| 131 | #define SDHCI_CAN_VDD_300␉0x02000000␊ |
| 132 | #define SDHCI_CAN_VDD_180␉0x04000000␊ |
| 133 | #define SDHCI_CAN_64BIT␉0x10000000␊ |
| 134 | ␊ |
| 135 | /* 44-47 reserved for more caps */␊ |
| 136 | ␊ |
| 137 | #define SDHCI_MAX_CURRENT␉0x48␊ |
| 138 | ␊ |
| 139 | /* 4C-4F reserved for more max current */␊ |
| 140 | ␊ |
| 141 | #define SDHCI_SET_ACMD12_ERROR␉0x50␊ |
| 142 | #define SDHCI_SET_INT_ERROR␉0x52␊ |
| 143 | ␊ |
| 144 | #define SDHCI_ADMA_ERROR␉0x54␊ |
| 145 | ␊ |
| 146 | /* 55-57 reserved */␊ |
| 147 | ␊ |
| 148 | #define SDHCI_ADMA_ADDRESS␉0x58␊ |
| 149 | ␊ |
| 150 | /* 60-FB reserved */␊ |
| 151 | ␊ |
| 152 | #define SDHCI_SLOT_INT_STATUS␉0xFC␊ |
| 153 | ␊ |
| 154 | #define SDHCI_HOST_VERSION␉0xFE␊ |
| 155 | #define SDHCI_VENDOR_VER_MASK␉0xFF00␊ |
| 156 | #define SDHCI_VENDOR_VER_SHIFT␉8␊ |
| 157 | #define SDHCI_SPEC_VER_MASK␉0x00FF␊ |
| 158 | #define SDHCI_SPEC_VER_SHIFT␉0␊ |
| 159 | #define SDHCI_SPEC_100␉0␊ |
| 160 | #define SDHCI_SPEC_200␉1␊ |
| 161 | ␊ |
| 162 | #ifdef LINUX_STRUCTURE␊ |
| 163 | struct sdhci_ops;␊ |
| 164 | ␊ |
| 165 | struct sdhci_host {␊ |
| 166 | ␉/* Data set by hardware interface driver */␊ |
| 167 | ␉const char␉␉*hw_name;␉/* Hardware bus name */␊ |
| 168 | ␊ |
| 169 | ␉unsigned int␉␉quirks;␉␉/* Deviations from spec. */␊ |
| 170 | ␊ |
| 171 | /* Controller doesn't honor resets unless we touch the clock register */␊ |
| 172 | #define SDHCI_QUIRK_CLOCK_BEFORE_RESET␉␉␉(1<<0)␊ |
| 173 | /* Controller has bad caps bits, but really supports DMA */␊ |
| 174 | #define SDHCI_QUIRK_FORCE_DMA␉␉␉␉(1<<1)␊ |
| 175 | /* Controller doesn't like to be reset when there is no card inserted. */␊ |
| 176 | #define SDHCI_QUIRK_NO_CARD_NO_RESET␉␉␉(1<<2)␊ |
| 177 | /* Controller doesn't like clearing the power reg before a change */␊ |
| 178 | #define SDHCI_QUIRK_SINGLE_POWER_WRITE␉␉␉(1<<3)␊ |
| 179 | /* Controller has flaky internal state so reset it on each ios change */␊ |
| 180 | #define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS␉␉(1<<4)␊ |
| 181 | /* Controller has an unusable DMA engine */␊ |
| 182 | #define SDHCI_QUIRK_BROKEN_DMA␉␉␉␉(1<<5)␊ |
| 183 | /* Controller has an unusable ADMA engine */␊ |
| 184 | #define SDHCI_QUIRK_BROKEN_ADMA␉␉␉␉(1<<6)␊ |
| 185 | /* Controller can only DMA from 32-bit aligned addresses */␊ |
| 186 | #define SDHCI_QUIRK_32BIT_DMA_ADDR␉␉␉(1<<7)␊ |
| 187 | /* Controller can only DMA chunk sizes that are a multiple of 32 bits */␊ |
| 188 | #define SDHCI_QUIRK_32BIT_DMA_SIZE␉␉␉(1<<8)␊ |
| 189 | /* Controller can only ADMA chunks that are a multiple of 32 bits */␊ |
| 190 | #define SDHCI_QUIRK_32BIT_ADMA_SIZE␉␉␉(1<<9)␊ |
| 191 | /* Controller needs to be reset after each request to stay stable */␊ |
| 192 | #define SDHCI_QUIRK_RESET_AFTER_REQUEST␉␉␉(1<<10)␊ |
| 193 | /* Controller needs voltage and power writes to happen separately */␊ |
| 194 | #define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER␉␉(1<<11)␊ |
| 195 | /* Controller provides an incorrect timeout value for transfers */␊ |
| 196 | #define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL␉␉␉(1<<12)␊ |
| 197 | /* Controller has an issue with buffer bits for small transfers */␊ |
| 198 | #define SDHCI_QUIRK_BROKEN_SMALL_PIO␉␉␉(1<<13)␊ |
| 199 | ␊ |
| 200 | ␉int␉␉␉irq;␉␉/* Device IRQ */␊ |
| 201 | ␉void __iomem *␉␉ioaddr;␉␉/* Mapped address */␊ |
| 202 | ␊ |
| 203 | ␉const struct sdhci_ops␉*ops;␉␉/* Low level hw interface */␊ |
| 204 | ␊ |
| 205 | ␉/* Internal data */␊ |
| 206 | ␉struct mmc_host␉␉*mmc;␉␉/* MMC structure */␊ |
| 207 | ␉u64␉␉␉dma_mask;␉/* custom DMA mask */␊ |
| 208 | ␊ |
| 209 | #ifdef CONFIG_LEDS_CLASS␊ |
| 210 | ␉struct led_classdev␉led;␉␉/* LED control */␊ |
| 211 | #endif␊ |
| 212 | ␊ |
| 213 | ␉spinlock_t␉␉lock;␉␉/* Mutex */␊ |
| 214 | ␊ |
| 215 | ␉int␉␉␉flags;␉␉/* Host attributes */␊ |
| 216 | #define SDHCI_USE_DMA␉␉(1<<0)␉␉/* Host is DMA capable */␊ |
| 217 | #define SDHCI_USE_ADMA␉␉(1<<1)␉␉/* Host is ADMA capable */␊ |
| 218 | #define SDHCI_REQ_USE_DMA␉(1<<2)␉␉/* Use DMA for this req. */␊ |
| 219 | #define SDHCI_DEVICE_DEAD␉(1<<3)␉␉/* Device unresponsive */␊ |
| 220 | ␊ |
| 221 | ␉unsigned int␉␉version;␉/* SDHCI spec. version */␊ |
| 222 | ␊ |
| 223 | ␉unsigned int␉␉max_clk;␉/* Max possible freq (MHz) */␊ |
| 224 | ␉unsigned int␉␉timeout_clk;␉/* Timeout freq (KHz) */␊ |
| 225 | ␊ |
| 226 | ␉unsigned int␉␉clock;␉␉/* Current clock (MHz) */␊ |
| 227 | ␉unsigned short␉␉power;␉␉/* Current voltage */␊ |
| 228 | ␊ |
| 229 | ␉struct mmc_request␉*mrq;␉␉/* Current request */␊ |
| 230 | ␉struct mmc_command␉*cmd;␉␉/* Current command */␊ |
| 231 | ␉struct mmc_data␉␉*data;␉␉/* Current data request */␊ |
| 232 | ␉unsigned int␉␉data_early:1;␉/* Data finished before cmd */␊ |
| 233 | ␊ |
| 234 | ␉struct sg_mapping_iter␉sg_miter;␉/* SG state for PIO */␊ |
| 235 | ␉unsigned int␉␉blocks;␉␉/* remaining PIO blocks */␊ |
| 236 | ␊ |
| 237 | ␉int␉␉␉sg_count;␉/* Mapped sg entries */␊ |
| 238 | ␊ |
| 239 | ␉u8␉␉␉*adma_desc;␉/* ADMA descriptor table */␊ |
| 240 | ␉u8␉␉␉*align_buffer;␉/* Bounce buffer */␊ |
| 241 | ␊ |
| 242 | ␉dma_addr_t␉␉adma_addr;␉/* Mapped ADMA descr. table */␊ |
| 243 | ␉dma_addr_t␉␉align_addr;␉/* Mapped bounce buffer */␊ |
| 244 | ␊ |
| 245 | ␉struct tasklet_struct␉card_tasklet;␉/* Tasklet structures */␊ |
| 246 | ␉struct tasklet_struct␉finish_tasklet;␊ |
| 247 | ␊ |
| 248 | ␉struct timer_list␉timer;␉␉/* Timer for timeouts */␊ |
| 249 | ␊ |
| 250 | ␉unsigned long␉␉private[0] ____cacheline_aligned;␊ |
| 251 | };␊ |
| 252 | ␊ |
| 253 | ␊ |
| 254 | struct sdhci_ops {␊ |
| 255 | ␉int␉␉(*enable_dma)(struct sdhci_host *host);␊ |
| 256 | };␊ |
| 257 | ␊ |
| 258 | ␊ |
| 259 | extern struct sdhci_host *sdhci_alloc_host(struct device *dev,␊ |
| 260 | ␉size_t priv_size);␊ |
| 261 | extern void sdhci_free_host(struct sdhci_host *host);␊ |
| 262 | ␊ |
| 263 | static inline void *sdhci_priv(struct sdhci_host *host)␊ |
| 264 | {␊ |
| 265 | ␉return (void *)host->private;␊ |
| 266 | }␊ |
| 267 | ␊ |
| 268 | extern int sdhci_add_host(struct sdhci_host *host);␊ |
| 269 | extern void sdhci_remove_host(struct sdhci_host *host, int dead);␊ |
| 270 | ␊ |
| 271 | #ifdef CONFIG_PM␊ |
| 272 | extern int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state);␊ |
| 273 | extern int sdhci_resume_host(struct sdhci_host *host);␊ |
| 274 | #endif␊ |
| 275 | ␊ |
| 276 | #endif /* LINUX_STRUCTURE */␊ |
| 277 | ␊ |
| 278 | #endif /* SDHCI_H */␊ |
| 279 | |
