/* * HDA injector / Audio Enabler * * Copyright (C) 2012 Chameleon Team * Edit by Fabio (ErmaC) * * HDA injector is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * HDA injector is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * Alternatively you can choose to comply with APSL * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * ****************************************************************************** * http://www.leidinger.net/FreeBSD/dox/dev_sound/html/df/d54/hdac_8c_source.html * * Copyright (c) 2006 Stephane E. Potvin * Copyright (c) 2006 Ariff Abdullah * Copyright (c) 2008-2012 Alexander Motin * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * Intel High Definition Audio (Controller) driver for FreeBSD. * ******************************************************************************/ #ifndef __LIBSAIO_HDA_H #define __LIBSAIO_HDA_H static char *get_hda_controller_name( uint16_t controller_device_id, uint16_t controller_vendor_id ); static char *get_hda_codec_name( uint16_t codec_vendor_id, uint16_t codec_device_id, uint8_t codec_revision_id, uint8_t codec_stepping_id ); bool setup_hda_devprop( pci_dt_t *hda_dev ); static int immediate_command(uint32_t command, uint32_t* response); static uint32_t get_parameter(uint8_t codec_id, uint8_t node_id, uint8_t parameter_id); static int getHDABar(uint32_t pci_addr, uint32_t* bar_phys_addr); void probe_hda_bus(uint32_t pci_addr); struct hda_controller_devices; typedef struct { uint32_t model; char *desc; // char quirks_on; // char quirks_off; } hda_controller_devices; struct hdacc_codecs; typedef struct { uint32_t id; uint32_t rev; const char *name; } hdacc_codecs; /**************************************************************************** * Miscellanious defines ****************************************************************************/ /* Controller models */ #define HDA_MODEL_CONSTRUCT(vendor, model) (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) /* Intel */ #define INTEL_VENDORID PCI_VENDOR_ID_INTEL #define HDA_INTEL_OAK HDA_MODEL_CONSTRUCT(INTEL, 0x080a) /* Oaktrail */ #define HDA_INTEL_BAY HDA_MODEL_CONSTRUCT(INTEL, 0x0f04) /* BayTrail */ #define HDA_INTEL_HSW1 HDA_MODEL_CONSTRUCT(INTEL, 0x0a0c) /* Haswell */ #define HDA_INTEL_HSW2 HDA_MODEL_CONSTRUCT(INTEL, 0x0c0c) /* Haswell */ #define HDA_INTEL_HSW3 HDA_MODEL_CONSTRUCT(INTEL, 0x0d0c) /* Haswell */ #define HDA_INTEL_BDW HDA_MODEL_CONSTRUCT(INTEL, 0x160c) /* Broadwell */ #define HDA_INTEL_BROXTON_T HDA_MODEL_CONSTRUCT(INTEL, 0x1a98) /* Broxton-T */ #define HDA_INTEL_CPT HDA_MODEL_CONSTRUCT(INTEL, 0x1c20) /* CPT */ #define HDA_INTEL_PATSBURG HDA_MODEL_CONSTRUCT(INTEL, 0x1d20) /* PBG */ #define HDA_INTEL_PPT1 HDA_MODEL_CONSTRUCT(INTEL, 0x1e20) /* Panther Point */ #define HDA_INTEL_BRASWELL HDA_MODEL_CONSTRUCT(INTEL, 0x2284) /* Braswell */ #define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) /* ICH6 */ #define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) /* ESB2 */ #define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) /* ICH7 */ #define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) /* ICH8 */ #define HDA_INTEL_82801I HDA_MODEL_CONSTRUCT(INTEL, 0x293e) /* ICH9 */ #define HDA_INTEL_ICH9 HDA_MODEL_CONSTRUCT(INTEL, 0x293f) /* ICH9 */ #define HDA_INTEL_82801JI HDA_MODEL_CONSTRUCT(INTEL, 0x3a3e) /* ICH10 */ #define HDA_INTEL_82801JD HDA_MODEL_CONSTRUCT(INTEL, 0x3a6e) /* ICH10 */ #define HDA_INTEL_PCH HDA_MODEL_CONSTRUCT(INTEL, 0x3b56) /* 5 Series/3400 */ #define HDA_INTEL_PCH2 HDA_MODEL_CONSTRUCT(INTEL, 0x3b57) /* 5 Series/3400 */ #define HDA_INTEL_BROXTON_P HDA_MODEL_CONSTRUCT(INTEL, 0x5a98) /* Broxton-P(Apollolake) */ #define HDA_INTEL_MACBOOKPRO92 HDA_MODEL_CONSTRUCT(INTEL, 0x7270) #define HDA_INTEL_SCH HDA_MODEL_CONSTRUCT(INTEL, 0x811b) /* Poulsbo */ #define HDA_INTEL_LPT1 HDA_MODEL_CONSTRUCT(INTEL, 0x8c20) /* Lynx Point */ #define HDA_INTEL_LPT2 HDA_MODEL_CONSTRUCT(INTEL, 0x8c21) /* Lynx Point */ #define HDA_INTEL_WCPT HDA_MODEL_CONSTRUCT(INTEL, 0x8ca0) /* 9 Series */ #define HDA_INTEL_WELLS1 HDA_MODEL_CONSTRUCT(INTEL, 0x8d20) /* Wellsburg */ #define HDA_INTEL_WELLS2 HDA_MODEL_CONSTRUCT(INTEL, 0x8d21) /* Wellsburg */ #define HDA_INTEL_WCPTLP HDA_MODEL_CONSTRUCT(INTEL, 0x9ca0) /* Wildcat Point-LP */ #define HDA_INTEL_LPTLP1 HDA_MODEL_CONSTRUCT(INTEL, 0x9c20) /* Lynx Point-LP */ #define HDA_INTEL_LPTLP2 HDA_MODEL_CONSTRUCT(INTEL, 0x9c21) /* Lynx Point-LP */ #define HDA_INTEL_SRSPLP HDA_MODEL_CONSTRUCT(INTEL, 0x9d70) /* Sunrise Point-LP */ #define HDA_INTEL_KABYLAKE_LP HDA_MODEL_CONSTRUCT(INTEL, 0x9d71) /* Kabylake-LP */ #define HDA_INTEL_SRSP HDA_MODEL_CONSTRUCT(INTEL, 0xa170) /* Sunrise Point */ #define HDA_INTEL_KABYLAKE HDA_MODEL_CONSTRUCT(INTEL, 0xa171) /* Kabylake */ #define HDA_INTEL_LEWISBURG1 HDA_MODEL_CONSTRUCT(INTEL, 0xa1f0) /* Lewisburg */ #define HDA_INTEL_LEWISBURG2 HDA_MODEL_CONSTRUCT(INTEL, 0xa270) /* Lewisburg */ #define HDA_INTEL_UNPT HDA_MODEL_CONSTRUCT(INTEL, 0xa2f0) /* Kabylake-H */ #define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) /* Nvidia */ #define NVIDIA_VENDORID PCI_VENDOR_ID_NVIDIA #define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) #define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) #define HDA_NVIDIA_MCP61_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) #define HDA_NVIDIA_MCP61_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) #define HDA_NVIDIA_MCP65_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) #define HDA_NVIDIA_MCP65_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) #define HDA_NVIDIA_MCP67_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055c) #define HDA_NVIDIA_MCP67_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055d) #define HDA_NVIDIA_MCP78_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0774) #define HDA_NVIDIA_MCP78_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0775) #define HDA_NVIDIA_MCP78_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0776) #define HDA_NVIDIA_MCP78_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0777) #define HDA_NVIDIA_MCP73_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x07fc) #define HDA_NVIDIA_MCP73_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x07fd) #define HDA_NVIDIA_MCP79_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac0) #define HDA_NVIDIA_MCP79_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac1) #define HDA_NVIDIA_MCP79_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac2) #define HDA_NVIDIA_MCP79_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac3) #define HDA_NVIDIA_0BE2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0be2) #define HDA_NVIDIA_0BE3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0be3) // [GeForce 210] HDAcodec #define HDA_NVIDIA_0BE4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0be4) // [GeForge GT 240] HDACodec 10de000d (0d00de10) #define HDA_NVIDIA_GT100 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0be5) // [GeForge GTX 470] HDACodec 10de0010 (1000de10) #define HDA_NVIDIA_GT106 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0be9) #define HDA_NVIDIA_GT108 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0bea) // HDACodec #define HDA_NVIDIA_GT104 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0beb) #define HDA_NVIDIA_GT116 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0bee) #define HDA_NVIDIA_MCP89_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d94) #define HDA_NVIDIA_MCP89_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d95) #define HDA_NVIDIA_MCP89_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d96) #define HDA_NVIDIA_MCP89_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d97) #define HDA_NVIDIA_GF119 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0e08) #define HDA_NVIDIA_GF110_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0e09) #define HDA_NVIDIA_GF110_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0e0c) // HDACodec de101600 (10de0016), Controller Binary de100c0e x2 #define HDA_NVIDIA_GK104 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0e0a) #define HDA_NVIDIA_GK106 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0e0b) #define HDA_NVIDIA_GK110 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0e1a) #define HDA_NVIDIA_GK107 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0e1b) // HDACodec de104200 (10de0042) #define HDA_NVIDIA_GP104_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x10f0) // GeForce GTX 1070 #define HDA_NVIDIA_GM204_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0fbb) // GeForce GTX 970 #define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) /* ATI */ #define ATI_VENDORID PCI_VENDOR_ID_ATI //#define HDA_ATI_0002 HDA_MODEL_CONSTRUCT(ATI, 0x0002) /* ATI HDMI */ //#define HDA_ATI_1308 HDA_MODEL_CONSTRUCT(ATI, 0x1308) /* ATI HDMI */ //#define HDA_ATI_177A HDA_MODEL_CONSTRUCT(ATI, 0x157a) /* ATI HDMI */ //#define HDA_ATI_15B3 HDA_MODEL_CONSTRUCT(ATI, 0x15b3) /* ATI HDMI */ #define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) /* ATI SB 450/600/700/800/900 */ #define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) /* ATI SB 450/600/700/800/900 */ #define HDA_ATI_HUDSON HDA_MODEL_CONSTRUCT(ATI, 0x780d) /* PCI_DEVICE(0x1022, 0x780d) */ #define HDA_ATI_RS600 HDA_MODEL_CONSTRUCT(ATI, 0x793b) /* ATI HDMI */ #define HDA_ATI_RS690 HDA_MODEL_CONSTRUCT(ATI, 0x7919) /* ATI HDMI */ #define HDA_ATI_RS780 HDA_MODEL_CONSTRUCT(ATI, 0x960f) #define HDA_ATI_RS880 HDA_MODEL_CONSTRUCT(ATI, 0x970f) /* ATI HDMI */ //#define HDA_ATI_9840 HDA_MODEL_CONSTRUCT(ATI, 0x9840) /* ATI HDMI */ #define HDA_ATI_TRINITY HDA_MODEL_CONSTRUCT(ATI, 0x9902) /* ATI HDMI */ #define HDA_ATI_R600 HDA_MODEL_CONSTRUCT(ATI, 0xaa00) /* ATI HDMI */ #define HDA_ATI_RV630 HDA_MODEL_CONSTRUCT(ATI, 0xaa08) /* ATI HDMI */ #define HDA_ATI_RV610 HDA_MODEL_CONSTRUCT(ATI, 0xaa10) /* ATI HDMI */ #define HDA_ATI_RV670 HDA_MODEL_CONSTRUCT(ATI, 0xaa18) /* ATI HDMI */ #define HDA_ATI_RV635 HDA_MODEL_CONSTRUCT(ATI, 0xaa20) /* ATI HDMI */ #define HDA_ATI_RV620 HDA_MODEL_CONSTRUCT(ATI, 0xaa28) /* ATI HDMI */ #define HDA_ATI_RV770 HDA_MODEL_CONSTRUCT(ATI, 0xaa30) /* ATI HDMI */ #define HDA_ATI_RV730 HDA_MODEL_CONSTRUCT(ATI, 0xaa38) /* ATI HDMI */ #define HDA_ATI_RV710 HDA_MODEL_CONSTRUCT(ATI, 0xaa40) /* ATI HDMI */ #define HDA_ATI_RV740 HDA_MODEL_CONSTRUCT(ATI, 0xaa48) /* ATI HDMI */ #define HDA_ATI_RV870 HDA_MODEL_CONSTRUCT(ATI, 0xaa50) /* ATI HDMI */ #define HDA_ATI_RV840 HDA_MODEL_CONSTRUCT(ATI, 0xaa58) /* ATI HDMI */ #define HDA_ATI_RV830 HDA_MODEL_CONSTRUCT(ATI, 0xaa60) /* ATI HDMI */ #define HDA_ATI_RV810 HDA_MODEL_CONSTRUCT(ATI, 0xaa68) /* ATI HDMI */ #define HDA_ATI_RV970 HDA_MODEL_CONSTRUCT(ATI, 0xaa80) /* ATI HDMI */ #define HDA_ATI_RV940 HDA_MODEL_CONSTRUCT(ATI, 0xaa88) /* ATI HDMI */ #define HDA_ATI_RV930 HDA_MODEL_CONSTRUCT(ATI, 0xaa90) /* ATI HDMI */ #define HDA_ATI_RV910 HDA_MODEL_CONSTRUCT(ATI, 0xaa98) /* ATI HDMI */ #define HDA_ATI_R1000 HDA_MODEL_CONSTRUCT(ATI, 0xaaa0) /* ATI HDMI */ #define HDA_ATI_SI HDA_MODEL_CONSTRUCT(ATI, 0xaaa8) /* ATI HDMI */ #define HDA_ATI_VERDE HDA_MODEL_CONSTRUCT(ATI, 0xaab0) /* ATI HDMI */ //#define HDA_ATI_AAC0 HDA_MODEL_CONSTRUCT(ATI, 0xaac0) /* ATI HDMI */ //#define HDA_ATI_AAC8 HDA_MODEL_CONSTRUCT(ATI, 0xaac8) /* ATI HDMI */ //#define HDA_ATI_AAD8 HDA_MODEL_CONSTRUCT(ATI, 0xaad8) /* ATI HDMI */ //#define HDA_ATI_AAE8 HDA_MODEL_CONSTRUCT(ATI, 0xaae8) /* ATI HDMI */ //#define HDA_ATI_AAE0 HDA_MODEL_CONSTRUCT(ATI, 0xaae0) /* ATI HDMI */ //#define HDA_ATI_AAF0 HDA_MODEL_CONSTRUCT(ATI, 0xaaf0) /* ATI HDMI */ #define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) /* RDC */ #define RDC_VENDORID 0x17f3 #define HDA_RDC_M3010 HDA_MODEL_CONSTRUCT(RDC, 0x3010) /* Vortex86MX */ /* VIA */ #define VIA_VENDORID 0x1106 #define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) /* VIA VT8251/VT8237A */ //#define HDA_VIA_VT71XX HDA_MODEL_CONSTRUCT(VIA, 0x9170) /* VIA GFX VT7122/VX900 */ //#define HDA_VIA_VT61XX HDA_MODEL_CONSTRUCT(VIA, 0x9140) /* VIA GFX VT6122/VX11 */ #define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) /* SiS */ #define SIS_VENDORID 0x1039 #define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) /* SIS966 */ #define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) /* ULI */ #define ULI_VENDORID 0x10b9 #define HDA_ULI_M5461 HDA_MODEL_CONSTRUCT(ULI, 0x5461) /* ULI M5461 */ #define HDA_ULI_ALL HDA_MODEL_CONSTRUCT(ULI, 0xffff) /* Teradici */ //{ PCI_DEVICE(0x6549, 0x1200), //{ PCI_DEVICE(0x6549, 0x2200} /* CTHDA chips */ //{ PCI_DEVICE(0x1102, 0x0010), //{ PCI_DEVICE(0x1102, 0x0012), /* this entry seems still valid -- i.e. without emu20kx chip */ //{ PCI_DEVICE(0x1102, 0x0009 /* CM8888 */ //{ PCI_DEVICE(0x13f6, 0x5011), /* VMware HDAudio */ //{ PCI_DEVICE(0x15ad, 0x1977), //#define HDEF_PATH "PciRoot(0x0)/Pci(0x1b,0x0)" //#define PINCONF_LEN ( sizeof(default_PinConfiguration) / sizeof(uint8_t) ) #define HDA0_LEN ( sizeof(default_HDEF_layout_id) / sizeof(uint8_t) ) #define HDA1_LEN ( sizeof(default_HDAU_layout_id) / sizeof(uint8_t) ) /* =================== C O D E C I N F O R M A T I O N ===================== */ #define HDA_CODEC_CONSTRUCT(vendor, id) (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) /* Cirrus Logic */ #define CIRRUSLOGIC_VENDORID 0x1013 #define HDA_CODEC_CS4206 HDA_CODEC_CONSTRUCT(CIRRUSLOGIC, 0x4206) #define HDA_CODEC_CS4207 HDA_CODEC_CONSTRUCT(CIRRUSLOGIC, 0x4207) #define HDA_CODEC_CS4208 HDA_CODEC_CONSTRUCT(CIRRUSLOGIC, 0x4208) #define HDA_CODEC_CS4210 HDA_CODEC_CONSTRUCT(CIRRUSLOGIC, 0x4210) #define HDA_CODEC_CS4213 HDA_CODEC_CONSTRUCT(CIRRUSLOGIC, 0x4213) #define HDA_CODEC_CSXXXX HDA_CODEC_CONSTRUCT(CIRRUSLOGIC, 0xffff) /* Realtek */ #define REALTEK_VENDORID PCI_VENDOR_ID_REALTEK #define HDA_CODEC_ALC221 HDA_CODEC_CONSTRUCT(REALTEK, 0x0221) #define HDA_CODEC_ALC231 HDA_CODEC_CONSTRUCT(REALTEK, 0x0231) #define HDA_CODEC_ALC233 HDA_CODEC_CONSTRUCT(REALTEK, 0x0233) #define HDA_CODEC_ALC235 HDA_CODEC_CONSTRUCT(REALTEK, 0x0235) #define HDA_CODEC_ALC255 HDA_CODEC_CONSTRUCT(REALTEK, 0x0255) #define HDA_CODEC_ALC256 HDA_CODEC_CONSTRUCT(REALTEK, 0x0256) #define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) #define HDA_CODEC_ALC262 HDA_CODEC_CONSTRUCT(REALTEK, 0x0262) #define HDA_CODEC_ALC267 HDA_CODEC_CONSTRUCT(REALTEK, 0x0267) #define HDA_CODEC_ALC268 HDA_CODEC_CONSTRUCT(REALTEK, 0x0268) #define HDA_CODEC_ALC269 HDA_CODEC_CONSTRUCT(REALTEK, 0x0269) #define HDA_CODEC_ALC270 HDA_CODEC_CONSTRUCT(REALTEK, 0x0270) #define HDA_CODEC_ALC272 HDA_CODEC_CONSTRUCT(REALTEK, 0x0272) #define HDA_CODEC_ALC273 HDA_CODEC_CONSTRUCT(REALTEK, 0x0273) #define HDA_CODEC_ALC275 HDA_CODEC_CONSTRUCT(REALTEK, 0x0275) #define HDA_CODEC_ALC276 HDA_CODEC_CONSTRUCT(REALTEK, 0x0276) #define HDA_CODEC_ALC280 HDA_CODEC_CONSTRUCT(REALTEK, 0x0280) #define HDA_CODEC_ALC282 HDA_CODEC_CONSTRUCT(REALTEK, 0x0282) #define HDA_CODEC_ALC283 HDA_CODEC_CONSTRUCT(REALTEK, 0x0283) #define HDA_CODEC_ALC284 HDA_CODEC_CONSTRUCT(REALTEK, 0x0284) #define HDA_CODEC_ALC285 HDA_CODEC_CONSTRUCT(REALTEK, 0x0285) #define HDA_CODEC_ALC286 HDA_CODEC_CONSTRUCT(REALTEK, 0x0286) #define HDA_CODEC_ALC288 HDA_CODEC_CONSTRUCT(REALTEK, 0x0288) #define HDA_CODEC_ALC290 HDA_CODEC_CONSTRUCT(REALTEK, 0x0290) #define HDA_CODEC_ALC292 HDA_CODEC_CONSTRUCT(REALTEK, 0x0292) #define HDA_CODEC_ALC293 HDA_CODEC_CONSTRUCT(REALTEK, 0x0293) #define HDA_CODEC_ALC298 HDA_CODEC_CONSTRUCT(REALTEK, 0x0298) #define HDA_CODEC_ALC660 HDA_CODEC_CONSTRUCT(REALTEK, 0x0660) #define HDA_CODEC_ALC662 HDA_CODEC_CONSTRUCT(REALTEK, 0x0662) #define HDA_CODEC_ALC663 HDA_CODEC_CONSTRUCT(REALTEK, 0x0663) #define HDA_CODEC_ALC665 HDA_CODEC_CONSTRUCT(REALTEK, 0x0665) #define HDA_CODEC_ALC667 HDA_CODEC_CONSTRUCT(REALTEK, 0x0667) #define HDA_CODEC_ALC668 HDA_CODEC_CONSTRUCT(REALTEK, 0x0668) #define HDA_CODEC_ALC670 HDA_CODEC_CONSTRUCT(REALTEK, 0x0670) #define HDA_CODEC_ALC671 HDA_CODEC_CONSTRUCT(REALTEK, 0x0671) #define HDA_CODEC_ALC680 HDA_CODEC_CONSTRUCT(REALTEK, 0x0680) #define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) #define HDA_CODEC_ALC861VD HDA_CODEC_CONSTRUCT(REALTEK, 0x0862) #define HDA_CODEC_ALC867 HDA_CODEC_CONSTRUCT(REALTEK, 0x0867) #define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) #define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) #define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) #define HDA_CODEC_ALC885 HDA_CODEC_CONSTRUCT(REALTEK, 0x0885) #define HDA_CODEC_ALC886 HDA_CODEC_CONSTRUCT(REALTEK, 0x0886) #define HDA_CODEC_ALC887 HDA_CODEC_CONSTRUCT(REALTEK, 0x0887) #define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888) #define HDA_CODEC_ALC889 HDA_CODEC_CONSTRUCT(REALTEK, 0x0889) #define HDA_CODEC_ALC892 HDA_CODEC_CONSTRUCT(REALTEK, 0x0892) #define HDA_CODEC_ALC898 HDA_CODEC_CONSTRUCT(REALTEK, 0x0899) //#define HDA_CODEC_ALC898 HDA_CODEC_CONSTRUCT(REALTEK, 0x0898) //#define HDA_CODEC_ALC899 HDA_CODEC_CONSTRUCT(REALTEK, 0x0899) #define HDA_CODEC_ALC900 HDA_CODEC_CONSTRUCT(REALTEK, 0x0900) #define HDA_CODEC_ALCS1220A HDA_CODEC_CONSTRUCT(REALTEK, 0x1168) #define HDA_CODEC_ALC1220 HDA_CODEC_CONSTRUCT(REALTEK, 0x1220) #define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) /* Motorola */ #define MOTO_VENDORID PCI_VENDOR_ID_MOTOROLA #define HDA_CODEC_MOTOXXXX HDA_CODEC_CONSTRUCT(MOTO, 0xffff) /* Creative */ #define CREATIVE_VENDORID 0x1102 #define HDA_CODEC_XFIEA HDA_CODEC_CONSTRUCT(CREATIVE, 0x000a) #define HDA_CODEC_XFIED HDA_CODEC_CONSTRUCT(CREATIVE, 0x000b) #define HDA_CODEC_SB0880 HDA_CODEC_CONSTRUCT(CREATIVE, 0x000d) #define HDA_CODEC_CA0132 HDA_CODEC_CONSTRUCT(CREATIVE, 0x0011) #define HDA_CODEC_CAXXXX HDA_CODEC_CONSTRUCT(CREATIVE, 0xffff) /* Analog Devices */ #define ANALOGDEVICES_VENDORID 0x11d4 #define HDA_CODEC_AD1884A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x184a) #define HDA_CODEC_AD1882 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1882) #define HDA_CODEC_AD1883 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1883) #define HDA_CODEC_AD1884 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1884) #define HDA_CODEC_AD1984A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x194a) #define HDA_CODEC_AD1984B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x194b) #define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1981) #define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1983) #define HDA_CODEC_AD1984 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1984) #define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1986) #define HDA_CODEC_AD1987 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1987) #define HDA_CODEC_AD1988 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1988) #define HDA_CODEC_AD1988B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x198b) #define HDA_CODEC_AD1882A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x882a) #define HDA_CODEC_AD1989A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x989a) #define HDA_CODEC_AD1989B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x989b) #define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0xffff) /* CMedia */ #define CMEDIA_VENDORID 0x13f6 #define HDA_CODEC_CMI8880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x8880) #define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x9880) #define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) /* CMedia */ #define CMEDIA2_VENDORID 0x434d #define HDA_CODEC_CMI98802 HDA_CODEC_CONSTRUCT(CMEDIA2, 0x4980) #define HDA_CODEC_CMIXXXX2 HDA_CODEC_CONSTRUCT(CMEDIA2, 0xffff) /* Sigmatel */ #define SIGMATEL_VENDORID 0x8384 #define HDA_CODEC_STAC9230X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7612) #define HDA_CODEC_STAC9230D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7613) #define HDA_CODEC_STAC9229X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7614) #define HDA_CODEC_STAC9229D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7615) #define HDA_CODEC_STAC9228X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7616) #define HDA_CODEC_STAC9228D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7617) #define HDA_CODEC_STAC9227X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618) #define HDA_CODEC_STAC9227D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7619) #define HDA_CODEC_STAC9274 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7620) #define HDA_CODEC_STAC9274D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7621) #define HDA_CODEC_STAC9273X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7622) #define HDA_CODEC_STAC9273D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7623) #define HDA_CODEC_STAC9272X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7624) #define HDA_CODEC_STAC9272D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7625) #define HDA_CODEC_STAC9271X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7626) #define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627) #define HDA_CODEC_STAC9274X5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7628) #define HDA_CODEC_STAC9274D5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7629) #define HDA_CODEC_STAC9202 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7632) #define HDA_CODEC_STAC9202D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7633) #define HDA_CODEC_STAC9250 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7634) #define HDA_CODEC_STAC9250D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7635) #define HDA_CODEC_STAC9251 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7636) #define HDA_CODEC_STAC9250D_1 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7637) #define HDA_CODEC_IDT92HD700X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7638) #define HDA_CODEC_IDT92HD700D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7639) #define HDA_CODEC_IDT92HD206X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7645) #define HDA_CODEC_IDT92HD206D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7646) #define HDA_CODEC_CXD9872RDK HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7661) #define HDA_CODEC_STAC9872AK HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7662) #define HDA_CODEC_CXD9872AKD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7664) #define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) #define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) #define HDA_CODEC_STAC9221_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7682) #define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) #define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) #define HDA_CODEC_STAC9200D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7691) #define HDA_CODEC_IDT92HD005 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7698) #define HDA_CODEC_IDT92HD005D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7699) #define HDA_CODEC_STAC9205X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a0) #define HDA_CODEC_STAC9205D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a1) #define HDA_CODEC_STAC9204X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a2) #define HDA_CODEC_STAC9204D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a3) #define HDA_CODEC_STAC9255 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a4) #define HDA_CODEC_STAC9255D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a5) #define HDA_CODEC_STAC9254 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a6) #define HDA_CODEC_STAC9254D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a7) #define HDA_CODEC_STAC9220_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7880) #define HDA_CODEC_STAC9220_A1 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7882) #define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) /* IDT */ #define IDT_VENDORID 0x111d #define HDA_CODEC_IDT92HD75BX HDA_CODEC_CONSTRUCT(IDT, 0x7603) #define HDA_CODEC_IDT92HD83C1X HDA_CODEC_CONSTRUCT(IDT, 0x7604) #define HDA_CODEC_IDT92HD81B1X HDA_CODEC_CONSTRUCT(IDT, 0x7605) #define HDA_CODEC_IDT92HD75B3 HDA_CODEC_CONSTRUCT(IDT, 0x7608) #define HDA_CODEC_IDT92HD88B3 HDA_CODEC_CONSTRUCT(IDT, 0x7666) #define HDA_CODEC_IDT92HD88B1 HDA_CODEC_CONSTRUCT(IDT, 0x7667) #define HDA_CODEC_IDT92HD88B2 HDA_CODEC_CONSTRUCT(IDT, 0x7668) #define HDA_CODEC_IDT92HD88B4 HDA_CODEC_CONSTRUCT(IDT, 0x7669) #define HDA_CODEC_IDT92HD73D1 HDA_CODEC_CONSTRUCT(IDT, 0x7674) #define HDA_CODEC_IDT92HD73C1 HDA_CODEC_CONSTRUCT(IDT, 0x7675) #define HDA_CODEC_IDT92HD73E1 HDA_CODEC_CONSTRUCT(IDT, 0x7676) #define HDA_CODEC_IDT92HD95 HDA_CODEC_CONSTRUCT(IDT, 0x7695) #define HDA_CODEC_IDT92HD71B8 HDA_CODEC_CONSTRUCT(IDT, 0x76b0) #define HDA_CODEC_IDT92HD71B8_2 HDA_CODEC_CONSTRUCT(IDT, 0x76b1) #define HDA_CODEC_IDT92HD71B7 HDA_CODEC_CONSTRUCT(IDT, 0x76b2) #define HDA_CODEC_IDT92HD71B7_2 HDA_CODEC_CONSTRUCT(IDT, 0x76b3) #define HDA_CODEC_IDT92HD71B6 HDA_CODEC_CONSTRUCT(IDT, 0x76b4) #define HDA_CODEC_IDT92HD71B6_2 HDA_CODEC_CONSTRUCT(IDT, 0x76b5) #define HDA_CODEC_IDT92HD71B5 HDA_CODEC_CONSTRUCT(IDT, 0x76b6) #define HDA_CODEC_IDT92HD71B5_2 HDA_CODEC_CONSTRUCT(IDT, 0x76b7) #define HDA_CODEC_IDT92HD89C3 HDA_CODEC_CONSTRUCT(IDT, 0x76c0) #define HDA_CODEC_IDT92HD89C2 HDA_CODEC_CONSTRUCT(IDT, 0x76c1) #define HDA_CODEC_IDT92HD89C1 HDA_CODEC_CONSTRUCT(IDT, 0x76c2) #define HDA_CODEC_IDT92HD89B3 HDA_CODEC_CONSTRUCT(IDT, 0x76c3) #define HDA_CODEC_IDT92HD89B2 HDA_CODEC_CONSTRUCT(IDT, 0x76c4) #define HDA_CODEC_IDT92HD89B1 HDA_CODEC_CONSTRUCT(IDT, 0x76c5) #define HDA_CODEC_IDT92HD89E3 HDA_CODEC_CONSTRUCT(IDT, 0x76c6) #define HDA_CODEC_IDT92HD89E2 HDA_CODEC_CONSTRUCT(IDT, 0x76c7) #define HDA_CODEC_IDT92HD89E1 HDA_CODEC_CONSTRUCT(IDT, 0x76c8) #define HDA_CODEC_IDT92HD89D3 HDA_CODEC_CONSTRUCT(IDT, 0x76c9) #define HDA_CODEC_IDT92HD89D2 HDA_CODEC_CONSTRUCT(IDT, 0x76ca) #define HDA_CODEC_IDT92HD89D1 HDA_CODEC_CONSTRUCT(IDT, 0x76cb) #define HDA_CODEC_IDT92HD89F3 HDA_CODEC_CONSTRUCT(IDT, 0x76cc) #define HDA_CODEC_IDT92HD89F2 HDA_CODEC_CONSTRUCT(IDT, 0x76cd) #define HDA_CODEC_IDT92HD89F1 HDA_CODEC_CONSTRUCT(IDT, 0x76ce) #define HDA_CODEC_IDT92HD87B1_3 HDA_CODEC_CONSTRUCT(IDT, 0x76d1) #define HDA_CODEC_IDT92HD83C1C HDA_CODEC_CONSTRUCT(IDT, 0x76d4) #define HDA_CODEC_IDT92HD81B1C HDA_CODEC_CONSTRUCT(IDT, 0x76d5) #define HDA_CODEC_IDT92HD87B2_4 HDA_CODEC_CONSTRUCT(IDT, 0x76d9) #define HDA_CODEC_IDT92HD93BXX HDA_CODEC_CONSTRUCT(IDT, 0x76df) #define HDA_CODEC_IDT92HD91BXX HDA_CODEC_CONSTRUCT(IDT, 0x76e0) #define HDA_CODEC_IDT92HD98BXX HDA_CODEC_CONSTRUCT(IDT, 0x76e3) #define HDA_CODEC_IDT92HD99BXX HDA_CODEC_CONSTRUCT(IDT, 0x76e5) #define HDA_CODEC_IDT92HD90BXX HDA_CODEC_CONSTRUCT(IDT, 0x76e7) #define HDA_CODEC_IDT92HD66B1X5 HDA_CODEC_CONSTRUCT(IDT, 0x76e8) #define HDA_CODEC_IDT92HD66B2X5 HDA_CODEC_CONSTRUCT(IDT, 0x76e9) #define HDA_CODEC_IDT92HD66B3X5 HDA_CODEC_CONSTRUCT(IDT, 0x76ea) #define HDA_CODEC_IDT92HD66C1X5 HDA_CODEC_CONSTRUCT(IDT, 0x76eb) #define HDA_CODEC_IDT92HD66C2X5 HDA_CODEC_CONSTRUCT(IDT, 0x76ec) #define HDA_CODEC_IDT92HD66C3X5 HDA_CODEC_CONSTRUCT(IDT, 0x76ed) #define HDA_CODEC_IDT92HD66B1X3 HDA_CODEC_CONSTRUCT(IDT, 0x76ee) #define HDA_CODEC_IDT92HD66B2X3 HDA_CODEC_CONSTRUCT(IDT, 0x76ef) #define HDA_CODEC_IDT92HD66B3X3 HDA_CODEC_CONSTRUCT(IDT, 0x76f0) #define HDA_CODEC_IDT92HD66C1X3 HDA_CODEC_CONSTRUCT(IDT, 0x76f1) #define HDA_CODEC_IDT92HD66C2X3 HDA_CODEC_CONSTRUCT(IDT, 0x76f2) #define HDA_CODEC_IDT92HD66C3_65 HDA_CODEC_CONSTRUCT(IDT, 0x76f3) #define HDA_CODEC_IDTXXXX HDA_CODEC_CONSTRUCT(IDT, 0xffff) /* Silicon Image */ #define SII_VENDORID 0x1095 #define HDA_CODEC_SII1390 HDA_CODEC_CONSTRUCT(SII, 0x1390) #define HDA_CODEC_SII1392 HDA_CODEC_CONSTRUCT(SII, 0x1392) #define HDA_CODEC_SIIXXXX HDA_CODEC_CONSTRUCT(SII, 0xffff) /* LSI - Lucent/Agere */ #define AGERE_VENDORID 0x11c1 #define HDA_CODEC_AGEREXXXX HDA_CODEC_CONSTRUCT(AGERE, 0xffff) /* Conexant */ #define CONEXANT_VENDORID 0x14f1 #define HDA_CODEC_CX20549 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) #define HDA_CODEC_CX20551 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) #define HDA_CODEC_CX20561 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5051) #define HDA_CODEC_CX20582 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5066) #define HDA_CODEC_CX20583 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5067) #define HDA_CODEC_CX20584 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5068) #define HDA_CODEC_CX20585 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5069) #define HDA_CODEC_CX20588 HDA_CODEC_CONSTRUCT(CONEXANT, 0x506c) #define HDA_CODEC_CX20590 HDA_CODEC_CONSTRUCT(CONEXANT, 0x506e) #define HDA_CODEC_CX20631 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5097) #define HDA_CODEC_CX20632 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5098) #define HDA_CODEC_CX20641 HDA_CODEC_CONSTRUCT(CONEXANT, 0x50a1) #define HDA_CODEC_CX20642 HDA_CODEC_CONSTRUCT(CONEXANT, 0x50a2) #define HDA_CODEC_CX20651 HDA_CODEC_CONSTRUCT(CONEXANT, 0x50ab) #define HDA_CODEC_CX20652 HDA_CODEC_CONSTRUCT(CONEXANT, 0x50ac) #define HDA_CODEC_CX20664 HDA_CODEC_CONSTRUCT(CONEXANT, 0x50b8) #define HDA_CODEC_CX20665 HDA_CODEC_CONSTRUCT(CONEXANT, 0x50b9) #define HDA_CODEC_CX20751 HDA_CODEC_CONSTRUCT(CONEXANT, 0x510f) #define HDA_CODEC_CX20751_2 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5110) #define HDA_CODEC_CX20751_4 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5111) #define HDA_CODEC_CX20755 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5113) #define HDA_CODEC_CX20756 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5114) #define HDA_CODEC_CX20757 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5115) #define HDA_CODEC_CX20952 HDA_CODEC_CONSTRUCT(CONEXANT, 0x51d7) #define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) /* VIA */ #define HDA_CODEC_VT1708_8 HDA_CODEC_CONSTRUCT(VIA, 0x1708) #define HDA_CODEC_VT1708_9 HDA_CODEC_CONSTRUCT(VIA, 0x1709) #define HDA_CODEC_VT1708_A HDA_CODEC_CONSTRUCT(VIA, 0x170a) #define HDA_CODEC_VT1708_B HDA_CODEC_CONSTRUCT(VIA, 0x170b) #define HDA_CODEC_VT1709_0 HDA_CODEC_CONSTRUCT(VIA, 0xe710) #define HDA_CODEC_VT1709_1 HDA_CODEC_CONSTRUCT(VIA, 0xe711) #define HDA_CODEC_VT1709_2 HDA_CODEC_CONSTRUCT(VIA, 0xe712) #define HDA_CODEC_VT1709_3 HDA_CODEC_CONSTRUCT(VIA, 0xe713) #define HDA_CODEC_VT1709_4 HDA_CODEC_CONSTRUCT(VIA, 0xe714) #define HDA_CODEC_VT1709_5 HDA_CODEC_CONSTRUCT(VIA, 0xe715) #define HDA_CODEC_VT1709_6 HDA_CODEC_CONSTRUCT(VIA, 0xe716) #define HDA_CODEC_VT1709_7 HDA_CODEC_CONSTRUCT(VIA, 0xe717) #define HDA_CODEC_VT1708B_0 HDA_CODEC_CONSTRUCT(VIA, 0xe720) #define HDA_CODEC_VT1708B_1 HDA_CODEC_CONSTRUCT(VIA, 0xe721) #define HDA_CODEC_VT1708B_2 HDA_CODEC_CONSTRUCT(VIA, 0xe722) #define HDA_CODEC_VT1708B_3 HDA_CODEC_CONSTRUCT(VIA, 0xe723) #define HDA_CODEC_VT1708B_4 HDA_CODEC_CONSTRUCT(VIA, 0xe724) #define HDA_CODEC_VT1708B_5 HDA_CODEC_CONSTRUCT(VIA, 0xe725) #define HDA_CODEC_VT1708B_6 HDA_CODEC_CONSTRUCT(VIA, 0xe726) #define HDA_CODEC_VT1708B_7 HDA_CODEC_CONSTRUCT(VIA, 0xe727) #define HDA_CODEC_VT1708S_0 HDA_CODEC_CONSTRUCT(VIA, 0x0397) #define HDA_CODEC_VT1708S_1 HDA_CODEC_CONSTRUCT(VIA, 0x1397) #define HDA_CODEC_VT1708S_2 HDA_CODEC_CONSTRUCT(VIA, 0x2397) #define HDA_CODEC_VT1708S_3 HDA_CODEC_CONSTRUCT(VIA, 0x3397) #define HDA_CODEC_VT1708S_4 HDA_CODEC_CONSTRUCT(VIA, 0x4397) #define HDA_CODEC_VT1708S_5 HDA_CODEC_CONSTRUCT(VIA, 0x5397) #define HDA_CODEC_VT1708S_6 HDA_CODEC_CONSTRUCT(VIA, 0x6397) #define HDA_CODEC_VT1708S_7 HDA_CODEC_CONSTRUCT(VIA, 0x7397) #define HDA_CODEC_VT1702_0 HDA_CODEC_CONSTRUCT(VIA, 0x0398) #define HDA_CODEC_VT1702_1 HDA_CODEC_CONSTRUCT(VIA, 0x1398) #define HDA_CODEC_VT1702_2 HDA_CODEC_CONSTRUCT(VIA, 0x2398) #define HDA_CODEC_VT1702_3 HDA_CODEC_CONSTRUCT(VIA, 0x3398) #define HDA_CODEC_VT1702_4 HDA_CODEC_CONSTRUCT(VIA, 0x4398) #define HDA_CODEC_VT1702_5 HDA_CODEC_CONSTRUCT(VIA, 0x5398) #define HDA_CODEC_VT1702_6 HDA_CODEC_CONSTRUCT(VIA, 0x6398) #define HDA_CODEC_VT1702_7 HDA_CODEC_CONSTRUCT(VIA, 0x7398) #define HDA_CODEC_VT1716S_0 HDA_CODEC_CONSTRUCT(VIA, 0x0433) #define HDA_CODEC_VT1716S_1 HDA_CODEC_CONSTRUCT(VIA, 0xa721) #define HDA_CODEC_VT1718S_0 HDA_CODEC_CONSTRUCT(VIA, 0x0428) #define HDA_CODEC_VT1718S_1 HDA_CODEC_CONSTRUCT(VIA, 0x4428) #define HDA_CODEC_VT1802_0 HDA_CODEC_CONSTRUCT(VIA, 0x0446) #define HDA_CODEC_VT1802_1 HDA_CODEC_CONSTRUCT(VIA, 0x8446) #define HDA_CODEC_VT1812 HDA_CODEC_CONSTRUCT(VIA, 0x0448) #define HDA_CODEC_VT1818S HDA_CODEC_CONSTRUCT(VIA, 0x0440) #define HDA_CODEC_VT1828S HDA_CODEC_CONSTRUCT(VIA, 0x4441) #define HDA_CODEC_VT2002P_0 HDA_CODEC_CONSTRUCT(VIA, 0x0438) #define HDA_CODEC_VT2002P_1 HDA_CODEC_CONSTRUCT(VIA, 0x4438) #define HDA_CODEC_VT2020 HDA_CODEC_CONSTRUCT(VIA, 0x0441) #define HDA_CODEC_VTXXXX HDA_CODEC_CONSTRUCT(VIA, 0xffff) /* ATI */ #define HDA_CODEC_ATIRS600_1 HDA_CODEC_CONSTRUCT(ATI, 0x793c) #define HDA_CODEC_ATIRS600_2 HDA_CODEC_CONSTRUCT(ATI, 0x7919) #define HDA_CODEC_ATIRS690 HDA_CODEC_CONSTRUCT(ATI, 0x791a) #define HDA_CODEC_ATIR6XX HDA_CODEC_CONSTRUCT(ATI, 0xaa01) #define HDA_CODEC_ATIXXXX HDA_CODEC_CONSTRUCT(ATI, 0xffff) /* NVIDIA */ #define HDA_CODEC_NVIDIAMCP78 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0002) #define HDA_CODEC_NVIDIAMCP78_2 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0003) #define HDA_CODEC_NVIDIAMCP78_3 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0005) #define HDA_CODEC_NVIDIAMCP78_4 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0006) #define HDA_CODEC_NVIDIAMCP7A HDA_CODEC_CONSTRUCT(NVIDIA, 0x0007) #define HDA_CODEC_NVIDIAGT220 HDA_CODEC_CONSTRUCT(NVIDIA, 0x000a) #define HDA_CODEC_NVIDIAGT21X HDA_CODEC_CONSTRUCT(NVIDIA, 0x000b) #define HDA_CODEC_NVIDIAMCP89 HDA_CODEC_CONSTRUCT(NVIDIA, 0x000c) #define HDA_CODEC_NVIDIAGT240 HDA_CODEC_CONSTRUCT(NVIDIA, 0x000d) #define HDA_CODEC_NVIDIAGTX470 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0010) #define HDA_CODEC_NVIDIAGTS450 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0011) #define HDA_CODEC_NVIDIAGT440 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0014) #define HDA_CODEC_NVIDIAGTX550 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0015) #define HDA_CODEC_NVIDIAGTX570 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0018) #define HDA_CODEC_NVIDIAGT610 HDA_CODEC_CONSTRUCT(NVIDIA, 0x001c) #define HDA_CODEC_NVIDIAMCP67 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0067) #define HDA_CODEC_NVIDIAMCP73 HDA_CODEC_CONSTRUCT(NVIDIA, 0x8001) #define HDA_CODEC_NVIDIAXXXX HDA_CODEC_CONSTRUCT(NVIDIA, 0xffff) /* Chrontel */ #define CHRONTEL_VENDORID 0x17e8 #define HDA_CODEC_CHXXXX HDA_CODEC_CONSTRUCT(CHRONTEL, 0xffff) /* LG */ #define LG_VENDORID 0x1854 #define HDA_CODEC_LGXXXX HDA_CODEC_CONSTRUCT(LG, 0xffff) /* Wolfson Microelectronics */ #define WOLFSON_VENDORID 0x14ec #define HDA_CODEC_WMXXXX HDA_CODEC_CONSTRUCT(WOLFSON, 0xffff) /* QEMU */ #define QEMU_VENDORID 0x1af4 #define HDA_CODEC_QEMUXXXX HDA_CODEC_CONSTRUCT(QEMU, 0xffff) /* INTEL */ #define HDA_CODEC_INTELIP HDA_CODEC_CONSTRUCT(INTEL, 0x0054) #define HDA_CODEC_INTELBL HDA_CODEC_CONSTRUCT(INTEL, 0x2801) #define HDA_CODEC_INTELCA HDA_CODEC_CONSTRUCT(INTEL, 0x2802) #define HDA_CODEC_INTELEL HDA_CODEC_CONSTRUCT(INTEL, 0x2803) #define HDA_CODEC_INTELIP2 HDA_CODEC_CONSTRUCT(INTEL, 0x2804) #define HDA_CODEC_INTELCPT HDA_CODEC_CONSTRUCT(INTEL, 0x2805) #define HDA_CODEC_INTELPPT HDA_CODEC_CONSTRUCT(INTEL, 0x2806) // Panther Point HDMI #define HDA_CODEC_INTELLLP HDA_CODEC_CONSTRUCT(INTEL, 0x2807) // Haswell HDMI #define HDA_CODEC_INTELBRW HDA_CODEC_CONSTRUCT(INTEL, 0x2808) // Broadwell HDMI #define HDA_CODEC_INTELSKL HDA_CODEC_CONSTRUCT(INTEL, 0x2809) // Skylake HDMI #define HDA_CODEC_INTELBRO HDA_CODEC_CONSTRUCT(INTEL, 0x280a) // Broxton HDMI #define HDA_CODEC_INTELKAB HDA_CODEC_CONSTRUCT(INTEL, 0x280b) // Kabylake HDMI #define HDA_CODEC_INTELCDT HDA_CODEC_CONSTRUCT(INTEL, 0x2880) // CedarTrail HDMI #define HDA_CODEC_INTELVLV HDA_CODEC_CONSTRUCT(INTEL, 0x2882) // Valleyview2 HDMI #define HDA_CODEC_INTELBSW HDA_CODEC_CONSTRUCT(INTEL, 0x2883) // Braswell HDMI #define HDA_CODEC_INTELCL HDA_CODEC_CONSTRUCT(INTEL, 0x29fb) // Crestline HDMI #define HDA_CODEC_INTELXXXX HDA_CODEC_CONSTRUCT(INTEL, 0xffff) /**************************************************************************** * HDA Controller Register Set ****************************************************************************/ #define HDAC_GCAP 0x00 /* 2 - Global Capabilities*/ #define HDAC_VMIN 0x02 /* 1 - Minor Version */ #define HDAC_VMAJ 0x03 /* 1 - Major Version */ #define HDAC_OUTPAY 0x04 /* 2 - Output Payload Capability */ #define HDAC_INPAY 0x06 /* 2 - Input Payload Capability */ #define HDAC_GCTL 0x08 /* 4 - Global Control */ #define HDAC_WAKEEN 0x0c /* 2 - Wake Enable */ #define HDAC_STATESTS 0x0e /* 2 - State Change Status */ #define HDAC_GSTS 0x10 /* 2 - Global Status */ #define HDAC_OUTSTRMPAY 0x18 /* 2 - Output Stream Payload Capability */ #define HDAC_INSTRMPAY 0x1a /* 2 - Input Stream Payload Capability */ #define HDAC_INTCTL 0x20 /* 4 - Interrupt Control */ #define HDAC_INTSTS 0x24 /* 4 - Interrupt Status */ #define HDAC_WALCLK 0x30 /* 4 - Wall Clock Counter */ #define HDAC_SSYNC 0x38 /* 4 - Stream Synchronization */ #define HDAC_CORBLBASE 0x40 /* 4 - CORB Lower Base Address */ #define HDAC_CORBUBASE 0x44 /* 4 - CORB Upper Base Address */ #define HDAC_CORBWP 0x48 /* 2 - CORB Write Pointer */ #define HDAC_CORBRP 0x4a /* 2 - CORB Read Pointer */ #define HDAC_CORBCTL 0x4c /* 1 - CORB Control */ #define HDAC_CORBSTS 0x4d /* 1 - CORB Status */ #define HDAC_CORBSIZE 0x4e /* 1 - CORB Size */ #define HDAC_RIRBLBASE 0x50 /* 4 - RIRB Lower Base Address */ #define HDAC_RIRBUBASE 0x54 /* 4 - RIRB Upper Base Address */ #define HDAC_RIRBWP 0x58 /* 2 - RIRB Write Pointer */ #define HDAC_RINTCNT 0x5a /* 2 - Response Interrupt Count */ #define HDAC_RIRBCTL 0x5c /* 1 - RIRB Control */ #define HDAC_RIRBSTS 0x5d /* 1 - RIRB Status */ #define HDAC_RIRBSIZE 0x5e /* 1 - RIRB Size */ #define HDAC_ICOI 0x60 /* 4 - Immediate Command Output Interface */ #define HDAC_ICII 0x64 /* 4 - Immediate Command Input Interface */ #define HDAC_ICIS 0x68 /* 2 - Immediate Command Status */ #define HDAC_DPIBLBASE 0x70 /* 4 - DMA Position Buffer Lower Base */ #define HDAC_DPIBUBASE 0x74 /* 4 - DMA Position Buffer Upper Base */ #define HDAC_SDCTL0 0x80 /* 3 - Stream Descriptor Control */ #define HDAC_SDCTL1 0x81 /* 3 - Stream Descriptor Control */ #define HDAC_SDCTL2 0x82 /* 3 - Stream Descriptor Control */ #define HDAC_SDSTS 0x83 /* 1 - Stream Descriptor Status */ #define HDAC_SDLPIB 0x84 /* 4 - Link Position in Buffer */ #define HDAC_SDCBL 0x88 /* 4 - Cyclic Buffer Length */ #define HDAC_SDLVI 0x8C /* 2 - Last Valid Index */ #define HDAC_SDFIFOS 0x90 /* 2 - FIFOS */ #define HDAC_SDFMT 0x92 /* 2 - fmt */ #define HDAC_SDBDPL 0x98 /* 4 - Buffer Descriptor Pointer Lower Base */ #define HDAC_SDBDPU 0x9C /* 4 - Buffer Descriptor Pointer Upper Base */ #define _HDAC_ISDOFFSET(n, iss, oss) (0x80 + ((n) * 0x20)) #define _HDAC_ISDCTL(n, iss, oss) (0x00 + _HDAC_ISDOFFSET(n, iss, oss)) #define _HDAC_ISDSTS(n, iss, oss) (0x03 + _HDAC_ISDOFFSET(n, iss, oss)) #define _HDAC_ISDPICB(n, iss, oss) (0x04 + _HDAC_ISDOFFSET(n, iss, oss)) #define _HDAC_ISDCBL(n, iss, oss) (0x08 + _HDAC_ISDOFFSET(n, iss, oss)) #define _HDAC_ISDLVI(n, iss, oss) (0x0c + _HDAC_ISDOFFSET(n, iss, oss)) #define _HDAC_ISDFIFOD(n, iss, oss) (0x10 + _HDAC_ISDOFFSET(n, iss, oss)) #define _HDAC_ISDFMT(n, iss, oss) (0x12 + _HDAC_ISDOFFSET(n, iss, oss)) #define _HDAC_ISDBDPL(n, iss, oss) (0x18 + _HDAC_ISDOFFSET(n, iss, oss)) #define _HDAC_ISDBDPU(n, iss, oss) (0x1c + _HDAC_ISDOFFSET(n, iss, oss)) #define _HDAC_OSDOFFSET(n, iss, oss) (0x80 + ((iss) * 0x20) + ((n) * 0x20)) #define _HDAC_OSDCTL(n, iss, oss) (0x00 + _HDAC_OSDOFFSET(n, iss, oss)) #define _HDAC_OSDSTS(n, iss, oss) (0x03 + _HDAC_OSDOFFSET(n, iss, oss)) #define _HDAC_OSDPICB(n, iss, oss) (0x04 + _HDAC_OSDOFFSET(n, iss, oss)) #define _HDAC_OSDCBL(n, iss, oss) (0x08 + _HDAC_OSDOFFSET(n, iss, oss)) #define _HDAC_OSDLVI(n, iss, oss) (0x0c + _HDAC_OSDOFFSET(n, iss, oss)) #define _HDAC_OSDFIFOD(n, iss, oss) (0x10 + _HDAC_OSDOFFSET(n, iss, oss)) #define _HDAC_OSDFMT(n, iss, oss) (0x12 + _HDAC_OSDOFFSET(n, iss, oss)) #define _HDAC_OSDBDPL(n, iss, oss) (0x18 + _HDAC_OSDOFFSET(n, iss, oss)) #define _HDAC_OSDBDPU(n, iss, oss) (0x1c + _HDAC_OSDOFFSET(n, iss, oss)) #define _HDAC_BSDOFFSET(n, iss, oss) (0x80 + ((iss) * 0x20) + ((oss) * 0x20) + ((n) * 0x20)) #define _HDAC_BSDCTL(n, iss, oss) (0x00 + _HDAC_BSDOFFSET(n, iss, oss)) #define _HDAC_BSDSTS(n, iss, oss) (0x03 + _HDAC_BSDOFFSET(n, iss, oss)) #define _HDAC_BSDPICB(n, iss, oss) (0x04 + _HDAC_BSDOFFSET(n, iss, oss)) #define _HDAC_BSDCBL(n, iss, oss) (0x08 + _HDAC_BSDOFFSET(n, iss, oss)) #define _HDAC_BSDLVI(n, iss, oss) (0x0c + _HDAC_BSDOFFSET(n, iss, oss)) #define _HDAC_BSDFIFOD(n, iss, oss) (0x10 + _HDAC_BSDOFFSET(n, iss, oss)) #define _HDAC_BSDFMT(n, iss, oss) (0x12 + _HDAC_BSDOFFSET(n, iss, oss)) #define _HDAC_BSDBDPL(n, iss, oss) (0x18 + _HDAC_BSDOFFSET(n, iss, oss)) #define _HDAC_BSDBDBU(n, iss, oss) (0x1c + _HDAC_BSDOFFSET(n, iss, oss)) /**************************************************************************** * HDA Controller Register Fields ****************************************************************************/ /* GCAP - Global Capabilities */ #define HDAC_GCAP_64OK 0x0001 #define HDAC_GCAP_NSDO_MASK 0x0006 #define HDAC_GCAP_NSDO_SHIFT 1 #define HDAC_GCAP_BSS_MASK 0x00f8 #define HDAC_GCAP_BSS_SHIFT 3 #define HDAC_GCAP_ISS_MASK 0x0f00 #define HDAC_GCAP_ISS_SHIFT 8 #define HDAC_GCAP_OSS_MASK 0xf000 #define HDAC_GCAP_OSS_SHIFT 12 #define HDAC_GCAP_NSDO_1SDO 0x00 #define HDAC_GCAP_NSDO_2SDO 0x02 #define HDAC_GCAP_NSDO_4SDO 0x04 #define HDAC_GCAP_BSS(gcap) \ (((gcap) & HDAC_GCAP_BSS_MASK) >> HDAC_GCAP_BSS_SHIFT) #define HDAC_GCAP_ISS(gcap) \ (((gcap) & HDAC_GCAP_ISS_MASK) >> HDAC_GCAP_ISS_SHIFT) #define HDAC_GCAP_OSS(gcap) \ (((gcap) & HDAC_GCAP_OSS_MASK) >> HDAC_GCAP_OSS_SHIFT) #define HDAC_GCAP_NSDO(gcap) \ (((gcap) & HDAC_GCAP_NSDO_MASK) >> HDAC_GCAP_NSDO_SHIFT) /* GCTL - Global Control */ #define HDAC_GCTL_CRST 0x00000001 #define HDAC_GCTL_FCNTRL 0x00000002 #define HDAC_GCTL_UNSOL 0x00000100 /* WAKEEN - Wake Enable */ #define HDAC_WAKEEN_SDIWEN_MASK 0x7fff #define HDAC_WAKEEN_SDIWEN_SHIFT 0 /* STATESTS - State Change Status */ #define HDAC_STATESTS_SDIWAKE_MASK 0x7fff #define HDAC_STATESTS_SDIWAKE_SHIFT 0 #define HDAC_STATESTS_SDIWAKE(statests, n) \ (((((statests) & HDAC_STATESTS_SDIWAKE_MASK) >> \ HDAC_STATESTS_SDIWAKE_SHIFT) >> (n)) & 0x0001) /* GSTS - Global Status */ #define HDAC_GSTS_FSTS 0x0002 /* INTCTL - Interrut Control */ #define HDAC_INTCTL_SIE_MASK 0x3fffffff #define HDAC_INTCTL_SIE_SHIFT 0 #define HDAC_INTCTL_CIE 0x40000000 #define HDAC_INTCTL_GIE 0x80000000 /* INTSTS - Interrupt Status */ #define HDAC_INTSTS_SIS_MASK 0x3fffffff #define HDAC_INTSTS_SIS_SHIFT 0 #define HDAC_INTSTS_CIS 0x40000000 #define HDAC_INTSTS_GIS 0x80000000 /* SSYNC - Stream Synchronization */ #define HDAC_SSYNC_SSYNC_MASK 0x3fffffff #define HDAC_SSYNC_SSYNC_SHIFT 0 /* CORBWP - CORB Write Pointer */ #define HDAC_CORBWP_CORBWP_MASK 0x00ff #define HDAC_CORBWP_CORBWP_SHIFT 0 /* CORBRP - CORB Read Pointer */ #define HDAC_CORBRP_CORBRP_MASK 0x00ff #define HDAC_CORBRP_CORBRP_SHIFT 0 #define HDAC_CORBRP_CORBRPRST 0x8000 /* CORBCTL - CORB Control */ #define HDAC_CORBCTL_CMEIE 0x01 #define HDAC_CORBCTL_CORBRUN 0x02 /* CORBSTS - CORB Status */ #define HDAC_CORBSTS_CMEI 0x01 /* CORBSIZE - CORB Size */ #define HDAC_CORBSIZE_CORBSIZE_MASK 0x03 #define HDAC_CORBSIZE_CORBSIZE_SHIFT 0 #define HDAC_CORBSIZE_CORBSZCAP_MASK 0xf0 #define HDAC_CORBSIZE_CORBSZCAP_SHIFT 4 #define HDAC_CORBSIZE_CORBSIZE_2 0x00 #define HDAC_CORBSIZE_CORBSIZE_16 0x01 #define HDAC_CORBSIZE_CORBSIZE_256 0x02 #define HDAC_CORBSIZE_CORBSZCAP_2 0x10 #define HDAC_CORBSIZE_CORBSZCAP_16 0x20 #define HDAC_CORBSIZE_CORBSZCAP_256 0x40 #define HDAC_CORBSIZE_CORBSIZE(corbsize) \ (((corbsize) & HDAC_CORBSIZE_CORBSIZE_MASK) >> HDAC_CORBSIZE_CORBSIZE_SHIFT) /* RIRBWP - RIRB Write Pointer */ #define HDAC_RIRBWP_RIRBWP_MASK 0x00ff #define HDAC_RIRBWP_RIRBWP_SHIFT 0 #define HDAC_RIRBWP_RIRBWPRST 0x8000 /* RINTCTN - Response Interrupt Count */ #define HDAC_RINTCNT_MASK 0x00ff #define HDAC_RINTCNT_SHIFT 0 /* RIRBCTL - RIRB Control */ #define HDAC_RIRBCTL_RINTCTL 0x01 #define HDAC_RIRBCTL_RIRBDMAEN 0x02 #define HDAC_RIRBCTL_RIRBOIC 0x04 /* RIRBSTS - RIRB Status */ #define HDAC_RIRBSTS_RINTFL 0x01 #define HDAC_RIRBSTS_RIRBOIS 0x04 /* RIRBSIZE - RIRB Size */ #define HDAC_RIRBSIZE_RIRBSIZE_MASK 0x03 #define HDAC_RIRBSIZE_RIRBSIZE_SHIFT 0 #define HDAC_RIRBSIZE_RIRBSZCAP_MASK 0xf0 #define HDAC_RIRBSIZE_RIRBSZCAP_SHIFT 4 #define HDAC_RIRBSIZE_RIRBSIZE_2 0x00 #define HDAC_RIRBSIZE_RIRBSIZE_16 0x01 #define HDAC_RIRBSIZE_RIRBSIZE_256 0x02 #define HDAC_RIRBSIZE_RIRBSZCAP_2 0x10 #define HDAC_RIRBSIZE_RIRBSZCAP_16 0x20 #define HDAC_RIRBSIZE_RIRBSZCAP_256 0x40 #define HDAC_RIRBSIZE_RIRBSIZE(rirbsize) \ (((rirbsize) & HDAC_RIRBSIZE_RIRBSIZE_MASK) >> HDAC_RIRBSIZE_RIRBSIZE_SHIFT) /* DPLBASE - DMA Position Lower Base Address */ #define HDAC_DPLBASE_DPLBASE_MASK 0xffffff80 #define HDAC_DPLBASE_DPLBASE_SHIFT 7 #define HDAC_DPLBASE_DPLBASE_DMAPBE 0x00000001 /* SDCTL - Stream Descriptor Control */ #define HDAC_SDCTL_SRST 0x000001 #define HDAC_SDCTL_RUN 0x000002 #define HDAC_SDCTL_IOCE 0x000004 #define HDAC_SDCTL_FEIE 0x000008 #define HDAC_SDCTL_DEIE 0x000010 #define HDAC_SDCTL2_STRIPE_MASK 0x03 #define HDAC_SDCTL2_STRIPE_SHIFT 0 #define HDAC_SDCTL2_TP 0x04 #define HDAC_SDCTL2_DIR 0x08 #define HDAC_SDCTL2_STRM_MASK 0xf0 #define HDAC_SDCTL2_STRM_SHIFT 4 #define HDAC_SDSTS_DESE (1 << 4) #define HDAC_SDSTS_FIFOE (1 << 3) #define HDAC_SDSTS_BCIS (1 << 2) /**************************************************************************** * Helper Macros ****************************************************************************/ #define HDA_DMA_ALIGNMENT 128 #define HDA_BDL_MIN 2 #define HDA_BDL_MAX 256 #define HDA_BDL_DEFAULT HDA_BDL_MIN #define HDA_BLK_MIN HDA_DMA_ALIGNMENT #define HDA_BLK_ALIGN (~(HDA_BLK_MIN - 1)) #define HDA_BUFSZ_MIN (HDA_BDL_MIN * HDA_BLK_MIN) #define HDA_BUFSZ_MAX 262144 #define HDA_BUFSZ_DEFAULT 65536 #define HDA_GPIO_MAX 8 #define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ (fl) == 0xffffffff || \ (((fl) & 0xffff0000) == 0xffff0000 && \ ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ (((fl) & 0x0000ffff) == 0x0000ffff && \ ((fl) & 0xffff0000) == ((v) & 0xffff0000))) #define HDA_MATCH_ALL 0xffffffff #define HDA_INVALID 0xffffffff #define HDA_BOOTVERBOSE(stmt) do { \ if (bootverbose != 0 || snd_verbose > 3) { \ stmt \ } \ } while (0) #define HDA_BOOTHVERBOSE(stmt) do { \ if (snd_verbose > 3) { \ stmt \ } \ } while (0) #define hda_command(dev, verb) \ HDAC_CODEC_COMMAND(device_get_parent(dev), (dev), (verb)) extern void probe_hda_bus(uint32_t pci_addr); #endif /* !__LIBSAIO_HDA_H */