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1diff -xrevision -x.svn -x.DS_Store -x.config -Naur trunk/i386/libsaio/acpi_patcher.c trunkcleanup/i386/libsaio/acpi_patcher.c␊
2--- trunk/i386/libsaio/acpi_patcher.c␉2013-06-21 10:48:40.000000000 -0400␊
3+++ trunkcleanup/i386/libsaio/acpi_patcher.c␉2013-06-21 10:38:23.000000000 -0400␊
4@@ -439,11 +439,10 @@␊
5 ␉␉␉{␊
6 ␉␉␉␉switch (Platform.CPU.Model) ␊
7 ␉␉␉␉{␊
8-␉␉␉␉␉case CPU_MODEL_DOTHAN:␉// Intel Pentium M␊
9-␉␉␉␉␉case CPU_MODEL_YONAH:␉// Intel Mobile Core Solo, Duo␊
10-␉␉␉␉␉case CPU_MODEL_MEROM:␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊
11-␉␉␉␉␉case CPU_MODEL_PENRYN:␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊
12-␉␉␉␉␉case CPU_MODEL_ATOM:␉// Intel Atom (45nm)␊
13+␉␉␉␉␉case CPU_MODEL_YONAH:␊
14+␉␉␉␉␉case CPU_MODEL_MEROM:␊
15+␉␉␉␉␉case CPU_MODEL_PENRYN:␊
16+␉␉␉␉␉case CPU_MODEL_ATOM:␊
17 ␉␉␉␉␉{␊
18 ␉␉␉␉␉␉bool cpu_dynamic_fsb = false;␊
19 ␊
20@@ -561,20 +560,20 @@␊
21 ␊
22 ␉␉␉␉␉␉break;␊
23 ␉␉␉␉␉}␊
24-␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
25-␉␉␉␉␉case CPU_MODEL_DALES:␉␉␊
26-␉␉␉␉␉case CPU_MODEL_CLARKDALE:␉// Intel Core i3, i5 LGA1156 (32nm)␊
27-␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
28-␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65xx␊
29-␉␉␉␉␉case CPU_MODEL_WESTMERE:␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
30-␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉// Intel Xeon E7␊
31-␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊
32-␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE_XEON:// Intel Core i7, Xeon E5 LGA2011 (32nm)␊
33-␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (22nm)␊
34+␉␉␉␉␉case CPU_MODEL_NEHALEM:␊
35+␉␉␉␉␉case CPU_MODEL_FIELDS:␊
36+␉␉␉␉␉case CPU_MODEL_DALES:␊
37+␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␊
38+␉␉␉␉␉case CPU_MODEL_DALES_32NM:␊
39+␉␉␉␉␉case CPU_MODEL_WESTMERE:␊
40+␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␊
41+␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␊
42+␉␉␉␉␉case CPU_MODEL_JAKETOWN:␊
43+␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␊
44 ␊
45 ␉␉␉␉␉{␊
46 ␉␉␉␉␉if ((Platform.CPU.Model == CPU_MODEL_SANDYBRIDGE) ||␊
47-␉␉␉␉␉␉(Platform.CPU.Model == CPU_MODEL_SANDYBRIDGE_XEON))␊
48+␉␉␉␉␉␉(Platform.CPU.Model == CPU_MODEL_JAKETOWN))␊
49 ␉␉␉␉␉{␊
50 ␉␉␉␉␉␉ maximum.Control = (rdmsr64(MSR_IA32_PERF_STATUS) >> 8) & 0xff;␊
51 ␉␉␉␉␉} else {␊
52diff -xrevision -x.svn -x.DS_Store -x.config -Naur trunk/i386/libsaio/cpu.c trunkcleanup/i386/libsaio/cpu.c␊
53--- trunk/i386/libsaio/cpu.c␉2013-06-21 10:48:40.000000000 -0400␊
54+++ trunkcleanup/i386/libsaio/cpu.c␉2013-06-21 09:50:37.000000000 -0400␊
55@@ -370,30 +370,24 @@␊
56 ␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) || (p->CPU.Family == 0x0f && p->CPU.Model >= 0x03)) {␊
57 ␉␉␉/* Nehalem CPU model */␊
58 ␉␉␉if (p->CPU.Family == 0x06 && (p->CPU.Model == CPU_MODEL_NEHALEM␉␉||␊
59-␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_FIELDS␉||␊
60-␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_DALES␉||␊
61-␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_CLARKDALE␉||␊
62-␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_WESTMERE␉||␊
63-␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_NEHALEM_EX␉||␊
64-␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_WESTMERE_EX ||␊
65-␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_SANDYBRIDGE ||␊
66-␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_SANDYBRIDGE_XEON ||␊
67-␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_IVYBRIDGE_XEON␉||␊
68-␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_IVYBRIDGE ||␊
69-␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_HASWELL_DT ||␊
70-␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_HASWELL_MB ||␊
71-␉␉␉␉␉␉␉␉␉␉ //p->CPU.Model == CPU_MODEL_HASWELL_H ||␊
72-␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_HASWELL_ULT ||␊
73-␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_HASWELL_ULX ))␊
74+␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_FIELDS␉␉||␊
75+␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_DALES␉␉||␊
76+␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_NEHALEM_EX␉||␊
77+␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_DALES_32NM␉||␊
78+␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_WESTMERE␉||␊
79+␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_WESTMERE_EX␉||␊
80+␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_SANDYBRIDGE␉||␊
81+␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_JAKETOWN␉||␊
82+␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_IVYBRIDGE␉))␊
83 ␉␉␉{␊
84 ␉␉␉␉msr = rdmsr64(MSR_PLATFORM_INFO);␊
85 ␉␉␉␉DBG("msr(%d): platform_info %08x\n", __LINE__, bitfield(msr, 31, 0));␊
86-␉␉␉␉bus_ratio_max = bitfield(msr, 14, 8);␊
87-␉␉␉␉bus_ratio_min = bitfield(msr, 46, 40); //valv: not sure about this one (Remarq.1)␊
88+␉␉␉␉bus_ratio_max = bitfield(msr, 15, 8);␊
89+␉␉␉␉bus_ratio_min = bitfield(msr, 47, 40);␊
90 ␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊
91 ␉␉␉␉DBG("msr(%d): flex_ratio %08x\n", __LINE__, bitfield(msr, 31, 0));␊
92 ␉␉␉␉if (bitfield(msr, 16, 16)) {␊
93-␉␉␉␉␉flex_ratio = bitfield(msr, 14, 8);␊
94+␉␉␉␉␉flex_ratio = bitfield(msr, 15, 8);␊
95 ␉␉␉␉␉/* bcc9: at least on the gigabyte h67ma-ud2h,␊
96 ␉␉␉␉␉ where the cpu multipler can't be changed to␊
97 ␉␉␉␉␉ allow overclocking, the flex_ratio msr has unexpected (to OSX)␊
98diff -xrevision -x.svn -x.DS_Store -x.config -Naur trunk/i386/libsaio/cpu.h trunkcleanup/i386/libsaio/cpu.h␊
99--- trunk/i386/libsaio/cpu.h␉2013-06-21 10:48:40.000000000 -0400␊
100+++ trunkcleanup/i386/libsaio/cpu.h␉2013-06-21 08:55:00.000000000 -0400␊
101@@ -42,40 +42,22 @@␊
102 ␊
103 // CPUID Values␊
104 ␊
105-#define CPUID_MODEL_PRESCOTT␉␉3 // 0x03 Celeron D, Pentium 4 (90nm)␊
106-#define CPUID_MODEL_NOCONA␉␉4 // 0x04 Xeon Nocona, Irwindale (90nm)␊
107-#define CPUID_MODEL_PRESLER␉␉6 // 0x06 Pentium 4, Pentium D (65nm)␊
108-#define CPUID_MODEL_PENTIUM_M␉␉9 // 0x09␊
109-#define CPUID_MODEL_DOTHAN␉␉13 // 0x0D Dothan␊
110-#define CPUID_MODEL_YONAH␉␉14 // 0x0E Intel Mobile Core Solo, Duo␊
111-#define CPUID_MODEL_MEROM␉␉15 // 0x0F Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊
112-#define CPUID_MODEL_CONROE␉␉15 // 0x0F␊
113-#define CPUID_MODEL_CELERON␉␉22 // 0x16␊
114-#define CPUID_MODEL_PENRYN␉␉23 // 0x17 Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊
115-#define CPUID_MODEL_WOLFDALE␉␉23 // 0x17␊
116-#define CPUID_MODEL_NEHALEM␉␉26 // 0x1A Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
117-#define CPUID_MODEL_ATOM␉␉28 // 0x1C Intel Atom (45nm) Pineview, Silverthorne␊
118-#define CPUID_MODEL_XEON_MP␉␉29 // 0x1D MP 7400␊
119-#define CPUID_MODEL_FIELDS␉␉30 // 0x1E Intel Core i5, i7, Xeon X34xx LGA1156 (45nm),(Clarksfiled, Lynnfield, Jasper Forest)␊
120-#define CPUID_MODEL_DALES␉␉31 // 0x1F Havendale, Auburndale␊
121-#define CPUID_MODEL_CLARKDALE␉␉37 // 0x25 Intel Core i3, i5 LGA1156 (32nm), (Arrandale, Clarksdale)␊
122-#define CPUID_MODEL_ATOM_SAN␉␉38 // 0x26␊
123-#define CPUID_MODEL_LINCROFT␉␉39 // 0x27 Intel Atom (45nm) Z6xx (single core)␊
124-#define CPUID_MODEL_SANDYBRIDGE␉␉42 // 0x2A Intel Core i3, i5, i7 LGA1155 (32nm)␊
125-#define CPUID_MODEL_WESTMERE␉␉44 // 0x2C Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
126-#define CPUID_MODEL_SANDYBRIDGE_XEON␉45 // 0x2D Intel Xeon E5 LGA2011 (32nm), SandyBridge-E, SandyBridge-EN, SandyBridge-EP␊
127-#define CPUID_MODEL_NEHALEM_EX␉␉46 // 0x2E Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x␊
128-#define CPUID_MODEL_WESTMERE_EX␉␉47 // 0x2F Intel Xeon E7␊
129-#define CPUID_MODEL_ATOM_2000␉␉54 // 0x36 Intel Atom (32nm) Cedarview␊
130-#define CPUID_MODEL_IVYBRIDGE␉␉58 // 0x3A Intel Core i5, i7 LGA1155 (22nm)␊
131-#define CPUID_MODEL_HASWELL_DT␉␉60 // 0x3C␊
132-#define CPUID_MODEL_IVYBRIDGE_XEON␉62 // 0x3E␊
133-#define CPUID_MODEL_HASWELL_MB␉␉63 // 0x3F␊
134-//#define CPUID_MODEL_HASWELL_H␉␉?? // 0x??␊
135-#define CPUID_MODEL_HASWELL_ULT␉␉69 // 0x45␊
136-#define CPUID_MODEL_HASWELL_ULX␉␉70 // 0x46␊
137-␊
138-/* HASWELL-DT HASWELL-MB HASWELL-H HASWELL-ULT HASWELL ULX*/␊
139+#define CPUID_MODEL_YONAH␉14␊
140+#define CPUID_MODEL_MEROM␉15␊
141+#define CPUID_MODEL_PENRYN␉23␊
142+#define CPUID_MODEL_NEHALEM␉26␊
143+#define CPUID_MODEL_ATOM␉28␊
144+#define CPUID_MODEL_ATOM_Z6␉38␊
145+#define CPUID_MODEL_ATOM_32NM␉54␊
146+#define CPUID_MODEL_FIELDS␉30␊
147+#define CPUID_MODEL_DALES␉31␊
148+#define CPUID_MODEL_NEHALEM_EX␉46␊
149+#define CPUID_MODEL_DALES_32NM␉37␊
150+#define CPUID_MODEL_WESTMERE␉44␊
151+#define CPUID_MODEL_WESTMERE_EX␉47␊
152+#define CPUID_MODEL_SANDYBRIDGE␉42␊
153+#define CPUID_MODEL_JAKETOWN␉45␊
154+#define CPUID_MODEL_IVYBRIDGE␉58␊
155 ␊
156 static inline uint64_t rdtsc64(void)␊
157 {␊
158diff -xrevision -x.svn -x.DS_Store -x.config -Naur trunk/i386/libsaio/platform.h trunkcleanup/i386/libsaio/platform.h␊
159--- trunk/i386/libsaio/platform.h␉2013-06-21 10:48:40.000000000 -0400␊
160+++ trunkcleanup/i386/libsaio/platform.h␉2013-06-21 08:59:47.000000000 -0400␊
161@@ -30,38 +30,22 @@␊
162 #define CPUID_88␉␉␉9␊
163 #define CPUID_MAX␉␉␉10␊
164 ␊
165-#define CPU_MODEL_PRESCOTT␉␉0x03␉␉␉// Celeron D, Pentium 4 (90nm)␊
166-#define CPU_MODEL_NOCONA␉␉0x04␉␉␉// Xeon Nocona, Irwindale (90nm)␊
167-#define CPU_MODEL_PRESLER␉␉0x06␉␉␉// Pentium 4, Pentium D (65nm)␊
168-#define CPU_MODEL_PENTIUM_M␉␉0x09␉␉␉// Banias␊
169-#define CPU_MODEL_DOTHAN␉␉0x0D␉␉␉// Dothan␊
170-#define CPU_MODEL_YONAH␉␉␉0x0E␉␉␉// Sossaman, Yonah␊
171-#define CPU_MODEL_MEROM␉␉␉0x0F␉␉␉// Allendale, Conroe, Kentsfield, Woodcrest, Clovertown, Tigerton, Merom␊
172-#define CPU_MODEL_CONROE␉␉0x0F␉␉␉// ␊
173-#define CPU_MODEL_CELERON␉␉0x16␉␉␉// ␊
174-#define CPU_MODEL_PENRYN␉␉0x17␉␉␉// Wolfdale, Yorkfield, Harpertown, Penryn␊
175-#define CPU_MODEL_WOLFDALE␉␉0x17␉␉␉// ␊
176-#define CPU_MODEL_NEHALEM␉␉0x1A␉␉␉// Bloomfield. Nehalem-EP, Nehalem-WS, Gainestown␊
177-#define CPU_MODEL_ATOM␉␉␉0x1C␉␉␉// Pineview␊
178-#define CPU_MODEL_XEON_MP␉␉0x1D␉␉␉// MP 7400␊
179-#define CPU_MODEL_FIELDS␉␉0x1E␉␉␉// Lynnfield, Clarksfield, Jasper Forest␊
180-#define CPU_MODEL_DALES␉␉␉0x1F␉␉␉// Havendale, Auburndale␊
181-#define CPU_MODEL_CLARKDALE␉␉0x25␉␉␉// Clarkdale, Arrandale␊
182-#define CPU_MODEL_ATOM_SAN␉␉0x26␉␉␉// Lincroft␊
183-#define CPU_MODEL_LINCROFT␉␉0x27␉␉␉// ␊
184-#define CPU_MODEL_SANDYBRIDGE␉␉0x2A␉␉␉// Sandy Bridge␊
185-#define CPU_MODEL_WESTMERE␉␉0x2C␉␉␉// Gulftown, Westmere-EP, Westmere-WS␊
186-#define CPU_MODEL_SANDYBRIDGE_XEON␉0x2D␉␉␉// Sandy Bridge-E, Sandy Bridge-EP␊
187-#define CPU_MODEL_NEHALEM_EX␉␉0x2E␉␉␉// Beckton␊
188-#define CPU_MODEL_WESTMERE_EX␉␉0x2F␉␉␉// Westmere-EX␊
189-#define CPU_MODEL_ATOM_2000␉␉0x36␉␉␉// Cedarview␊
190-#define CPU_MODEL_IVYBRIDGE␉␉0x3A␉␉␉// Ivy Bridge␊
191-#define CPU_MODEL_HASWELL_DT␉␉0x3C␉␉␉// Haswell DT␊
192-#define CPU_MODEL_IVYBRIDGE_XEON␉0x3E␉␉␉// Ivy Bridge Xeon␊
193-#define CPU_MODEL_HASWELL_MB␉␉0x3F␉␉␉// Haswell MB␊
194-//#define CPU_MODEL_HASWELL_H␉␉0x??␉␉␉// Haswell H␊
195-#define CPU_MODEL_HASWELL_ULT␉␉0x45␉␉␉// Haswell ULT␊
196-#define CPU_MODEL_HASWELL_ULX␉␉0x46␉␉␉// Haswell ULX␊
197+#define CPU_MODEL_YONAH␉␉0x0E␊
198+#define CPU_MODEL_MEROM␉␉0x0F␊
199+#define CPU_MODEL_PENRYN␉0x17␊
200+#define CPU_MODEL_NEHALEM␉0x1A␊
201+#define CPU_MODEL_ATOM␉␉0x1C␊
202+#define CPU_MODEL_ATOM_Z6␉0x26␊
203+#define CPU_MODEL_ATOM_32NM␉0x36␊
204+#define CPU_MODEL_FIELDS␉0x1E␊
205+#define CPU_MODEL_DALES␉␉0x1F␊
206+#define CPU_MODEL_NEHALEM_EX␉0x2E␊
207+#define CPU_MODEL_DALES_32NM␉0x25␊
208+#define CPU_MODEL_WESTMERE␉0x2C␊
209+#define CPU_MODEL_WESTMERE_EX␉0x2F␊
210+#define CPU_MODEL_SANDYBRIDGE␉0x2A␊
211+#define CPU_MODEL_JAKETOWN␉0x2D␊
212+#define CPU_MODEL_IVYBRIDGE␉0x3A␊
213 ␊
214 /* CPU Features */␊
215 #define CPU_FEATURE_MMX␉␉␉0x00000001␉␉// MMX Instruction Set␊
216diff -xrevision -x.svn -x.DS_Store -x.config -Naur trunk/i386/libsaio/smbios.c trunkcleanup/i386/libsaio/smbios.c␊
217--- trunk/i386/libsaio/smbios.c␉2013-06-21 10:48:40.000000000 -0400␊
218+++ trunkcleanup/i386/libsaio/smbios.c␉2013-06-21 10:47:58.000000000 -0400␊
219@@ -325,30 +325,30 @@␊
220 ␉␉␉␉␉{␊
221 ␉␉␉␉␉␉switch (Platform.CPU.Model)␊
222 ␉␉␉␉␉␉{␊
223-␉␉␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
224+␉␉␉␉␉␉␉case CPU_MODEL_FIELDS:␊
225 ␉␉␉␉␉␉␉case CPU_MODEL_DALES:␊
226-␉␉␉␉␉␉␉case CPU_MODEL_CLARKDALE:␉␉// Intel Core i3, i5 LGA1156 (32nm)␊
227+␉␉␉␉␉␉␉case CPU_MODEL_DALES_32NM:␊
228 ␉␉␉␉␉␉␉␉defaultBIOSInfo.version␉␉␉= kDefaultiMacNehalemBIOSVersion;␊
229 ␉␉␉␉␉␉␉␉defaultSystemInfo.productName␉= kDefaultiMacNehalem;␊
230 ␉␉␉␉␉␉␉␉defaultSystemInfo.family␉␉= kDefaultiMacFamily;␊
231 ␉␉␉␉␉␉␉␉break;␊
232 ␊
233-␉␉␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␉␉␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊
234-␉␉␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE_XEON:␉␉␉// Intel Core i7, Xeon E5 LGA2011 (32nm)␊
235-␉␉␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␉␉␉// Intel Core i3, i5, i7 LGA1155 (22nm)␊
236+␉␉␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␊
237+␉␉␉␉␉␉␉case CPU_MODEL_JAKETOWN:␊
238+␉␉␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␊
239 ␉␉␉␉␉␉␉␉defaultBIOSInfo.version␉␉␉= kDefaultiMacSandyBIOSVersion;␊
240 ␉␉␉␉␉␉␉␉defaultSystemInfo.productName␉= kDefaultiMacSandy;␊
241 ␉␉␉␉␉␉␉␉defaultSystemInfo.family␉␉= kDefaultiMacFamily;␊
242 ␉␉␉␉␉␉␉␉break;␊
243-␉␉␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
244-␉␉␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␉␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x␊
245+␉␉␉␉␉␉␉case CPU_MODEL_NEHALEM:␊
246+␉␉␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␊
247 ␉␉␉␉␉␉␉␉defaultBIOSInfo.version␉␉␉= kDefaultMacProNehalemBIOSVersion;␊
248 ␉␉␉␉␉␉␉␉defaultSystemInfo.productName␉= kDefaultMacProNehalem;␊
249 ␉␉␉␉␉␉␉␉defaultSystemInfo.family␉␉= kDefaultMacProFamily;␊
250 ␉␉␉␉␉␉␉␉break;␊
251 ␊
252-␉␉␉␉␉␉␉case CPU_MODEL_WESTMERE:␉␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
253-␉␉␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉␉// Intel Xeon E7␊
254+␉␉␉␉␉␉␉case CPU_MODEL_WESTMERE:␊
255+␉␉␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␊
256 ␉␉␉␉␉␉␉␉defaultBIOSInfo.version␉␉␉= kDefaultMacProWestmereBIOSVersion;␊
257 ␉␉␉␉␉␉␉␉defaultBIOSInfo.releaseDate␉␉= kDefaulMacProWestmereBIOSReleaseDate;␊
258 ␉␉␉␉␉␉␉␉defaultSystemInfo.productName␉= kDefaultMacProWestmere;␊
259@@ -569,17 +569,15 @@␊
260 ␉␉{␊
261 ␉␉␉switch (Platform.CPU.Model)␊
262 ␉␉␉{␊
263-␉␉␉␉case CPU_MODEL_FIELDS:␉␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
264+␉␉␉␉case CPU_MODEL_NEHALEM:␊
265+␉␉␉␉case CPU_MODEL_FIELDS:␊
266 ␉␉␉␉case CPU_MODEL_DALES:␊
267-␉␉␉␉case CPU_MODEL_CLARKDALE:␉// Intel Core i3, i5 LGA1156 (32nm)␊
268-␉␉␉␉case CPU_MODEL_NEHALEM:␉␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
269-␉␉␉␉case CPU_MODEL_NEHALEM_EX:␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x␊
270-␉␉␉␉case CPU_MODEL_WESTMERE:␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
271-␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉// Intel Xeon E7␊
272-␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊
273-␉␉␉␉case CPU_MODEL_IVYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (22nm)␊
274-␉␉␉␉case CPU_MODEL_IVYBRIDGE_XEON:␊
275-␉␉␉␉case CPU_MODEL_SANDYBRIDGE_XEON:// Intel Core i7, Xeon E5 LGA2011 (32nm)␊
276+␉␉␉␉case CPU_MODEL_NEHALEM_EX:␊
277+␉␉␉␉case CPU_MODEL_DALES_32NM:␊
278+␉␉␉␉case CPU_MODEL_WESTMERE:␊
279+␉␉␉␉case CPU_MODEL_WESTMERE_EX:␊
280+␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␊
281+␉␉␉␉case CPU_MODEL_JAKETOWN:␊
282 ␉␉␉␉␉break;␊
283 ␊
284 ␉␉␉␉default:␊
285diff -xrevision -x.svn -x.DS_Store -x.config -Naur trunk/i386/libsaio/smbios_getters.c trunkcleanup/i386/libsaio/smbios_getters.c␊
286--- trunk/i386/libsaio/smbios_getters.c␉2013-06-21 10:48:40.000000000 -0400␊
287+++ trunkcleanup/i386/libsaio/smbios_getters.c␉2013-06-21 11:14:07.000000000 -0400␊
288@@ -32,7 +32,7 @@␊
289 ␉␉␉␉␉␉// set external clock to 0 for SANDY␊
290 ␉␉␉␉␉␉// removes FSB info from system profiler as on real mac's. ␊
291 ␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␊
292-␉␉␉␉␉case CPU_MODEL_IVYBRIDGE_XEON:␊
293+␉␉␉␉␉case CPU_MODEL_JAKETOWN:␊
294 ␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␊
295 ␉␉␉␉␉␉value->word = 0;␊
296 ␉␉␉␉␉␉break;␊
297@@ -70,20 +70,19 @@␊
298 ␉␉␉{␊
299 ␉␉␉␉switch (Platform.CPU.Model)␊
300 ␉␉␉␉{␊
301-␉␉␉␉␉case CPU_MODEL_DOTHAN:␉␉// Intel Pentium M␊
302-␉␉␉␉␉case CPU_MODEL_YONAH:␉␉// Intel Mobile Core Solo, Duo␊
303-␉␉␉␉␉case CPU_MODEL_MEROM:␉␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊
304-␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊
305-␉␉␉␉␉case CPU_MODEL_ATOM:␉␉// Intel Atom (45nm)␊
306+␉␉␉␉␉case CPU_MODEL_YONAH:␊
307+␉␉␉␉␉case CPU_MODEL_MEROM:␊
308+␉␉␉␉␉case CPU_MODEL_PENRYN:␊
309+␉␉␉␉␉case CPU_MODEL_ATOM:␊
310 ␉␉␉␉␉␉return false;␊
311 ␊
312-␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
313-␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
314+␉␉␉␉␉case CPU_MODEL_NEHALEM:␊
315+␉␉␉␉␉case CPU_MODEL_FIELDS:␊
316 ␉␉␉␉␉case CPU_MODEL_DALES:␊
317-␉␉␉␉␉case CPU_MODEL_CLARKDALE:␉// Intel Core i3, i5 LGA1156 (32nm)␊
318-␉␉␉␉␉case CPU_MODEL_WESTMERE:␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
319-␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x␊
320-␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉// Intel Xeon E7␊
321+␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␊
322+␉␉␉␉␉case CPU_MODEL_DALES_32NM:␊
323+␉␉␉␉␉case CPU_MODEL_WESTMERE:␊
324+␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␊
325 ␉␉␉␉␉{␊
326 ␉␉␉␉␉␉// thanks to dgobe for i3/i5/i7 bus speed detection␊
327 ␉␉␉␉␉␉int nhm_bus = 0x3F;␊
328@@ -156,17 +155,17 @@␊
329 ␉␉␉{␊
330 ␉␉␉␉switch (Platform.CPU.Model)␊
331 ␉␉␉␉{␊
332-␉␉␉␉␉case CPU_MODEL_DOTHAN:␉␉␉␉// Intel Pentium M␊
333-␉␉␉␉␉case CPU_MODEL_YONAH:␉␉␉␉// Intel Mobile Core Solo, Duo␊
334-␉␉␉␉␉case CPU_MODEL_MEROM:␉␉␉␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊
335-␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉␉␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊
336-␉␉␉␉␉case CPU_MODEL_ATOM:␉␉␉␉// Intel Atom (45nm)␊
337+␉␉␉␉␉case CPU_MODEL_YONAH:␊
338+␉␉␉␉␉case CPU_MODEL_MEROM:␊
339+␉␉␉␉␉case CPU_MODEL_PENRYN:␊
340+␉␉␉␉␉case CPU_MODEL_ATOM:␊
341 ␉␉␉␉␉␉return true;␊
342 ␊
343-␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉␉␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
344-␉␉␉␉␉case CPU_MODEL_WESTMERE:␉␉␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
345-␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉␉␉// Intel Xeon E7␊
346-␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE_XEON:␉␉␉// Intel Core i7, Xeon E5-xxxx LGA2011 (32nm)␊
347+␉␉␉␉␉case CPU_MODEL_NEHALEM: ␊
348+␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␊
349+␉␉␉␉␉case CPU_MODEL_WESTMERE:␊
350+␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␊
351+␉␉␉␉␉case CPU_MODEL_JAKETOWN:␊
352 ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)"))␊
353 ␉␉␉␉␉␉␉value->word = 0x0501;␉␉␉// Xeon ␊
354 ␉␉␉␉␉␉else␊
355@@ -190,9 +189,9 @@␊
356 ␉␉␉␉␉␉␉value->word = 0x0701;␉␉␉// Core i7␊
357 ␉␉␉␉␉␉return true;␊
358 ␊
359-␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␉␉␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊
360-␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␉␉␉// Intel Core i3, i5, i7 LGA1155 (22nm)␊
361-␉␉␉␉␉case CPU_MODEL_CLARKDALE:␉␉␉// Intel Core i3, i5 LGA1156 (32nm)␊
362+␉␉␉␉␉case CPU_MODEL_DALES_32NM:␊
363+␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␊
364+␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␊
365 ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3"))␊
366 ␉␉␉␉␉␉␉value->word = 0x0901;␉␉␉// Core i3␊
367 ␉␉␉␉␉␉else␊
368diff -xrevision -x.svn -x.DS_Store -x.config -Naur trunk/i386/modules/AcpiCodec/acpi_codec.c trunkcleanup/i386/modules/AcpiCodec/acpi_codec.c␊
369--- trunk/i386/modules/AcpiCodec/acpi_codec.c␉2013-06-21 10:48:44.000000000 -0400␊
370+++ trunkcleanup/i386/modules/AcpiCodec/acpi_codec.c␉2013-06-21 10:41:42.000000000 -0400␊
371@@ -778,7 +778,7 @@␊
372 ␊
373 static bool is_jaketown(void)␊
374 {␊
375- return Platform.CPU.Model == CPU_MODEL_SANDYBRIDGE_XEON;␊
376+ return Platform.CPU.Model == CPU_MODEL_JAKETOWN;␊
377 }␊
378 ␊
379 static U32 get_bclk(void)␊
380@@ -1069,11 +1069,10 @@␊
381 ␉␉{␊
382 ␉␉␉switch (Platform.CPU.Model) ␊
383 ␉␉␉{␊
384-␉␉␉␉case CPU_MODEL_DOTHAN: ␊
385-␉␉␉␉case CPU_MODEL_YONAH: // Yonah␊
386-␉␉␉␉case CPU_MODEL_MEROM: // Merom␊
387-␉␉␉␉case CPU_MODEL_PENRYN: // Penryn␊
388-␉␉␉␉case CPU_MODEL_ATOM: // Intel Atom (45nm)␊
389+␉␉␉␉case CPU_MODEL_YONAH:␊
390+␉␉␉␉case CPU_MODEL_MEROM:␊
391+␉␉␉␉case CPU_MODEL_PENRYN:␊
392+␉␉␉␉case CPU_MODEL_ATOM:␊
393 ␉␉␉␉{␊
394 ␉␉␉␉␉␊
395 ␉␉␉␉␉cpu->core_c1_supported = ((sub_Cstates >> 4) & 0xf) ? 1 : 0;␊
396@@ -1119,15 +1118,15 @@␊
397 ␉␉␉␉␉␊
398 ␉␉␉␉␉break;␊
399 ␉␉␉␉} ␊
400+␉␉␉␉case CPU_MODEL_NEHALEM:␊
401 ␉␉␉␉case CPU_MODEL_FIELDS:␊
402 ␉␉␉␉case CPU_MODEL_DALES:␊
403-␉␉␉␉case CPU_MODEL_CLARKDALE:␊
404-␉␉␉␉case CPU_MODEL_NEHALEM: ␊
405 ␉␉␉␉case CPU_MODEL_NEHALEM_EX:␊
406+␉␉␉␉case CPU_MODEL_DALES_32NM:␊
407 ␉␉␉␉case CPU_MODEL_WESTMERE:␊
408 ␉␉␉␉case CPU_MODEL_WESTMERE_EX:␊
409 ␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␊
410-␉␉␉␉case CPU_MODEL_SANDYBRIDGE_XEON:␊
411+␉␉␉␉case CPU_MODEL_JAKETOWN:␊
412 ␉␉␉␉{␉␉␊
413 ␉␉␉␉␉␊
414 ␉␉␉␉␉cpu->core_c1_supported = ((sub_Cstates >> 4) & 0xf) ? 1 : 0;␊
415@@ -1330,11 +1329,10 @@␊
416 ␉␉␉{␊
417 ␉␉␉␉switch (Platform.CPU.Model) ␊
418 ␉␉␉␉{␊
419-␉␉␉␉␉case CPU_MODEL_DOTHAN: ␊
420-␉␉␉␉␉case CPU_MODEL_YONAH: // Yonah␊
421-␉␉␉␉␉case CPU_MODEL_MEROM: // Merom␊
422-␉␉␉␉␉case CPU_MODEL_PENRYN: // Penryn␊
423-␉␉␉␉␉case CPU_MODEL_ATOM: // Intel Atom (45nm)␊
424+␉␉␉␉␉case CPU_MODEL_YONAH:␊
425+␉␉␉␉␉case CPU_MODEL_MEROM:␊
426+␉␉␉␉␉case CPU_MODEL_PENRYN:␊
427+␉␉␉␉␉case CPU_MODEL_ATOM:␊
428 ␉␉␉␉␉{␊
429 ␉␉␉␉␉␉bool cpu_dynamic_fsb = false;␊
430 ␉␉␉␉␉␉␊
431@@ -1453,15 +1451,15 @@␊
432 ␉␉␉␉␉␉}␊
433 ␉␉␉␉␉␉break;␊
434 ␉␉␉␉␉} ␊
435+␉␉␉␉␉case CPU_MODEL_NEHALEM:␊
436 ␉␉␉␉␉case CPU_MODEL_FIELDS:␊
437 ␉␉␉␉␉case CPU_MODEL_DALES:␊
438-␉␉␉␉␉case CPU_MODEL_CLARKDALE:␊
439-␉␉␉␉␉case CPU_MODEL_NEHALEM: ␊
440 ␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␊
441+␉␉␉␉␉case CPU_MODEL_DALES_32NM:␊
442 ␉␉␉␉␉case CPU_MODEL_WESTMERE:␊
443 ␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␊
444 ␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␊
445-␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE_XEON:␊
446+␉␉␉␉␉case CPU_MODEL_JAKETOWN:␊
447 ␉␉␉␉␉{␉␉␊
448 ␉␉␉␉␉␉␊
449 ␉␉␉␉␉␉maximum.Control = rdmsr64(MSR_IA32_PERF_STATUS) & 0xff; // Seems it always contains maximum multiplier value (with turbo, that's we need)...␊
450

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Attachment to issue 344

Created: 10 years 9 months ago by Alex J