Chameleon

Chameleon Commit Details

Date:2012-05-27 15:34:11 (2 years 2 months ago)
Author:ErmaC
Commit:1981
Parents: 1980
Message:Improvements and code cleanup.
Changes:
D/branches/ErmaC/Trunk/i386/libsaio/lzss.c
R/branches/ErmaC/Trunk/i386/libsaio/ati_reg.h → /branches/ErmaC/Trunk/i386/libsaio/ati.h
M/branches/ErmaC/Trunk/i386/boot2/gui.c
M/branches/ErmaC/Trunk/i386/libsaio/platform.h
M/branches/ErmaC/Trunk/i386/libsaio/Makefile
M/branches/ErmaC/Trunk/i386/libsaio/smbios.c
M/branches/ErmaC/Trunk/i386/libsaio/ati.c
M/branches/ErmaC/Trunk/i386/boot2/lzss.c
M/branches/ErmaC/Trunk/i386/libsaio/gma.c

File differences

branches/ErmaC/Trunk/i386/libsaio/ati_reg.h
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311
2312
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432
2433
2434
2435
2436
2437
2438
2439
2440
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467
2468
2469
2470
2471
2472
2473
2474
2475
2476
2477
2478
2479
2480
2481
2482
2483
2484
2485
2486
2487
2488
2489
2490
2491
2492
2493
2494
2495
2496
2497
2498
2499
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510
2511
2512
2513
2514
2515
2516
2517
2518
2519
2520
2521
2522
2523
2524
2525
2526
2527
2528
2529
2530
2531
2532
2533
2534
2535
2536
2537
2538
2539
2540
2541
2542
2543
2544
2545
2546
2547
2548
2549
2550
2551
2552
2553
2554
2555
2556
2557
2558
2559
2560
2561
2562
2563
2564
2565
2566
2567
2568
2569
2570
2571
2572
2573
2574
2575
2576
2577
2578
2579
2580
2581
2582
2583
2584
2585
2586
2587
2588
2589
2590
2591
2592
2593
2594
2595
2596
2597
2598
2599
2600
2601
2602
2603
2604
2605
2606
2607
2608
2609
2610
2611
2612
2613
2614
2615
2616
2617
2618
2619
2620
2621
2622
2623
2624
2625
2626
2627
2628
2629
2630
2631
2632
2633
2634
2635
2636
2637
2638
2639
2640
2641
2642
2643
2644
2645
2646
2647
2648
2649
2650
2651
2652
2653
2654
2655
2656
2657
2658
2659
2660
2661
2662
2663
2664
2665
2666
2667
2668
2669
2670
2671
2672
2673
2674
2675
2676
2677
2678
2679
2680
2681
2682
2683
2684
2685
2686
2687
2688
2689
2690
2691
2692
2693
2694
2695
2696
2697
2698
2699
2700
2701
2702
2703
2704
2705
2706
2707
2708
2709
2710
2711
2712
2713
2714
2715
2716
2717
2718
2719
2720
2721
2722
2723
2724
2725
2726
2727
2728
2729
2730
2731
2732
2733
2734
2735
2736
2737
2738
2739
2740
2741
2742
2743
2744
2745
2746
2747
2748
2749
2750
2751
2752
2753
2754
2755
2756
2757
2758
2759
2760
2761
2762
2763
2764
2765
2766
2767
2768
2769
2770
2771
2772
2773
2774
2775
2776
2777
2778
2779
2780
2781
2782
2783
2784
2785
2786
2787
2788
2789
2790
2791
2792
2793
2794
2795
2796
2797
2798
2799
2800
2801
2802
2803
2804
2805
2806
2807
2808
2809
2810
2811
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821
2822
2823
2824
2825
2826
2827
2828
2829
2830
2831
2832
2833
2834
2835
2836
2837
2838
2839
2840
2841
2842
2843
2844
2845
2846
2847
2848
2849
2850
2851
2852
2853
2854
2855
2856
2857
2858
2859
2860
2861
2862
2863
2864
2865
2866
2867
2868
2869
2870
2871
2872
2873
2874
2875
2876
2877
2878
2879
2880
2881
2882
2883
2884
2885
2886
2887
2888
2889
2890
2891
2892
2893
2894
2895
2896
2897
2898
2899
2900
2901
2902
2903
2904
2905
2906
2907
2908
2909
2910
2911
2912
2913
2914
2915
2916
2917
2918
2919
2920
2921
2922
2923
2924
2925
2926
2927
2928
2929
2930
2931
2932
2933
2934
2935
2936
2937
2938
2939
2940
2941
2942
2943
2944
2945
2946
2947
2948
2949
2950
2951
2952
2953
2954
2955
2956
2957
2958
2959
2960
2961
2962
2963
2964
2965
2966
2967
2968
2969
2970
2971
2972
2973
2974
2975
2976
2977
2978
2979
2980
2981
2982
2983
2984
2985
2986
2987
2988
2989
2990
2991
2992
2993
2994
2995
2996
2997
2998
2999
3000
3001
3002
3003
3004
3005
3006
3007
3008
3009
3010
3011
3012
3013
3014
3015
3016
3017
3018
3019
3020
3021
3022
3023
3024
3025
3026
3027
3028
3029
3030
3031
3032
3033
3034
3035
3036
3037
3038
3039
3040
3041
3042
3043
3044
3045
3046
3047
3048
3049
3050
3051
3052
3053
3054
3055
3056
3057
3058
3059
3060
3061
3062
3063
3064
3065
3066
3067
3068
3069
3070
3071
3072
3073
3074
3075
3076
3077
3078
3079
3080
3081
3082
3083
3084
3085
3086
3087
3088
3089
3090
3091
3092
3093
3094
3095
3096
3097
3098
3099
3100
3101
3102
3103
3104
3105
3106
3107
3108
3109
3110
3111
3112
3113
3114
3115
3116
3117
3118
3119
3120
3121
3122
3123
3124
3125
3126
3127
3128
3129
3130
3131
3132
3133
3134
3135
3136
3137
3138
3139
3140
3141
3142
3143
3144
3145
3146
3147
3148
3149
3150
3151
3152
3153
3154
3155
3156
3157
3158
3159
3160
3161
3162
3163
3164
3165
3166
3167
3168
3169
3170
3171
3172
3173
3174
3175
3176
3177
3178
3179
3180
3181
3182
3183
3184
3185
3186
3187
3188
3189
3190
3191
3192
3193
3194
3195
3196
3197
3198
3199
3200
3201
3202
3203
3204
3205
3206
3207
3208
3209
3210
3211
3212
3213
3214
3215
3216
3217
3218
3219
3220
3221
3222
3223
3224
3225
3226
3227
3228
3229
3230
3231
3232
3233
3234
3235
3236
3237
3238
3239
3240
3241
3242
3243
3244
3245
3246
3247
3248
3249
3250
3251
3252
3253
3254
3255
3256
3257
3258
3259
3260
3261
3262
3263
3264
3265
3266
3267
3268
3269
3270
3271
3272
3273
3274
3275
3276
3277
3278
3279
3280
3281
3282
3283
3284
3285
3286
3287
3288
3289
3290
3291
3292
3293
3294
3295
3296
3297
3298
3299
3300
3301
3302
3303
3304
3305
3306
3307
3308
3309
3310
3311
3312
3313
3314
3315
3316
3317
3318
3319
3320
3321
3322
3323
3324
3325
3326
3327
3328
3329
3330
3331
3332
3333
3334
3335
3336
3337
3338
3339
3340
3341
3342
3343
3344
3345
3346
3347
3348
3349
3350
3351
3352
3353
3354
3355
3356
3357
3358
3359
3360
3361
3362
3363
3364
3365
3366
3367
3368
3369
3370
3371
3372
3373
3374
3375
3376
3377
3378
3379
3380
3381
3382
3383
3384
3385
3386
3387
3388
3389
3390
3391
3392
3393
3394
3395
3396
3397
3398
3399
3400
3401
3402
3403
3404
3405
3406
3407
3408
3409
3410
3411
3412
3413
3414
3415
3416
3417
3418
3419
3420
3421
3422
3423
3424
3425
3426
3427
3428
3429
3430
3431
3432
3433
3434
3435
3436
3437
3438
3439
3440
3441
3442
3443
3444
3445
3446
3447
3448
3449
3450
3451
3452
3453
3454
3455
3456
3457
3458
3459
3460
3461
3462
3463
3464
3465
3466
3467
3468
3469
3470
3471
3472
3473
3474
3475
3476
3477
3478
3479
3480
3481
3482
3483
3484
3485
3486
3487
3488
3489
3490
3491
3492
3493
3494
3495
3496
3497
3498
3499
3500
3501
3502
3503
3504
3505
3506
3507
3508
3509
3510
3511
3512
3513
3514
3515
3516
3517
3518
3519
3520
3521
3522
3523
3524
3525
3526
3527
3528
3529
3530
3531
3532
3533
3534
3535
3536
3537
3538
3539
3540
3541
3542
3543
3544
3545
3546
3547
3548
3549
3550
3551
3552
3553
3554
3555
3556
3557
3558
3559
3560
3561
3562
3563
3564
3565
3566
3567
3568
3569
3570
3571
3572
3573
3574
3575
3576
3577
3578
3579
3580
3581
3582
3583
3584
3585
3586
3587
3588
3589
3590
3591
3592
3593
3594
3595
3596
3597
3598
3599
3600
3601
3602
3603
3604
3605
3606
3607
3608
3609
3610
3611
3612
3613
3614
3615
3616
3617
3618
3619
3620
3621
3622
3623
3624
3625
3626
3627
3628
3629
3630
3631
3632
3633
3634
3635
3636
3637
3638
3639
3640
3641
3642
3643
3644
3645
3646
3647
3648
3649
3650
3651
3652
3653
3654
3655
3656
3657
3658
3659
3660
3661
3662
3663
3664
3665
3666
3667
3668
3669
3670
3671
3672
3673
3674
3675
3676
3677
3678
3679
3680
3681
3682
3683
3684
3685
3686
3687
3688
3689
3690
3691
3692
3693
3694
3695
3696
3697
3698
3699
3700
3701
3702
3703
3704
3705
3706
3707
3708
3709
3710
3711
3712
3713
3714
3715
3716
3717
3718
3719
3720
3721
3722
3723
3724
3725
3726
3727
3728
3729
3730
3731
3732
3733
3734
3735
3736
3737
3738
3739
3740
3741
3742
3743
3744
3745
3746
3747
3748
3749
3750
3751
3752
3753
3754
3755
3756
3757
3758
3759
3760
3761
3762
3763
3764
3765
3766
3767
3768
3769
3770
3771
3772
3773
3774
3775
3776
3777
3778
3779
3780
3781
3782
3783
3784
3785
3786
3787
3788
3789
3790
3791
3792
3793
3794
3795
3796
3797
3798
3799
3800
3801
3802
3803
3804
3805
3806
3807
3808
3809
3810
3811
3812
3813
3814
3815
3816
3817
3818
3819
3820
3821
3822
3823
3824
3825
3826
3827
3828
3829
3830
3831
3832
3833
3834
3835
3836
3837
3838
3839
3840
3841
3842
3843
3844
3845
3846
3847
3848
3849
3850
3851
3852
3853
3854
3855
3856
3857
3858
3859
3860
3861
3862
3863
3864
3865
3866
3867
3868
3869
3870
3871
3872
3873
3874
3875
3876
3877
3878
3879
3880
3881
3882
3883
3884
3885
3886
3887
3888
3889
3890
3891
3892
3893
3894
3895
3896
3897
3898
3899
3900
3901
3902
3903
3904
3905
3906
3907
3908
3909
3910
3911
3912
3913
3914
3915
3916
3917
3918
3919
3920
3921
3922
3923
3924
3925
3926
3927
3928
3929
3930
3931
3932
3933
3934
3935
3936
3937
3938
3939
3940
3941
3942
3943
3944
3945
3946
3947
3948
3949
3950
3951
3952
3953
3954
3955
3956
3957
3958
3959
3960
3961
3962
3963
3964
3965
3966
3967
3968
3969
3970
3971
3972
3973
3974
3975
3976
3977
3978
3979
3980
3981
3982
3983
3984
3985
3986
3987
3988
3989
3990
3991
3992
3993
3994
3995
3996
3997
3998
3999
4000
4001
4002
4003
4004
4005
4006
4007
4008
4009
4010
4011
4012
4013
4014
4015
4016
4017
4018
4019
4020
4021
4022
4023
4024
4025
4026
4027
4028
4029
4030
4031
4032
4033
4034
4035
4036
4037
4038
4039
4040
4041
4042
4043
4044
4045
4046
4047
4048
4049
4050
4051
4052
4053
4054
4055
4056
4057
4058
4059
4060
4061
4062
4063
4064
4065
4066
4067
4068
4069
4070
4071
4072
4073
4074
4075
4076
4077
4078
4079
4080
4081
4082
4083
4084
4085
4086
4087
4088
4089
4090
4091
4092
4093
4094
4095
4096
4097
4098
4099
4100
4101
4102
4103
4104
4105
4106
4107
4108
4109
4110
4111
4112
4113
4114
4115
4116
4117
4118
4119
4120
4121
4122
4123
4124
4125
4126
4127
4128
4129
4130
4131
4132
4133
4134
4135
4136
4137
4138
4139
4140
4141
4142
4143
4144
4145
4146
4147
4148
4149
4150
4151
4152
4153
4154
4155
4156
4157
4158
4159
4160
4161
4162
4163
4164
4165
4166
4167
4168
4169
4170
4171
4172
4173
4174
4175
4176
4177
4178
4179
4180
4181
4182
4183
4184
4185
4186
4187
4188
4189
4190
4191
4192
4193
4194
4195
4196
4197
4198
4199
4200
4201
4202
4203
4204
4205
4206
4207
4208
4209
4210
4211
4212
4213
4214
4215
4216
4217
4218
4219
4220
4221
4222
4223
4224
4225
4226
4227
4228
4229
4230
4231
4232
4233
4234
4235
4236
4237
4238
4239
4240
4241
4242
4243
4244
4245
4246
4247
4248
4249
4250
4251
4252
4253
4254
4255
4256
4257
4258
4259
4260
4261
4262
4263
4264
4265
4266
4267
4268
4269
4270
4271
4272
4273
4274
4275
4276
4277
4278
4279
4280
4281
4282
4283
4284
4285
4286
4287
4288
4289
4290
4291
4292
4293
4294
4295
4296
4297
4298
4299
4300
4301
4302
4303
4304
4305
4306
4307
4308
4309
4310
4311
4312
4313
4314
4315
4316
4317
4318
4319
4320
4321
4322
4323
4324
4325
4326
4327
4328
4329
4330
4331
4332
4333
4334
4335
4336
4337
4338
4339
4340
4341
4342
4343
4344
4345
4346
4347
4348
4349
4350
4351
4352
4353
4354
4355
4356
4357
4358
4359
4360
4361
4362
4363
4364
4365
4366
4367
4368
4369
4370
4371
4372
4373
4374
4375
4376
4377
4378
4379
4380
4381
4382
4383
4384
4385
4386
4387
4388
4389
4390
4391
4392
4393
4394
4395
4396
4397
4398
4399
4400
4401
4402
4403
4404
4405
4406
4407
4408
4409
4410
4411
4412
4413
4414
4415
4416
4417
4418
4419
4420
4421
4422
4423
4424
4425
4426
4427
4428
4429
4430
4431
4432
4433
4434
4435
4436
4437
4438
4439
4440
4441
4442
4443
4444
4445
4446
4447
4448
4449
4450
4451
4452
4453
4454
4455
4456
4457
4458
4459
4460
4461
4462
4463
4464
4465
4466
4467
4468
4469
4470
4471
4472
4473
4474
4475
4476
4477
4478
4479
4480
4481
4482
4483
4484
4485
4486
4487
4488
4489
4490
4491
4492
4493
4494
4495
4496
4497
4498
4499
4500
4501
4502
4503
4504
4505
4506
4507
4508
4509
4510
4511
4512
4513
4514
4515
4516
4517
4518
4519
4520
4521
4522
4523
4524
4525
4526
4527
4528
4529
4530
4531
4532
4533
4534
4535
4536
4537
4538
4539
4540
4541
4542
4543
4544
4545
4546
4547
4548
4549
4550
4551
4552
4553
4554
4555
4556
4557
4558
4559
4560
4561
4562
4563
4564
4565
4566
4567
4568
4569
4570
4571
4572
4573
4574
4575
4576
4577
4578
4579
4580
4581
4582
4583
4584
4585
4586
4587
4588
4589
4590
4591
4592
4593
4594
4595
4596
4597
4598
4599
4600
4601
4602
4603
4604
4605
4606
4607
4608
4609
4610
4611
4612
4613
4614
4615
4616
4617
4618
4619
4620
4621
4622
4623
4624
4625
4626
4627
4628
4629
4630
4631
4632
4633
4634
4635
4636
4637
4638
4639
4640
4641
4642
4643
4644
4645
4646
4647
4648
4649
4650
4651
4652
4653
4654
4655
4656
4657
4658
4659
4660
4661
4662
4663
4664
4665
4666
4667
4668
4669
4670
4671
4672
4673
4674
4675
4676
4677
4678
4679
4680
4681
4682
4683
4684
4685
4686
4687
4688
4689
4690
4691
4692
4693
4694
4695
4696
4697
4698
4699
4700
4701
4702
4703
4704
4705
4706
4707
4708
4709
4710
4711
4712
4713
4714
4715
4716
4717
4718
4719
4720
4721
4722
4723
4724
4725
4726
4727
4728
4729
4730
4731
4732
4733
4734
4735
4736
4737
4738
4739
4740
4741
4742
4743
4744
4745
4746
4747
4748
4749
4750
4751
4752
4753
4754
4755
4756
4757
4758
4759
4760
4761
4762
4763
4764
4765
4766
4767
4768
4769
4770
4771
4772
4773
4774
4775
4776
4777
4778
4779
4780
4781
4782
4783
4784
4785
4786
4787
4788
4789
4790
4791
4792
4793
4794
4795
4796
4797
4798
4799
4800
4801
4802
4803
4804
4805
4806
4807
4808
4809
4810
4811
4812
4813
4814
4815
4816
4817
4818
4819
4820
4821
4822
4823
4824
4825
4826
4827
4828
4829
4830
4831
4832
4833
4834
4835
4836
4837
4838
4839
4840
4841
4842
4843
4844
4845
4846
4847
4848
4849
4850
4851
4852
4853
4854
4855
4856
4857
4858
4859
4860
4861
4862
4863
4864
4865
4866
4867
4868
4869
4870
4871
4872
4873
4874
4875
4876
4877
4878
4879
4880
4881
4882
4883
4884
4885
4886
4887
4888
4889
4890
4891
4892
4893
4894
4895
4896
4897
4898
4899
4900
4901
4902
4903
4904
4905
4906
4907
4908
4909
4910
4911
4912
4913
4914
4915
4916
4917
4918
4919
4920
4921
4922
4923
4924
4925
4926
4927
4928
4929
4930
4931
4932
4933
4934
4935
4936
4937
4938
4939
4940
4941
4942
4943
4944
4945
4946
4947
4948
4949
4950
4951
4952
4953
4954
4955
4956
4957
4958
4959
4960
4961
4962
4963
4964
4965
4966
4967
4968
4969
4970
4971
4972
4973
4974
4975
4976
4977
4978
4979
4980
4981
4982
4983
4984
4985
4986
4987
4988
4989
4990
4991
4992
4993
4994
4995
4996
4997
4998
4999
5000
5001
5002
5003
5004
5005
5006
5007
5008
5009
5010
5011
5012
5013
5014
5015
5016
5017
5018
5019
5020
5021
5022
5023
5024
5025
5026
5027
5028
5029
5030
5031
5032
5033
5034
5035
5036
5037
5038
5039
5040
5041
5042
5043
5044
5045
5046
5047
5048
5049
5050
5051
5052
5053
5054
5055
5056
5057
5058
5059
5060
5061
5062
5063
5064
5065
5066
5067
5068
5069
5070
5071
5072
5073
5074
5075
5076
5077
5078
5079
5080
5081
5082
5083
5084
5085
5086
5087
5088
5089
5090
5091
5092
5093
5094
5095
5096
5097
5098
5099
5100
5101
5102
5103
5104
5105
5106
5107
5108
5109
5110
5111
5112
5113
5114
5115
5116
5117
5118
5119
5120
5121
5122
5123
5124
5125
5126
5127
5128
5129
5130
5131
5132
5133
5134
5135
5136
5137
5138
5139
5140
5141
5142
5143
5144
5145
5146
5147
5148
5149
5150
5151
5152
5153
5154
5155
5156
5157
5158
5159
5160
5161
5162
5163
5164
5165
5166
5167
5168
5169
5170
5171
5172
5173
5174
5175
5176
5177
5178
5179
5180
5181
5182
5183
5184
5185
5186
5187
5188
5189
5190
5191
5192
5193
5194
5195
5196
5197
5198
5199
5200
5201
5202
5203
5204
5205
5206
5207
5208
5209
5210
5211
5212
5213
5214
5215
5216
5217
5218
5219
5220
5221
5222
5223
5224
5225
5226
5227
5228
5229
5230
5231
5232
5233
5234
5235
5236
5237
5238
5239
5240
5241
5242
5243
5244
5245
5246
5247
5248
5249
5250
5251
5252
5253
5254
5255
5256
5257
5258
5259
5260
5261
5262
5263
5264
5265
5266
5267
5268
5269
5270
5271
5272
5273
5274
5275
5276
5277
5278
5279
5280
5281
5282
5283
5284
5285
5286
5287
5288
5289
5290
5291
5292
5293
5294
5295
5296
5297
5298
5299
5300
5301
5302
5303
5304
5305
5306
5307
5308
5309
5310
5311
5312
5313
5314
5315
5316
5317
5318
5319
5320
5321
5322
5323
5324
5325
5326
5327
5328
5329
5330
5331
5332
5333
5334
5335
5336
5337
5338
5339
5340
5341
5342
5343
5344
5345
5346
5347
5348
5349
5350
5351
5352
5353
5354
5355
5356
5357
5358
5359
5360
5361
5362
5363
5364
5365
5366
5367
5368
5369
5370
5371
5372
5373
5374
5375
5376
5377
5378
5379
5380
5381
5382
5383
5384
5385
5386
5387
5388
5389
5390
5391
5392
5393
5394
5395
5396
5397
5398
5399
5400
5401
5402
5403
5404
5405
5406
5407
5408
5409
5410
5411
5412
5413
5414
5415
5416
5417
5418
5419
5420
5421
5422
5423
5424
5425
5426
5427
5428
5429
5430
5431
5432
5433
5434
5435
5436
5437
5438
5439
5440
5441
5442
5443
5444
5445
5446
5447
5448
5449
5450
5451
5452
5453
5454
5455
5456
5457
5458
5459
5460
5461
5462
5463
5464
5465
5466
5467
5468
5469
5470
5471
5472
5473
5474
5475
5476
5477
5478
5479
5480
5481
5482
5483
5484
5485
5486
5487
5488
5489
5490
5491
5492
5493
5494
5495
5496
5497
5498
5499
5500
5501
5502
5503
5504
5505
5506
5507
5508
5509
5510
5511
5512
5513
5514
5515
5516
5517
5518
5519
5520
5521
5522
5523
5524
5525
5526
5527
5528
5529
5530
5531
5532
5533
5534
5535
5536
5537
5538
5539
5540
5541
5542
5543
5544
5545
5546
5547
5548
5549
5550
5551
5552
5553
5554
5555
5556
5557
5558
5559
5560
5561
5562
5563
5564
5565
5566
5567
5568
5569
5570
5571
5572
5573
5574
5575
5576
5577
5578
5579
5580
5581
5582
5583
5584
5585
5586
5587
5588
5589
5590
5591
5592
5593
5594
5595
5596
5597
5598
5599
5600
5601
5602
5603
5604
5605
5606
5607
5608
5609
5610
5611
5612
5613
5614
5615
5616
5617
5618
5619
5620
5621
5622
5623
5624
5625
5626
5627
5628
5629
5630
5631
5632
5633
5634
5635
5636
5637
5638
5639
5640
5641
5642
5643
5644
5645
5646
5647
5648
5649
5650
5651
5652
5653
5654
5655
5656
5657
5658
5659
5660
5661
5662
5663
5664
5665
5666
5667
5668
5669
5670
5671
5672
/*
* Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
* VA Linux Systems Inc., Fremont, California.
*
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation on the rights to use, copy, modify, merge,
* publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
* THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
/*
* Authors:
* Kevin E. Martin <martin@xfree86.org>
* Rickard E. Faith <faith@valinux.com>
* Alan Hourihane <alanh@fairlite.demon.co.uk>
*
* References:
*
* !!!! FIXME !!!!
* RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical
* Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April
* 1999.
*
* !!!! FIXME !!!!
* RAGE 128 Software Development Manual (Technical Reference Manual P/N
* SDK-G04000 Rev. 0.01), ATI Technologies: June 1999.
*
*/
/* !!!! FIXME !!!! NOTE: THIS FILE HAS BEEN CONVERTED FROM r128_reg.h
* AND CONTAINS REGISTERS AND REGISTER DEFINITIONS THAT ARE NOT CORRECT
* ON THE RADEON. A FULL AUDIT OF THIS CODE IS NEEDED! */
#ifndef _ATI_REG_H_
#define _ATI_REG_H_
#define ATI_DATATYPE_VQ0
#define ATI_DATATYPE_CI41
#define ATI_DATATYPE_CI82
#define ATI_DATATYPE_ARGB15553
#define ATI_DATATYPE_RGB5654
#define ATI_DATATYPE_RGB8885
#define ATI_DATATYPE_ARGB88886
#define ATI_DATATYPE_RGB3327
#define ATI_DATATYPE_Y88
#define ATI_DATATYPE_RGB89
#define ATI_DATATYPE_CI1610
#define ATI_DATATYPE_VYUY_42211
#define ATI_DATATYPE_YVYU_42212
#define ATI_DATATYPE_AYUV_44414
#define ATI_DATATYPE_ARGB444415
/* Registers for 2D/Video/Overlay */
#define RADEON_ADAPTER_ID 0x0f2c /* PCI */
#define RADEON_AGP_BASE 0x0170
#define RADEON_AGP_CNTL 0x0174
# define RADEON_AGP_APER_SIZE_256MB (0x00 << 0)
# define RADEON_AGP_APER_SIZE_128MB (0x20 << 0)
# define RADEON_AGP_APER_SIZE_64MB (0x30 << 0)
# define RADEON_AGP_APER_SIZE_32MB (0x38 << 0)
# define RADEON_AGP_APER_SIZE_16MB (0x3c << 0)
# define RADEON_AGP_APER_SIZE_8MB (0x3e << 0)
# define RADEON_AGP_APER_SIZE_4MB (0x3f << 0)
# define RADEON_AGP_APER_SIZE_MASK (0x3f << 0)
#define RADEON_STATUS_PCI_CONFIG 0x06
# define RADEON_CAP_LIST 0x100000
#define RADEON_CAPABILITIES_PTR_PCI_CONFIG 0x34 /* offset in PCI config*/
# define RADEON_CAP_PTR_MASK 0xfc /* mask off reserved bits of CAP_PTR */
# define RADEON_CAP_ID_NULL 0x00 /* End of capability list */
# define RADEON_CAP_ID_AGP 0x02 /* AGP capability ID */
# define RADEON_CAP_ID_EXP 0x10 /* PCI Express */
#define RADEON_AGP_COMMAND 0x0f60 /* PCI */
#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config*/
# define RADEON_AGP_ENABLE (1<<8)
#define RADEON_AGP_PLL_CNTL 0x000b /* PLL */
#define RADEON_AGP_STATUS 0x0f5c /* PCI */
# define RADEON_AGP_1X_MODE 0x01
# define RADEON_AGP_2X_MODE 0x02
# define RADEON_AGP_4X_MODE 0x04
# define RADEON_AGP_FW_MODE 0x10
# define RADEON_AGP_MODE_MASK 0x17
# define RADEON_AGPv3_MODE 0x08
# define RADEON_AGPv3_4X_MODE 0x01
# define RADEON_AGPv3_8X_MODE 0x02
#define RADEON_ATTRDR 0x03c1 /* VGA */
#define RADEON_ATTRDW 0x03c0 /* VGA */
#define RADEON_ATTRX 0x03c0 /* VGA */
#define RADEON_AUX_WINDOW_HORZ_CNTL 0x02d8
#define RADEON_AUX_WINDOW_VERT_CNTL 0x02dc
#define RADEON_BASE_CODE 0x0f0b
#define RADEON_BIOS_0_SCRATCH 0x0010
# define RADEON_FP_PANEL_SCALABLE (1 << 16)
# define RADEON_FP_PANEL_SCALE_EN (1 << 17)
# define RADEON_FP_CHIP_SCALE_EN (1 << 18)
# define RADEON_DRIVER_BRIGHTNESS_EN (1 << 26)
# define RADEON_DISPLAY_ROT_MASK (3 << 28)
# define RADEON_DISPLAY_ROT_00 (0 << 28)
# define RADEON_DISPLAY_ROT_90 (1 << 28)
# define RADEON_DISPLAY_ROT_180 (2 << 28)
# define RADEON_DISPLAY_ROT_270 (3 << 28)
#define RADEON_BIOS_1_SCRATCH 0x0014
#define RADEON_BIOS_2_SCRATCH 0x0018
#define RADEON_BIOS_3_SCRATCH 0x001c
#define RADEON_BIOS_4_SCRATCH 0x0020
# define RADEON_CRT1_ATTACHED_MASK (3 << 0)
# define RADEON_CRT1_ATTACHED_MONO (1 << 0)
# define RADEON_CRT1_ATTACHED_COLOR (2 << 0)
# define RADEON_LCD1_ATTACHED (1 << 2)
# define RADEON_DFP1_ATTACHED (1 << 3)
# define RADEON_TV1_ATTACHED_MASK (3 << 4)
# define RADEON_TV1_ATTACHED_COMP (1 << 4)
# define RADEON_TV1_ATTACHED_SVIDEO (2 << 4)
# define RADEON_CRT2_ATTACHED_MASK (3 << 8)
# define RADEON_CRT2_ATTACHED_MONO (1 << 8)
# define RADEON_CRT2_ATTACHED_COLOR (2 << 8)
# define RADEON_DFP2_ATTACHED (1 << 11)
#define RADEON_BIOS_5_SCRATCH 0x0024
# define RADEON_LCD1_ON (1 << 0)
# define RADEON_CRT1_ON (1 << 1)
# define RADEON_TV1_ON (1 << 2)
# define RADEON_DFP1_ON (1 << 3)
# define RADEON_CRT2_ON (1 << 5)
# define RADEON_CV1_ON (1 << 6)
# define RADEON_DFP2_ON (1 << 7)
# define RADEON_LCD1_CRTC_MASK (1 << 8)
# define RADEON_LCD1_CRTC_SHIFT 8
# define RADEON_CRT1_CRTC_MASK (1 << 9)
# define RADEON_CRT1_CRTC_SHIFT 9
# define RADEON_TV1_CRTC_MASK (1 << 10)
# define RADEON_TV1_CRTC_SHIFT 10
# define RADEON_DFP1_CRTC_MASK (1 << 11)
# define RADEON_DFP1_CRTC_SHIFT 11
# define RADEON_CRT2_CRTC_MASK (1 << 12)
# define RADEON_CRT2_CRTC_SHIFT 12
# define RADEON_CV1_CRTC_MASK (1 << 13)
# define RADEON_CV1_CRTC_SHIFT 13
# define RADEON_DFP2_CRTC_MASK (1 << 14)
# define RADEON_DFP2_CRTC_SHIFT 14
#define RADEON_BIOS_6_SCRATCH 0x0028
# define RADEON_ACC_MODE_CHANGE (1 << 2)
# define RADEON_EXT_DESKTOP_MODE (1 << 3)
# define RADEON_LCD_DPMS_ON (1 << 20)
# define RADEON_CRT_DPMS_ON (1 << 21)
# define RADEON_TV_DPMS_ON (1 << 22)
# define RADEON_DFP_DPMS_ON (1 << 23)
# define RADEON_DPMS_MASK (3 << 24)
# define RADEON_DPMS_ON (0 << 24)
# define RADEON_DPMS_STANDBY (1 << 24)
# define RADEON_DPMS_SUSPEND (2 << 24)
# define RADEON_DPMS_OFF (3 << 24)
# define RADEON_SCREEN_BLANKING (1 << 26)
# define RADEON_DRIVER_CRITICAL (1 << 27)
# define RADEON_DISPLAY_SWITCHING_DIS (1 << 30)
#define RADEON_BIOS_7_SCRATCH 0x002c
# define RADEON_SYS_HOTKEY (1 << 10)
# define RADEON_DRV_LOADED (1 << 12)
#define RADEON_BIOS_ROM 0x0f30 /* PCI */
#define RADEON_BIST 0x0f0f /* PCI */
#define RADEON_BRUSH_DATA0 0x1480
#define RADEON_BRUSH_DATA1 0x1484
#define RADEON_BRUSH_DATA10 0x14a8
#define RADEON_BRUSH_DATA11 0x14ac
#define RADEON_BRUSH_DATA12 0x14b0
#define RADEON_BRUSH_DATA13 0x14b4
#define RADEON_BRUSH_DATA14 0x14b8
#define RADEON_BRUSH_DATA15 0x14bc
#define RADEON_BRUSH_DATA16 0x14c0
#define RADEON_BRUSH_DATA17 0x14c4
#define RADEON_BRUSH_DATA18 0x14c8
#define RADEON_BRUSH_DATA19 0x14cc
#define RADEON_BRUSH_DATA2 0x1488
#define RADEON_BRUSH_DATA20 0x14d0
#define RADEON_BRUSH_DATA21 0x14d4
#define RADEON_BRUSH_DATA22 0x14d8
#define RADEON_BRUSH_DATA23 0x14dc
#define RADEON_BRUSH_DATA24 0x14e0
#define RADEON_BRUSH_DATA25 0x14e4
#define RADEON_BRUSH_DATA26 0x14e8
#define RADEON_BRUSH_DATA27 0x14ec
#define RADEON_BRUSH_DATA28 0x14f0
#define RADEON_BRUSH_DATA29 0x14f4
#define RADEON_BRUSH_DATA3 0x148c
#define RADEON_BRUSH_DATA30 0x14f8
#define RADEON_BRUSH_DATA31 0x14fc
#define RADEON_BRUSH_DATA32 0x1500
#define RADEON_BRUSH_DATA33 0x1504
#define RADEON_BRUSH_DATA34 0x1508
#define RADEON_BRUSH_DATA35 0x150c
#define RADEON_BRUSH_DATA36 0x1510
#define RADEON_BRUSH_DATA37 0x1514
#define RADEON_BRUSH_DATA38 0x1518
#define RADEON_BRUSH_DATA39 0x151c
#define RADEON_BRUSH_DATA4 0x1490
#define RADEON_BRUSH_DATA40 0x1520
#define RADEON_BRUSH_DATA41 0x1524
#define RADEON_BRUSH_DATA42 0x1528
#define RADEON_BRUSH_DATA43 0x152c
#define RADEON_BRUSH_DATA44 0x1530
#define RADEON_BRUSH_DATA45 0x1534
#define RADEON_BRUSH_DATA46 0x1538
#define RADEON_BRUSH_DATA47 0x153c
#define RADEON_BRUSH_DATA48 0x1540
#define RADEON_BRUSH_DATA49 0x1544
#define RADEON_BRUSH_DATA5 0x1494
#define RADEON_BRUSH_DATA50 0x1548
#define RADEON_BRUSH_DATA51 0x154c
#define RADEON_BRUSH_DATA52 0x1550
#define RADEON_BRUSH_DATA53 0x1554
#define RADEON_BRUSH_DATA54 0x1558
#define RADEON_BRUSH_DATA55 0x155c
#define RADEON_BRUSH_DATA56 0x1560
#define RADEON_BRUSH_DATA57 0x1564
#define RADEON_BRUSH_DATA58 0x1568
#define RADEON_BRUSH_DATA59 0x156c
#define RADEON_BRUSH_DATA6 0x1498
#define RADEON_BRUSH_DATA60 0x1570
#define RADEON_BRUSH_DATA61 0x1574
#define RADEON_BRUSH_DATA62 0x1578
#define RADEON_BRUSH_DATA63 0x157c
#define RADEON_BRUSH_DATA7 0x149c
#define RADEON_BRUSH_DATA8 0x14a0
#define RADEON_BRUSH_DATA9 0x14a4
#define RADEON_BRUSH_SCALE 0x1470
#define RADEON_BRUSH_Y_X 0x1474
#define RADEON_BUS_CNTL 0x0030
# define RADEON_BUS_MASTER_DIS (1 << 6)
# define RADEON_BUS_BIOS_DIS_ROM (1 << 12)
# define RADEON_BUS_RD_DISCARD_EN (1 << 24)
# define RADEON_BUS_RD_ABORT_EN (1 << 25)
# define RADEON_BUS_MSTR_DISCONNECT_EN (1 << 28)
# define RADEON_BUS_WRT_BURST (1 << 29)
# define RADEON_BUS_READ_BURST (1 << 30)
#define RADEON_BUS_CNTL1 0x0034
# define RADEON_BUS_WAIT_ON_LOCK_EN (1 << 4)
#define RADEON_PCIE_INDEX 0x0030
#define RADEON_PCIE_DATA 0x0034
#define R600_PCIE_PORT_INDEX 0x0038
#define R600_PCIE_PORT_DATA 0x003c
/* PCIE_LC_LINK_WIDTH_CNTL is PCIE on r1xx-r5xx, PCIE_PORT on r6xx-r7xx */
#define RADEON_PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE */
# define RADEON_PCIE_LC_LINK_WIDTH_SHIFT 0
# define RADEON_PCIE_LC_LINK_WIDTH_MASK 0x7
# define RADEON_PCIE_LC_LINK_WIDTH_X0 0
# define RADEON_PCIE_LC_LINK_WIDTH_X1 1
# define RADEON_PCIE_LC_LINK_WIDTH_X2 2
# define RADEON_PCIE_LC_LINK_WIDTH_X4 3
# define RADEON_PCIE_LC_LINK_WIDTH_X8 4
# define RADEON_PCIE_LC_LINK_WIDTH_X12 5
# define RADEON_PCIE_LC_LINK_WIDTH_X16 6
# define RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT 4
# define RADEON_PCIE_LC_LINK_WIDTH_RD_MASK 0x70
# define R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)
# define RADEON_PCIE_LC_RECONFIG_NOW (1 << 8)
# define RADEON_PCIE_LC_RECONFIG_LATER (1 << 9)
# define RADEON_PCIE_LC_SHORT_RECONFIG_EN (1 << 10)
# define R600_PCIE_LC_RENEGOTIATE_EN (1 << 10)
# define R600_PCIE_LC_SHORT_RECONFIG_EN (1 << 11)
#define R600_TARGET_AND_CURRENT_PROFILE_INDEX 0x70c
#define R700_TARGET_AND_CURRENT_PROFILE_INDEX 0x66c
#define RADEON_CACHE_CNTL 0x1724
#define RADEON_CACHE_LINE 0x0f0c /* PCI */
#define RADEON_CAPABILITIES_ID 0x0f50 /* PCI */
#define RADEON_CAPABILITIES_PTR 0x0f34 /* PCI */
#define RADEON_CLK_PIN_CNTL 0x0001 /* PLL */
# define RADEON_DONT_USE_XTALIN (1 << 4)
# define RADEON_SCLK_DYN_START_CNTL (1 << 15)
#define RADEON_CLOCK_CNTL_DATA 0x000c
#define RADEON_CLOCK_CNTL_INDEX 0x0008
# define RADEON_PLL_WR_EN (1 << 7)
# define RADEON_PLL_DIV_SEL (3 << 8)
# define RADEON_PLL2_DIV_SEL_MASK ~(3 << 8)
#define RADEON_M_SPLL_REF_FB_DIV 0x000a /* PLL */
# define RADEON_M_SPLL_REF_DIV_MASK 0xff
# define RADEON_M_SPLL_REF_DIV_SHIFT 0
# define RADEON_MPLL_FB_DIV_MASK 0xff
# define RADEON_MPLL_FB_DIV_SHIFT 8
# define RADEON_SPLL_FB_DIV_MASK 0xff
# define RADEON_SPLL_FB_DIV_SHIFT 16
#define RADEON_SPLL_CNTL 0x000c /* PLL */
# define RADEON_SPLL_SLEEP (1 << 0)
# define RADEON_SPLL_RESET (1 << 1)
# define RADEON_SPLL_PCP_MASK 0x7
# define RADEON_SPLL_PCP_SHIFT 8
# define RADEON_SPLL_PVG_MASK 0x7
# define RADEON_SPLL_PVG_SHIFT 11
# define RADEON_SPLL_PDC_MASK 0x3
# define RADEON_SPLL_PDC_SHIFT 14
#define RADEON_CLK_PWRMGT_CNTL 0x0014 /* PLL */
# define RADEON_ENGIN_DYNCLK_MODE (1 << 12)
# define RADEON_ACTIVE_HILO_LAT_MASK (3 << 13)
# define RADEON_ACTIVE_HILO_LAT_SHIFT 13
# define RADEON_DISP_DYN_STOP_LAT_MASK (1 << 12)
# define RADEON_MC_BUSY (1 << 16)
# define RADEON_DLL_READY (1 << 19)
# define RADEON_CG_NO1_DEBUG_0 (1 << 24)
# define RADEON_CG_NO1_DEBUG_MASK (0x1f << 24)
# define RADEON_DYN_STOP_MODE_MASK (7 << 21)
# define RADEON_TVPLL_PWRMGT_OFF (1 << 30)
# define RADEON_TVCLK_TURNOFF (1 << 31)
#define RADEON_PLL_PWRMGT_CNTL 0x0015 /* PLL */
# define RADEON_TCL_BYPASS_DISABLE (1 << 20)
#define RADEON_CLR_CMP_CLR_3D 0x1a24
#define RADEON_CLR_CMP_CLR_DST 0x15c8
#define RADEON_CLR_CMP_CLR_SRC 0x15c4
#define RADEON_CLR_CMP_CNTL 0x15c0
# define RADEON_SRC_CMP_EQ_COLOR (4 << 0)
# define RADEON_SRC_CMP_NEQ_COLOR (5 << 0)
# define RADEON_CLR_CMP_SRC_SOURCE (1 << 24)
#define RADEON_CLR_CMP_MASK 0x15cc
# define RADEON_CLR_CMP_MSK 0xffffffff
#define RADEON_CLR_CMP_MASK_3D 0x1A28
#define RADEON_COMMAND 0x0f04 /* PCI */
#define RADEON_COMPOSITE_SHADOW_ID 0x1a0c
#define RADEON_CONFIG_APER_0_BASE 0x0100
#define RADEON_CONFIG_APER_1_BASE 0x0104
#define RADEON_CONFIG_APER_SIZE 0x0108
#define RADEON_CONFIG_BONDS 0x00e8
#define RADEON_CONFIG_CNTL 0x00e0
# define RADEON_CFG_ATI_REV_A11 (0 << 16)
# define RADEON_CFG_ATI_REV_A12 (1 << 16)
# define RADEON_CFG_ATI_REV_A13 (2 << 16)
# define RADEON_CFG_ATI_REV_ID_MASK (0xf << 16)
#define RADEON_CONFIG_MEMSIZE 0x00f8
#define RADEON_CONFIG_MEMSIZE_EMBEDDED 0x0114
#define RADEON_CONFIG_REG_1_BASE 0x010c
#define RADEON_CONFIG_REG_APER_SIZE 0x0110
#define RADEON_CONFIG_XSTRAP 0x00e4
#define RADEON_CONSTANT_COLOR_C 0x1d34
# define RADEON_CONSTANT_COLOR_MASK 0x00ffffff
# define RADEON_CONSTANT_COLOR_ONE 0x00ffffff
# define RADEON_CONSTANT_COLOR_ZERO 0x00000000
#define RADEON_CRC_CMDFIFO_ADDR 0x0740
#define RADEON_CRC_CMDFIFO_DOUT 0x0744
#define RADEON_GRPH_BUFFER_CNTL 0x02f0
# define RADEON_GRPH_START_REQ_MASK (0x7f)
# define RADEON_GRPH_START_REQ_SHIFT 0
# define RADEON_GRPH_STOP_REQ_MASK (0x7f<<8)
# define RADEON_GRPH_STOP_REQ_SHIFT 8
# define RADEON_GRPH_CRITICAL_POINT_MASK (0x7f<<16)
# define RADEON_GRPH_CRITICAL_POINT_SHIFT 16
# define RADEON_GRPH_CRITICAL_CNTL (1<<28)
# define RADEON_GRPH_BUFFER_SIZE (1<<29)
# define RADEON_GRPH_CRITICAL_AT_SOF (1<<30)
# define RADEON_GRPH_STOP_CNTL (1<<31)
#define RADEON_GRPH2_BUFFER_CNTL 0x03f0
# define RADEON_GRPH2_START_REQ_MASK (0x7f)
# define RADEON_GRPH2_START_REQ_SHIFT 0
# define RADEON_GRPH2_STOP_REQ_MASK (0x7f<<8)
# define RADEON_GRPH2_STOP_REQ_SHIFT 8
# define RADEON_GRPH2_CRITICAL_POINT_MASK (0x7f<<16)
# define RADEON_GRPH2_CRITICAL_POINT_SHIFT 16
# define RADEON_GRPH2_CRITICAL_CNTL (1<<28)
# define RADEON_GRPH2_BUFFER_SIZE (1<<29)
# define RADEON_GRPH2_CRITICAL_AT_SOF (1<<30)
# define RADEON_GRPH2_STOP_CNTL (1<<31)
#define RADEON_CRTC_CRNT_FRAME 0x0214
#define RADEON_CRTC_EXT_CNTL 0x0054
# define RADEON_CRTC_VGA_XOVERSCAN (1 << 0)
# define RADEON_VGA_ATI_LINEAR (1 << 3)
# define RADEON_XCRT_CNT_EN (1 << 6)
# define RADEON_CRTC_HSYNC_DIS (1 << 8)
# define RADEON_CRTC_VSYNC_DIS (1 << 9)
# define RADEON_CRTC_DISPLAY_DIS (1 << 10)
# define RADEON_CRTC_SYNC_TRISTAT (1 << 11)
# define RADEON_CRTC_CRT_ON (1 << 15)
#define RADEON_CRTC_EXT_CNTL_DPMS_BYTE 0x0055
# define RADEON_CRTC_HSYNC_DIS_BYTE (1 << 0)
# define RADEON_CRTC_VSYNC_DIS_BYTE (1 << 1)
# define RADEON_CRTC_DISPLAY_DIS_BYTE (1 << 2)
#define RADEON_CRTC_GEN_CNTL 0x0050
# define RADEON_CRTC_DBL_SCAN_EN (1 << 0)
# define RADEON_CRTC_INTERLACE_EN (1 << 1)
# define RADEON_CRTC_CSYNC_EN (1 << 4)
# define RADEON_CRTC_ICON_EN (1 << 15)
# define RADEON_CRTC_CUR_EN (1 << 16)
# define RADEON_CRTC_CUR_MODE_MASK (7 << 20)
# define RADEON_CRTC_EXT_DISP_EN (1 << 24)
# define RADEON_CRTC_EN (1 << 25)
# define RADEON_CRTC_DISP_REQ_EN_B (1 << 26)
#define RADEON_CRTC2_GEN_CNTL 0x03f8
# define RADEON_CRTC2_DBL_SCAN_EN (1 << 0)
# define RADEON_CRTC2_INTERLACE_EN (1 << 1)
# define RADEON_CRTC2_SYNC_TRISTAT (1 << 4)
# define RADEON_CRTC2_HSYNC_TRISTAT (1 << 5)
# define RADEON_CRTC2_VSYNC_TRISTAT (1 << 6)
# define RADEON_CRTC2_CRT2_ON (1 << 7)
# define RADEON_CRTC2_PIX_WIDTH_SHIFT 8
# define RADEON_CRTC2_PIX_WIDTH_MASK (0xf << 8)
# define RADEON_CRTC2_ICON_EN (1 << 15)
# define RADEON_CRTC2_CUR_EN (1 << 16)
# define RADEON_CRTC2_CUR_MODE_MASK (7 << 20)
# define RADEON_CRTC2_DISP_DIS (1 << 23)
# define RADEON_CRTC2_EN (1 << 25)
# define RADEON_CRTC2_DISP_REQ_EN_B (1 << 26)
# define RADEON_CRTC2_CSYNC_EN (1 << 27)
# define RADEON_CRTC2_HSYNC_DIS (1 << 28)
# define RADEON_CRTC2_VSYNC_DIS (1 << 29)
#define RADEON_CRTC_MORE_CNTL 0x27c
# define RADEON_CRTC_AUTO_HORZ_CENTER_EN (1<<2)
# define RADEON_CRTC_AUTO_VERT_CENTER_EN (1<<3)
# define RADEON_CRTC_H_CUTOFF_ACTIVE_EN (1<<4)
# define RADEON_CRTC_V_CUTOFF_ACTIVE_EN (1<<5)
#define RADEON_CRTC_GUI_TRIG_VLINE 0x0218
# define RADEON_CRTC_GUI_TRIG_VLINE_START_SHIFT 0
# define RADEON_CRTC_GUI_TRIG_VLINE_INV (1 << 15)
# define RADEON_CRTC_GUI_TRIG_VLINE_END_SHIFT 16
# define RADEON_CRTC_GUI_TRIG_VLINE_STALL (1 << 30)
#define RADEON_CRTC_H_SYNC_STRT_WID 0x0204
# define RADEON_CRTC_H_SYNC_STRT_PIX (0x07 << 0)
# define RADEON_CRTC_H_SYNC_STRT_CHAR (0x3ff << 3)
# define RADEON_CRTC_H_SYNC_STRT_CHAR_SHIFT 3
# define RADEON_CRTC_H_SYNC_WID (0x3f << 16)
# define RADEON_CRTC_H_SYNC_WID_SHIFT 16
# define RADEON_CRTC_H_SYNC_POL (1 << 23)
#define RADEON_CRTC2_H_SYNC_STRT_WID 0x0304
# define RADEON_CRTC2_H_SYNC_STRT_PIX (0x07 << 0)
# define RADEON_CRTC2_H_SYNC_STRT_CHAR (0x3ff << 3)
# define RADEON_CRTC2_H_SYNC_STRT_CHAR_SHIFT 3
# define RADEON_CRTC2_H_SYNC_WID (0x3f << 16)
# define RADEON_CRTC2_H_SYNC_WID_SHIFT 16
# define RADEON_CRTC2_H_SYNC_POL (1 << 23)
#define RADEON_CRTC_H_TOTAL_DISP 0x0200
# define RADEON_CRTC_H_TOTAL (0x03ff << 0)
# define RADEON_CRTC_H_TOTAL_SHIFT 0
# define RADEON_CRTC_H_DISP (0x01ff << 16)
# define RADEON_CRTC_H_DISP_SHIFT 16
#define RADEON_CRTC2_H_TOTAL_DISP 0x0300
# define RADEON_CRTC2_H_TOTAL (0x03ff << 0)
# define RADEON_CRTC2_H_TOTAL_SHIFT 0
# define RADEON_CRTC2_H_DISP (0x01ff << 16)
# define RADEON_CRTC2_H_DISP_SHIFT 16
#define RADEON_CRTC_OFFSET_RIGHT 0x0220
#define RADEON_CRTC_OFFSET 0x0224
#define RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET (1<<30)
#define RADEON_CRTC_OFFSET__OFFSET_LOCK (1<<31)
#define RADEON_CRTC2_OFFSET 0x0324
#define RADEON_CRTC2_OFFSET__GUI_TRIG_OFFSET (1<<30)
#define RADEON_CRTC2_OFFSET__OFFSET_LOCK (1<<31)
#define RADEON_CRTC_OFFSET_CNTL 0x0228
# define RADEON_CRTC_TILE_LINE_SHIFT 0
# define RADEON_CRTC_TILE_LINE_RIGHT_SHIFT 4
#define R300_CRTC_X_Y_MODE_EN_RIGHT(1 << 6)
#define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_MASK (3 << 7)
#define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_AUTO (0 << 7)
#define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_SINGLE (1 << 7)
#define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DOUBLE (2 << 7)
#define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DIS (3 << 7)
#define R300_CRTC_X_Y_MODE_EN(1 << 9)
#define R300_CRTC_MICRO_TILE_BUFFER_MASK (3 << 10)
#define R300_CRTC_MICRO_TILE_BUFFER_AUTO (0 << 10)
#define R300_CRTC_MICRO_TILE_BUFFER_SINGLE (1 << 10)
#define R300_CRTC_MICRO_TILE_BUFFER_DOUBLE (2 << 10)
#define R300_CRTC_MICRO_TILE_BUFFER_DIS (3 << 10)
#define R300_CRTC_MICRO_TILE_EN_RIGHT(1 << 12)
#define R300_CRTC_MICRO_TILE_EN(1 << 13)
#define R300_CRTC_MACRO_TILE_EN_RIGHT(1 << 14)
# define R300_CRTC_MACRO_TILE_EN (1 << 15)
# define RADEON_CRTC_TILE_EN_RIGHT (1 << 14)
# define RADEON_CRTC_TILE_EN (1 << 15)
# define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)
# define RADEON_CRTC_STEREO_OFFSET_EN (1 << 17)
#define R300_CRTC_TILE_X0_Y0 0x0350
#define R300_CRTC2_TILE_X0_Y0 0x0358
#define RADEON_CRTC2_OFFSET_CNTL 0x0328
# define RADEON_CRTC2_OFFSET_FLIP_CNTL (1 << 16)
# define RADEON_CRTC2_TILE_EN (1 << 15)
#define RADEON_CRTC_PITCH 0x022c
#define RADEON_CRTC_PITCH__SHIFT 0
#define RADEON_CRTC_PITCH__RIGHT_SHIFT16
#define RADEON_CRTC2_PITCH 0x032c
#define RADEON_CRTC_STATUS 0x005c
# define RADEON_CRTC_VBLANK_SAVE (1 << 1)
# define RADEON_CRTC_VBLANK_SAVE_CLEAR (1 << 1)
#define RADEON_CRTC2_STATUS 0x03fc
# define RADEON_CRTC2_VBLANK_SAVE (1 << 1)
# define RADEON_CRTC2_VBLANK_SAVE_CLEAR (1 << 1)
#define RADEON_CRTC_V_SYNC_STRT_WID 0x020c
# define RADEON_CRTC_V_SYNC_STRT (0x7ff << 0)
# define RADEON_CRTC_V_SYNC_STRT_SHIFT 0
# define RADEON_CRTC_V_SYNC_WID (0x1f << 16)
# define RADEON_CRTC_V_SYNC_WID_SHIFT 16
# define RADEON_CRTC_V_SYNC_POL (1 << 23)
#define RADEON_CRTC2_V_SYNC_STRT_WID 0x030c
# define RADEON_CRTC2_V_SYNC_STRT (0x7ff << 0)
# define RADEON_CRTC2_V_SYNC_STRT_SHIFT 0
# define RADEON_CRTC2_V_SYNC_WID (0x1f << 16)
# define RADEON_CRTC2_V_SYNC_WID_SHIFT 16
# define RADEON_CRTC2_V_SYNC_POL (1 << 23)
#define RADEON_CRTC_V_TOTAL_DISP 0x0208
# define RADEON_CRTC_V_TOTAL (0x07ff << 0)
# define RADEON_CRTC_V_TOTAL_SHIFT 0
# define RADEON_CRTC_V_DISP (0x07ff << 16)
# define RADEON_CRTC_V_DISP_SHIFT 16
#define RADEON_CRTC2_V_TOTAL_DISP 0x0308
# define RADEON_CRTC2_V_TOTAL (0x07ff << 0)
# define RADEON_CRTC2_V_TOTAL_SHIFT 0
# define RADEON_CRTC2_V_DISP (0x07ff << 16)
# define RADEON_CRTC2_V_DISP_SHIFT 16
#define RADEON_CRTC_VLINE_CRNT_VLINE 0x0210
# define RADEON_CRTC_CRNT_VLINE_MASK (0x7ff << 16)
#define RADEON_CRTC2_CRNT_FRAME 0x0314
#define RADEON_CRTC2_GUI_TRIG_VLINE 0x0318
#define RADEON_CRTC2_STATUS 0x03fc
#define RADEON_CRTC2_VLINE_CRNT_VLINE 0x0310
#define RADEON_CRTC8_DATA 0x03d5 /* VGA, 0x3b5 */
#define RADEON_CRTC8_IDX 0x03d4 /* VGA, 0x3b4 */
#define RADEON_CUR_CLR0 0x026c
#define RADEON_CUR_CLR1 0x0270
#define RADEON_CUR_HORZ_VERT_OFF 0x0268
#define RADEON_CUR_HORZ_VERT_POSN 0x0264
#define RADEON_CUR_OFFSET 0x0260
# define RADEON_CUR_LOCK (1 << 31)
#define RADEON_CUR2_CLR0 0x036c
#define RADEON_CUR2_CLR1 0x0370
#define RADEON_CUR2_HORZ_VERT_OFF 0x0368
#define RADEON_CUR2_HORZ_VERT_POSN 0x0364
#define RADEON_CUR2_OFFSET 0x0360
# define RADEON_CUR2_LOCK (1 << 31)
#define RADEON_DAC_CNTL 0x0058
# define RADEON_DAC_RANGE_CNTL (3 << 0)
# define RADEON_DAC_RANGE_CNTL_PS2 (2 << 0)
# define RADEON_DAC_RANGE_CNTL_MASK 0x03
# define RADEON_DAC_BLANKING (1 << 2)
# define RADEON_DAC_CMP_EN (1 << 3)
# define RADEON_DAC_CMP_OUTPUT (1 << 7)
# define RADEON_DAC_8BIT_EN (1 << 8)
# define RADEON_DAC_TVO_EN (1 << 10)
# define RADEON_DAC_VGA_ADR_EN (1 << 13)
# define RADEON_DAC_PDWN (1 << 15)
# define RADEON_DAC_MASK_ALL (0xff << 24)
#define RADEON_DAC_CNTL2 0x007c
# define RADEON_DAC2_TV_CLK_SEL (0 << 1)
# define RADEON_DAC2_DAC_CLK_SEL (1 << 0)
# define RADEON_DAC2_DAC2_CLK_SEL (1 << 1)
# define RADEON_DAC2_PALETTE_ACC_CTL (1 << 5)
# define RADEON_DAC2_CMP_EN (1 << 7)
# define RADEON_DAC2_CMP_OUT_R (1 << 8)
# define RADEON_DAC2_CMP_OUT_G (1 << 9)
# define RADEON_DAC2_CMP_OUT_B (1 << 10)
# define RADEON_DAC2_CMP_OUTPUT (1 << 11)
#define RADEON_DAC_EXT_CNTL 0x0280
# define RADEON_DAC2_FORCE_BLANK_OFF_EN (1 << 0)
# define RADEON_DAC2_FORCE_DATA_EN (1 << 1)
# define RADEON_DAC_FORCE_BLANK_OFF_EN (1 << 4)
# define RADEON_DAC_FORCE_DATA_EN (1 << 5)
# define RADEON_DAC_FORCE_DATA_SEL_MASK (3 << 6)
# define RADEON_DAC_FORCE_DATA_SEL_R (0 << 6)
# define RADEON_DAC_FORCE_DATA_SEL_G (1 << 6)
# define RADEON_DAC_FORCE_DATA_SEL_B (2 << 6)
# define RADEON_DAC_FORCE_DATA_SEL_RGB (3 << 6)
# define RADEON_DAC_FORCE_DATA_MASK 0x0003ff00
# define RADEON_DAC_FORCE_DATA_SHIFT 8
#define RADEON_DAC_MACRO_CNTL 0x0d04
# define RADEON_DAC_PDWN_R (1 << 16)
# define RADEON_DAC_PDWN_G (1 << 17)
# define RADEON_DAC_PDWN_B (1 << 18)
#define RADEON_TV_DAC_CNTL 0x088c
# define RADEON_TV_DAC_NBLANK (1 << 0)
# define RADEON_TV_DAC_NHOLD (1 << 1)
# define RADEON_TV_DAC_PEDESTAL (1 << 2)
# define RADEON_TV_MONITOR_DETECT_EN (1 << 4)
# define RADEON_TV_DAC_CMPOUT (1 << 5)
# define RADEON_TV_DAC_STD_MASK (3 << 8)
# define RADEON_TV_DAC_STD_PAL (0 << 8)
# define RADEON_TV_DAC_STD_NTSC (1 << 8)
# define RADEON_TV_DAC_STD_PS2 (2 << 8)
# define RADEON_TV_DAC_STD_RS343 (3 << 8)
# define RADEON_TV_DAC_BGSLEEP (1 << 6)
# define RADEON_TV_DAC_BGADJ_MASK (0xf << 16)
# define RADEON_TV_DAC_BGADJ_SHIFT 16
# define RADEON_TV_DAC_DACADJ_MASK (0xf << 20)
# define RADEON_TV_DAC_DACADJ_SHIFT 20
# define RADEON_TV_DAC_RDACPD (1 << 24)
# define RADEON_TV_DAC_GDACPD (1 << 25)
# define RADEON_TV_DAC_BDACPD (1 << 26)
# define RADEON_TV_DAC_RDACDET (1 << 29)
# define RADEON_TV_DAC_GDACDET (1 << 30)
# define RADEON_TV_DAC_BDACDET (1 << 31)
# define R420_TV_DAC_DACADJ_MASK (0x1f << 20)
# define R420_TV_DAC_RDACPD (1 << 25)
# define R420_TV_DAC_GDACPD (1 << 26)
# define R420_TV_DAC_BDACPD (1 << 27)
# define R420_TV_DAC_TVENABLE (1 << 28)
#define RADEON_DISP_HW_DEBUG 0x0d14
# define RADEON_CRT2_DISP1_SEL (1 << 5)
#define RADEON_DISP_OUTPUT_CNTL 0x0d64
# define RADEON_DISP_DAC_SOURCE_MASK 0x03
# define RADEON_DISP_DAC2_SOURCE_MASK 0x0c
# define RADEON_DISP_DAC_SOURCE_CRTC2 0x01
# define RADEON_DISP_DAC_SOURCE_RMX 0x02
# define RADEON_DISP_DAC_SOURCE_LTU 0x03
# define RADEON_DISP_DAC2_SOURCE_CRTC2 0x04
# define RADEON_DISP_TVDAC_SOURCE_MASK (0x03 << 2)
# define RADEON_DISP_TVDAC_SOURCE_CRTC 0x0
# define RADEON_DISP_TVDAC_SOURCE_CRTC2 (0x01 << 2)
# define RADEON_DISP_TVDAC_SOURCE_RMX (0x02 << 2)
# define RADEON_DISP_TVDAC_SOURCE_LTU (0x03 << 2)
# define RADEON_DISP_TRANS_MATRIX_MASK (0x03 << 4)
# define RADEON_DISP_TRANS_MATRIX_ALPHA_MSB (0x00 << 4)
# define RADEON_DISP_TRANS_MATRIX_GRAPHICS (0x01 << 4)
# define RADEON_DISP_TRANS_MATRIX_VIDEO (0x02 << 4)
# define RADEON_DISP_TV_SOURCE_CRTC (1 << 16) /* crtc1 or crtc2 */
# define RADEON_DISP_TV_SOURCE_LTU (0 << 16) /* linear transform unit */
#define RADEON_DISP_TV_OUT_CNTL 0x0d6c
# define RADEON_DISP_TV_PATH_SRC_CRTC2 (1 << 16)
# define RADEON_DISP_TV_PATH_SRC_CRTC1 (0 << 16)
#define RADEON_DAC_CRC_SIG 0x02cc
#define RADEON_DAC_DATA 0x03c9 /* VGA */
#define RADEON_DAC_MASK 0x03c6 /* VGA */
#define RADEON_DAC_R_INDEX 0x03c7 /* VGA */
#define RADEON_DAC_W_INDEX 0x03c8 /* VGA */
#define RADEON_DDA_CONFIG 0x02e0
#define RADEON_DDA_ON_OFF 0x02e4
#define RADEON_DEFAULT_OFFSET 0x16e0
#define RADEON_DEFAULT_PITCH 0x16e4
#define RADEON_DEFAULT_SC_BOTTOM_RIGHT 0x16e8
# define RADEON_DEFAULT_SC_RIGHT_MAX (0x1fff << 0)
# define RADEON_DEFAULT_SC_BOTTOM_MAX (0x1fff << 16)
#define RADEON_DESTINATION_3D_CLR_CMP_VAL 0x1820
#define RADEON_DESTINATION_3D_CLR_CMP_MSK 0x1824
#define RADEON_DEVICE_ID 0x0f02 /* PCI */
#define RADEON_DISP_MISC_CNTL 0x0d00
# define RADEON_SOFT_RESET_GRPH_PP (1 << 0)
#define RADEON_DISP_MERGE_CNTL 0x0d60
# define RADEON_DISP_ALPHA_MODE_MASK 0x03
# define RADEON_DISP_ALPHA_MODE_KEY 0
# define RADEON_DISP_ALPHA_MODE_PER_PIXEL 1
# define RADEON_DISP_ALPHA_MODE_GLOBAL 2
# define RADEON_DISP_RGB_OFFSET_EN (1 << 8)
# define RADEON_DISP_GRPH_ALPHA_MASK (0xff << 16)
# define RADEON_DISP_OV0_ALPHA_MASK (0xff << 24)
#define RADEON_DISP_LIN_TRANS_BYPASS (0x01 << 9)
#define RADEON_DISP2_MERGE_CNTL 0x0d68
# define RADEON_DISP2_RGB_OFFSET_EN (1 << 8)
#define RADEON_DISP_LIN_TRANS_GRPH_A 0x0d80
#define RADEON_DISP_LIN_TRANS_GRPH_B 0x0d84
#define RADEON_DISP_LIN_TRANS_GRPH_C 0x0d88
#define RADEON_DISP_LIN_TRANS_GRPH_D 0x0d8c
#define RADEON_DISP_LIN_TRANS_GRPH_E 0x0d90
#define RADEON_DISP_LIN_TRANS_GRPH_F 0x0d98
#define RADEON_DP_BRUSH_BKGD_CLR 0x1478
#define RADEON_DP_BRUSH_FRGD_CLR 0x147c
#define RADEON_DP_CNTL 0x16c0
# define RADEON_DST_X_LEFT_TO_RIGHT (1 << 0)
# define RADEON_DST_Y_TOP_TO_BOTTOM (1 << 1)
# define RADEON_DP_DST_TILE_LINEAR (0 << 3)
# define RADEON_DP_DST_TILE_MACRO (1 << 3)
# define RADEON_DP_DST_TILE_MICRO (2 << 3)
# define RADEON_DP_DST_TILE_BOTH (3 << 3)
#define RADEON_DP_CNTL_XDIR_YDIR_YMAJOR 0x16d0
# define RADEON_DST_Y_MAJOR (1 << 2)
# define RADEON_DST_Y_DIR_TOP_TO_BOTTOM (1 << 15)
# define RADEON_DST_X_DIR_LEFT_TO_RIGHT (1 << 31)
#define RADEON_DP_DATATYPE 0x16c4
# define RADEON_HOST_BIG_ENDIAN_EN (1 << 29)
#define RADEON_DP_GUI_MASTER_CNTL 0x146c
# define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
# define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
# define RADEON_GMC_SRC_CLIPPING (1 << 2)
# define RADEON_GMC_DST_CLIPPING (1 << 3)
# define RADEON_GMC_BRUSH_DATATYPE_MASK (0x0f << 4)
# define RADEON_GMC_BRUSH_8X8_MONO_FG_BG (0 << 4)
# define RADEON_GMC_BRUSH_8X8_MONO_FG_LA (1 << 4)
# define RADEON_GMC_BRUSH_1X8_MONO_FG_BG (4 << 4)
# define RADEON_GMC_BRUSH_1X8_MONO_FG_LA (5 << 4)
# define RADEON_GMC_BRUSH_32x1_MONO_FG_BG (6 << 4)
# define RADEON_GMC_BRUSH_32x1_MONO_FG_LA (7 << 4)
# define RADEON_GMC_BRUSH_32x32_MONO_FG_BG (8 << 4)
# define RADEON_GMC_BRUSH_32x32_MONO_FG_LA (9 << 4)
# define RADEON_GMC_BRUSH_8x8_COLOR (10 << 4)
# define RADEON_GMC_BRUSH_1X8_COLOR (12 << 4)
# define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)
# define RADEON_GMC_BRUSH_NONE (15 << 4)
# define RADEON_GMC_DST_8BPP_CI (2 << 8)
# define RADEON_GMC_DST_15BPP (3 << 8)
# define RADEON_GMC_DST_16BPP (4 << 8)
# define RADEON_GMC_DST_24BPP (5 << 8)
# define RADEON_GMC_DST_32BPP (6 << 8)
# define RADEON_GMC_DST_8BPP_RGB (7 << 8)
# define RADEON_GMC_DST_Y8 (8 << 8)
# define RADEON_GMC_DST_RGB8 (9 << 8)
# define RADEON_GMC_DST_VYUY (11 << 8)
# define RADEON_GMC_DST_YVYU (12 << 8)
# define RADEON_GMC_DST_AYUV444 (14 << 8)
# define RADEON_GMC_DST_ARGB4444 (15 << 8)
# define RADEON_GMC_DST_DATATYPE_MASK (0x0f << 8)
# define RADEON_GMC_DST_DATATYPE_SHIFT 8
# define RADEON_GMC_SRC_DATATYPE_MASK (3 << 12)
# define RADEON_GMC_SRC_DATATYPE_MONO_FG_BG (0 << 12)
# define RADEON_GMC_SRC_DATATYPE_MONO_FG_LA (1 << 12)
# define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)
# define RADEON_GMC_BYTE_PIX_ORDER (1 << 14)
# define RADEON_GMC_BYTE_MSB_TO_LSB (0 << 14)
# define RADEON_GMC_BYTE_LSB_TO_MSB (1 << 14)
# define RADEON_GMC_CONVERSION_TEMP (1 << 15)
# define RADEON_GMC_CONVERSION_TEMP_6500 (0 << 15)
# define RADEON_GMC_CONVERSION_TEMP_9300 (1 << 15)
# define RADEON_GMC_ROP3_MASK (0xff << 16)
# define RADEON_DP_SRC_SOURCE_MASK (7 << 24)
# define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)
# define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)
# define RADEON_GMC_3D_FCN_EN (1 << 27)
# define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)
# define RADEON_GMC_AUX_CLIP_DIS (1 << 29)
# define RADEON_GMC_WR_MSK_DIS (1 << 30)
# define RADEON_GMC_LD_BRUSH_Y_X (1 << 31)
# define RADEON_ROP3_ZERO 0x00000000
# define RADEON_ROP3_DSa 0x00880000
# define RADEON_ROP3_SDna 0x00440000
# define RADEON_ROP3_S 0x00cc0000
# define RADEON_ROP3_DSna 0x00220000
# define RADEON_ROP3_D 0x00aa0000
# define RADEON_ROP3_DSx 0x00660000
# define RADEON_ROP3_DSo 0x00ee0000
# define RADEON_ROP3_DSon 0x00110000
# define RADEON_ROP3_DSxn 0x00990000
# define RADEON_ROP3_Dn 0x00550000
# define RADEON_ROP3_SDno 0x00dd0000
# define RADEON_ROP3_Sn 0x00330000
# define RADEON_ROP3_DSno 0x00bb0000
# define RADEON_ROP3_DSan 0x00770000
# define RADEON_ROP3_ONE 0x00ff0000
# define RADEON_ROP3_DPa 0x00a00000
# define RADEON_ROP3_PDna 0x00500000
# define RADEON_ROP3_P 0x00f00000
# define RADEON_ROP3_DPna 0x000a0000
# define RADEON_ROP3_D 0x00aa0000
# define RADEON_ROP3_DPx 0x005a0000
# define RADEON_ROP3_DPo 0x00fa0000
# define RADEON_ROP3_DPon 0x00050000
# define RADEON_ROP3_PDxn 0x00a50000
# define RADEON_ROP3_PDno 0x00f50000
# define RADEON_ROP3_Pn 0x000f0000
# define RADEON_ROP3_DPno 0x00af0000
# define RADEON_ROP3_DPan 0x005f0000
#define RADEON_DP_GUI_MASTER_CNTL_C 0x1c84
#define RADEON_DP_MIX 0x16c8
#define RADEON_DP_SRC_BKGD_CLR 0x15dc
#define RADEON_DP_SRC_FRGD_CLR 0x15d8
#define RADEON_DP_WRITE_MASK 0x16cc
#define RADEON_DST_BRES_DEC 0x1630
#define RADEON_DST_BRES_ERR 0x1628
#define RADEON_DST_BRES_INC 0x162c
#define RADEON_DST_BRES_LNTH 0x1634
#define RADEON_DST_BRES_LNTH_SUB 0x1638
#define RADEON_DST_HEIGHT 0x1410
#define RADEON_DST_HEIGHT_WIDTH 0x143c
#define RADEON_DST_HEIGHT_WIDTH_8 0x158c
#define RADEON_DST_HEIGHT_WIDTH_BW 0x15b4
#define RADEON_DST_HEIGHT_Y 0x15a0
#define RADEON_DST_LINE_START 0x1600
#define RADEON_DST_LINE_END 0x1604
#define RADEON_DST_LINE_PATCOUNT 0x1608
# define RADEON_BRES_CNTL_SHIFT 8
#define RADEON_DST_OFFSET 0x1404
#define RADEON_DST_PITCH 0x1408
#define RADEON_DST_PITCH_OFFSET 0x142c
#define RADEON_DST_PITCH_OFFSET_C 0x1c80
# define RADEON_PITCH_SHIFT 21
# define RADEON_DST_TILE_LINEAR (0 << 30)
# define RADEON_DST_TILE_MACRO (1 << 30)
# define RADEON_DST_TILE_MICRO (2 << 30)
# define RADEON_DST_TILE_BOTH (3 << 30)
#define RADEON_DST_WIDTH 0x140c
#define RADEON_DST_WIDTH_HEIGHT 0x1598
#define RADEON_DST_WIDTH_X 0x1588
#define RADEON_DST_WIDTH_X_INCY 0x159c
#define RADEON_DST_X 0x141c
#define RADEON_DST_X_SUB 0x15a4
#define RADEON_DST_X_Y 0x1594
#define RADEON_DST_Y 0x1420
#define RADEON_DST_Y_SUB 0x15a8
#define RADEON_DST_Y_X 0x1438
#define RADEON_FCP_CNTL 0x0910
# define RADEON_FCP0_SRC_PCICLK 0
# define RADEON_FCP0_SRC_PCLK 1
# define RADEON_FCP0_SRC_PCLKb 2
# define RADEON_FCP0_SRC_HREF 3
# define RADEON_FCP0_SRC_GND 4
# define RADEON_FCP0_SRC_HREFb 5
#define RADEON_FLUSH_1 0x1704
#define RADEON_FLUSH_2 0x1708
#define RADEON_FLUSH_3 0x170c
#define RADEON_FLUSH_4 0x1710
#define RADEON_FLUSH_5 0x1714
#define RADEON_FLUSH_6 0x1718
#define RADEON_FLUSH_7 0x171c
#define RADEON_FOG_3D_TABLE_START 0x1810
#define RADEON_FOG_3D_TABLE_END 0x1814
#define RADEON_FOG_3D_TABLE_DENSITY 0x181c
#define RADEON_FOG_TABLE_INDEX 0x1a14
#define RADEON_FOG_TABLE_DATA 0x1a18
#define RADEON_FP_CRTC_H_TOTAL_DISP 0x0250
#define RADEON_FP_CRTC_V_TOTAL_DISP 0x0254
# define RADEON_FP_CRTC_H_TOTAL_MASK 0x000003ff
# define RADEON_FP_CRTC_H_DISP_MASK 0x01ff0000
# define RADEON_FP_CRTC_V_TOTAL_MASK 0x00000fff
# define RADEON_FP_CRTC_V_DISP_MASK 0x0fff0000
# define RADEON_FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8
# define RADEON_FP_H_SYNC_WID_MASK 0x003f0000
# define RADEON_FP_V_SYNC_STRT_MASK 0x00000fff
# define RADEON_FP_V_SYNC_WID_MASK 0x001f0000
# define RADEON_FP_CRTC_H_TOTAL_SHIFT 0x00000000
# define RADEON_FP_CRTC_H_DISP_SHIFT 0x00000010
# define RADEON_FP_CRTC_V_TOTAL_SHIFT 0x00000000
# define RADEON_FP_CRTC_V_DISP_SHIFT 0x00000010
# define RADEON_FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003
# define RADEON_FP_H_SYNC_WID_SHIFT 0x00000010
# define RADEON_FP_V_SYNC_STRT_SHIFT 0x00000000
# define RADEON_FP_V_SYNC_WID_SHIFT 0x00000010
#define RADEON_FP_GEN_CNTL 0x0284
# define RADEON_FP_FPON (1 << 0)
# define RADEON_FP_BLANK_EN (1 << 1)
# define RADEON_FP_TMDS_EN (1 << 2)
# define RADEON_FP_PANEL_FORMAT (1 << 3)
# define RADEON_FP_EN_TMDS (1 << 7)
# define RADEON_FP_DETECT_SENSE (1 << 8)
# define R200_FP_SOURCE_SEL_MASK (3 << 10)
# define R200_FP_SOURCE_SEL_CRTC1 (0 << 10)
# define R200_FP_SOURCE_SEL_CRTC2 (1 << 10)
# define R200_FP_SOURCE_SEL_RMX (2 << 10)
# define R200_FP_SOURCE_SEL_TRANS (3 << 10)
# define RADEON_FP_SEL_CRTC1 (0 << 13)
# define RADEON_FP_SEL_CRTC2 (1 << 13)
# define RADEON_FP_CRTC_DONT_SHADOW_HPAR (1 << 15)
# define RADEON_FP_CRTC_DONT_SHADOW_VPAR (1 << 16)
# define RADEON_FP_CRTC_DONT_SHADOW_HEND (1 << 17)
# define RADEON_FP_CRTC_USE_SHADOW_VEND (1 << 18)
# define RADEON_FP_RMX_HVSYNC_CONTROL_EN (1 << 20)
# define RADEON_FP_DFP_SYNC_SEL (1 << 21)
# define RADEON_FP_CRTC_LOCK_8DOT (1 << 22)
# define RADEON_FP_CRT_SYNC_SEL (1 << 23)
# define RADEON_FP_USE_SHADOW_EN (1 << 24)
# define RADEON_FP_CRT_SYNC_ALT (1 << 26)
#define RADEON_FP2_GEN_CNTL 0x0288
# define RADEON_FP2_BLANK_EN (1 << 1)
# define RADEON_FP2_ON (1 << 2)
# define RADEON_FP2_PANEL_FORMAT (1 << 3)
# define RADEON_FP2_DETECT_SENSE (1 << 8)
# define R200_FP2_SOURCE_SEL_MASK (3 << 10)
# define R200_FP2_SOURCE_SEL_CRTC1 (0 << 10)
# define R200_FP2_SOURCE_SEL_CRTC2 (1 << 10)
# define R200_FP2_SOURCE_SEL_RMX (2 << 10)
# define R200_FP2_SOURCE_SEL_TRANS_UNIT (3 << 10)
# define RADEON_FP2_SRC_SEL_MASK (3 << 13)
# define RADEON_FP2_SRC_SEL_CRTC2 (1 << 13)
# define RADEON_FP2_FP_POL (1 << 16)
# define RADEON_FP2_LP_POL (1 << 17)
# define RADEON_FP2_SCK_POL (1 << 18)
# define RADEON_FP2_LCD_CNTL_MASK (7 << 19)
# define RADEON_FP2_PAD_FLOP_EN (1 << 22)
# define RADEON_FP2_CRC_EN (1 << 23)
# define RADEON_FP2_CRC_READ_EN (1 << 24)
# define RADEON_FP2_DVO_EN (1 << 25)
# define RADEON_FP2_DVO_RATE_SEL_SDR (1 << 26)
# define R200_FP2_DVO_RATE_SEL_SDR (1 << 27)
# define R200_FP2_DVO_CLOCK_MODE_SINGLE (1 << 28)
# define R300_FP2_DVO_DUAL_CHANNEL_EN (1 << 29)
#define RADEON_FP_H_SYNC_STRT_WID 0x02c4
#define RADEON_FP_H2_SYNC_STRT_WID 0x03c4
#define RADEON_FP_HORZ_STRETCH 0x028c
#define RADEON_FP_HORZ2_STRETCH 0x038c
# define RADEON_HORZ_STRETCH_RATIO_MASK 0xffff
# define RADEON_HORZ_STRETCH_RATIO_MAX 4096
# define RADEON_HORZ_PANEL_SIZE (0x1ff << 16)
# define RADEON_HORZ_PANEL_SHIFT 16
# define RADEON_HORZ_STRETCH_PIXREP (0 << 25)
# define RADEON_HORZ_STRETCH_BLEND (1 << 26)
# define RADEON_HORZ_STRETCH_ENABLE (1 << 25)
# define RADEON_HORZ_AUTO_RATIO (1 << 27)
# define RADEON_HORZ_FP_LOOP_STRETCH (0x7 << 28)
# define RADEON_HORZ_AUTO_RATIO_INC (1 << 31)
#define RADEON_FP_HORZ_VERT_ACTIVE 0x0278
#define RADEON_FP_V_SYNC_STRT_WID 0x02c8
#define RADEON_FP_VERT_STRETCH 0x0290
#define RADEON_FP_V2_SYNC_STRT_WID 0x03c8
#define RADEON_FP_VERT2_STRETCH 0x0390
# define RADEON_VERT_PANEL_SIZE (0xfff << 12)
# define RADEON_VERT_PANEL_SHIFT 12
# define RADEON_VERT_STRETCH_RATIO_MASK 0xfff
# define RADEON_VERT_STRETCH_RATIO_SHIFT 0
# define RADEON_VERT_STRETCH_RATIO_MAX 4096
# define RADEON_VERT_STRETCH_ENABLE (1 << 25)
# define RADEON_VERT_STRETCH_LINEREP (0 << 26)
# define RADEON_VERT_STRETCH_BLEND (1 << 26)
# define RADEON_VERT_AUTO_RATIO_EN (1 << 27)
#define RADEON_VERT_AUTO_RATIO_INC (1 << 31)
# define RADEON_VERT_STRETCH_RESERVED 0x71000000
#define RS400_FP_2ND_GEN_CNTL 0x0384
# define RS400_FP_2ND_ON (1 << 0)
# define RS400_FP_2ND_BLANK_EN (1 << 1)
# define RS400_TMDS_2ND_EN (1 << 2)
# define RS400_PANEL_FORMAT_2ND (1 << 3)
# define RS400_FP_2ND_EN_TMDS (1 << 7)
# define RS400_FP_2ND_DETECT_SENSE (1 << 8)
# define RS400_FP_2ND_SOURCE_SEL_MASK (3 << 10)
# define RS400_FP_2ND_SOURCE_SEL_CRTC1 (0 << 10)
# define RS400_FP_2ND_SOURCE_SEL_CRTC2 (1 << 10)
# define RS400_FP_2ND_SOURCE_SEL_RMX (2 << 10)
# define RS400_FP_2ND_DETECT_EN (1 << 12)
# define RS400_HPD_2ND_SEL (1 << 13)
#define RS400_FP2_2_GEN_CNTL 0x0388
# define RS400_FP2_2_BLANK_EN (1 << 1)
# define RS400_FP2_2_ON (1 << 2)
# define RS400_FP2_2_PANEL_FORMAT (1 << 3)
# define RS400_FP2_2_DETECT_SENSE (1 << 8)
# define RS400_FP2_2_SOURCE_SEL_MASK (3 << 10)
# define RS400_FP2_2_SOURCE_SEL_CRTC1 (0 << 10)
# define RS400_FP2_2_SOURCE_SEL_CRTC2 (1 << 10)
# define RS400_FP2_2_SOURCE_SEL_RMX (2 << 10)
# define RS400_FP2_2_DVO2_EN (1 << 25)
#define RS400_TMDS2_CNTL 0x0394
#define RS400_TMDS2_TRANSMITTER_CNTL 0x03a4
# define RS400_TMDS2_PLLEN (1 << 0)
# define RS400_TMDS2_PLLRST (1 << 1)
#define RADEON_GEN_INT_CNTL 0x0040
#define RADEON_GEN_INT_STATUS 0x0044
# define RADEON_VSYNC_INT_AK (1 << 2)
# define RADEON_VSYNC_INT (1 << 2)
# define RADEON_VSYNC2_INT_AK (1 << 6)
# define RADEON_VSYNC2_INT (1 << 6)
#define RADEON_GENENB 0x03c3 /* VGA */
#define RADEON_GENFC_RD 0x03ca /* VGA */
#define RADEON_GENFC_WT 0x03da /* VGA, 0x03ba */
#define RADEON_GENMO_RD 0x03cc /* VGA */
#define RADEON_GENMO_WT 0x03c2 /* VGA */
#define RADEON_GENS0 0x03c2 /* VGA */
#define RADEON_GENS1 0x03da /* VGA, 0x03ba */
#define RADEON_GPIO_MONID 0x0068 /* DDC interface via I2C */ /* DDC3 */
#define RADEON_GPIO_MONIDB 0x006c
#define RADEON_GPIO_CRT2_DDC 0x006c
#define RADEON_GPIO_DVI_DDC 0x0064 /* DDC2 */
#define RADEON_GPIO_VGA_DDC 0x0060 /* DDC1 */
# define RADEON_GPIO_A_0 (1 << 0)
# define RADEON_GPIO_A_1 (1 << 1)
# define RADEON_GPIO_Y_0 (1 << 8)
# define RADEON_GPIO_Y_1 (1 << 9)
# define RADEON_GPIO_Y_SHIFT_0 8
# define RADEON_GPIO_Y_SHIFT_1 9
# define RADEON_GPIO_EN_0 (1 << 16)
# define RADEON_GPIO_EN_1 (1 << 17)
# define RADEON_GPIO_MASK_0 (1 << 24) /*??*/
# define RADEON_GPIO_MASK_1 (1 << 25) /*??*/
#define RADEON_GRPH8_DATA 0x03cf /* VGA */
#define RADEON_GRPH8_IDX 0x03ce /* VGA */
#define RADEON_GUI_SCRATCH_REG0 0x15e0
#define RADEON_GUI_SCRATCH_REG1 0x15e4
#define RADEON_GUI_SCRATCH_REG2 0x15e8
#define RADEON_GUI_SCRATCH_REG3 0x15ec
#define RADEON_GUI_SCRATCH_REG4 0x15f0
#define RADEON_GUI_SCRATCH_REG5 0x15f4
#define RADEON_HEADER 0x0f0e /* PCI */
#define RADEON_HOST_DATA0 0x17c0
#define RADEON_HOST_DATA1 0x17c4
#define RADEON_HOST_DATA2 0x17c8
#define RADEON_HOST_DATA3 0x17cc
#define RADEON_HOST_DATA4 0x17d0
#define RADEON_HOST_DATA5 0x17d4
#define RADEON_HOST_DATA6 0x17d8
#define RADEON_HOST_DATA7 0x17dc
#define RADEON_HOST_DATA_LAST 0x17e0
#define RADEON_HOST_PATH_CNTL 0x0130
# define RADEON_HDP_SOFT_RESET (1 << 26)
# define RADEON_HDP_APER_CNTL (1 << 23)
#define RADEON_HTOTAL_CNTL 0x0009 /* PLL */
# define RADEON_HTOT_CNTL_VGA_EN (1 << 28)
#define RADEON_HTOTAL2_CNTL 0x002e /* PLL */
/* Multimedia I2C bus */
#define RADEON_I2C_CNTL_0 0x0090
#define RADEON_I2C_DONE (1 << 0)
#define RADEON_I2C_NACK (1 << 1)
#define RADEON_I2C_HALT (1 << 2)
#define RADEON_I2C_SOFT_RST (1 << 5)
#define RADEON_I2C_DRIVE_EN (1 << 6)
#define RADEON_I2C_DRIVE_SEL (1 << 7)
#define RADEON_I2C_START (1 << 8)
#define RADEON_I2C_STOP (1 << 9)
#define RADEON_I2C_RECEIVE (1 << 10)
#define RADEON_I2C_ABORT (1 << 11)
#define RADEON_I2C_GO (1 << 12)
#define RADEON_I2C_CNTL_1 0x0094
#define RADEON_I2C_SEL (1 << 16)
#define RADEON_I2C_EN (1 << 17)
#define RADEON_I2C_DATA 0x0098
#define RADEON_DVI_I2C_CNTL_0 0x02e0
# define R200_DVI_I2C_PIN_SEL(x) ((x) << 3)
# define R200_SEL_DDC1 0 /* 0x60 - VGA_DDC */
# define R200_SEL_DDC2 1 /* 0x64 - DVI_DDC */
# define R200_SEL_DDC3 2 /* 0x68 - MONID_DDC */
#define RADEON_DVI_I2C_CNTL_1 0x02e4
#define RADEON_DVI_I2C_DATA 0x02e8
#define RADEON_INTERRUPT_LINE 0x0f3c /* PCI */
#define RADEON_INTERRUPT_PIN 0x0f3d /* PCI */
#define RADEON_IO_BASE 0x0f14 /* PCI */
#define RADEON_LATENCY 0x0f0d /* PCI */
#define RADEON_LEAD_BRES_DEC 0x1608
#define RADEON_LEAD_BRES_LNTH 0x161c
#define RADEON_LEAD_BRES_LNTH_SUB 0x1624
#define RADEON_LVDS_GEN_CNTL 0x02d0
# define RADEON_LVDS_ON (1 << 0)
# define RADEON_LVDS_DISPLAY_DIS (1 << 1)
# define RADEON_LVDS_PANEL_TYPE (1 << 2)
# define RADEON_LVDS_PANEL_FORMAT (1 << 3)
# define RADEON_LVDS_RST_FM (1 << 6)
# define RADEON_LVDS_EN (1 << 7)
# define RADEON_LVDS_BL_MOD_LEVEL_SHIFT 8
# define RADEON_LVDS_BL_MOD_LEVEL_MASK (0xff << 8)
# define RADEON_LVDS_BL_MOD_EN (1 << 16)
# define RADEON_LVDS_DIGON (1 << 18)
# define RADEON_LVDS_BLON (1 << 19)
# define RADEON_LVDS_SEL_CRTC2 (1 << 23)
#define RADEON_LVDS_PLL_CNTL 0x02d4
# define RADEON_HSYNC_DELAY_SHIFT 28
# define RADEON_HSYNC_DELAY_MASK (0xf << 28)
# define RADEON_LVDS_PLL_EN (1 << 16)
# define RADEON_LVDS_PLL_RESET (1 << 17)
# define R300_LVDS_SRC_SEL_MASK (3 << 18)
# define R300_LVDS_SRC_SEL_CRTC1 (0 << 18)
# define R300_LVDS_SRC_SEL_CRTC2 (1 << 18)
# define R300_LVDS_SRC_SEL_RMX (2 << 18)
#define RADEON_MAX_LATENCY 0x0f3f /* PCI */
#define RADEON_MC_AGP_LOCATION 0x014c
#define RADEON_MC_FB_LOCATION 0x0148
#define RADEON_DISPLAY_BASE_ADDR 0x23c
#define RADEON_DISPLAY2_BASE_ADDR 0x33c
#define RADEON_OV0_BASE_ADDR 0x43c
#define RADEON_NB_TOM 0x15c
#define R300_MC_INIT_MISC_LAT_TIMER 0x180
# define R300_MC_DISP0R_INIT_LAT_SHIFT 8
# define R300_MC_DISP0R_INIT_LAT_MASK 0xf
# define R300_MC_DISP1R_INIT_LAT_SHIFT 12
# define R300_MC_DISP1R_INIT_LAT_MASK 0xf
#define RADEON_MCLK_CNTL 0x0012 /* PLL */
# define RADEON_FORCEON_MCLKA (1 << 16)
# define RADEON_FORCEON_MCLKB (1 << 17)
# define RADEON_FORCEON_YCLKA (1 << 18)
# define RADEON_FORCEON_YCLKB (1 << 19)
# define RADEON_FORCEON_MC (1 << 20)
# define RADEON_FORCEON_AIC (1 << 21)
# define R300_DISABLE_MC_MCLKA (1 << 21)
# define R300_DISABLE_MC_MCLKB (1 << 21)
#define RADEON_MCLK_MISC 0x001f /* PLL */
# define RADEON_MC_MCLK_MAX_DYN_STOP_LAT (1 << 12)
# define RADEON_IO_MCLK_MAX_DYN_STOP_LAT (1 << 13)
# define RADEON_MC_MCLK_DYN_ENABLE (1 << 14)
# define RADEON_IO_MCLK_DYN_ENABLE (1 << 15)
#define RADEON_LCD_GPIO_MASK 0x01a0
#define RADEON_GPIOPAD_EN 0x01a0
#define RADEON_LCD_GPIO_Y_REG 0x01a4
#define RADEON_MDGPIO_A_REG 0x01ac
#define RADEON_MDGPIO_EN_REG 0x01b0
#define RADEON_MDGPIO_MASK 0x0198
#define RADEON_GPIOPAD_MASK 0x0198
#define RADEON_GPIOPAD_A 0x019c
#define RADEON_MDGPIO_Y_REG 0x01b4
#define RADEON_MEM_ADDR_CONFIG 0x0148
#define RADEON_MEM_BASE 0x0f10 /* PCI */
#define RADEON_MEM_CNTL 0x0140
# define RADEON_MEM_NUM_CHANNELS_MASK 0x01
# define RADEON_MEM_USE_B_CH_ONLY (1 << 1)
# define RV100_HALF_MODE (1 << 3)
# define R300_MEM_NUM_CHANNELS_MASK 0x03
# define R300_MEM_USE_CD_CH_ONLY (1 << 2)
#define RADEON_MEM_TIMING_CNTL 0x0144 /* EXT_MEM_CNTL */
#define RADEON_MEM_INIT_LAT_TIMER 0x0154
#define RADEON_MEM_INTF_CNTL 0x014c
#define RADEON_MEM_SDRAM_MODE_REG 0x0158
# define RADEON_SDRAM_MODE_MASK 0xffff0000
# define RADEON_B3MEM_RESET_MASK 0x6fffffff
# define RADEON_MEM_CFG_TYPE_DDR (1 << 30)
#define RADEON_MEM_STR_CNTL 0x0150
# define RADEON_MEM_PWRUP_COMPL_A (1 << 0)
# define RADEON_MEM_PWRUP_COMPL_B (1 << 1)
# define R300_MEM_PWRUP_COMPL_C (1 << 2)
# define R300_MEM_PWRUP_COMPL_D (1 << 3)
# define RADEON_MEM_PWRUP_COMPLETE 0x03
# define R300_MEM_PWRUP_COMPLETE 0x0f
#define RADEON_MC_STATUS 0x0150
# define RADEON_MC_IDLE (1 << 2)
# define R300_MC_IDLE (1 << 4)
#define RADEON_MEM_VGA_RP_SEL 0x003c
#define RADEON_MEM_VGA_WP_SEL 0x0038
#define RADEON_MIN_GRANT 0x0f3e /* PCI */
#define RADEON_MM_DATA 0x0004
#define RADEON_MM_INDEX 0x0000
#define RADEON_MPLL_CNTL 0x000e /* PLL */
#define RADEON_MPP_TB_CONFIG 0x01c0 /* ? */
#define RADEON_MPP_GP_CONFIG 0x01c8 /* ? */
#define RADEON_SEPROM_CNTL1 0x01c0
# define RADEON_SCK_PRESCALE_SHIFT 24
# define RADEON_SCK_PRESCALE_MASK (0xff << 24)
#define R300_MC_IND_INDEX 0x01f8
# define R300_MC_IND_ADDR_MASK 0x3f
# define R300_MC_IND_WR_EN (1 << 8)
#define R300_MC_IND_DATA 0x01fc
#define R300_MC_READ_CNTL_AB 0x017c
# define R300_MEM_RBS_POSITION_A_MASK 0x03
#define R300_MC_READ_CNTL_CD_mcind 0x24
# define R300_MEM_RBS_POSITION_C_MASK 0x03
#define RADEON_N_VIF_COUNT 0x0248
#define RADEON_OV0_AUTO_FLIP_CNTL 0x0470
# define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_BUF_NUM 0x00000007
# define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_REPEAT_FIELD 0x00000008
# define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD 0x00000010
# define RADEON_OV0_AUTO_FLIP_CNTL_IGNORE_REPEAT_FIELD 0x00000020
# define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE 0x00000040
# define RADEON_OV0_AUTO_FLIP_CNTL_VID_PORT_SELECT 0x00000300
# define RADEON_OV0_AUTO_FLIP_CNTL_P1_FIRST_LINE_EVEN 0x00010000
# define RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_EVEN_DOWN 0x00040000
# define RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_ODD_DOWN 0x00080000
# define RADEON_OV0_AUTO_FLIP_CNTL_FIELD_POL_SOURCE 0x00800000
#define RADEON_OV0_COLOUR_CNTL 0x04E0
#define RADEON_OV0_DEINTERLACE_PATTERN 0x0474
#define RADEON_OV0_EXCLUSIVE_HORZ 0x0408
# define RADEON_EXCL_HORZ_START_MASK 0x000000ff
# define RADEON_EXCL_HORZ_END_MASK 0x0000ff00
# define RADEON_EXCL_HORZ_BACK_PORCH_MASK 0x00ff0000
# define RADEON_EXCL_HORZ_EXCLUSIVE_EN 0x80000000
#define RADEON_OV0_EXCLUSIVE_VERT 0x040C
# define RADEON_EXCL_VERT_START_MASK 0x000003ff
# define RADEON_EXCL_VERT_END_MASK 0x03ff0000
#define RADEON_OV0_FILTER_CNTL 0x04A0
# define RADEON_FILTER_PROGRAMMABLE_COEF 0x0
# define RADEON_FILTER_HC_COEF_HORZ_Y 0x1
# define RADEON_FILTER_HC_COEF_HORZ_UV 0x2
# define RADEON_FILTER_HC_COEF_VERT_Y 0x4
# define RADEON_FILTER_HC_COEF_VERT_UV 0x8
# define RADEON_FILTER_HARDCODED_COEF 0xf
# define RADEON_FILTER_COEF_MASK 0xf
#define RADEON_OV0_FOUR_TAP_COEF_0 0x04B0
#define RADEON_OV0_FOUR_TAP_COEF_1 0x04B4
#define RADEON_OV0_FOUR_TAP_COEF_2 0x04B8
#define RADEON_OV0_FOUR_TAP_COEF_3 0x04BC
#define RADEON_OV0_FOUR_TAP_COEF_4 0x04C0
#define RADEON_OV0_FLAG_CNTL 0x04DC
#define RADEON_OV0_GAMMA_000_00F 0x0d40
#define RADEON_OV0_GAMMA_010_01F 0x0d44
#define RADEON_OV0_GAMMA_020_03F 0x0d48
#define RADEON_OV0_GAMMA_040_07F 0x0d4c
#define RADEON_OV0_GAMMA_080_0BF 0x0e00
#define RADEON_OV0_GAMMA_0C0_0FF 0x0e04
#define RADEON_OV0_GAMMA_100_13F 0x0e08
#define RADEON_OV0_GAMMA_140_17F 0x0e0c
#define RADEON_OV0_GAMMA_180_1BF 0x0e10
#define RADEON_OV0_GAMMA_1C0_1FF 0x0e14
#define RADEON_OV0_GAMMA_200_23F 0x0e18
#define RADEON_OV0_GAMMA_240_27F 0x0e1c
#define RADEON_OV0_GAMMA_280_2BF 0x0e20
#define RADEON_OV0_GAMMA_2C0_2FF 0x0e24
#define RADEON_OV0_GAMMA_300_33F 0x0e28
#define RADEON_OV0_GAMMA_340_37F 0x0e2c
#define RADEON_OV0_GAMMA_380_3BF 0x0d50
#define RADEON_OV0_GAMMA_3C0_3FF 0x0d54
#define RADEON_OV0_GRAPHICS_KEY_CLR_LOW 0x04EC
#define RADEON_OV0_GRAPHICS_KEY_CLR_HIGH 0x04F0
#define RADEON_OV0_H_INC 0x0480
#define RADEON_OV0_KEY_CNTL 0x04F4
# define RADEON_VIDEO_KEY_FN_MASK 0x00000003L
# define RADEON_VIDEO_KEY_FN_FALSE 0x00000000L
# define RADEON_VIDEO_KEY_FN_TRUE 0x00000001L
# define RADEON_VIDEO_KEY_FN_EQ 0x00000002L
# define RADEON_VIDEO_KEY_FN_NE 0x00000003L
# define RADEON_GRAPHIC_KEY_FN_MASK 0x00000030L
# define RADEON_GRAPHIC_KEY_FN_FALSE 0x00000000L
# define RADEON_GRAPHIC_KEY_FN_TRUE 0x00000010L
# define RADEON_GRAPHIC_KEY_FN_EQ 0x00000020L
# define RADEON_GRAPHIC_KEY_FN_NE 0x00000030L
# define RADEON_CMP_MIX_MASK 0x00000100L
# define RADEON_CMP_MIX_OR 0x00000000L
# define RADEON_CMP_MIX_AND 0x00000100L
#define RADEON_OV0_LIN_TRANS_A 0x0d20
#define RADEON_OV0_LIN_TRANS_B 0x0d24
#define RADEON_OV0_LIN_TRANS_C 0x0d28
#define RADEON_OV0_LIN_TRANS_D 0x0d2c
#define RADEON_OV0_LIN_TRANS_E 0x0d30
#define RADEON_OV0_LIN_TRANS_F 0x0d34
#define RADEON_OV0_P1_BLANK_LINES_AT_TOP 0x0430
# define RADEON_P1_BLNK_LN_AT_TOP_M1_MASK 0x00000fffL
# define RADEON_P1_ACTIVE_LINES_M1 0x0fff0000L
#define RADEON_OV0_P1_H_ACCUM_INIT 0x0488
#define RADEON_OV0_P1_V_ACCUM_INIT 0x0428
# define RADEON_OV0_P1_MAX_LN_IN_PER_LN_OUT 0x00000003L
# define RADEON_OV0_P1_V_ACCUM_INIT_MASK 0x01ff8000L
#define RADEON_OV0_P1_X_START_END 0x0494
#define RADEON_OV0_P2_X_START_END 0x0498
#define RADEON_OV0_P23_BLANK_LINES_AT_TOP 0x0434
# define RADEON_P23_BLNK_LN_AT_TOP_M1_MASK 0x000007ffL
# define RADEON_P23_ACTIVE_LINES_M1 0x07ff0000L
#define RADEON_OV0_P23_H_ACCUM_INIT 0x048C
#define RADEON_OV0_P23_V_ACCUM_INIT 0x042C
#define RADEON_OV0_P3_X_START_END 0x049C
#define RADEON_OV0_REG_LOAD_CNTL 0x0410
# define RADEON_REG_LD_CTL_LOCK 0x00000001L
# define RADEON_REG_LD_CTL_VBLANK_DURING_LOCK 0x00000002L
# define RADEON_REG_LD_CTL_STALL_GUI_UNTIL_FLIP 0x00000004L
# define RADEON_REG_LD_CTL_LOCK_READBACK 0x00000008L
# define RADEON_REG_LD_CTL_FLIP_READBACK 0x00000010L
#define RADEON_OV0_SCALE_CNTL 0x0420
# define RADEON_SCALER_HORZ_PICK_NEAREST 0x00000004L
# define RADEON_SCALER_VERT_PICK_NEAREST 0x00000008L
# define RADEON_SCALER_SIGNED_UV 0x00000010L
# define RADEON_SCALER_GAMMA_SEL_MASK 0x00000060L
# define RADEON_SCALER_GAMMA_SEL_BRIGHT 0x00000000L
# define RADEON_SCALER_GAMMA_SEL_G22 0x00000020L
# define RADEON_SCALER_GAMMA_SEL_G18 0x00000040L
# define RADEON_SCALER_GAMMA_SEL_G14 0x00000060L
# define RADEON_SCALER_COMCORE_SHIFT_UP_ONE 0x00000080L
# define RADEON_SCALER_SURFAC_FORMAT 0x00000f00L
# define RADEON_SCALER_SOURCE_15BPP 0x00000300L
# define RADEON_SCALER_SOURCE_16BPP 0x00000400L
# define RADEON_SCALER_SOURCE_32BPP 0x00000600L
# define RADEON_SCALER_SOURCE_YUV9 0x00000900L
# define RADEON_SCALER_SOURCE_YUV12 0x00000A00L
# define RADEON_SCALER_SOURCE_VYUY422 0x00000B00L
# define RADEON_SCALER_SOURCE_YVYU422 0x00000C00L
# define RADEON_SCALER_ADAPTIVE_DEINT 0x00001000L
# define RADEON_SCALER_TEMPORAL_DEINT 0x00002000L
# define RADEON_SCALER_CRTC_SEL 0x00004000L
# define RADEON_SCALER_SMART_SWITCH 0x00008000L
# define RADEON_SCALER_BURST_PER_PLANE 0x007F0000L
# define RADEON_SCALER_DOUBLE_BUFFER 0x01000000L
# define RADEON_SCALER_DIS_LIMIT 0x08000000L
# define RADEON_SCALER_LIN_TRANS_BYPASS 0x10000000L
# define RADEON_SCALER_INT_EMU 0x20000000L
# define RADEON_SCALER_ENABLE 0x40000000L
# define RADEON_SCALER_SOFT_RESET 0x80000000L
#define RADEON_OV0_STEP_BY 0x0484
#define RADEON_OV0_TEST 0x04F8
#define RADEON_OV0_V_INC 0x0424
#define RADEON_OV0_VID_BUF_PITCH0_VALUE 0x0460
#define RADEON_OV0_VID_BUF_PITCH1_VALUE 0x0464
#define RADEON_OV0_VID_BUF0_BASE_ADRS 0x0440
# define RADEON_VIF_BUF0_PITCH_SEL 0x00000001L
# define RADEON_VIF_BUF0_TILE_ADRS 0x00000002L
# define RADEON_VIF_BUF0_BASE_ADRS_MASK 0x03fffff0L
# define RADEON_VIF_BUF0_1ST_LINE_LSBS_MASK 0x48000000L
#define RADEON_OV0_VID_BUF1_BASE_ADRS 0x0444
# define RADEON_VIF_BUF1_PITCH_SEL 0x00000001L
# define RADEON_VIF_BUF1_TILE_ADRS 0x00000002L
# define RADEON_VIF_BUF1_BASE_ADRS_MASK 0x03fffff0L
# define RADEON_VIF_BUF1_1ST_LINE_LSBS_MASK 0x48000000L
#define RADEON_OV0_VID_BUF2_BASE_ADRS 0x0448
# define RADEON_VIF_BUF2_PITCH_SEL 0x00000001L
# define RADEON_VIF_BUF2_TILE_ADRS 0x00000002L
# define RADEON_VIF_BUF2_BASE_ADRS_MASK 0x03fffff0L
# define RADEON_VIF_BUF2_1ST_LINE_LSBS_MASK 0x48000000L
#define RADEON_OV0_VID_BUF3_BASE_ADRS 0x044C
#define RADEON_OV0_VID_BUF4_BASE_ADRS 0x0450
#define RADEON_OV0_VID_BUF5_BASE_ADRS 0x0454
#define RADEON_OV0_VIDEO_KEY_CLR_HIGH 0x04E8
#define RADEON_OV0_VIDEO_KEY_CLR_LOW 0x04E4
#define RADEON_OV0_Y_X_START 0x0400
#define RADEON_OV0_Y_X_END 0x0404
#define RADEON_OV1_Y_X_START 0x0600
#define RADEON_OV1_Y_X_END 0x0604
#define RADEON_OVR_CLR 0x0230
#define RADEON_OVR_WID_LEFT_RIGHT 0x0234
#define RADEON_OVR_WID_TOP_BOTTOM 0x0238
/* first capture unit */
#define RADEON_CAP0_BUF0_OFFSET 0x0920
#define RADEON_CAP0_BUF1_OFFSET 0x0924
#define RADEON_CAP0_BUF0_EVEN_OFFSET 0x0928
#define RADEON_CAP0_BUF1_EVEN_OFFSET 0x092C
#define RADEON_CAP0_BUF_PITCH 0x0930
#define RADEON_CAP0_V_WINDOW 0x0934
#define RADEON_CAP0_H_WINDOW 0x0938
#define RADEON_CAP0_VBI0_OFFSET 0x093C
#define RADEON_CAP0_VBI1_OFFSET 0x0940
#define RADEON_CAP0_VBI_V_WINDOW 0x0944
#define RADEON_CAP0_VBI_H_WINDOW 0x0948
#define RADEON_CAP0_PORT_MODE_CNTL 0x094C
#define RADEON_CAP0_TRIG_CNTL 0x0950
#define RADEON_CAP0_DEBUG 0x0954
#define RADEON_CAP0_CONFIG 0x0958
# define RADEON_CAP0_CONFIG_CONTINUOS 0x00000001
# define RADEON_CAP0_CONFIG_START_FIELD_EVEN 0x00000002
# define RADEON_CAP0_CONFIG_START_BUF_GET 0x00000004
# define RADEON_CAP0_CONFIG_START_BUF_SET 0x00000008
# define RADEON_CAP0_CONFIG_BUF_TYPE_ALT 0x00000010
# define RADEON_CAP0_CONFIG_BUF_TYPE_FRAME 0x00000020
# define RADEON_CAP0_CONFIG_ONESHOT_MODE_FRAME 0x00000040
# define RADEON_CAP0_CONFIG_BUF_MODE_DOUBLE 0x00000080
# define RADEON_CAP0_CONFIG_BUF_MODE_TRIPLE 0x00000100
# define RADEON_CAP0_CONFIG_MIRROR_EN 0x00000200
# define RADEON_CAP0_CONFIG_ONESHOT_MIRROR_EN 0x00000400
# define RADEON_CAP0_CONFIG_VIDEO_SIGNED_UV 0x00000800
# define RADEON_CAP0_CONFIG_ANC_DECODE_EN 0x00001000
# define RADEON_CAP0_CONFIG_VBI_EN 0x00002000
# define RADEON_CAP0_CONFIG_SOFT_PULL_DOWN_EN 0x00004000
# define RADEON_CAP0_CONFIG_VIP_EXTEND_FLAG_EN 0x00008000
# define RADEON_CAP0_CONFIG_FAKE_FIELD_EN 0x00010000
# define RADEON_CAP0_CONFIG_ODD_ONE_MORE_LINE 0x00020000
# define RADEON_CAP0_CONFIG_EVEN_ONE_MORE_LINE 0x00040000
# define RADEON_CAP0_CONFIG_HORZ_DIVIDE_2 0x00080000
# define RADEON_CAP0_CONFIG_HORZ_DIVIDE_4 0x00100000
# define RADEON_CAP0_CONFIG_VERT_DIVIDE_2 0x00200000
# define RADEON_CAP0_CONFIG_VERT_DIVIDE_4 0x00400000
# define RADEON_CAP0_CONFIG_FORMAT_BROOKTREE 0x00000000
# define RADEON_CAP0_CONFIG_FORMAT_CCIR656 0x00800000
# define RADEON_CAP0_CONFIG_FORMAT_ZV 0x01000000
# define RADEON_CAP0_CONFIG_FORMAT_VIP 0x01800000
# define RADEON_CAP0_CONFIG_FORMAT_TRANSPORT 0x02000000
# define RADEON_CAP0_CONFIG_HORZ_DECIMATOR 0x04000000
# define RADEON_CAP0_CONFIG_VIDEO_IN_YVYU422 0x00000000
# define RADEON_CAP0_CONFIG_VIDEO_IN_VYUY422 0x20000000
# define RADEON_CAP0_CONFIG_VBI_DIVIDE_2 0x40000000
# define RADEON_CAP0_CONFIG_VBI_DIVIDE_4 0x80000000
#define RADEON_CAP0_ANC_ODD_OFFSET 0x095C
#define RADEON_CAP0_ANC_EVEN_OFFSET 0x0960
#define RADEON_CAP0_ANC_H_WINDOW 0x0964
#define RADEON_CAP0_VIDEO_SYNC_TEST 0x0968
#define RADEON_CAP0_ONESHOT_BUF_OFFSET 0x096C
#define RADEON_CAP0_BUF_STATUS 0x0970
/* #define RADEON_CAP0_DWNSC_XRATIO 0x0978 */
/* #define RADEON_CAP0_XSHARPNESS 0x097C */
#define RADEON_CAP0_VBI2_OFFSET 0x0980
#define RADEON_CAP0_VBI3_OFFSET 0x0984
#define RADEON_CAP0_ANC2_OFFSET 0x0988
#define RADEON_CAP0_ANC3_OFFSET 0x098C
#define RADEON_VID_BUFFER_CONTROL 0x0900
/* second capture unit */
#define RADEON_CAP1_BUF0_OFFSET 0x0990
#define RADEON_CAP1_BUF1_OFFSET 0x0994
#define RADEON_CAP1_BUF0_EVEN_OFFSET 0x0998
#define RADEON_CAP1_BUF1_EVEN_OFFSET 0x099C
#define RADEON_CAP1_BUF_PITCH 0x09A0
#define RADEON_CAP1_V_WINDOW 0x09A4
#define RADEON_CAP1_H_WINDOW 0x09A8
#define RADEON_CAP1_VBI_ODD_OFFSET 0x09AC
#define RADEON_CAP1_VBI_EVEN_OFFSET 0x09B0
#define RADEON_CAP1_VBI_V_WINDOW 0x09B4
#define RADEON_CAP1_VBI_H_WINDOW 0x09B8
#define RADEON_CAP1_PORT_MODE_CNTL 0x09BC
#define RADEON_CAP1_TRIG_CNTL 0x09C0
#define RADEON_CAP1_DEBUG 0x09C4
#define RADEON_CAP1_CONFIG 0x09C8
#define RADEON_CAP1_ANC_ODD_OFFSET 0x09CC
#define RADEON_CAP1_ANC_EVEN_OFFSET 0x09D0
#define RADEON_CAP1_ANC_H_WINDOW 0x09D4
#define RADEON_CAP1_VIDEO_SYNC_TEST 0x09D8
#define RADEON_CAP1_ONESHOT_BUF_OFFSET 0x09DC
#define RADEON_CAP1_BUF_STATUS 0x09E0
#define RADEON_CAP1_DWNSC_XRATIO 0x09E8
#define RADEON_CAP1_XSHARPNESS 0x09EC
/* misc multimedia registers */
#define RADEON_IDCT_RUNS 0x1F80
#define RADEON_IDCT_LEVELS 0x1F84
#define RADEON_IDCT_CONTROL 0x1FBC
#define RADEON_IDCT_AUTH_CONTROL 0x1F88
#define RADEON_IDCT_AUTH 0x1F8C
#define RADEON_P2PLL_CNTL 0x002a /* P2PLL */
# define RADEON_P2PLL_RESET (1 << 0)
# define RADEON_P2PLL_SLEEP (1 << 1)
# define RADEON_P2PLL_PVG_MASK (7 << 11)
# define RADEON_P2PLL_PVG_SHIFT 11
# define RADEON_P2PLL_ATOMIC_UPDATE_EN (1 << 16)
# define RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN (1 << 17)
# define RADEON_P2PLL_ATOMIC_UPDATE_VSYNC (1 << 18)
#define RADEON_P2PLL_DIV_0 0x002c
# define RADEON_P2PLL_FB0_DIV_MASK 0x07ff
# define RADEON_P2PLL_POST0_DIV_MASK 0x00070000
#define RADEON_P2PLL_REF_DIV 0x002B /* PLL */
# define RADEON_P2PLL_REF_DIV_MASK 0x03ff
# define RADEON_P2PLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */
# define RADEON_P2PLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */
# define R300_PPLL_REF_DIV_ACC_MASK (0x3ff << 18)
# define R300_PPLL_REF_DIV_ACC_SHIFT 18
#define RADEON_PALETTE_DATA 0x00b4
#define RADEON_PALETTE_30_DATA 0x00b8
#define RADEON_PALETTE_INDEX 0x00b0
#define RADEON_PCI_GART_PAGE 0x017c
#define RADEON_PIXCLKS_CNTL 0x002d
# define RADEON_PIX2CLK_SRC_SEL_MASK 0x03
# define RADEON_PIX2CLK_SRC_SEL_CPUCLK 0x00
# define RADEON_PIX2CLK_SRC_SEL_PSCANCLK 0x01
# define RADEON_PIX2CLK_SRC_SEL_BYTECLK 0x02
# define RADEON_PIX2CLK_SRC_SEL_P2PLLCLK 0x03
# define RADEON_PIX2CLK_ALWAYS_ONb (1<<6)
# define RADEON_PIX2CLK_DAC_ALWAYS_ONb (1<<7)
# define RADEON_PIXCLK_TV_SRC_SEL (1 << 8)
# define RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb (1 << 9)
# define R300_DVOCLK_ALWAYS_ONb (1 << 10)
# define RADEON_PIXCLK_BLEND_ALWAYS_ONb (1 << 11)
# define RADEON_PIXCLK_GV_ALWAYS_ONb (1 << 12)
# define RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb (1 << 13)
# define R300_PIXCLK_DVO_ALWAYS_ONb (1 << 13)
# define RADEON_PIXCLK_LVDS_ALWAYS_ONb (1 << 14)
# define RADEON_PIXCLK_TMDS_ALWAYS_ONb (1 << 15)
# define R300_PIXCLK_TRANS_ALWAYS_ONb (1 << 16)
# define R300_PIXCLK_TVO_ALWAYS_ONb (1 << 17)
# define R300_P2G2CLK_ALWAYS_ONb (1 << 18)
# define R300_P2G2CLK_DAC_ALWAYS_ONb (1 << 19)
# define R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF (1 << 23)
#define RADEON_PLANE_3D_MASK_C 0x1d44
#define RADEON_PLL_TEST_CNTL 0x0013 /* PLL */
# define RADEON_PLL_MASK_READ_B (1 << 9)
#define RADEON_PMI_CAP_ID 0x0f5c /* PCI */
#define RADEON_PMI_DATA 0x0f63 /* PCI */
#define RADEON_PMI_NXT_CAP_PTR 0x0f5d /* PCI */
#define RADEON_PMI_PMC_REG 0x0f5e /* PCI */
#define RADEON_PMI_PMCSR_REG 0x0f60 /* PCI */
#define RADEON_PMI_REGISTER 0x0f5c /* PCI */
#define RADEON_PPLL_CNTL 0x0002 /* PLL */
# define RADEON_PPLL_RESET (1 << 0)
# define RADEON_PPLL_SLEEP (1 << 1)
# define RADEON_PPLL_PVG_MASK (7 << 11)
# define RADEON_PPLL_PVG_SHIFT 11
# define RADEON_PPLL_ATOMIC_UPDATE_EN (1 << 16)
# define RADEON_PPLL_VGA_ATOMIC_UPDATE_EN (1 << 17)
# define RADEON_PPLL_ATOMIC_UPDATE_VSYNC (1 << 18)
#define RADEON_PPLL_DIV_0 0x0004 /* PLL */
#define RADEON_PPLL_DIV_1 0x0005 /* PLL */
#define RADEON_PPLL_DIV_2 0x0006 /* PLL */
#define RADEON_PPLL_DIV_3 0x0007 /* PLL */
# define RADEON_PPLL_FB3_DIV_MASK 0x07ff
# define RADEON_PPLL_POST3_DIV_MASK 0x00070000
#define RADEON_PPLL_REF_DIV 0x0003 /* PLL */
# define RADEON_PPLL_REF_DIV_MASK 0x03ff
# define RADEON_PPLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */
# define RADEON_PPLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */
#define RADEON_PWR_MNGMT_CNTL_STATUS 0x0f60 /* PCI */
#define RADEON_RBBM_GUICNTL 0x172c
# define RADEON_HOST_DATA_SWAP_NONE (0 << 0)
# define RADEON_HOST_DATA_SWAP_16BIT (1 << 0)
# define RADEON_HOST_DATA_SWAP_32BIT (2 << 0)
# define RADEON_HOST_DATA_SWAP_HDW (3 << 0)
#define RADEON_RBBM_SOFT_RESET 0x00f0
# define RADEON_SOFT_RESET_CP (1 << 0)
# define RADEON_SOFT_RESET_HI (1 << 1)
# define RADEON_SOFT_RESET_SE (1 << 2)
# define RADEON_SOFT_RESET_RE (1 << 3)
# define RADEON_SOFT_RESET_PP (1 << 4)
# define RADEON_SOFT_RESET_E2 (1 << 5)
# define RADEON_SOFT_RESET_RB (1 << 6)
# define RADEON_SOFT_RESET_HDP (1 << 7)
#define RADEON_RBBM_STATUS 0x0e40
# define RADEON_RBBM_FIFOCNT_MASK 0x007f
# define RADEON_RBBM_ACTIVE (1 << 31)
#define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c
# define RADEON_RB2D_DC_FLUSH (3 << 0)
# define RADEON_RB2D_DC_FREE (3 << 2)
# define RADEON_RB2D_DC_FLUSH_ALL 0xf
# define RADEON_RB2D_DC_BUSY (1 << 31)
#define RADEON_RB2D_DSTCACHE_MODE 0x3428
#define RADEON_DSTCACHE_CTLSTAT 0x1714
#define RADEON_RB3D_ZCACHE_MODE 0x3250
#define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254
# define RADEON_RB3D_ZC_FLUSH_ALL 0x5
#define RADEON_RB3D_DSTCACHE_MODE 0x3258
# define RADEON_RB3D_DC_CACHE_ENABLE (0)
# define RADEON_RB3D_DC_2D_CACHE_DISABLE (1)
# define RADEON_RB3D_DC_3D_CACHE_DISABLE (2)
# define RADEON_RB3D_DC_CACHE_DISABLE (3)
# define RADEON_RB3D_DC_2D_CACHE_LINESIZE_128 (1 << 2)
# define RADEON_RB3D_DC_3D_CACHE_LINESIZE_128 (2 << 2)
# define RADEON_RB3D_DC_2D_CACHE_AUTOFLUSH (1 << 8)
# define RADEON_RB3D_DC_3D_CACHE_AUTOFLUSH (2 << 8)
# define R200_RB3D_DC_2D_CACHE_AUTOFREE (1 << 10)
# define R200_RB3D_DC_3D_CACHE_AUTOFREE (2 << 10)
# define RADEON_RB3D_DC_FORCE_RMW (1 << 16)
# define RADEON_RB3D_DC_DISABLE_RI_FILL (1 << 24)
# define RADEON_RB3D_DC_DISABLE_RI_READ (1 << 25)
#define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325C
# define RADEON_RB3D_DC_FLUSH (3 << 0)
# define RADEON_RB3D_DC_FREE (3 << 2)
# define RADEON_RB3D_DC_FLUSH_ALL 0xf
# define RADEON_RB3D_DC_BUSY (1 << 31)
#define RADEON_REG_BASE 0x0f18 /* PCI */
#define RADEON_REGPROG_INF 0x0f09 /* PCI */
#define RADEON_REVISION_ID 0x0f08 /* PCI */
#define RADEON_SC_BOTTOM 0x164c
#define RADEON_SC_BOTTOM_RIGHT 0x16f0
#define RADEON_SC_BOTTOM_RIGHT_C 0x1c8c
#define RADEON_SC_LEFT 0x1640
#define RADEON_SC_RIGHT 0x1644
#define RADEON_SC_TOP 0x1648
#define RADEON_SC_TOP_LEFT 0x16ec
#define RADEON_SC_TOP_LEFT_C 0x1c88
# define RADEON_SC_SIGN_MASK_LO 0x8000
# define RADEON_SC_SIGN_MASK_HI 0x80000000
#define RADEON_SCLK_CNTL 0x000d /* PLL */
# define RADEON_SCLK_SRC_SEL_MASK 0x0007
# define RADEON_DYN_STOP_LAT_MASK 0x00007ff8
# define RADEON_CP_MAX_DYN_STOP_LAT 0x0008
# define RADEON_SCLK_FORCEON_MASK 0xffff8000
# define RADEON_SCLK_FORCE_DISP2 (1<<15)
# define RADEON_SCLK_FORCE_CP (1<<16)
# define RADEON_SCLK_FORCE_HDP (1<<17)
# define RADEON_SCLK_FORCE_DISP1 (1<<18)
# define RADEON_SCLK_FORCE_TOP (1<<19)
# define RADEON_SCLK_FORCE_E2 (1<<20)
# define RADEON_SCLK_FORCE_SE (1<<21)
# define RADEON_SCLK_FORCE_IDCT (1<<22)
# define RADEON_SCLK_FORCE_VIP (1<<23)
# define RADEON_SCLK_FORCE_RE (1<<24)
# define RADEON_SCLK_FORCE_PB (1<<25)
# define RADEON_SCLK_FORCE_TAM (1<<26)
# define RADEON_SCLK_FORCE_TDM (1<<27)
# define RADEON_SCLK_FORCE_RB (1<<28)
# define RADEON_SCLK_FORCE_TV_SCLK (1<<29)
# define RADEON_SCLK_FORCE_SUBPIC (1<<30)
# define RADEON_SCLK_FORCE_OV0 (1<<31)
# define R300_SCLK_FORCE_VAP (1<<21)
# define R300_SCLK_FORCE_SR (1<<25)
# define R300_SCLK_FORCE_PX (1<<26)
# define R300_SCLK_FORCE_TX (1<<27)
# define R300_SCLK_FORCE_US (1<<28)
# define R300_SCLK_FORCE_SU (1<<30)
#define R300_SCLK_CNTL2 0x1e /* PLL */
# define R300_SCLK_TCL_MAX_DYN_STOP_LAT (1<<10)
# define R300_SCLK_GA_MAX_DYN_STOP_LAT (1<<11)
# define R300_SCLK_CBA_MAX_DYN_STOP_LAT (1<<12)
# define R300_SCLK_FORCE_TCL (1<<13)
# define R300_SCLK_FORCE_CBA (1<<14)
# define R300_SCLK_FORCE_GA (1<<15)
#define RADEON_SCLK_MORE_CNTL 0x0035 /* PLL */
# define RADEON_SCLK_MORE_MAX_DYN_STOP_LAT 0x0007
# define RADEON_SCLK_MORE_FORCEON 0x0700
#define RADEON_SDRAM_MODE_REG 0x0158
#define RADEON_SEQ8_DATA 0x03c5 /* VGA */
#define RADEON_SEQ8_IDX 0x03c4 /* VGA */
#define RADEON_SNAPSHOT_F_COUNT 0x0244
#define RADEON_SNAPSHOT_VH_COUNTS 0x0240
#define RADEON_SNAPSHOT_VIF_COUNT 0x024c
#define RADEON_SRC_OFFSET 0x15ac
#define RADEON_SRC_PITCH 0x15b0
#define RADEON_SRC_PITCH_OFFSET 0x1428
#define RADEON_SRC_SC_BOTTOM 0x165c
#define RADEON_SRC_SC_BOTTOM_RIGHT 0x16f4
#define RADEON_SRC_SC_RIGHT 0x1654
#define RADEON_SRC_X 0x1414
#define RADEON_SRC_X_Y 0x1590
#define RADEON_SRC_Y 0x1418
#define RADEON_SRC_Y_X 0x1434
#define RADEON_STATUS 0x0f06 /* PCI */
#define RADEON_SUBPIC_CNTL 0x0540 /* ? */
#define RADEON_SUB_CLASS 0x0f0a /* PCI */
#define RADEON_SURFACE_CNTL 0x0b00
# define RADEON_SURF_TRANSLATION_DIS (1 << 8)
# define RADEON_NONSURF_AP0_SWP_16BPP (1 << 20)
# define RADEON_NONSURF_AP0_SWP_32BPP (1 << 21)
# define RADEON_NONSURF_AP1_SWP_16BPP (1 << 22)
# define RADEON_NONSURF_AP1_SWP_32BPP (1 << 23)
#define RADEON_SURFACE0_INFO 0x0b0c
# define RADEON_SURF_TILE_COLOR_MACRO (0 << 16)
# define RADEON_SURF_TILE_COLOR_BOTH (1 << 16)
# define RADEON_SURF_TILE_DEPTH_32BPP (2 << 16)
# define RADEON_SURF_TILE_DEPTH_16BPP (3 << 16)
# define R200_SURF_TILE_NONE (0 << 16)
# define R200_SURF_TILE_COLOR_MACRO (1 << 16)
# define R200_SURF_TILE_COLOR_MICRO (2 << 16)
# define R200_SURF_TILE_COLOR_BOTH (3 << 16)
# define R200_SURF_TILE_DEPTH_32BPP (4 << 16)
# define R200_SURF_TILE_DEPTH_16BPP (5 << 16)
# define R300_SURF_TILE_NONE (0 << 16)
# define R300_SURF_TILE_COLOR_MACRO (1 << 16)
# define R300_SURF_TILE_DEPTH_32BPP (2 << 16)
# define RADEON_SURF_AP0_SWP_16BPP (1 << 20)
# define RADEON_SURF_AP0_SWP_32BPP (1 << 21)
# define RADEON_SURF_AP1_SWP_16BPP (1 << 22)
# define RADEON_SURF_AP1_SWP_32BPP (1 << 23)
#define RADEON_SURFACE0_LOWER_BOUND 0x0b04
#define RADEON_SURFACE0_UPPER_BOUND 0x0b08
#define RADEON_SURFACE1_INFO 0x0b1c
#define RADEON_SURFACE1_LOWER_BOUND 0x0b14
#define RADEON_SURFACE1_UPPER_BOUND 0x0b18
#define RADEON_SURFACE2_INFO 0x0b2c
#define RADEON_SURFACE2_LOWER_BOUND 0x0b24
#define RADEON_SURFACE2_UPPER_BOUND 0x0b28
#define RADEON_SURFACE3_INFO 0x0b3c
#define RADEON_SURFACE3_LOWER_BOUND 0x0b34
#define RADEON_SURFACE3_UPPER_BOUND 0x0b38
#define RADEON_SURFACE4_INFO 0x0b4c
#define RADEON_SURFACE4_LOWER_BOUND 0x0b44
#define RADEON_SURFACE4_UPPER_BOUND 0x0b48
#define RADEON_SURFACE5_INFO 0x0b5c
#define RADEON_SURFACE5_LOWER_BOUND 0x0b54
#define RADEON_SURFACE5_UPPER_BOUND 0x0b58
#define RADEON_SURFACE6_INFO 0x0b6c
#define RADEON_SURFACE6_LOWER_BOUND 0x0b64
#define RADEON_SURFACE6_UPPER_BOUND 0x0b68
#define RADEON_SURFACE7_INFO 0x0b7c
#define RADEON_SURFACE7_LOWER_BOUND 0x0b74
#define RADEON_SURFACE7_UPPER_BOUND 0x0b78
#define RADEON_SW_SEMAPHORE 0x013c
#define RADEON_TEST_DEBUG_CNTL 0x0120
#define RADEON_TEST_DEBUG_CNTL__TEST_DEBUG_OUT_EN 0x00000001
#define RADEON_TEST_DEBUG_MUX 0x0124
#define RADEON_TEST_DEBUG_OUT 0x012c
#define RADEON_TMDS_PLL_CNTL 0x02a8
#define RADEON_TMDS_TRANSMITTER_CNTL 0x02a4
# define RADEON_TMDS_TRANSMITTER_PLLEN 1
# define RADEON_TMDS_TRANSMITTER_PLLRST 2
#define RADEON_TRAIL_BRES_DEC 0x1614
#define RADEON_TRAIL_BRES_ERR 0x160c
#define RADEON_TRAIL_BRES_INC 0x1610
#define RADEON_TRAIL_X 0x1618
#define RADEON_TRAIL_X_SUB 0x1620
#define RADEON_VCLK_ECP_CNTL 0x0008 /* PLL */
# define RADEON_VCLK_SRC_SEL_MASK 0x03
# define RADEON_VCLK_SRC_SEL_CPUCLK 0x00
# define RADEON_VCLK_SRC_SEL_PSCANCLK 0x01
# define RADEON_VCLK_SRC_SEL_BYTECLK 0x02
# define RADEON_VCLK_SRC_SEL_PPLLCLK 0x03
# define RADEON_PIXCLK_ALWAYS_ONb (1<<6)
# define RADEON_PIXCLK_DAC_ALWAYS_ONb (1<<7)
# define R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF (1<<23)
#define RADEON_VENDOR_ID 0x0f00 /* PCI */
#define RADEON_VGA_DDA_CONFIG 0x02e8
#define RADEON_VGA_DDA_ON_OFF 0x02ec
#define RADEON_VID_BUFFER_CONTROL 0x0900
#define RADEON_VIDEOMUX_CNTL 0x0190
/* VIP bus */
#define RADEON_VIPH_CH0_DATA 0x0c00
#define RADEON_VIPH_CH1_DATA 0x0c04
#define RADEON_VIPH_CH2_DATA 0x0c08
#define RADEON_VIPH_CH3_DATA 0x0c0c
#define RADEON_VIPH_CH0_ADDR 0x0c10
#define RADEON_VIPH_CH1_ADDR 0x0c14
#define RADEON_VIPH_CH2_ADDR 0x0c18
#define RADEON_VIPH_CH3_ADDR 0x0c1c
#define RADEON_VIPH_CH0_SBCNT 0x0c20
#define RADEON_VIPH_CH1_SBCNT 0x0c24
#define RADEON_VIPH_CH2_SBCNT 0x0c28
#define RADEON_VIPH_CH3_SBCNT 0x0c2c
#define RADEON_VIPH_CH0_ABCNT 0x0c30
#define RADEON_VIPH_CH1_ABCNT 0x0c34
#define RADEON_VIPH_CH2_ABCNT 0x0c38
#define RADEON_VIPH_CH3_ABCNT 0x0c3c
#define RADEON_VIPH_CONTROL 0x0c40
# define RADEON_VIP_BUSY 0
# define RADEON_VIP_IDLE 1
# define RADEON_VIP_RESET 2
# define RADEON_VIPH_EN (1 << 21)
#define RADEON_VIPH_DV_LAT 0x0c44
#define RADEON_VIPH_BM_CHUNK 0x0c48
#define RADEON_VIPH_DV_INT 0x0c4c
#define RADEON_VIPH_TIMEOUT_STAT 0x0c50
#define RADEON_VIPH_TIMEOUT_STAT__VIPH_REG_STAT 0x00000010
#define RADEON_VIPH_TIMEOUT_STAT__VIPH_REG_AK 0x00000010
#define RADEON_VIPH_TIMEOUT_STAT__VIPH_REGR_DIS 0x01000000
#define RADEON_VIPH_REG_DATA 0x0084
#define RADEON_VIPH_REG_ADDR 0x0080
#define RADEON_WAIT_UNTIL 0x1720
# define RADEON_WAIT_CRTC_PFLIP (1 << 0)
# define RADEON_WAIT_RE_CRTC_VLINE (1 << 1)
# define RADEON_WAIT_FE_CRTC_VLINE (1 << 2)
# define RADEON_WAIT_CRTC_VLINE (1 << 3)
# define RADEON_WAIT_DMA_VID_IDLE (1 << 8)
# define RADEON_WAIT_DMA_GUI_IDLE (1 << 9)
# define RADEON_WAIT_CMDFIFO (1 << 10) /* wait for CMDFIFO_ENTRIES */
# define RADEON_WAIT_OV0_FLIP (1 << 11)
# define RADEON_WAIT_AGP_FLUSH (1 << 13)
# define RADEON_WAIT_2D_IDLE (1 << 14)
# define RADEON_WAIT_3D_IDLE (1 << 15)
# define RADEON_WAIT_2D_IDLECLEAN (1 << 16)
# define RADEON_WAIT_3D_IDLECLEAN (1 << 17)
# define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)
# define RADEON_CMDFIFO_ENTRIES_SHIFT 10
# define RADEON_CMDFIFO_ENTRIES_MASK 0x7f
# define RADEON_WAIT_VAP_IDLE (1 << 28)
# define RADEON_WAIT_BOTH_CRTC_PFLIP (1 << 30)
# define RADEON_ENG_DISPLAY_SELECT_CRTC0 (0 << 31)
# define RADEON_ENG_DISPLAY_SELECT_CRTC1 (1 << 31)
#define RADEON_X_MPLL_REF_FB_DIV 0x000a /* PLL */
#define RADEON_XCLK_CNTL 0x000d /* PLL */
#define RADEON_XDLL_CNTL 0x000c /* PLL */
#define RADEON_XPLL_CNTL 0x000b /* PLL */
/* Registers for 3D/TCL */
#define RADEON_PP_BORDER_COLOR_0 0x1d40
#define RADEON_PP_BORDER_COLOR_1 0x1d44
#define RADEON_PP_BORDER_COLOR_2 0x1d48
#define RADEON_PP_CNTL 0x1c38
# define RADEON_STIPPLE_ENABLE (1 << 0)
# define RADEON_SCISSOR_ENABLE (1 << 1)
# define RADEON_PATTERN_ENABLE (1 << 2)
# define RADEON_SHADOW_ENABLE (1 << 3)
# define RADEON_TEX_ENABLE_MASK (0xf << 4)
# define RADEON_TEX_0_ENABLE (1 << 4)
# define RADEON_TEX_1_ENABLE (1 << 5)
# define RADEON_TEX_2_ENABLE (1 << 6)
# define RADEON_TEX_3_ENABLE (1 << 7)
# define RADEON_TEX_BLEND_ENABLE_MASK (0xf << 12)
# define RADEON_TEX_BLEND_0_ENABLE (1 << 12)
# define RADEON_TEX_BLEND_1_ENABLE (1 << 13)
# define RADEON_TEX_BLEND_2_ENABLE (1 << 14)
# define RADEON_TEX_BLEND_3_ENABLE (1 << 15)
# define RADEON_PLANAR_YUV_ENABLE (1 << 20)
# define RADEON_SPECULAR_ENABLE (1 << 21)
# define RADEON_FOG_ENABLE (1 << 22)
# define RADEON_ALPHA_TEST_ENABLE (1 << 23)
# define RADEON_ANTI_ALIAS_NONE (0 << 24)
# define RADEON_ANTI_ALIAS_LINE (1 << 24)
# define RADEON_ANTI_ALIAS_POLY (2 << 24)
# define RADEON_ANTI_ALIAS_LINE_POLY (3 << 24)
# define RADEON_BUMP_MAP_ENABLE (1 << 26)
# define RADEON_BUMPED_MAP_T0 (0 << 27)
# define RADEON_BUMPED_MAP_T1 (1 << 27)
# define RADEON_BUMPED_MAP_T2 (2 << 27)
# define RADEON_TEX_3D_ENABLE_0 (1 << 29)
# define RADEON_TEX_3D_ENABLE_1 (1 << 30)
# define RADEON_MC_ENABLE (1 << 31)
#define RADEON_PP_FOG_COLOR 0x1c18
# define RADEON_FOG_COLOR_MASK 0x00ffffff
# define RADEON_FOG_VERTEX (0 << 24)
# define RADEON_FOG_TABLE (1 << 24)
# define RADEON_FOG_USE_DEPTH (0 << 25)
# define RADEON_FOG_USE_DIFFUSE_ALPHA (2 << 25)
# define RADEON_FOG_USE_SPEC_ALPHA (3 << 25)
#define RADEON_PP_LUM_MATRIX 0x1d00
#define RADEON_PP_MISC 0x1c14
# define RADEON_REF_ALPHA_MASK 0x000000ff
# define RADEON_ALPHA_TEST_FAIL (0 << 8)
# define RADEON_ALPHA_TEST_LESS (1 << 8)
# define RADEON_ALPHA_TEST_LEQUAL (2 << 8)
# define RADEON_ALPHA_TEST_EQUAL (3 << 8)
# define RADEON_ALPHA_TEST_GEQUAL (4 << 8)
# define RADEON_ALPHA_TEST_GREATER (5 << 8)
# define RADEON_ALPHA_TEST_NEQUAL (6 << 8)
# define RADEON_ALPHA_TEST_PASS (7 << 8)
# define RADEON_ALPHA_TEST_OP_MASK (7 << 8)
# define RADEON_CHROMA_FUNC_FAIL (0 << 16)
# define RADEON_CHROMA_FUNC_PASS (1 << 16)
# define RADEON_CHROMA_FUNC_NEQUAL (2 << 16)
# define RADEON_CHROMA_FUNC_EQUAL (3 << 16)
# define RADEON_CHROMA_KEY_NEAREST (0 << 18)
# define RADEON_CHROMA_KEY_ZERO (1 << 18)
# define RADEON_SHADOW_ID_AUTO_INC (1 << 20)
# define RADEON_SHADOW_FUNC_EQUAL (0 << 21)
# define RADEON_SHADOW_FUNC_NEQUAL (1 << 21)
# define RADEON_SHADOW_PASS_1 (0 << 22)
# define RADEON_SHADOW_PASS_2 (1 << 22)
# define RADEON_RIGHT_HAND_CUBE_D3D (0 << 24)
# define RADEON_RIGHT_HAND_CUBE_OGL (1 << 24)
#define RADEON_PP_ROT_MATRIX_0 0x1d58
#define RADEON_PP_ROT_MATRIX_1 0x1d5c
#define RADEON_PP_TXFILTER_0 0x1c54
#define RADEON_PP_TXFILTER_1 0x1c6c
#define RADEON_PP_TXFILTER_2 0x1c84
# define RADEON_MAG_FILTER_NEAREST (0 << 0)
# define RADEON_MAG_FILTER_LINEAR (1 << 0)
# define RADEON_MAG_FILTER_MASK (1 << 0)
# define RADEON_MIN_FILTER_NEAREST (0 << 1)
# define RADEON_MIN_FILTER_LINEAR (1 << 1)
# define RADEON_MIN_FILTER_NEAREST_MIP_NEAREST (2 << 1)
# define RADEON_MIN_FILTER_NEAREST_MIP_LINEAR (3 << 1)
# define RADEON_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 1)
# define RADEON_MIN_FILTER_LINEAR_MIP_LINEAR (7 << 1)
# define RADEON_MIN_FILTER_ANISO_NEAREST (8 << 1)
# define RADEON_MIN_FILTER_ANISO_LINEAR (9 << 1)
# define RADEON_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (10 << 1)
# define RADEON_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (11 << 1)
# define RADEON_MIN_FILTER_MASK (15 << 1)
# define RADEON_MAX_ANISO_1_TO_1 (0 << 5)
# define RADEON_MAX_ANISO_2_TO_1 (1 << 5)
# define RADEON_MAX_ANISO_4_TO_1 (2 << 5)
# define RADEON_MAX_ANISO_8_TO_1 (3 << 5)
# define RADEON_MAX_ANISO_16_TO_1 (4 << 5)
# define RADEON_MAX_ANISO_MASK (7 << 5)
# define RADEON_LOD_BIAS_MASK (0xff << 8)
# define RADEON_LOD_BIAS_SHIFT 8
# define RADEON_MAX_MIP_LEVEL_MASK (0x0f << 16)
# define RADEON_MAX_MIP_LEVEL_SHIFT 16
# define RADEON_YUV_TO_RGB (1 << 20)
# define RADEON_YUV_TEMPERATURE_COOL (0 << 21)
# define RADEON_YUV_TEMPERATURE_HOT (1 << 21)
# define RADEON_YUV_TEMPERATURE_MASK (1 << 21)
# define RADEON_WRAPEN_S (1 << 22)
# define RADEON_CLAMP_S_WRAP (0 << 23)
# define RADEON_CLAMP_S_MIRROR (1 << 23)
# define RADEON_CLAMP_S_CLAMP_LAST (2 << 23)
# define RADEON_CLAMP_S_MIRROR_CLAMP_LAST (3 << 23)
# define RADEON_CLAMP_S_CLAMP_BORDER (4 << 23)
# define RADEON_CLAMP_S_MIRROR_CLAMP_BORDER (5 << 23)
# define RADEON_CLAMP_S_CLAMP_GL (6 << 23)
# define RADEON_CLAMP_S_MIRROR_CLAMP_GL (7 << 23)
# define RADEON_CLAMP_S_MASK (7 << 23)
# define RADEON_WRAPEN_T (1 << 26)
# define RADEON_CLAMP_T_WRAP (0 << 27)
# define RADEON_CLAMP_T_MIRROR (1 << 27)
# define RADEON_CLAMP_T_CLAMP_LAST (2 << 27)
# define RADEON_CLAMP_T_MIRROR_CLAMP_LAST (3 << 27)
# define RADEON_CLAMP_T_CLAMP_BORDER (4 << 27)
# define RADEON_CLAMP_T_MIRROR_CLAMP_BORDER (5 << 27)
# define RADEON_CLAMP_T_CLAMP_GL (6 << 27)
# define RADEON_CLAMP_T_MIRROR_CLAMP_GL (7 << 27)
# define RADEON_CLAMP_T_MASK (7 << 27)
# define RADEON_BORDER_MODE_OGL (0 << 31)
# define RADEON_BORDER_MODE_D3D (1 << 31)
#define RADEON_PP_TXFORMAT_0 0x1c58
#define RADEON_PP_TXFORMAT_1 0x1c70
#define RADEON_PP_TXFORMAT_2 0x1c88
# define RADEON_TXFORMAT_I8 (0 << 0)
# define RADEON_TXFORMAT_AI88 (1 << 0)
# define RADEON_TXFORMAT_RGB332 (2 << 0)
# define RADEON_TXFORMAT_ARGB1555 (3 << 0)
# define RADEON_TXFORMAT_RGB565 (4 << 0)
# define RADEON_TXFORMAT_ARGB4444 (5 << 0)
# define RADEON_TXFORMAT_ARGB8888 (6 << 0)
# define RADEON_TXFORMAT_RGBA8888 (7 << 0)
# define RADEON_TXFORMAT_Y8 (8 << 0)
# define RADEON_TXFORMAT_VYUY422 (10 << 0)
# define RADEON_TXFORMAT_YVYU422 (11 << 0)
# define RADEON_TXFORMAT_DXT1 (12 << 0)
# define RADEON_TXFORMAT_DXT23 (14 << 0)
# define RADEON_TXFORMAT_DXT45 (15 << 0)
# define RADEON_TXFORMAT_FORMAT_MASK (31 << 0)
# define RADEON_TXFORMAT_FORMAT_SHIFT 0
# define RADEON_TXFORMAT_APPLE_YUV_MODE (1 << 5)
# define RADEON_TXFORMAT_ALPHA_IN_MAP (1 << 6)
# define RADEON_TXFORMAT_NON_POWER2 (1 << 7)
# define RADEON_TXFORMAT_WIDTH_MASK (15 << 8)
# define RADEON_TXFORMAT_WIDTH_SHIFT 8
# define RADEON_TXFORMAT_HEIGHT_MASK (15 << 12)
# define RADEON_TXFORMAT_HEIGHT_SHIFT 12
# define RADEON_TXFORMAT_F5_WIDTH_MASK (15 << 16)
# define RADEON_TXFORMAT_F5_WIDTH_SHIFT 16
# define RADEON_TXFORMAT_F5_HEIGHT_MASK (15 << 20)
# define RADEON_TXFORMAT_F5_HEIGHT_SHIFT 20
# define RADEON_TXFORMAT_ST_ROUTE_STQ0 (0 << 24)
# define RADEON_TXFORMAT_ST_ROUTE_MASK (3 << 24)
# define RADEON_TXFORMAT_ST_ROUTE_STQ1 (1 << 24)
# define RADEON_TXFORMAT_ST_ROUTE_STQ2 (2 << 24)
# define RADEON_TXFORMAT_ENDIAN_NO_SWAP (0 << 26)
# define RADEON_TXFORMAT_ENDIAN_16BPP_SWAP (1 << 26)
# define RADEON_TXFORMAT_ENDIAN_32BPP_SWAP (2 << 26)
# define RADEON_TXFORMAT_ENDIAN_HALFDW_SWAP (3 << 26)
# define RADEON_TXFORMAT_ALPHA_MASK_ENABLE (1 << 28)
# define RADEON_TXFORMAT_CHROMA_KEY_ENABLE (1 << 29)
# define RADEON_TXFORMAT_CUBIC_MAP_ENABLE (1 << 30)
# define RADEON_TXFORMAT_PERSPECTIVE_ENABLE (1 << 31)
#define RADEON_PP_CUBIC_FACES_0 0x1d24
#define RADEON_PP_CUBIC_FACES_1 0x1d28
#define RADEON_PP_CUBIC_FACES_2 0x1d2c
# define RADEON_FACE_WIDTH_1_SHIFT 0
# define RADEON_FACE_HEIGHT_1_SHIFT 4
# define RADEON_FACE_WIDTH_1_MASK (0xf << 0)
# define RADEON_FACE_HEIGHT_1_MASK (0xf << 4)
# define RADEON_FACE_WIDTH_2_SHIFT 8
# define RADEON_FACE_HEIGHT_2_SHIFT 12
# define RADEON_FACE_WIDTH_2_MASK (0xf << 8)
# define RADEON_FACE_HEIGHT_2_MASK (0xf << 12)
# define RADEON_FACE_WIDTH_3_SHIFT 16
# define RADEON_FACE_HEIGHT_3_SHIFT 20
# define RADEON_FACE_WIDTH_3_MASK (0xf << 16)
# define RADEON_FACE_HEIGHT_3_MASK (0xf << 20)
# define RADEON_FACE_WIDTH_4_SHIFT 24
# define RADEON_FACE_HEIGHT_4_SHIFT 28
# define RADEON_FACE_WIDTH_4_MASK (0xf << 24)
# define RADEON_FACE_HEIGHT_4_MASK (0xf << 28)
#define RADEON_PP_TXOFFSET_0 0x1c5c
#define RADEON_PP_TXOFFSET_1 0x1c74
#define RADEON_PP_TXOFFSET_2 0x1c8c
# define RADEON_TXO_ENDIAN_NO_SWAP (0 << 0)
# define RADEON_TXO_ENDIAN_BYTE_SWAP (1 << 0)
# define RADEON_TXO_ENDIAN_WORD_SWAP (2 << 0)
# define RADEON_TXO_ENDIAN_HALFDW_SWAP (3 << 0)
# define RADEON_TXO_MACRO_LINEAR (0 << 2)
# define RADEON_TXO_MACRO_TILE (1 << 2)
# define RADEON_TXO_MICRO_LINEAR (0 << 3)
# define RADEON_TXO_MICRO_TILE_X2 (1 << 3)
# define RADEON_TXO_MICRO_TILE_OPT (2 << 3)
# define RADEON_TXO_OFFSET_MASK 0xffffffe0
# define RADEON_TXO_OFFSET_SHIFT 5
#define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */
#define RADEON_PP_CUBIC_OFFSET_T0_1 0x1dd4
#define RADEON_PP_CUBIC_OFFSET_T0_2 0x1dd8
#define RADEON_PP_CUBIC_OFFSET_T0_3 0x1ddc
#define RADEON_PP_CUBIC_OFFSET_T0_4 0x1de0
#define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00
#define RADEON_PP_CUBIC_OFFSET_T1_1 0x1e04
#define RADEON_PP_CUBIC_OFFSET_T1_2 0x1e08
#define RADEON_PP_CUBIC_OFFSET_T1_3 0x1e0c
#define RADEON_PP_CUBIC_OFFSET_T1_4 0x1e10
#define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14
#define RADEON_PP_CUBIC_OFFSET_T2_1 0x1e18
#define RADEON_PP_CUBIC_OFFSET_T2_2 0x1e1c
#define RADEON_PP_CUBIC_OFFSET_T2_3 0x1e20
#define RADEON_PP_CUBIC_OFFSET_T2_4 0x1e24
#define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */
#define RADEON_PP_TEX_SIZE_1 0x1d0c
#define RADEON_PP_TEX_SIZE_2 0x1d14
# define RADEON_TEX_USIZE_MASK (0x7ff << 0)
# define RADEON_TEX_USIZE_SHIFT 0
# define RADEON_TEX_VSIZE_MASK (0x7ff << 16)
# define RADEON_TEX_VSIZE_SHIFT 16
# define RADEON_SIGNED_RGB_MASK (1 << 30)
# define RADEON_SIGNED_RGB_SHIFT 30
# define RADEON_SIGNED_ALPHA_MASK (1 << 31)
# define RADEON_SIGNED_ALPHA_SHIFT 31
#define RADEON_PP_TEX_PITCH_0 0x1d08 /* NPOT */
#define RADEON_PP_TEX_PITCH_1 0x1d10 /* NPOT */
#define RADEON_PP_TEX_PITCH_2 0x1d18 /* NPOT */
/* note: bits 13-5: 32 byte aligned stride of texture map */
#define RADEON_PP_TXCBLEND_0 0x1c60
#define RADEON_PP_TXCBLEND_1 0x1c78
#define RADEON_PP_TXCBLEND_2 0x1c90
# define RADEON_COLOR_ARG_A_SHIFT 0
# define RADEON_COLOR_ARG_A_MASK (0x1f << 0)
# define RADEON_COLOR_ARG_A_ZERO (0 << 0)
# define RADEON_COLOR_ARG_A_CURRENT_COLOR (2 << 0)
# define RADEON_COLOR_ARG_A_CURRENT_ALPHA (3 << 0)
# define RADEON_COLOR_ARG_A_DIFFUSE_COLOR (4 << 0)
# define RADEON_COLOR_ARG_A_DIFFUSE_ALPHA (5 << 0)
# define RADEON_COLOR_ARG_A_SPECULAR_COLOR (6 << 0)
# define RADEON_COLOR_ARG_A_SPECULAR_ALPHA (7 << 0)
# define RADEON_COLOR_ARG_A_TFACTOR_COLOR (8 << 0)
# define RADEON_COLOR_ARG_A_TFACTOR_ALPHA (9 << 0)
# define RADEON_COLOR_ARG_A_T0_COLOR (10 << 0)
# define RADEON_COLOR_ARG_A_T0_ALPHA (11 << 0)
# define RADEON_COLOR_ARG_A_T1_COLOR (12 << 0)
# define RADEON_COLOR_ARG_A_T1_ALPHA (13 << 0)
# define RADEON_COLOR_ARG_A_T2_COLOR (14 << 0)
# define RADEON_COLOR_ARG_A_T2_ALPHA (15 << 0)
# define RADEON_COLOR_ARG_A_T3_COLOR (16 << 0)
# define RADEON_COLOR_ARG_A_T3_ALPHA (17 << 0)
# define RADEON_COLOR_ARG_B_SHIFT 5
# define RADEON_COLOR_ARG_B_MASK (0x1f << 5)
# define RADEON_COLOR_ARG_B_ZERO (0 << 5)
# define RADEON_COLOR_ARG_B_CURRENT_COLOR (2 << 5)
# define RADEON_COLOR_ARG_B_CURRENT_ALPHA (3 << 5)
# define RADEON_COLOR_ARG_B_DIFFUSE_COLOR (4 << 5)
# define RADEON_COLOR_ARG_B_DIFFUSE_ALPHA (5 << 5)
# define RADEON_COLOR_ARG_B_SPECULAR_COLOR (6 << 5)
# define RADEON_COLOR_ARG_B_SPECULAR_ALPHA (7 << 5)
# define RADEON_COLOR_ARG_B_TFACTOR_COLOR (8 << 5)
# define RADEON_COLOR_ARG_B_TFACTOR_ALPHA (9 << 5)
# define RADEON_COLOR_ARG_B_T0_COLOR (10 << 5)
# define RADEON_COLOR_ARG_B_T0_ALPHA (11 << 5)
# define RADEON_COLOR_ARG_B_T1_COLOR (12 << 5)
# define RADEON_COLOR_ARG_B_T1_ALPHA (13 << 5)
# define RADEON_COLOR_ARG_B_T2_COLOR (14 << 5)
# define RADEON_COLOR_ARG_B_T2_ALPHA (15 << 5)
# define RADEON_COLOR_ARG_B_T3_COLOR (16 << 5)
# define RADEON_COLOR_ARG_B_T3_ALPHA (17 << 5)
# define RADEON_COLOR_ARG_C_SHIFT 10
# define RADEON_COLOR_ARG_C_MASK (0x1f << 10)
# define RADEON_COLOR_ARG_C_ZERO (0 << 10)
# define RADEON_COLOR_ARG_C_CURRENT_COLOR (2 << 10)
# define RADEON_COLOR_ARG_C_CURRENT_ALPHA (3 << 10)
# define RADEON_COLOR_ARG_C_DIFFUSE_COLOR (4 << 10)
# define RADEON_COLOR_ARG_C_DIFFUSE_ALPHA (5 << 10)
# define RADEON_COLOR_ARG_C_SPECULAR_COLOR (6 << 10)
# define RADEON_COLOR_ARG_C_SPECULAR_ALPHA (7 << 10)
# define RADEON_COLOR_ARG_C_TFACTOR_COLOR (8 << 10)
# define RADEON_COLOR_ARG_C_TFACTOR_ALPHA (9 << 10)
# define RADEON_COLOR_ARG_C_T0_COLOR (10 << 10)
# define RADEON_COLOR_ARG_C_T0_ALPHA (11 << 10)
# define RADEON_COLOR_ARG_C_T1_COLOR (12 << 10)
# define RADEON_COLOR_ARG_C_T1_ALPHA (13 << 10)
# define RADEON_COLOR_ARG_C_T2_COLOR (14 << 10)
# define RADEON_COLOR_ARG_C_T2_ALPHA (15 << 10)
# define RADEON_COLOR_ARG_C_T3_COLOR (16 << 10)
# define RADEON_COLOR_ARG_C_T3_ALPHA (17 << 10)
# define RADEON_COMP_ARG_A (1 << 15)
# define RADEON_COMP_ARG_A_SHIFT 15
# define RADEON_COMP_ARG_B (1 << 16)
# define RADEON_COMP_ARG_B_SHIFT 16
# define RADEON_COMP_ARG_C (1 << 17)
# define RADEON_COMP_ARG_C_SHIFT 17
# define RADEON_BLEND_CTL_MASK (7 << 18)
# define RADEON_BLEND_CTL_ADD (0 << 18)
# define RADEON_BLEND_CTL_SUBTRACT (1 << 18)
# define RADEON_BLEND_CTL_ADDSIGNED (2 << 18)
# define RADEON_BLEND_CTL_BLEND (3 << 18)
# define RADEON_BLEND_CTL_DOT3 (4 << 18)
# define RADEON_SCALE_SHIFT 21
# define RADEON_SCALE_MASK (3 << 21)
# define RADEON_SCALE_1X (0 << 21)
# define RADEON_SCALE_2X (1 << 21)
# define RADEON_SCALE_4X (2 << 21)
# define RADEON_CLAMP_TX (1 << 23)
# define RADEON_T0_EQ_TCUR (1 << 24)
# define RADEON_T1_EQ_TCUR (1 << 25)
# define RADEON_T2_EQ_TCUR (1 << 26)
# define RADEON_T3_EQ_TCUR (1 << 27)
# define RADEON_COLOR_ARG_MASK 0x1f
# define RADEON_COMP_ARG_SHIFT 15
#define RADEON_PP_TXABLEND_0 0x1c64
#define RADEON_PP_TXABLEND_1 0x1c7c
#define RADEON_PP_TXABLEND_2 0x1c94
# define RADEON_ALPHA_ARG_A_SHIFT 0
# define RADEON_ALPHA_ARG_A_MASK (0xf << 0)
# define RADEON_ALPHA_ARG_A_ZERO (0 << 0)
# define RADEON_ALPHA_ARG_A_CURRENT_ALPHA (1 << 0)
# define RADEON_ALPHA_ARG_A_DIFFUSE_ALPHA (2 << 0)
# define RADEON_ALPHA_ARG_A_SPECULAR_ALPHA (3 << 0)
# define RADEON_ALPHA_ARG_A_TFACTOR_ALPHA (4 << 0)
# define RADEON_ALPHA_ARG_A_T0_ALPHA (5 << 0)
# define RADEON_ALPHA_ARG_A_T1_ALPHA (6 << 0)
# define RADEON_ALPHA_ARG_A_T2_ALPHA (7 << 0)
# define RADEON_ALPHA_ARG_A_T3_ALPHA (8 << 0)
# define RADEON_ALPHA_ARG_B_SHIFT 4
# define RADEON_ALPHA_ARG_B_MASK (0xf << 4)
# define RADEON_ALPHA_ARG_B_ZERO (0 << 4)
# define RADEON_ALPHA_ARG_B_CURRENT_ALPHA (1 << 4)
# define RADEON_ALPHA_ARG_B_DIFFUSE_ALPHA (2 << 4)
# define RADEON_ALPHA_ARG_B_SPECULAR_ALPHA (3 << 4)
# define RADEON_ALPHA_ARG_B_TFACTOR_ALPHA (4 << 4)
# define RADEON_ALPHA_ARG_B_T0_ALPHA (5 << 4)
# define RADEON_ALPHA_ARG_B_T1_ALPHA (6 << 4)
# define RADEON_ALPHA_ARG_B_T2_ALPHA (7 << 4)
# define RADEON_ALPHA_ARG_B_T3_ALPHA (8 << 4)
# define RADEON_ALPHA_ARG_C_SHIFT 8
# define RADEON_ALPHA_ARG_C_MASK (0xf << 8)
# define RADEON_ALPHA_ARG_C_ZERO (0 << 8)
# define RADEON_ALPHA_ARG_C_CURRENT_ALPHA (1 << 8)
# define RADEON_ALPHA_ARG_C_DIFFUSE_ALPHA (2 << 8)
# define RADEON_ALPHA_ARG_C_SPECULAR_ALPHA (3 << 8)
# define RADEON_ALPHA_ARG_C_TFACTOR_ALPHA (4 << 8)
# define RADEON_ALPHA_ARG_C_T0_ALPHA (5 << 8)
# define RADEON_ALPHA_ARG_C_T1_ALPHA (6 << 8)
# define RADEON_ALPHA_ARG_C_T2_ALPHA (7 << 8)
# define RADEON_ALPHA_ARG_C_T3_ALPHA (8 << 8)
# define RADEON_DOT_ALPHA_DONT_REPLICATE (1 << 9)
# define RADEON_ALPHA_ARG_MASK 0xf
#define RADEON_PP_TFACTOR_0 0x1c68
#define RADEON_PP_TFACTOR_1 0x1c80
#define RADEON_PP_TFACTOR_2 0x1c98
#define RADEON_RB3D_BLENDCNTL 0x1c20
# define RADEON_COMB_FCN_MASK (3 << 12)
# define RADEON_COMB_FCN_ADD_CLAMP (0 << 12)
# define RADEON_COMB_FCN_ADD_NOCLAMP (1 << 12)
# define RADEON_COMB_FCN_SUB_CLAMP (2 << 12)
# define RADEON_COMB_FCN_SUB_NOCLAMP (3 << 12)
# define RADEON_SRC_BLEND_GL_ZERO (32 << 16)
# define RADEON_SRC_BLEND_GL_ONE (33 << 16)
# define RADEON_SRC_BLEND_GL_SRC_COLOR (34 << 16)
# define RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 16)
# define RADEON_SRC_BLEND_GL_DST_COLOR (36 << 16)
# define RADEON_SRC_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 16)
# define RADEON_SRC_BLEND_GL_SRC_ALPHA (38 << 16)
# define RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 16)
# define RADEON_SRC_BLEND_GL_DST_ALPHA (40 << 16)
# define RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 16)
# define RADEON_SRC_BLEND_GL_SRC_ALPHA_SATURATE (42 << 16)
# define RADEON_SRC_BLEND_MASK (63 << 16)
# define RADEON_DST_BLEND_GL_ZERO (32 << 24)
# define RADEON_DST_BLEND_GL_ONE (33 << 24)
# define RADEON_DST_BLEND_GL_SRC_COLOR (34 << 24)
# define RADEON_DST_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 24)
# define RADEON_DST_BLEND_GL_DST_COLOR (36 << 24)
# define RADEON_DST_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 24)
# define RADEON_DST_BLEND_GL_SRC_ALPHA (38 << 24)
# define RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 24)
# define RADEON_DST_BLEND_GL_DST_ALPHA (40 << 24)
# define RADEON_DST_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 24)
# define RADEON_DST_BLEND_MASK (63 << 24)
#define RADEON_RB3D_CNTL 0x1c3c
# define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
# define RADEON_PLANE_MASK_ENABLE (1 << 1)
# define RADEON_DITHER_ENABLE (1 << 2)
# define RADEON_ROUND_ENABLE (1 << 3)
# define RADEON_SCALE_DITHER_ENABLE (1 << 4)
# define RADEON_DITHER_INIT (1 << 5)
# define RADEON_ROP_ENABLE (1 << 6)
# define RADEON_STENCIL_ENABLE (1 << 7)
# define RADEON_Z_ENABLE (1 << 8)
# define RADEON_DEPTH_XZ_OFFEST_ENABLE (1 << 9)
# define RADEON_COLOR_FORMAT_ARGB1555 (3 << 10)
# define RADEON_COLOR_FORMAT_RGB565 (4 << 10)
# define RADEON_COLOR_FORMAT_ARGB8888 (6 << 10)
# define RADEON_COLOR_FORMAT_RGB332 (7 << 10)
# define RADEON_COLOR_FORMAT_Y8 (8 << 10)
# define RADEON_COLOR_FORMAT_RGB8 (9 << 10)
# define RADEON_COLOR_FORMAT_YUV422_VYUY (11 << 10)
# define RADEON_COLOR_FORMAT_YUV422_YVYU (12 << 10)
# define RADEON_COLOR_FORMAT_aYUV444 (14 << 10)
# define RADEON_COLOR_FORMAT_ARGB4444 (15 << 10)
# define RADEON_CLRCMP_FLIP_ENABLE (1 << 14)
#define RADEON_RB3D_COLOROFFSET 0x1c40
# define RADEON_COLOROFFSET_MASK 0xfffffff0
#define RADEON_RB3D_COLORPITCH 0x1c48
# define RADEON_COLORPITCH_MASK 0x000001ff8
# define RADEON_COLOR_TILE_ENABLE (1 << 16)
# define RADEON_COLOR_MICROTILE_ENABLE (1 << 17)
# define RADEON_COLOR_ENDIAN_NO_SWAP (0 << 18)
# define RADEON_COLOR_ENDIAN_WORD_SWAP (1 << 18)
# define RADEON_COLOR_ENDIAN_DWORD_SWAP (2 << 18)
#define RADEON_RB3D_DEPTHOFFSET 0x1c24
#define RADEON_RB3D_DEPTHPITCH 0x1c28
# define RADEON_DEPTHPITCH_MASK 0x00001ff8
# define RADEON_DEPTH_ENDIAN_NO_SWAP (0 << 18)
# define RADEON_DEPTH_ENDIAN_WORD_SWAP (1 << 18)
# define RADEON_DEPTH_ENDIAN_DWORD_SWAP (2 << 18)
#define RADEON_RB3D_PLANEMASK 0x1d84
#define RADEON_RB3D_ROPCNTL 0x1d80
# define RADEON_ROP_MASK (15 << 8)
# define RADEON_ROP_CLEAR (0 << 8)
# define RADEON_ROP_NOR (1 << 8)
# define RADEON_ROP_AND_INVERTED (2 << 8)
# define RADEON_ROP_COPY_INVERTED (3 << 8)
# define RADEON_ROP_AND_REVERSE (4 << 8)
# define RADEON_ROP_INVERT (5 << 8)
# define RADEON_ROP_XOR (6 << 8)
# define RADEON_ROP_NAND (7 << 8)
# define RADEON_ROP_AND (8 << 8)
# define RADEON_ROP_EQUIV (9 << 8)
# define RADEON_ROP_NOOP (10 << 8)
# define RADEON_ROP_OR_INVERTED (11 << 8)
# define RADEON_ROP_COPY (12 << 8)
# define RADEON_ROP_OR_REVERSE (13 << 8)
# define RADEON_ROP_OR (14 << 8)
# define RADEON_ROP_SET (15 << 8)
#define RADEON_RB3D_STENCILREFMASK 0x1d7c
# define RADEON_STENCIL_REF_SHIFT 0
# define RADEON_STENCIL_REF_MASK (0xff << 0)
# define RADEON_STENCIL_MASK_SHIFT 16
# define RADEON_STENCIL_VALUE_MASK (0xff << 16)
# define RADEON_STENCIL_WRITEMASK_SHIFT 24
# define RADEON_STENCIL_WRITE_MASK (0xff << 24)
#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
# define RADEON_DEPTH_FORMAT_MASK (0xf << 0)
# define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
# define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)
# define RADEON_DEPTH_FORMAT_24BIT_FLOAT_Z (3 << 0)
# define RADEON_DEPTH_FORMAT_32BIT_INT_Z (4 << 0)
# define RADEON_DEPTH_FORMAT_32BIT_FLOAT_Z (5 << 0)
# define RADEON_DEPTH_FORMAT_16BIT_FLOAT_W (7 << 0)
# define RADEON_DEPTH_FORMAT_24BIT_FLOAT_W (9 << 0)
# define RADEON_DEPTH_FORMAT_32BIT_FLOAT_W (11 << 0)
# define RADEON_Z_TEST_NEVER (0 << 4)
# define RADEON_Z_TEST_LESS (1 << 4)
# define RADEON_Z_TEST_LEQUAL (2 << 4)
# define RADEON_Z_TEST_EQUAL (3 << 4)
# define RADEON_Z_TEST_GEQUAL (4 << 4)
# define RADEON_Z_TEST_GREATER (5 << 4)
# define RADEON_Z_TEST_NEQUAL (6 << 4)
# define RADEON_Z_TEST_ALWAYS (7 << 4)
# define RADEON_Z_TEST_MASK (7 << 4)
# define RADEON_STENCIL_TEST_NEVER (0 << 12)
# define RADEON_STENCIL_TEST_LESS (1 << 12)
# define RADEON_STENCIL_TEST_LEQUAL (2 << 12)
# define RADEON_STENCIL_TEST_EQUAL (3 << 12)
# define RADEON_STENCIL_TEST_GEQUAL (4 << 12)
# define RADEON_STENCIL_TEST_GREATER (5 << 12)
# define RADEON_STENCIL_TEST_NEQUAL (6 << 12)
# define RADEON_STENCIL_TEST_ALWAYS (7 << 12)
# define RADEON_STENCIL_TEST_MASK (0x7 << 12)
# define RADEON_STENCIL_FAIL_KEEP (0 << 16)
# define RADEON_STENCIL_FAIL_ZERO (1 << 16)
# define RADEON_STENCIL_FAIL_REPLACE (2 << 16)
# define RADEON_STENCIL_FAIL_INC (3 << 16)
# define RADEON_STENCIL_FAIL_DEC (4 << 16)
# define RADEON_STENCIL_FAIL_INVERT (5 << 16)
# define RADEON_STENCIL_FAIL_MASK (0x7 << 16)
# define RADEON_STENCIL_ZPASS_KEEP (0 << 20)
# define RADEON_STENCIL_ZPASS_ZERO (1 << 20)
# define RADEON_STENCIL_ZPASS_REPLACE (2 << 20)
# define RADEON_STENCIL_ZPASS_INC (3 << 20)
# define RADEON_STENCIL_ZPASS_DEC (4 << 20)
# define RADEON_STENCIL_ZPASS_INVERT (5 << 20)
# define RADEON_STENCIL_ZPASS_MASK (0x7 << 20)
# define RADEON_STENCIL_ZFAIL_KEEP (0 << 24)
# define RADEON_STENCIL_ZFAIL_ZERO (1 << 24)
# define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24)
# define RADEON_STENCIL_ZFAIL_INC (3 << 24)
# define RADEON_STENCIL_ZFAIL_DEC (4 << 24)
# define RADEON_STENCIL_ZFAIL_INVERT (5 << 24)
# define RADEON_STENCIL_ZFAIL_MASK (0x7 << 24)
# define RADEON_Z_COMPRESSION_ENABLE (1 << 28)
# define RADEON_FORCE_Z_DIRTY (1 << 29)
# define RADEON_Z_WRITE_ENABLE (1 << 30)
#define RADEON_RE_LINE_PATTERN 0x1cd0
# define RADEON_LINE_PATTERN_MASK 0x0000ffff
# define RADEON_LINE_REPEAT_COUNT_SHIFT 16
# define RADEON_LINE_PATTERN_START_SHIFT 24
# define RADEON_LINE_PATTERN_LITTLE_BIT_ORDER (0 << 28)
# define RADEON_LINE_PATTERN_BIG_BIT_ORDER (1 << 28)
# define RADEON_LINE_PATTERN_AUTO_RESET (1 << 29)
#define RADEON_RE_LINE_STATE 0x1cd4
# define RADEON_LINE_CURRENT_PTR_SHIFT 0
# define RADEON_LINE_CURRENT_COUNT_SHIFT 8
#define RADEON_RE_MISC 0x26c4
# define RADEON_STIPPLE_COORD_MASK 0x1f
# define RADEON_STIPPLE_X_OFFSET_SHIFT 0
# define RADEON_STIPPLE_X_OFFSET_MASK (0x1f << 0)
# define RADEON_STIPPLE_Y_OFFSET_SHIFT 8
# define RADEON_STIPPLE_Y_OFFSET_MASK (0x1f << 8)
# define RADEON_STIPPLE_LITTLE_BIT_ORDER (0 << 16)
# define RADEON_STIPPLE_BIG_BIT_ORDER (1 << 16)
#define RADEON_RE_SOLID_COLOR 0x1c1c
#define RADEON_RE_TOP_LEFT 0x26c0
# define RADEON_RE_LEFT_SHIFT 0
# define RADEON_RE_TOP_SHIFT 16
#define RADEON_RE_WIDTH_HEIGHT 0x1c44
# define RADEON_RE_WIDTH_SHIFT 0
# define RADEON_RE_HEIGHT_SHIFT 16
#define RADEON_SE_CNTL 0x1c4c
# define RADEON_FFACE_CULL_CW (0 << 0)
# define RADEON_FFACE_CULL_CCW (1 << 0)
# define RADEON_FFACE_CULL_DIR_MASK (1 << 0)
# define RADEON_BFACE_CULL (0 << 1)
# define RADEON_BFACE_SOLID (3 << 1)
# define RADEON_FFACE_CULL (0 << 3)
# define RADEON_FFACE_SOLID (3 << 3)
# define RADEON_FFACE_CULL_MASK (3 << 3)
# define RADEON_BADVTX_CULL_DISABLE (1 << 5)
# define RADEON_FLAT_SHADE_VTX_0 (0 << 6)
# define RADEON_FLAT_SHADE_VTX_1 (1 << 6)
# define RADEON_FLAT_SHADE_VTX_2 (2 << 6)
# define RADEON_FLAT_SHADE_VTX_LAST (3 << 6)
# define RADEON_DIFFUSE_SHADE_SOLID (0 << 8)
# define RADEON_DIFFUSE_SHADE_FLAT (1 << 8)
# define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8)
# define RADEON_DIFFUSE_SHADE_MASK (3 << 8)
# define RADEON_ALPHA_SHADE_SOLID (0 << 10)
# define RADEON_ALPHA_SHADE_FLAT (1 << 10)
# define RADEON_ALPHA_SHADE_GOURAUD (2 << 10)
# define RADEON_ALPHA_SHADE_MASK (3 << 10)
# define RADEON_SPECULAR_SHADE_SOLID (0 << 12)
# define RADEON_SPECULAR_SHADE_FLAT (1 << 12)
# define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12)
# define RADEON_SPECULAR_SHADE_MASK (3 << 12)
# define RADEON_FOG_SHADE_SOLID (0 << 14)
# define RADEON_FOG_SHADE_FLAT (1 << 14)
# define RADEON_FOG_SHADE_GOURAUD (2 << 14)
# define RADEON_FOG_SHADE_MASK (3 << 14)
# define RADEON_ZBIAS_ENABLE_POINT (1 << 16)
# define RADEON_ZBIAS_ENABLE_LINE (1 << 17)
# define RADEON_ZBIAS_ENABLE_TRI (1 << 18)
# define RADEON_WIDELINE_ENABLE (1 << 20)
# define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24)
# define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25)
# define RADEON_VTX_PIX_CENTER_D3D (0 << 27)
# define RADEON_VTX_PIX_CENTER_OGL (1 << 27)
# define RADEON_ROUND_MODE_TRUNC (0 << 28)
# define RADEON_ROUND_MODE_ROUND (1 << 28)
# define RADEON_ROUND_MODE_ROUND_EVEN (2 << 28)
# define RADEON_ROUND_MODE_ROUND_ODD (3 << 28)
# define RADEON_ROUND_PREC_16TH_PIX (0 << 30)
# define RADEON_ROUND_PREC_8TH_PIX (1 << 30)
# define RADEON_ROUND_PREC_4TH_PIX (2 << 30)
# define RADEON_ROUND_PREC_HALF_PIX (3 << 30)
#define R200_RE_CNTL0x1c50
# define R200_STIPPLE_ENABLE0x1
# define R200_SCISSOR_ENABLE0x2
# define R200_PATTERN_ENABLE0x4
# define R200_PERSPECTIVE_ENABLE0x8
# define R200_POINT_SMOOTH0x20
# define R200_VTX_STQ0_D3D0x00010000
# define R200_VTX_STQ1_D3D0x00040000
# define R200_VTX_STQ2_D3D0x00100000
# define R200_VTX_STQ3_D3D0x00400000
# define R200_VTX_STQ4_D3D0x01000000
# define R200_VTX_STQ5_D3D0x04000000
#define R200_RE_SCISSOR_TL_00x1cd8
#define R200_RE_SCISSOR_BR_00x1cdc
#define R200_RE_SCISSOR_TL_10x1ce0
#define R200_RE_SCISSOR_BR_10x1ce4
#define R200_RE_SCISSOR_TL_20x1ce8
#define R200_RE_SCISSOR_BR_20x1cec
# define R200_SCISSOR_X_SHIFT0
# define R200_SCISSOR_Y_SHIFT16
#define RADEON_SE_CNTL_STATUS 0x2140
# define RADEON_VC_NO_SWAP (0 << 0)
# define RADEON_VC_16BIT_SWAP (1 << 0)
# define RADEON_VC_32BIT_SWAP (2 << 0)
# define RADEON_VC_HALF_DWORD_SWAP (3 << 0)
# define RADEON_TCL_BYPASS (1 << 8)
#define RADEON_SE_COORD_FMT 0x1c50
# define RADEON_VTX_XY_PRE_MULT_1_OVER_W0 (1 << 0)
# define RADEON_VTX_Z_PRE_MULT_1_OVER_W0 (1 << 1)
# define RADEON_VTX_ST0_NONPARAMETRIC (1 << 8)
# define RADEON_VTX_ST1_NONPARAMETRIC (1 << 9)
# define RADEON_VTX_ST2_NONPARAMETRIC (1 << 10)
# define RADEON_VTX_ST3_NONPARAMETRIC (1 << 11)
# define RADEON_VTX_W0_NORMALIZE (1 << 12)
# define RADEON_VTX_W0_IS_NOT_1_OVER_W0 (1 << 16)
# define RADEON_VTX_ST0_PRE_MULT_1_OVER_W0 (1 << 17)
# define RADEON_VTX_ST1_PRE_MULT_1_OVER_W0 (1 << 19)
# define RADEON_VTX_ST2_PRE_MULT_1_OVER_W0 (1 << 21)
# define RADEON_VTX_ST3_PRE_MULT_1_OVER_W0 (1 << 23)
# define RADEON_TEX1_W_ROUTING_USE_W0 (0 << 26)
# define RADEON_TEX1_W_ROUTING_USE_Q1 (1 << 26)
#define RADEON_SE_LINE_WIDTH 0x1db8
#define RADEON_SE_TCL_LIGHT_MODEL_CTL 0x226c
# define RADEON_LIGHTING_ENABLE (1 << 0)
# define RADEON_LIGHT_IN_MODELSPACE (1 << 1)
# define RADEON_LOCAL_VIEWER (1 << 2)
# define RADEON_NORMALIZE_NORMALS (1 << 3)
# define RADEON_RESCALE_NORMALS (1 << 4)
# define RADEON_SPECULAR_LIGHTS (1 << 5)
# define RADEON_DIFFUSE_SPECULAR_COMBINE (1 << 6)
# define RADEON_LIGHT_ALPHA (1 << 7)
# define RADEON_LOCAL_LIGHT_VEC_GL (1 << 8)
# define RADEON_LIGHT_NO_NORMAL_AMBIENT_ONLY (1 << 9)
# define RADEON_LM_SOURCE_STATE_PREMULT 0
# define RADEON_LM_SOURCE_STATE_MULT 1
# define RADEON_LM_SOURCE_VERTEX_DIFFUSE 2
# define RADEON_LM_SOURCE_VERTEX_SPECULAR 3
# define RADEON_EMISSIVE_SOURCE_SHIFT 16
# define RADEON_AMBIENT_SOURCE_SHIFT 18
# define RADEON_DIFFUSE_SOURCE_SHIFT 20
# define RADEON_SPECULAR_SOURCE_SHIFT 22
#define RADEON_SE_TCL_MATERIAL_AMBIENT_RED 0x2220
#define RADEON_SE_TCL_MATERIAL_AMBIENT_GREEN 0x2224
#define RADEON_SE_TCL_MATERIAL_AMBIENT_BLUE 0x2228
#define RADEON_SE_TCL_MATERIAL_AMBIENT_ALPHA 0x222c
#define RADEON_SE_TCL_MATERIAL_DIFFUSE_RED 0x2230
#define RADEON_SE_TCL_MATERIAL_DIFFUSE_GREEN 0x2234
#define RADEON_SE_TCL_MATERIAL_DIFFUSE_BLUE 0x2238
#define RADEON_SE_TCL_MATERIAL_DIFFUSE_ALPHA 0x223c
#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210
#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_GREEN 0x2214
#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_BLUE 0x2218
#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_ALPHA 0x221c
#define RADEON_SE_TCL_MATERIAL_SPECULAR_RED 0x2240
#define RADEON_SE_TCL_MATERIAL_SPECULAR_GREEN 0x2244
#define RADEON_SE_TCL_MATERIAL_SPECULAR_BLUE 0x2248
#define RADEON_SE_TCL_MATERIAL_SPECULAR_ALPHA 0x224c
#define RADEON_SE_TCL_MATRIX_SELECT_0 0x225c
# define RADEON_MODELVIEW_0_SHIFT 0
# define RADEON_MODELVIEW_1_SHIFT 4
# define RADEON_MODELVIEW_2_SHIFT 8
# define RADEON_MODELVIEW_3_SHIFT 12
# define RADEON_IT_MODELVIEW_0_SHIFT 16
# define RADEON_IT_MODELVIEW_1_SHIFT 20
# define RADEON_IT_MODELVIEW_2_SHIFT 24
# define RADEON_IT_MODELVIEW_3_SHIFT 28
#define RADEON_SE_TCL_MATRIX_SELECT_1 0x2260
# define RADEON_MODELPROJECT_0_SHIFT 0
# define RADEON_MODELPROJECT_1_SHIFT 4
# define RADEON_MODELPROJECT_2_SHIFT 8
# define RADEON_MODELPROJECT_3_SHIFT 12
# define RADEON_TEXMAT_0_SHIFT 16
# define RADEON_TEXMAT_1_SHIFT 20
# define RADEON_TEXMAT_2_SHIFT 24
# define RADEON_TEXMAT_3_SHIFT 28
#define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254
# define RADEON_TCL_VTX_W0 (1 << 0)
# define RADEON_TCL_VTX_FP_DIFFUSE (1 << 1)
# define RADEON_TCL_VTX_FP_ALPHA (1 << 2)
# define RADEON_TCL_VTX_PK_DIFFUSE (1 << 3)
# define RADEON_TCL_VTX_FP_SPEC (1 << 4)
# define RADEON_TCL_VTX_FP_FOG (1 << 5)
# define RADEON_TCL_VTX_PK_SPEC (1 << 6)
# define RADEON_TCL_VTX_ST0 (1 << 7)
# define RADEON_TCL_VTX_ST1 (1 << 8)
# define RADEON_TCL_VTX_Q1 (1 << 9)
# define RADEON_TCL_VTX_ST2 (1 << 10)
# define RADEON_TCL_VTX_Q2 (1 << 11)
# define RADEON_TCL_VTX_ST3 (1 << 12)
# define RADEON_TCL_VTX_Q3 (1 << 13)
# define RADEON_TCL_VTX_Q0 (1 << 14)
# define RADEON_TCL_VTX_WEIGHT_COUNT_SHIFT 15
# define RADEON_TCL_VTX_NORM0 (1 << 18)
# define RADEON_TCL_VTX_XY1 (1 << 27)
# define RADEON_TCL_VTX_Z1 (1 << 28)
# define RADEON_TCL_VTX_W1 (1 << 29)
# define RADEON_TCL_VTX_NORM1 (1 << 30)
# define RADEON_TCL_VTX_Z0 (1 << 31)
#define RADEON_SE_TCL_OUTPUT_VTX_SEL 0x2258
# define RADEON_TCL_COMPUTE_XYZW (1 << 0)
# define RADEON_TCL_COMPUTE_DIFFUSE (1 << 1)
# define RADEON_TCL_COMPUTE_SPECULAR (1 << 2)
# define RADEON_TCL_FORCE_NAN_IF_COLOR_NAN (1 << 3)
# define RADEON_TCL_FORCE_INORDER_PROC (1 << 4)
# define RADEON_TCL_TEX_INPUT_TEX_0 0
# define RADEON_TCL_TEX_INPUT_TEX_1 1
# define RADEON_TCL_TEX_INPUT_TEX_2 2
# define RADEON_TCL_TEX_INPUT_TEX_3 3
# define RADEON_TCL_TEX_COMPUTED_TEX_0 8
# define RADEON_TCL_TEX_COMPUTED_TEX_1 9
# define RADEON_TCL_TEX_COMPUTED_TEX_2 10
# define RADEON_TCL_TEX_COMPUTED_TEX_3 11
# define RADEON_TCL_TEX_0_OUTPUT_SHIFT 16
# define RADEON_TCL_TEX_1_OUTPUT_SHIFT 20
# define RADEON_TCL_TEX_2_OUTPUT_SHIFT 24
# define RADEON_TCL_TEX_3_OUTPUT_SHIFT 28
#define RADEON_SE_TCL_PER_LIGHT_CTL_0 0x2270
# define RADEON_LIGHT_0_ENABLE (1 << 0)
# define RADEON_LIGHT_0_ENABLE_AMBIENT (1 << 1)
# define RADEON_LIGHT_0_ENABLE_SPECULAR (1 << 2)
# define RADEON_LIGHT_0_IS_LOCAL (1 << 3)
# define RADEON_LIGHT_0_IS_SPOT (1 << 4)
# define RADEON_LIGHT_0_DUAL_CONE (1 << 5)
# define RADEON_LIGHT_0_ENABLE_RANGE_ATTEN (1 << 6)
# define RADEON_LIGHT_0_CONSTANT_RANGE_ATTEN (1 << 7)
# define RADEON_LIGHT_0_SHIFT 0
# define RADEON_LIGHT_1_ENABLE (1 << 16)
# define RADEON_LIGHT_1_ENABLE_AMBIENT (1 << 17)
# define RADEON_LIGHT_1_ENABLE_SPECULAR (1 << 18)
# define RADEON_LIGHT_1_IS_LOCAL (1 << 19)
# define RADEON_LIGHT_1_IS_SPOT (1 << 20)
# define RADEON_LIGHT_1_DUAL_CONE (1 << 21)
# define RADEON_LIGHT_1_ENABLE_RANGE_ATTEN (1 << 22)
# define RADEON_LIGHT_1_CONSTANT_RANGE_ATTEN (1 << 23)
# define RADEON_LIGHT_1_SHIFT 16
#define RADEON_SE_TCL_PER_LIGHT_CTL_1 0x2274
# define RADEON_LIGHT_2_SHIFT 0
# define RADEON_LIGHT_3_SHIFT 16
#define RADEON_SE_TCL_PER_LIGHT_CTL_2 0x2278
# define RADEON_LIGHT_4_SHIFT 0
# define RADEON_LIGHT_5_SHIFT 16
#define RADEON_SE_TCL_PER_LIGHT_CTL_3 0x227c
# define RADEON_LIGHT_6_SHIFT 0
# define RADEON_LIGHT_7_SHIFT 16
#define RADEON_SE_TCL_SHININESS 0x2250
#define RADEON_SE_TCL_TEXTURE_PROC_CTL 0x2268
# define RADEON_TEXGEN_TEXMAT_0_ENABLE (1 << 0)
# define RADEON_TEXGEN_TEXMAT_1_ENABLE (1 << 1)
# define RADEON_TEXGEN_TEXMAT_2_ENABLE (1 << 2)
# define RADEON_TEXGEN_TEXMAT_3_ENABLE (1 << 3)
# define RADEON_TEXMAT_0_ENABLE (1 << 4)
# define RADEON_TEXMAT_1_ENABLE (1 << 5)
# define RADEON_TEXMAT_2_ENABLE (1 << 6)
# define RADEON_TEXMAT_3_ENABLE (1 << 7)
# define RADEON_TEXGEN_INPUT_MASK 0xf
# define RADEON_TEXGEN_INPUT_TEXCOORD_0 0
# define RADEON_TEXGEN_INPUT_TEXCOORD_1 1
# define RADEON_TEXGEN_INPUT_TEXCOORD_2 2
# define RADEON_TEXGEN_INPUT_TEXCOORD_3 3
# define RADEON_TEXGEN_INPUT_OBJ 4
# define RADEON_TEXGEN_INPUT_EYE 5
# define RADEON_TEXGEN_INPUT_EYE_NORMAL 6
# define RADEON_TEXGEN_INPUT_EYE_REFLECT 7
# define RADEON_TEXGEN_INPUT_EYE_NORMALIZED 8
# define RADEON_TEXGEN_0_INPUT_SHIFT 16
# define RADEON_TEXGEN_1_INPUT_SHIFT 20
# define RADEON_TEXGEN_2_INPUT_SHIFT 24
# define RADEON_TEXGEN_3_INPUT_SHIFT 28
#define RADEON_SE_TCL_UCP_VERT_BLEND_CTL 0x2264
# define RADEON_UCP_IN_CLIP_SPACE (1 << 0)
# define RADEON_UCP_IN_MODEL_SPACE (1 << 1)
# define RADEON_UCP_ENABLE_0 (1 << 2)
# define RADEON_UCP_ENABLE_1 (1 << 3)
# define RADEON_UCP_ENABLE_2 (1 << 4)
# define RADEON_UCP_ENABLE_3 (1 << 5)
# define RADEON_UCP_ENABLE_4 (1 << 6)
# define RADEON_UCP_ENABLE_5 (1 << 7)
# define RADEON_TCL_FOG_MASK (3 << 8)
# define RADEON_TCL_FOG_DISABLE (0 << 8)
# define RADEON_TCL_FOG_EXP (1 << 8)
# define RADEON_TCL_FOG_EXP2 (2 << 8)
# define RADEON_TCL_FOG_LINEAR (3 << 8)
# define RADEON_RNG_BASED_FOG (1 << 10)
# define RADEON_LIGHT_TWOSIDE (1 << 11)
# define RADEON_BLEND_OP_COUNT_MASK (7 << 12)
# define RADEON_BLEND_OP_COUNT_SHIFT 12
# define RADEON_POSITION_BLEND_OP_ENABLE (1 << 16)
# define RADEON_NORMAL_BLEND_OP_ENABLE (1 << 17)
# define RADEON_VERTEX_BLEND_SRC_0_PRIMARY (1 << 18)
# define RADEON_VERTEX_BLEND_SRC_0_SECONDARY (1 << 18)
# define RADEON_VERTEX_BLEND_SRC_1_PRIMARY (1 << 19)
# define RADEON_VERTEX_BLEND_SRC_1_SECONDARY (1 << 19)
# define RADEON_VERTEX_BLEND_SRC_2_PRIMARY (1 << 20)
# define RADEON_VERTEX_BLEND_SRC_2_SECONDARY (1 << 20)
# define RADEON_VERTEX_BLEND_SRC_3_PRIMARY (1 << 21)
# define RADEON_VERTEX_BLEND_SRC_3_SECONDARY (1 << 21)
# define RADEON_VERTEX_BLEND_WGT_MINUS_ONE (1 << 22)
# define RADEON_CULL_FRONT_IS_CW (0 << 28)
# define RADEON_CULL_FRONT_IS_CCW (1 << 28)
# define RADEON_CULL_FRONT (1 << 29)
# define RADEON_CULL_BACK (1 << 30)
# define RADEON_FORCE_W_TO_ONE (1 << 31)
#define RADEON_SE_VPORT_XSCALE 0x1d98
#define RADEON_SE_VPORT_XOFFSET 0x1d9c
#define RADEON_SE_VPORT_YSCALE 0x1da0
#define RADEON_SE_VPORT_YOFFSET 0x1da4
#define RADEON_SE_VPORT_ZSCALE 0x1da8
#define RADEON_SE_VPORT_ZOFFSET 0x1dac
#define RADEON_SE_ZBIAS_FACTOR 0x1db0
#define RADEON_SE_ZBIAS_CONSTANT 0x1db4
#define RADEON_SE_VTX_FMT 0x2080
# define RADEON_SE_VTX_FMT_XY 0x00000000
# define RADEON_SE_VTX_FMT_W0 0x00000001
# define RADEON_SE_VTX_FMT_FPCOLOR 0x00000002
# define RADEON_SE_VTX_FMT_FPALPHA 0x00000004
# define RADEON_SE_VTX_FMT_PKCOLOR 0x00000008
# define RADEON_SE_VTX_FMT_FPSPEC 0x00000010
# define RADEON_SE_VTX_FMT_FPFOG 0x00000020
# define RADEON_SE_VTX_FMT_PKSPEC 0x00000040
# define RADEON_SE_VTX_FMT_ST0 0x00000080
# define RADEON_SE_VTX_FMT_ST1 0x00000100
# define RADEON_SE_VTX_FMT_Q1 0x00000200
# define RADEON_SE_VTX_FMT_ST2 0x00000400
# define RADEON_SE_VTX_FMT_Q2 0x00000800
# define RADEON_SE_VTX_FMT_ST3 0x00001000
# define RADEON_SE_VTX_FMT_Q3 0x00002000
# define RADEON_SE_VTX_FMT_Q0 0x00004000
# define RADEON_SE_VTX_FMT_BLND_WEIGHT_CNT_MASK 0x00038000
# define RADEON_SE_VTX_FMT_N0 0x00040000
# define RADEON_SE_VTX_FMT_XY1 0x08000000
# define RADEON_SE_VTX_FMT_Z1 0x10000000
# define RADEON_SE_VTX_FMT_W1 0x20000000
# define RADEON_SE_VTX_FMT_N1 0x40000000
# define RADEON_SE_VTX_FMT_Z 0x80000000
#define RADEON_SE_VF_CNTL 0x2084
# define RADEON_VF_PRIM_TYPE_POINT_LIST 1
# define RADEON_VF_PRIM_TYPE_LINE_LIST 2
# define RADEON_VF_PRIM_TYPE_LINE_STRIP 3
# define RADEON_VF_PRIM_TYPE_TRIANGLE_LIST 4
# define RADEON_VF_PRIM_TYPE_TRIANGLE_FAN 5
# define RADEON_VF_PRIM_TYPE_TRIANGLE_STRIP 6
# define RADEON_VF_PRIM_TYPE_TRIANGLE_FLAG 7
# define RADEON_VF_PRIM_TYPE_RECTANGLE_LIST 8
# define RADEON_VF_PRIM_TYPE_POINT_LIST_3 9
# define RADEON_VF_PRIM_TYPE_LINE_LIST_3 10
# define RADEON_VF_PRIM_TYPE_SPIRIT_LIST 11
# define RADEON_VF_PRIM_TYPE_LINE_LOOP 12
# define RADEON_VF_PRIM_TYPE_QUAD_LIST 13
# define RADEON_VF_PRIM_TYPE_QUAD_STRIP 14
# define RADEON_VF_PRIM_TYPE_POLYGON 15
# define RADEON_VF_PRIM_WALK_STATE (0<<4)
# define RADEON_VF_PRIM_WALK_INDEX (1<<4)
# define RADEON_VF_PRIM_WALK_LIST (2<<4)
# define RADEON_VF_PRIM_WALK_DATA (3<<4)
# define RADEON_VF_COLOR_ORDER_RGBA (1<<6)
# define RADEON_VF_RADEON_MODE (1<<8)
# define RADEON_VF_TCL_OUTPUT_CTL_ENA (1<<9)
# define RADEON_VF_PROG_STREAM_ENA (1<<10)
# define RADEON_VF_INDEX_SIZE_SHIFT 11
# define RADEON_VF_NUM_VERTICES_SHIFT 16
#define RADEON_SE_PORT_DATA00x2000
#define R200_SE_VAP_CNTL0x2080
# define R200_VAP_TCL_ENABLE0x00000001
# define R200_VAP_SINGLE_BUF_STATE_ENABLE0x00000010
# define R200_VAP_FORCE_W_TO_ONE0x00010000
# define R200_VAP_D3D_TEX_DEFAULT0x00020000
# define R200_VAP_VF_MAX_VTX_NUM__SHIFT18
# define R200_VAP_VF_MAX_VTX_NUM(9 << 18)
# define R200_VAP_DX_CLIP_SPACE_DEF0x00400000
#define R200_VF_MAX_VTX_INDX0x210c
#define R200_VF_MIN_VTX_INDX0x2110
#define R200_SE_VTE_CNTL0x20b0
# define R200_VPORT_X_SCALE_ENA0x00000001
# define R200_VPORT_X_OFFSET_ENA0x00000002
# define R200_VPORT_Y_SCALE_ENA0x00000004
# define R200_VPORT_Y_OFFSET_ENA0x00000008
# define R200_VPORT_Z_SCALE_ENA0x00000010
# define R200_VPORT_Z_OFFSET_ENA0x00000020
# define R200_VTX_XY_FMT0x00000100
# define R200_VTX_Z_FMT0x00000200
# define R200_VTX_W0_FMT0x00000400
# define R200_VTX_W0_NORMALIZE0x00000800
# define R200_VTX_ST_DENORMALIZED0x00001000
#define R200_SE_VAP_CNTL_STATUS0x2140
# define R200_VC_NO_SWAP(0 << 0)
# define R200_VC_16BIT_SWAP(1 << 0)
# define R200_VC_32BIT_SWAP(2 << 0)
#define R200_RE_AUX_SCISSOR_CNTL0x26f0
# define R200_EXCLUSIVE_SCISSOR_00x01000000
# define R200_EXCLUSIVE_SCISSOR_10x02000000
# define R200_EXCLUSIVE_SCISSOR_20x04000000
# define R200_SCISSOR_ENABLE_00x10000000
# define R200_SCISSOR_ENABLE_10x20000000
# define R200_SCISSOR_ENABLE_20x40000000
#define R200_PP_TXFILTER_00x2c00
#define R200_PP_TXFILTER_10x2c20
#define R200_PP_TXFILTER_20x2c40
#define R200_PP_TXFILTER_30x2c60
#define R200_PP_TXFILTER_40x2c80
#define R200_PP_TXFILTER_50x2ca0
# define R200_MAG_FILTER_NEAREST(0 << 0)
# define R200_MAG_FILTER_LINEAR(1 << 0)
# define R200_MAG_FILTER_MASK(1 << 0)
# define R200_MIN_FILTER_NEAREST(0 << 1)
# define R200_MIN_FILTER_LINEAR(1 << 1)
# define R200_MIN_FILTER_NEAREST_MIP_NEAREST (2 << 1)
# define R200_MIN_FILTER_NEAREST_MIP_LINEAR (3 << 1)
# define R200_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 1)
# define R200_MIN_FILTER_LINEAR_MIP_LINEAR (7 << 1)
# define R200_MIN_FILTER_ANISO_NEAREST(8 << 1)
# define R200_MIN_FILTER_ANISO_LINEAR(9 << 1)
# define R200_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (10 << 1)
# define R200_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (11 << 1)
# define R200_MIN_FILTER_MASK(15 << 1)
# define R200_MAX_ANISO_1_TO_1(0 << 5)
# define R200_MAX_ANISO_2_TO_1(1 << 5)
# define R200_MAX_ANISO_4_TO_1(2 << 5)
# define R200_MAX_ANISO_8_TO_1(3 << 5)
# define R200_MAX_ANISO_16_TO_1(4 << 5)
# define R200_MAX_ANISO_MASK(7 << 5)
# define R200_MAX_MIP_LEVEL_MASK(0x0f << 16)
# define R200_MAX_MIP_LEVEL_SHIFT16
# define R200_YUV_TO_RGB(1 << 20)
# define R200_YUV_TEMPERATURE_COOL(0 << 21)
# define R200_YUV_TEMPERATURE_HOT(1 << 21)
# define R200_YUV_TEMPERATURE_MASK(1 << 21)
# define R200_WRAPEN_S(1 << 22)
# define R200_CLAMP_S_WRAP(0 << 23)
# define R200_CLAMP_S_MIRROR(1 << 23)
# define R200_CLAMP_S_CLAMP_LAST(2 << 23)
# define R200_CLAMP_S_MIRROR_CLAMP_LAST(3 << 23)
# define R200_CLAMP_S_CLAMP_BORDER(4 << 23)
# define R200_CLAMP_S_MIRROR_CLAMP_BORDER(5 << 23)
# define R200_CLAMP_S_CLAMP_GL(6 << 23)
# define R200_CLAMP_S_MIRROR_CLAMP_GL(7 << 23)
# define R200_CLAMP_S_MASK(7 << 23)
# define R200_WRAPEN_T(1 << 26)
# define R200_CLAMP_T_WRAP(0 << 27)
# define R200_CLAMP_T_MIRROR(1 << 27)
# define R200_CLAMP_T_CLAMP_LAST(2 << 27)
# define R200_CLAMP_T_MIRROR_CLAMP_LAST(3 << 27)
# define R200_CLAMP_T_CLAMP_BORDER(4 << 27)
# define R200_CLAMP_T_MIRROR_CLAMP_BORDER(5 << 27)
# define R200_CLAMP_T_CLAMP_GL(6 << 27)
# define R200_CLAMP_T_MIRROR_CLAMP_GL(7 << 27)
# define R200_CLAMP_T_MASK(7 << 27)
# define R200_KILL_LT_ZERO(1 << 30)
# define R200_BORDER_MODE_OGL(0 << 31)
# define R200_BORDER_MODE_D3D(1 << 31)
#define R200_PP_TXFORMAT_00x2c04
#define R200_PP_TXFORMAT_10x2c24
#define R200_PP_TXFORMAT_20x2c44
#define R200_PP_TXFORMAT_30x2c64
#define R200_PP_TXFORMAT_40x2c84
#define R200_PP_TXFORMAT_50x2ca4
# define R200_TXFORMAT_I8(0 << 0)
# define R200_TXFORMAT_AI88(1 << 0)
# define R200_TXFORMAT_RGB332(2 << 0)
# define R200_TXFORMAT_ARGB1555(3 << 0)
# define R200_TXFORMAT_RGB565(4 << 0)
# define R200_TXFORMAT_ARGB4444(5 << 0)
# define R200_TXFORMAT_ARGB8888(6 << 0)
# define R200_TXFORMAT_RGBA8888(7 << 0)
# define R200_TXFORMAT_Y8(8 << 0)
# define R200_TXFORMAT_AVYU4444(9 << 0)
# define R200_TXFORMAT_VYUY422(10 << 0)
# define R200_TXFORMAT_YVYU422(11 << 0)
# define R200_TXFORMAT_DXT1(12 << 0)
# define R200_TXFORMAT_DXT23(14 << 0)
# define R200_TXFORMAT_DXT45(15 << 0)
# define R200_TXFORMAT_ABGR8888(22 << 0)
# define R200_TXFORMAT_FORMAT_MASK(31 <<0)
# define R200_TXFORMAT_FORMAT_SHIFT0
# define R200_TXFORMAT_ALPHA_IN_MAP(1 << 6)
# define R200_TXFORMAT_NON_POWER2(1 << 7)
# define R200_TXFORMAT_WIDTH_MASK(15 <<8)
# define R200_TXFORMAT_WIDTH_SHIFT8
# define R200_TXFORMAT_HEIGHT_MASK(15 << 12)
# define R200_TXFORMAT_HEIGHT_SHIFT12
# define R200_TXFORMAT_F5_WIDTH_MASK(15 << 16)/* cube face 5 */
# define R200_TXFORMAT_F5_WIDTH_SHIFT16
# define R200_TXFORMAT_F5_HEIGHT_MASK(15 << 20)
# define R200_TXFORMAT_F5_HEIGHT_SHIFT20
# define R200_TXFORMAT_ST_ROUTE_STQ0(0 << 24)
# define R200_TXFORMAT_ST_ROUTE_STQ1(1 << 24)
# define R200_TXFORMAT_ST_ROUTE_STQ2(2 << 24)
# define R200_TXFORMAT_ST_ROUTE_STQ3(3 << 24)
# define R200_TXFORMAT_ST_ROUTE_STQ4(4 << 24)
# define R200_TXFORMAT_ST_ROUTE_STQ5(5 << 24)
# define R200_TXFORMAT_ST_ROUTE_MASK(7 << 24)
# define R200_TXFORMAT_ST_ROUTE_SHIFT24
# define R200_TXFORMAT_ALPHA_MASK_ENABLE(1 << 28)
# define R200_TXFORMAT_CHROMA_KEY_ENABLE(1 << 29)
# define R200_TXFORMAT_CUBIC_MAP_ENABLE(1 << 30)
#define R200_PP_TXFORMAT_X_0 0x2c08
#define R200_PP_TXFORMAT_X_1 0x2c28
#define R200_PP_TXFORMAT_X_2 0x2c48
#define R200_PP_TXFORMAT_X_3 0x2c68
#define R200_PP_TXFORMAT_X_4 0x2c88
#define R200_PP_TXFORMAT_X_5 0x2ca8
#define R200_PP_TXSIZE_00x2c0c /* NPOT only */
#define R200_PP_TXSIZE_10x2c2c /* NPOT only */
#define R200_PP_TXSIZE_20x2c4c /* NPOT only */
#define R200_PP_TXSIZE_30x2c6c /* NPOT only */
#define R200_PP_TXSIZE_40x2c8c /* NPOT only */
#define R200_PP_TXSIZE_50x2cac /* NPOT only */
#define R200_PP_TXPITCH_0 0x2c10 /* NPOT only */
#define R200_PP_TXPITCH_10x2c30 /* NPOT only */
#define R200_PP_TXPITCH_20x2c50 /* NPOT only */
#define R200_PP_TXPITCH_30x2c70 /* NPOT only */
#define R200_PP_TXPITCH_40x2c90 /* NPOT only */
#define R200_PP_TXPITCH_50x2cb0 /* NPOT only */
#define R200_PP_TXOFFSET_00x2d00
# define R200_TXO_ENDIAN_NO_SWAP(0 << 0)
# define R200_TXO_ENDIAN_BYTE_SWAP(1 << 0)
# define R200_TXO_ENDIAN_WORD_SWAP(2 << 0)
# define R200_TXO_ENDIAN_HALFDW_SWAP(3 << 0)
# define R200_TXO_MACRO_LINEAR(0 << 2)
# define R200_TXO_MACRO_TILE(1 << 2)
# define R200_TXO_MICRO_LINEAR(0 << 3)
# define R200_TXO_MICRO_TILE(1 << 3)
# define R200_TXO_OFFSET_MASK0xffffffe0
# define R200_TXO_OFFSET_SHIFT5
#define R200_PP_TXOFFSET_10x2d18
#define R200_PP_TXOFFSET_20x2d30
#define R200_PP_TXOFFSET_30x2d48
#define R200_PP_TXOFFSET_40x2d60
#define R200_PP_TXOFFSET_50x2d78
#define R200_PP_TFACTOR_00x2ee0
#define R200_PP_TFACTOR_10x2ee4
#define R200_PP_TFACTOR_20x2ee8
#define R200_PP_TFACTOR_30x2eec
#define R200_PP_TFACTOR_40x2ef0
#define R200_PP_TFACTOR_50x2ef4
#define R200_PP_TXCBLEND_00x2f00
# define R200_TXC_ARG_A_ZERO(0)
# define R200_TXC_ARG_A_CURRENT_COLOR(2)
# define R200_TXC_ARG_A_CURRENT_ALPHA(3)
# define R200_TXC_ARG_A_DIFFUSE_COLOR(4)
# define R200_TXC_ARG_A_DIFFUSE_ALPHA(5)
# define R200_TXC_ARG_A_SPECULAR_COLOR(6)
# define R200_TXC_ARG_A_SPECULAR_ALPHA(7)
# define R200_TXC_ARG_A_TFACTOR_COLOR(8)
# define R200_TXC_ARG_A_TFACTOR_ALPHA(9)
# define R200_TXC_ARG_A_R0_COLOR(10)
# define R200_TXC_ARG_A_R0_ALPHA(11)
# define R200_TXC_ARG_A_R1_COLOR(12)
# define R200_TXC_ARG_A_R1_ALPHA(13)
# define R200_TXC_ARG_A_R2_COLOR(14)
# define R200_TXC_ARG_A_R2_ALPHA(15)
# define R200_TXC_ARG_A_R3_COLOR(16)
# define R200_TXC_ARG_A_R3_ALPHA(17)
# define R200_TXC_ARG_A_R4_COLOR(18)
# define R200_TXC_ARG_A_R4_ALPHA(19)
# define R200_TXC_ARG_A_R5_COLOR(20)
# define R200_TXC_ARG_A_R5_ALPHA(21)
# define R200_TXC_ARG_A_TFACTOR1_COLOR(26)
# define R200_TXC_ARG_A_TFACTOR1_ALPHA(27)
# define R200_TXC_ARG_A_MASK(31 << 0)
# define R200_TXC_ARG_A_SHIFT0
# define R200_TXC_ARG_B_ZERO(0 << 5)
# define R200_TXC_ARG_B_CURRENT_COLOR(2 << 5)
# define R200_TXC_ARG_B_CURRENT_ALPHA(3 << 5)
# define R200_TXC_ARG_B_DIFFUSE_COLOR(4 << 5)
# define R200_TXC_ARG_B_DIFFUSE_ALPHA(5 << 5)
# define R200_TXC_ARG_B_SPECULAR_COLOR(6 << 5)
# define R200_TXC_ARG_B_SPECULAR_ALPHA(7 << 5)
# define R200_TXC_ARG_B_TFACTOR_COLOR(8 << 5)
# define R200_TXC_ARG_B_TFACTOR_ALPHA(9 << 5)
# define R200_TXC_ARG_B_R0_COLOR(10 << 5)
# define R200_TXC_ARG_B_R0_ALPHA(11 << 5)
# define R200_TXC_ARG_B_R1_COLOR(12 << 5)
# define R200_TXC_ARG_B_R1_ALPHA(13 << 5)
# define R200_TXC_ARG_B_R2_COLOR(14 << 5)
# define R200_TXC_ARG_B_R2_ALPHA(15 << 5)
# define R200_TXC_ARG_B_R3_COLOR(16 << 5)
# define R200_TXC_ARG_B_R3_ALPHA(17 << 5)
# define R200_TXC_ARG_B_R4_COLOR(18 << 5)
# define R200_TXC_ARG_B_R4_ALPHA(19 << 5)
# define R200_TXC_ARG_B_R5_COLOR(20 << 5)
# define R200_TXC_ARG_B_R5_ALPHA(21 << 5)
# define R200_TXC_ARG_B_TFACTOR1_COLOR(26 << 5)
# define R200_TXC_ARG_B_TFACTOR1_ALPHA(27 << 5)
# define R200_TXC_ARG_B_MASK(31 << 5)
# define R200_TXC_ARG_B_SHIFT5
# define R200_TXC_ARG_C_ZERO(0 << 10)
# define R200_TXC_ARG_C_CURRENT_COLOR(2 << 10)
# define R200_TXC_ARG_C_CURRENT_ALPHA(3 << 10)
# define R200_TXC_ARG_C_DIFFUSE_COLOR(4 << 10)
# define R200_TXC_ARG_C_DIFFUSE_ALPHA(5 << 10)
# define R200_TXC_ARG_C_SPECULAR_COLOR(6 << 10)
# define R200_TXC_ARG_C_SPECULAR_ALPHA(7 << 10)
# define R200_TXC_ARG_C_TFACTOR_COLOR(8 << 10)
# define R200_TXC_ARG_C_TFACTOR_ALPHA(9 << 10)
# define R200_TXC_ARG_C_R0_COLOR(10 << 10)
# define R200_TXC_ARG_C_R0_ALPHA(11 << 10)
# define R200_TXC_ARG_C_R1_COLOR(12 << 10)
# define R200_TXC_ARG_C_R1_ALPHA(13 << 10)
# define R200_TXC_ARG_C_R2_COLOR(14 << 10)
# define R200_TXC_ARG_C_R2_ALPHA(15 << 10)
# define R200_TXC_ARG_C_R3_COLOR(16 << 10)
# define R200_TXC_ARG_C_R3_ALPHA(17 << 10)
# define R200_TXC_ARG_C_R4_COLOR(18 << 10)
# define R200_TXC_ARG_C_R4_ALPHA(19 << 10)
# define R200_TXC_ARG_C_R5_COLOR(20 << 10)
# define R200_TXC_ARG_C_R5_ALPHA(21 << 10)
# define R200_TXC_ARG_C_TFACTOR1_COLOR(26 << 10)
# define R200_TXC_ARG_C_TFACTOR1_ALPHA(27 << 10)
# define R200_TXC_ARG_C_MASK(31 << 10)
# define R200_TXC_ARG_C_SHIFT10
# define R200_TXC_COMP_ARG_A(1 << 16)
# define R200_TXC_COMP_ARG_A_SHIFT(16)
# define R200_TXC_BIAS_ARG_A(1 << 17)
# define R200_TXC_SCALE_ARG_A(1 << 18)
# define R200_TXC_NEG_ARG_A(1 << 19)
# define R200_TXC_COMP_ARG_B(1 << 20)
# define R200_TXC_COMP_ARG_B_SHIFT(20)
# define R200_TXC_BIAS_ARG_B(1 << 21)
# define R200_TXC_SCALE_ARG_B(1 << 22)
# define R200_TXC_NEG_ARG_B(1 << 23)
# define R200_TXC_COMP_ARG_C(1 << 24)
# define R200_TXC_COMP_ARG_C_SHIFT(24)
# define R200_TXC_BIAS_ARG_C(1 << 25)
# define R200_TXC_SCALE_ARG_C(1 << 26)
# define R200_TXC_NEG_ARG_C(1 << 27)
# define R200_TXC_OP_MADD(0 << 28)
# define R200_TXC_OP_CND0(2 << 28)
# define R200_TXC_OP_LERP(3 << 28)
# define R200_TXC_OP_DOT3(4 << 28)
# define R200_TXC_OP_DOT4(5 << 28)
# define R200_TXC_OP_CONDITIONAL(6 << 28)
# define R200_TXC_OP_DOT2_ADD(7 << 28)
# define R200_TXC_OP_MASK(7 << 28)
#define R200_PP_TXCBLEND2_00x2f04
# define R200_TXC_TFACTOR_SEL_SHIFT0
# define R200_TXC_TFACTOR_SEL_MASK0x7
# define R200_TXC_TFACTOR1_SEL_SHIFT4
# define R200_TXC_TFACTOR1_SEL_MASK(0x7 << 4)
# define R200_TXC_SCALE_SHIFT8
# define R200_TXC_SCALE_MASK(7 << 8)
# define R200_TXC_SCALE_1X(0 << 8)
# define R200_TXC_SCALE_2X(1 << 8)
# define R200_TXC_SCALE_4X(2 << 8)
# define R200_TXC_SCALE_8X(3 << 8)
# define R200_TXC_SCALE_INV2(5 << 8)
# define R200_TXC_SCALE_INV4(6 << 8)
# define R200_TXC_SCALE_INV8(7 << 8)
# define R200_TXC_CLAMP_SHIFT12
# define R200_TXC_CLAMP_MASK(3 << 12)
# define R200_TXC_CLAMP_WRAP(0 << 12)
# define R200_TXC_CLAMP_0_1(1 << 12)
# define R200_TXC_CLAMP_8_8(2 << 12)
# define R200_TXC_OUTPUT_REG_MASK(7 << 16)
# define R200_TXC_OUTPUT_REG_NONE(0 << 16)
# define R200_TXC_OUTPUT_REG_R0(1 << 16)
# define R200_TXC_OUTPUT_REG_R1(2 << 16)
# define R200_TXC_OUTPUT_REG_R2(3 << 16)
# define R200_TXC_OUTPUT_REG_R3(4 << 16)
# define R200_TXC_OUTPUT_REG_R4(5 << 16)
# define R200_TXC_OUTPUT_REG_R5(6 << 16)
# define R200_TXC_OUTPUT_MASK_MASK(7 << 20)
# define R200_TXC_OUTPUT_MASK_RGB(0 << 20)
# define R200_TXC_OUTPUT_MASK_RG(1 << 20)
# define R200_TXC_OUTPUT_MASK_RB(2 << 20)
# define R200_TXC_OUTPUT_MASK_R(3 << 20)
# define R200_TXC_OUTPUT_MASK_GB(4 << 20)
# define R200_TXC_OUTPUT_MASK_G(5 << 20)
# define R200_TXC_OUTPUT_MASK_B(6 << 20)
# define R200_TXC_OUTPUT_MASK_NONE(7 << 20)
# define R200_TXC_REPL_NORMAL0
# define R200_TXC_REPL_RED1
# define R200_TXC_REPL_GREEN2
# define R200_TXC_REPL_BLUE3
# define R200_TXC_REPL_ARG_A_SHIFT26
# define R200_TXC_REPL_ARG_A_MASK(3 << 26)
# define R200_TXC_REPL_ARG_B_SHIFT28
# define R200_TXC_REPL_ARG_B_MASK(3 << 28)
# define R200_TXC_REPL_ARG_C_SHIFT30
# define R200_TXC_REPL_ARG_C_MASK(3 << 30)
#define R200_PP_TXABLEND_00x2f08
# define R200_TXA_ARG_A_ZERO(0)
# define R200_TXA_ARG_A_CURRENT_ALPHA(2) /* guess */
# define R200_TXA_ARG_A_CURRENT_BLUE(3) /* guess */
# define R200_TXA_ARG_A_DIFFUSE_ALPHA(4)
# define R200_TXA_ARG_A_DIFFUSE_BLUE(5)
# define R200_TXA_ARG_A_SPECULAR_ALPHA(6)
# define R200_TXA_ARG_A_SPECULAR_BLUE(7)
# define R200_TXA_ARG_A_TFACTOR_ALPHA(8)
# define R200_TXA_ARG_A_TFACTOR_BLUE(9)
# define R200_TXA_ARG_A_R0_ALPHA(10)
# define R200_TXA_ARG_A_R0_BLUE(11)
# define R200_TXA_ARG_A_R1_ALPHA(12)
# define R200_TXA_ARG_A_R1_BLUE(13)
# define R200_TXA_ARG_A_R2_ALPHA(14)
# define R200_TXA_ARG_A_R2_BLUE(15)
# define R200_TXA_ARG_A_R3_ALPHA(16)
# define R200_TXA_ARG_A_R3_BLUE(17)
# define R200_TXA_ARG_A_R4_ALPHA(18)
# define R200_TXA_ARG_A_R4_BLUE(19)
# define R200_TXA_ARG_A_R5_ALPHA(20)
# define R200_TXA_ARG_A_R5_BLUE(21)
# define R200_TXA_ARG_A_TFACTOR1_ALPHA(26)
# define R200_TXA_ARG_A_TFACTOR1_BLUE(27)
# define R200_TXA_ARG_A_MASK(31 << 0)
# define R200_TXA_ARG_A_SHIFT0
# define R200_TXA_ARG_B_ZERO(0 << 5)
# define R200_TXA_ARG_B_CURRENT_ALPHA(2 << 5) /* guess */
# define R200_TXA_ARG_B_CURRENT_BLUE(3 << 5) /* guess */
# define R200_TXA_ARG_B_DIFFUSE_ALPHA(4 << 5)
# define R200_TXA_ARG_B_DIFFUSE_BLUE(5 << 5)
# define R200_TXA_ARG_B_SPECULAR_ALPHA(6 << 5)
# define R200_TXA_ARG_B_SPECULAR_BLUE(7 << 5)
# define R200_TXA_ARG_B_TFACTOR_ALPHA(8 << 5)
# define R200_TXA_ARG_B_TFACTOR_BLUE(9 << 5)
# define R200_TXA_ARG_B_R0_ALPHA(10 << 5)
# define R200_TXA_ARG_B_R0_BLUE(11 << 5)
# define R200_TXA_ARG_B_R1_ALPHA(12 << 5)
# define R200_TXA_ARG_B_R1_BLUE(13 << 5)
# define R200_TXA_ARG_B_R2_ALPHA(14 << 5)
# define R200_TXA_ARG_B_R2_BLUE(15 << 5)
# define R200_TXA_ARG_B_R3_ALPHA(16 << 5)
# define R200_TXA_ARG_B_R3_BLUE(17 << 5)
# define R200_TXA_ARG_B_R4_ALPHA(18 << 5)
# define R200_TXA_ARG_B_R4_BLUE(19 << 5)
# define R200_TXA_ARG_B_R5_ALPHA(20 << 5)
# define R200_TXA_ARG_B_R5_BLUE(21 << 5)
# define R200_TXA_ARG_B_TFACTOR1_ALPHA(26 << 5)
# define R200_TXA_ARG_B_TFACTOR1_BLUE(27 << 5)
# define R200_TXA_ARG_B_MASK(31 << 5)
# define R200_TXA_ARG_B_SHIFT5
# define R200_TXA_ARG_C_ZERO(0 << 10)
# define R200_TXA_ARG_C_CURRENT_ALPHA(2 << 10) /* guess */
# define R200_TXA_ARG_C_CURRENT_BLUE(3 << 10) /* guess */
# define R200_TXA_ARG_C_DIFFUSE_ALPHA(4 << 10)
# define R200_TXA_ARG_C_DIFFUSE_BLUE(5 << 10)
# define R200_TXA_ARG_C_SPECULAR_ALPHA(6 << 10)
# define R200_TXA_ARG_C_SPECULAR_BLUE(7 << 10)
# define R200_TXA_ARG_C_TFACTOR_ALPHA(8 << 10)
# define R200_TXA_ARG_C_TFACTOR_BLUE(9 << 10)
# define R200_TXA_ARG_C_R0_ALPHA(10 << 10)
# define R200_TXA_ARG_C_R0_BLUE(11 << 10)
# define R200_TXA_ARG_C_R1_ALPHA(12 << 10)
# define R200_TXA_ARG_C_R1_BLUE(13 << 10)
# define R200_TXA_ARG_C_R2_ALPHA(14 << 10)
# define R200_TXA_ARG_C_R2_BLUE(15 << 10)
# define R200_TXA_ARG_C_R3_ALPHA(16 << 10)
# define R200_TXA_ARG_C_R3_BLUE(17 << 10)
# define R200_TXA_ARG_C_R4_ALPHA(18 << 10)
# define R200_TXA_ARG_C_R4_BLUE(19 << 10)
# define R200_TXA_ARG_C_R5_ALPHA(20 << 10)
# define R200_TXA_ARG_C_R5_BLUE(21 << 10)
# define R200_TXA_ARG_C_TFACTOR1_ALPHA(26 << 10)
# define R200_TXA_ARG_C_TFACTOR1_BLUE(27 << 10)
# define R200_TXA_ARG_C_MASK(31 << 10)
# define R200_TXA_ARG_C_SHIFT10
# define R200_TXA_COMP_ARG_A(1 << 16)
# define R200_TXA_COMP_ARG_A_SHIFT(16)
# define R200_TXA_BIAS_ARG_A(1 << 17)
# define R200_TXA_SCALE_ARG_A(1 << 18)
# define R200_TXA_NEG_ARG_A(1 << 19)
# define R200_TXA_COMP_ARG_B(1 << 20)
# define R200_TXA_COMP_ARG_B_SHIFT(20)
# define R200_TXA_BIAS_ARG_B(1 << 21)
# define R200_TXA_SCALE_ARG_B(1 << 22)
# define R200_TXA_NEG_ARG_B(1 << 23)
# define R200_TXA_COMP_ARG_C(1 << 24)
# define R200_TXA_COMP_ARG_C_SHIFT(24)
# define R200_TXA_BIAS_ARG_C(1 << 25)
# define R200_TXA_SCALE_ARG_C(1 << 26)
# define R200_TXA_NEG_ARG_C(1 << 27)
# define R200_TXA_OP_MADD(0 << 28)
# define R200_TXA_OP_CND0(2 << 28)
# define R200_TXA_OP_LERP(3 << 28)
# define R200_TXA_OP_CONDITIONAL(6 << 28)
# define R200_TXA_OP_MASK(7 << 28)
#define R200_PP_TXABLEND2_00x2f0c
# define R200_TXA_TFACTOR_SEL_SHIFT0
# define R200_TXA_TFACTOR_SEL_MASK0x7
# define R200_TXA_TFACTOR1_SEL_SHIFT4
# define R200_TXA_TFACTOR1_SEL_MASK(0x7 << 4)
# define R200_TXA_SCALE_SHIFT8
# define R200_TXA_SCALE_MASK(7 << 8)
# define R200_TXA_SCALE_1X(0 << 8)
# define R200_TXA_SCALE_2X(1 << 8)
# define R200_TXA_SCALE_4X(2 << 8)
# define R200_TXA_SCALE_8X(3 << 8)
# define R200_TXA_SCALE_INV2(5 << 8)
# define R200_TXA_SCALE_INV4(6 << 8)
# define R200_TXA_SCALE_INV8(7 << 8)
# define R200_TXA_CLAMP_SHIFT12
# define R200_TXA_CLAMP_MASK(3 << 12)
# define R200_TXA_CLAMP_WRAP(0 << 12)
# define R200_TXA_CLAMP_0_1(1 << 12)
# define R200_TXA_CLAMP_8_8(2 << 12)
# define R200_TXA_OUTPUT_REG_MASK(7 << 16)
# define R200_TXA_OUTPUT_REG_NONE(0 << 16)
# define R200_TXA_OUTPUT_REG_R0(1 << 16)
# define R200_TXA_OUTPUT_REG_R1(2 << 16)
# define R200_TXA_OUTPUT_REG_R2(3 << 16)
# define R200_TXA_OUTPUT_REG_R3(4 << 16)
# define R200_TXA_OUTPUT_REG_R4(5 << 16)
# define R200_TXA_OUTPUT_REG_R5(6 << 16)
# define R200_TXA_DOT_ALPHA(1 << 20)
# define R200_TXA_REPL_NORMAL0
# define R200_TXA_REPL_RED1
# define R200_TXA_REPL_GREEN2
# define R200_TXA_REPL_ARG_A_SHIFT26
# define R200_TXA_REPL_ARG_A_MASK(3 << 26)
# define R200_TXA_REPL_ARG_B_SHIFT28
# define R200_TXA_REPL_ARG_B_MASK(3 << 28)
# define R200_TXA_REPL_ARG_C_SHIFT30
# define R200_TXA_REPL_ARG_C_MASK(3 << 30)
#define R200_PP_TXCBLEND_10x2f10
#define R200_PP_TXCBLEND2_10x2f14
#define R200_PP_TXABLEND_10x2f18
#define R200_PP_TXABLEND2_10x2f1c
#define R200_PP_TXCBLEND_20x2f20
#define R200_PP_TXCBLEND2_20x2f24
#define R200_PP_TXABLEND_20x2f28
#define R200_PP_TXABLEND2_20x2f2c
#define R200_PP_TXCBLEND_30x2f30
#define R200_PP_TXCBLEND2_30x2f34
#define R200_PP_TXABLEND_30x2f38
#define R200_PP_TXABLEND2_30x2f3c
#define R200_SE_VTX_FMT_00x2088
# define R200_VTX_XY0 /* always have xy */
# define R200_VTX_Z0(1<<0)
# define R200_VTX_W0(1<<1)
# define R200_VTX_WEIGHT_COUNT_SHIFT(2)
# define R200_VTX_PV_MATRIX_SEL(1<<5)
# define R200_VTX_N0(1<<6)
# define R200_VTX_POINT_SIZE(1<<7)
# define R200_VTX_DISCRETE_FOG(1<<8)
# define R200_VTX_SHININESS_0(1<<9)
# define R200_VTX_SHININESS_1(1<<10)
# define R200_VTX_COLOR_NOT_PRESENT0
# define R200_VTX_PK_RGBA1
# define R200_VTX_FP_RGB2
# define R200_VTX_FP_RGBA3
# define R200_VTX_COLOR_MASK3
# define R200_VTX_COLOR_0_SHIFT11
# define R200_VTX_COLOR_1_SHIFT13
# define R200_VTX_COLOR_2_SHIFT15
# define R200_VTX_COLOR_3_SHIFT17
# define R200_VTX_COLOR_4_SHIFT19
# define R200_VTX_COLOR_5_SHIFT21
# define R200_VTX_COLOR_6_SHIFT23
# define R200_VTX_COLOR_7_SHIFT25
# define R200_VTX_XY1(1<<28)
# define R200_VTX_Z1(1<<29)
# define R200_VTX_W1(1<<30)
# define R200_VTX_N1(1<<31)
#define R200_SE_VTX_FMT_10x208c
# define R200_VTX_TEX0_COMP_CNT_SHIFT0
# define R200_VTX_TEX1_COMP_CNT_SHIFT3
# define R200_VTX_TEX2_COMP_CNT_SHIFT6
# define R200_VTX_TEX3_COMP_CNT_SHIFT9
# define R200_VTX_TEX4_COMP_CNT_SHIFT12
# define R200_VTX_TEX5_COMP_CNT_SHIFT15
#define R200_SE_TCL_OUTPUT_VTX_FMT_00x2090
#define R200_SE_TCL_OUTPUT_VTX_FMT_10x2094
#define R200_SE_TCL_OUTPUT_VTX_COMP_SEL0x2250
# define R200_OUTPUT_XYZW(1<<0)
# define R200_OUTPUT_COLOR_0(1<<8)
# define R200_OUTPUT_COLOR_1(1<<9)
# define R200_OUTPUT_TEX_0(1<<16)
# define R200_OUTPUT_TEX_1(1<<17)
# define R200_OUTPUT_TEX_2(1<<18)
# define R200_OUTPUT_TEX_3(1<<19)
# define R200_OUTPUT_TEX_4(1<<20)
# define R200_OUTPUT_TEX_5(1<<21)
# define R200_OUTPUT_TEX_MASK(0x3f<<16)
# define R200_OUTPUT_DISCRETE_FOG(1<<24)
# define R200_OUTPUT_PT_SIZE(1<<25)
# define R200_FORCE_INORDER_PROC(1<<31)
#define R200_PP_CNTL_X0x2cc4
#define R200_PP_TXMULTI_CTL_00x2c1c
#define R200_SE_VTX_STATE_CNTL0x2180
# define R200_UPDATE_USER_COLOR_0_ENA_MASK (1<<16)
/* Registers for CP and Microcode Engine */
#define RADEON_CP_ME_RAM_ADDR 0x07d4
#define RADEON_CP_ME_RAM_RADDR 0x07d8
#define RADEON_CP_ME_RAM_DATAH 0x07dc
#define RADEON_CP_ME_RAM_DATAL 0x07e0
#define RADEON_CP_RB_BASE 0x0700
#define RADEON_CP_RB_CNTL 0x0704
#define RADEON_CP_RB_RPTR_ADDR 0x070c
#define RADEON_CP_RB_RPTR 0x0710
#define RADEON_CP_RB_WPTR 0x0714
#define RADEON_CP_IB_BASE 0x0738
#define RADEON_CP_IB_BUFSZ 0x073c
#define RADEON_CP_CSQ_CNTL 0x0740
# define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0)
# define RADEON_CSQ_PRIDIS_INDDIS (0 << 28)
# define RADEON_CSQ_PRIPIO_INDDIS (1 << 28)
# define RADEON_CSQ_PRIBM_INDDIS (2 << 28)
# define RADEON_CSQ_PRIPIO_INDBM (3 << 28)
# define RADEON_CSQ_PRIBM_INDBM (4 << 28)
# define RADEON_CSQ_PRIPIO_INDPIO (15 << 28)
#define RADEON_CP_CSQ_STAT 0x07f8
# define RADEON_CSQ_RPTR_PRIMARY_MASK (0xff << 0)
# define RADEON_CSQ_WPTR_PRIMARY_MASK (0xff << 8)
# define RADEON_CSQ_RPTR_INDIRECT_MASK (0xff << 16)
# define RADEON_CSQ_WPTR_INDIRECT_MASK (0xff << 24)
#define RADEON_CP_CSQ_ADDR 0x07f0
#define RADEON_CP_CSQ_DATA 0x07f4
#define RADEON_CP_CSQ_APER_PRIMARY 0x1000
#define RADEON_CP_CSQ_APER_INDIRECT 0x1300
#define RADEON_CP_RB_WPTR_DELAY 0x0718
# define RADEON_PRE_WRITE_TIMER_SHIFT 0
# define RADEON_PRE_WRITE_LIMIT_SHIFT 23
#define RADEON_AIC_CNTL 0x01d0
# define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
#define RADEON_AIC_LO_ADDR 0x01dc
/* Constants */
#define RADEON_LAST_FRAME_REG RADEON_GUI_SCRATCH_REG0
#define RADEON_LAST_CLEAR_REG RADEON_GUI_SCRATCH_REG2
/* CP packet types */
#define RADEON_CP_PACKET0 0x00000000
#define RADEON_CP_PACKET1 0x40000000
#define RADEON_CP_PACKET2 0x80000000
#define RADEON_CP_PACKET3 0xC0000000
# define RADEON_CP_PACKET_MASK 0xC0000000
# define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000
# define RADEON_CP_PACKET_MAX_DWORDS (1 << 12)
# define RADEON_CP_PACKET0_REG_MASK 0x000007ff
# define RADEON_CP_PACKET1_REG0_MASK 0x000007ff
# define RADEON_CP_PACKET1_REG1_MASK 0x003ff800
#define RADEON_CP_PACKET0_ONE_REG_WR 0x00008000
#define RADEON_CP_PACKET3_NOP 0xC0001000
#define RADEON_CP_PACKET3_NEXT_CHAR 0xC0001900
#define RADEON_CP_PACKET3_PLY_NEXTSCAN 0xC0001D00
#define RADEON_CP_PACKET3_SET_SCISSORS 0xC0001E00
#define RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM 0xC0002300
#define RADEON_CP_PACKET3_LOAD_MICROCODE 0xC0002400
#define RADEON_CP_PACKET3_WAIT_FOR_IDLE 0xC0002600
#define RADEON_CP_PACKET3_3D_DRAW_VBUF 0xC0002800
#define RADEON_CP_PACKET3_3D_DRAW_IMMD 0xC0002900
#define RADEON_CP_PACKET3_3D_DRAW_INDX 0xC0002A00
#define RADEON_CP_PACKET3_LOAD_PALETTE 0xC0002C00
#define R200_CP_PACKET3_3D_DRAW_IMMD_2 0xc0003500
#define RADEON_CP_PACKET3_3D_LOAD_VBPNTR 0xC0002F00
#define RADEON_CP_PACKET3_CNTL_PAINT 0xC0009100
#define RADEON_CP_PACKET3_CNTL_BITBLT 0xC0009200
#define RADEON_CP_PACKET3_CNTL_SMALLTEXT 0xC0009300
#define RADEON_CP_PACKET3_CNTL_HOSTDATA_BLT 0xC0009400
#define RADEON_CP_PACKET3_CNTL_POLYLINE 0xC0009500
#define RADEON_CP_PACKET3_CNTL_POLYSCANLINES 0xC0009800
#define RADEON_CP_PACKET3_CNTL_PAINT_MULTI 0xC0009A00
#define RADEON_CP_PACKET3_CNTL_BITBLT_MULTI 0xC0009B00
#define RADEON_CP_PACKET3_CNTL_TRANS_BITBLT 0xC0009C00
#define RADEON_CP_VC_FRMT_XY 0x00000000
#define RADEON_CP_VC_FRMT_W0 0x00000001
#define RADEON_CP_VC_FRMT_FPCOLOR 0x00000002
#define RADEON_CP_VC_FRMT_FPALPHA 0x00000004
#define RADEON_CP_VC_FRMT_PKCOLOR 0x00000008
#define RADEON_CP_VC_FRMT_FPSPEC 0x00000010
#define RADEON_CP_VC_FRMT_FPFOG 0x00000020
#define RADEON_CP_VC_FRMT_PKSPEC 0x00000040
#define RADEON_CP_VC_FRMT_ST0 0x00000080
#define RADEON_CP_VC_FRMT_ST1 0x00000100
#define RADEON_CP_VC_FRMT_Q1 0x00000200
#define RADEON_CP_VC_FRMT_ST2 0x00000400
#define RADEON_CP_VC_FRMT_Q2 0x00000800
#define RADEON_CP_VC_FRMT_ST3 0x00001000
#define RADEON_CP_VC_FRMT_Q3 0x00002000
#define RADEON_CP_VC_FRMT_Q0 0x00004000
#define RADEON_CP_VC_FRMT_BLND_WEIGHT_CNT_MASK 0x00038000
#define RADEON_CP_VC_FRMT_N0 0x00040000
#define RADEON_CP_VC_FRMT_XY1 0x08000000
#define RADEON_CP_VC_FRMT_Z1 0x10000000
#define RADEON_CP_VC_FRMT_W1 0x20000000
#define RADEON_CP_VC_FRMT_N1 0x40000000
#define RADEON_CP_VC_FRMT_Z 0x80000000
#define RADEON_CP_VC_CNTL_PRIM_TYPE_NONE 0x00000000
#define RADEON_CP_VC_CNTL_PRIM_TYPE_POINT 0x00000001
#define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE 0x00000002
#define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP 0x00000003
#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST 0x00000004
#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN 0x00000005
#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP 0x00000006
#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_TYPE_2 0x00000007
#define RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST 0x00000008
#define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_POINT_LIST 0x00000009
#define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_LINE_LIST 0x0000000a
#define RADEON_CP_VC_CNTL_PRIM_TYPE_QUAD_LIST 0x0000000d
#define RADEON_CP_VC_CNTL_PRIM_WALK_IND 0x00000010
#define RADEON_CP_VC_CNTL_PRIM_WALK_LIST 0x00000020
#define RADEON_CP_VC_CNTL_PRIM_WALK_RING 0x00000030
#define RADEON_CP_VC_CNTL_COLOR_ORDER_BGRA 0x00000000
#define RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA 0x00000040
#define RADEON_CP_VC_CNTL_MAOS_ENABLE 0x00000080
#define RADEON_CP_VC_CNTL_VTX_FMT_NON_RADEON_MODE 0x00000000
#define RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE 0x00000100
#define RADEON_CP_VC_CNTL_TCL_DISABLE 0x00000000
#define RADEON_CP_VC_CNTL_TCL_ENABLE 0x00000200
#define RADEON_CP_VC_CNTL_NUM_SHIFT 16
#define RADEON_VS_MATRIX_0_ADDR 0
#define RADEON_VS_MATRIX_1_ADDR 4
#define RADEON_VS_MATRIX_2_ADDR 8
#define RADEON_VS_MATRIX_3_ADDR 12
#define RADEON_VS_MATRIX_4_ADDR 16
#define RADEON_VS_MATRIX_5_ADDR 20
#define RADEON_VS_MATRIX_6_ADDR 24
#define RADEON_VS_MATRIX_7_ADDR 28
#define RADEON_VS_MATRIX_8_ADDR 32
#define RADEON_VS_MATRIX_9_ADDR 36
#define RADEON_VS_MATRIX_10_ADDR 40
#define RADEON_VS_MATRIX_11_ADDR 44
#define RADEON_VS_MATRIX_12_ADDR 48
#define RADEON_VS_MATRIX_13_ADDR 52
#define RADEON_VS_MATRIX_14_ADDR 56
#define RADEON_VS_MATRIX_15_ADDR 60
#define RADEON_VS_LIGHT_AMBIENT_ADDR 64
#define RADEON_VS_LIGHT_DIFFUSE_ADDR 72
#define RADEON_VS_LIGHT_SPECULAR_ADDR 80
#define RADEON_VS_LIGHT_DIRPOS_ADDR 88
#define RADEON_VS_LIGHT_HWVSPOT_ADDR 96
#define RADEON_VS_LIGHT_ATTENUATION_ADDR 104
#define RADEON_VS_MATRIX_EYE2CLIP_ADDR 112
#define RADEON_VS_UCP_ADDR 116
#define RADEON_VS_GLOBAL_AMBIENT_ADDR 122
#define RADEON_VS_FOG_PARAM_ADDR 123
#define RADEON_VS_EYE_VECTOR_ADDR 124
#define RADEON_SS_LIGHT_DCD_ADDR 0
#define RADEON_SS_LIGHT_SPOT_EXPONENT_ADDR 8
#define RADEON_SS_LIGHT_SPOT_CUTOFF_ADDR 16
#define RADEON_SS_LIGHT_SPECULAR_THRESH_ADDR 24
#define RADEON_SS_LIGHT_RANGE_CUTOFF_ADDR 32
#define RADEON_SS_VERT_GUARD_CLIP_ADJ_ADDR 48
#define RADEON_SS_VERT_GUARD_DISCARD_ADJ_ADDR 49
#define RADEON_SS_HORZ_GUARD_CLIP_ADJ_ADDR 50
#define RADEON_SS_HORZ_GUARD_DISCARD_ADJ_ADDR 51
#define RADEON_SS_SHININESS 60
#define RADEON_TV_MASTER_CNTL 0x0800
# define RADEON_TV_ASYNC_RST (1 << 0)
# define RADEON_CRT_ASYNC_RST (1 << 1)
# define RADEON_RESTART_PHASE_FIX (1 << 3)
#define RADEON_TV_FIFO_ASYNC_RST (1 << 4)
#define RADEON_VIN_ASYNC_RST (1 << 5)
#define RADEON_AUD_ASYNC_RST (1 << 6)
#define RADEON_DVS_ASYNC_RST (1 << 7)
# define RADEON_CRT_FIFO_CE_EN (1 << 9)
# define RADEON_TV_FIFO_CE_EN (1 << 10)
# define RADEON_RE_SYNC_NOW_SEL_MASK (3 << 14)
# define RADEON_TVCLK_ALWAYS_ONb (1 << 30)
#define RADEON_TV_ON (1 << 31)
#define RADEON_TV_PRE_DAC_MUX_CNTL 0x0888
# define RADEON_Y_RED_EN (1 << 0)
# define RADEON_C_GRN_EN (1 << 1)
# define RADEON_CMP_BLU_EN (1 << 2)
# define RADEON_DAC_DITHER_EN (1 << 3)
# define RADEON_RED_MX_FORCE_DAC_DATA (6 << 4)
# define RADEON_GRN_MX_FORCE_DAC_DATA (6 << 8)
# define RADEON_BLU_MX_FORCE_DAC_DATA (6 << 12)
# define RADEON_TV_FORCE_DAC_DATA_SHIFT 16
#define RADEON_TV_RGB_CNTL 0x0804
# define RADEON_SWITCH_TO_BLUE (1 << 4)
# define RADEON_RGB_DITHER_EN (1 << 5)
# define RADEON_RGB_SRC_SEL_MASK (3 << 8)
# define RADEON_RGB_SRC_SEL_CRTC1 (0 << 8)
# define RADEON_RGB_SRC_SEL_RMX (1 << 8)
# define RADEON_RGB_SRC_SEL_CRTC2 (2 << 8)
# define RADEON_RGB_CONVERT_BY_PASS (1 << 10)
# define RADEON_UVRAM_READ_MARGIN_SHIFT 16
# define RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT 20
#define RADEON_RGB_ATTEN_SEL(x) ((x) << 24)
#define RADEON_TVOUT_SCALE_EN (1 << 26)
#define RADEON_RGB_ATTEN_VAL(x) ((x) << 28)
#define RADEON_TV_SYNC_CNTL 0x0808
# define RADEON_SYNC_OE (1 << 0)
# define RADEON_SYNC_OUT (1 << 1)
# define RADEON_SYNC_IN (1 << 2)
# define RADEON_SYNC_PUB (1 << 3)
# define RADEON_SYNC_PD (1 << 4)
# define RADEON_TV_SYNC_IO_DRIVE (1 << 5)
#define RADEON_TV_HTOTAL 0x080c
#define RADEON_TV_HDISP 0x0810
#define RADEON_TV_HSTART 0x0818
#define RADEON_TV_HCOUNT 0x081C
#define RADEON_TV_VTOTAL 0x0820
#define RADEON_TV_VDISP 0x0824
#define RADEON_TV_VCOUNT 0x0828
#define RADEON_TV_FTOTAL 0x082c
#define RADEON_TV_FCOUNT 0x0830
#define RADEON_TV_FRESTART 0x0834
#define RADEON_TV_HRESTART 0x0838
#define RADEON_TV_VRESTART 0x083c
#define RADEON_TV_HOST_READ_DATA 0x0840
#define RADEON_TV_HOST_WRITE_DATA 0x0844
#define RADEON_TV_HOST_RD_WT_CNTL 0x0848
#define RADEON_HOST_FIFO_RD (1 << 12)
#define RADEON_HOST_FIFO_RD_ACK (1 << 13)
#define RADEON_HOST_FIFO_WT (1 << 14)
#define RADEON_HOST_FIFO_WT_ACK (1 << 15)
#define RADEON_TV_VSCALER_CNTL1 0x084c
# define RADEON_UV_INC_MASK 0xffff
# define RADEON_UV_INC_SHIFT 0
# define RADEON_Y_W_EN (1 << 24)
# define RADEON_RESTART_FIELD (1 << 29) /* restart on field 0 */
# define RADEON_Y_DEL_W_SIG_SHIFT 26
#define RADEON_TV_TIMING_CNTL 0x0850
# define RADEON_H_INC_MASK 0xfff
# define RADEON_H_INC_SHIFT 0
# define RADEON_REQ_Y_FIRST (1 << 19)
# define RADEON_FORCE_BURST_ALWAYS (1 << 21)
# define RADEON_UV_POST_SCALE_BYPASS (1 << 23)
# define RADEON_UV_OUTPUT_POST_SCALE_SHIFT 24
#define RADEON_TV_VSCALER_CNTL2 0x0854
# define RADEON_DITHER_MODE (1 << 0)
# define RADEON_Y_OUTPUT_DITHER_EN (1 << 1)
# define RADEON_UV_OUTPUT_DITHER_EN (1 << 2)
# define RADEON_UV_TO_BUF_DITHER_EN (1 << 3)
#define RADEON_TV_Y_FALL_CNTL 0x0858
# define RADEON_Y_FALL_PING_PONG (1 << 16)
# define RADEON_Y_COEF_EN (1 << 17)
#define RADEON_TV_Y_RISE_CNTL 0x085c
# define RADEON_Y_RISE_PING_PONG (1 << 16)
#define RADEON_TV_Y_SAW_TOOTH_CNTL 0x0860
#define RADEON_TV_UPSAMP_AND_GAIN_CNTL 0x0864
#define RADEON_YUPSAMP_EN (1 << 0)
#define RADEON_UVUPSAMP_EN (1 << 2)
#define RADEON_TV_GAIN_LIMIT_SETTINGS 0x0868
# define RADEON_Y_GAIN_LIMIT_SHIFT 0
# define RADEON_UV_GAIN_LIMIT_SHIFT 16
#define RADEON_TV_LINEAR_GAIN_SETTINGS 0x086c
# define RADEON_Y_GAIN_SHIFT 0
# define RADEON_UV_GAIN_SHIFT 16
#define RADEON_TV_MODULATOR_CNTL1 0x0870
#define RADEON_YFLT_EN (1 << 2)
#define RADEON_UVFLT_EN (1 << 3)
# define RADEON_ALT_PHASE_EN (1 << 6)
# define RADEON_SYNC_TIP_LEVEL (1 << 7)
# define RADEON_BLANK_LEVEL_SHIFT 8
# define RADEON_SET_UP_LEVEL_SHIFT 16
#define RADEON_SLEW_RATE_LIMIT (1 << 23)
# define RADEON_CY_FILT_BLEND_SHIFT 28
#define RADEON_TV_MODULATOR_CNTL2 0x0874
# define RADEON_TV_U_BURST_LEVEL_MASK 0x1ff
# define RADEON_TV_V_BURST_LEVEL_MASK 0x1ff
# define RADEON_TV_V_BURST_LEVEL_SHIFT 16
#define RADEON_TV_CRC_CNTL 0x0890
#define RADEON_TV_UV_ADR 0x08ac
#define RADEON_MAX_UV_ADR_MASK 0x000000ff
#define RADEON_MAX_UV_ADR_SHIFT 0
#define RADEON_TABLE1_BOT_ADR_MASK 0x0000ff00
#define RADEON_TABLE1_BOT_ADR_SHIFT 8
#define RADEON_TABLE3_TOP_ADR_MASK 0x00ff0000
#define RADEON_TABLE3_TOP_ADR_SHIFT 16
#define RADEON_HCODE_TABLE_SEL_MASK 0x06000000
#define RADEON_HCODE_TABLE_SEL_SHIFT 25
#define RADEON_VCODE_TABLE_SEL_MASK 0x18000000
#define RADEON_VCODE_TABLE_SEL_SHIFT 27
#define RADEON_TV_MAX_FIFO_ADDR 0x1a7
#define RADEON_TV_MAX_FIFO_ADDR_INTERNAL 0x1ff
#define RADEON_TV_PLL_FINE_CNTL 0x0020/* PLL */
#define RADEON_TV_PLL_CNTL 0x0021/* PLL */
# define RADEON_TV_M0LO_MASK 0xff
# define RADEON_TV_M0HI_MASK 0x7
# define RADEON_TV_M0HI_SHIFT 18
# define RADEON_TV_N0LO_MASK 0x1ff
# define RADEON_TV_N0LO_SHIFT 8
# define RADEON_TV_N0HI_MASK 0x3
# define RADEON_TV_N0HI_SHIFT 21
# define RADEON_TV_P_MASK 0xf
# define RADEON_TV_P_SHIFT 24
# define RADEON_TV_SLIP_EN (1 << 23)
# define RADEON_TV_DTO_EN (1 << 28)
#define RADEON_TV_PLL_CNTL1 0x0022/* PLL */
# define RADEON_TVPLL_RESET (1 << 1)
# define RADEON_TVPLL_SLEEP (1 << 3)
# define RADEON_TVPLL_REFCLK_SEL (1 << 4)
# define RADEON_TVPCP_SHIFT 8
# define RADEON_TVPCP_MASK (7 << 8)
# define RADEON_TVPVG_SHIFT 11
# define RADEON_TVPVG_MASK (7 << 11)
# define RADEON_TVPDC_SHIFT 14
# define RADEON_TVPDC_MASK (3 << 14)
# define RADEON_TVPLL_TEST_DIS (1 << 31)
# define RADEON_TVCLK_SRC_SEL_TVPLL (1 << 30)
#define RS400_DISP2_REQ_CNTL10xe30
# define RS400_DISP2_START_REQ_LEVEL_SHIFT 0
# define RS400_DISP2_START_REQ_LEVEL_MASK 0x3ff
# define RS400_DISP2_STOP_REQ_LEVEL_SHIFT 12
# define RS400_DISP2_STOP_REQ_LEVEL_MASK 0x3ff
# define RS400_DISP2_ALLOW_FID_LEVEL_SHIFT 22
# define RS400_DISP2_ALLOW_FID_LEVEL_MASK 0x3ff
#define RS400_DISP2_REQ_CNTL20xe34
# define RS400_DISP2_CRITICAL_POINT_START_SHIFT 12
# define RS400_DISP2_CRITICAL_POINT_START_MASK 0x3ff
# define RS400_DISP2_CRITICAL_POINT_STOP_SHIFT 22
# define RS400_DISP2_CRITICAL_POINT_STOP_MASK 0x3ff
#define RS400_DMIF_MEM_CNTL10xe38
# define RS400_DISP2_START_ADR_SHIFT 0
# define RS400_DISP2_START_ADR_MASK 0x3ff
# define RS400_DISP1_CRITICAL_POINT_START_SHIFT 12
# define RS400_DISP1_CRITICAL_POINT_START_MASK 0x3ff
# define RS400_DISP1_CRITICAL_POINT_STOP_SHIFT 22
# define RS400_DISP1_CRITICAL_POINT_STOP_MASK 0x3ff
#define RS400_DISP1_REQ_CNTL10xe3c
# define RS400_DISP1_START_REQ_LEVEL_SHIFT 0
# define RS400_DISP1_START_REQ_LEVEL_MASK 0x3ff
# define RS400_DISP1_STOP_REQ_LEVEL_SHIFT 12
# define RS400_DISP1_STOP_REQ_LEVEL_MASK 0x3ff
# define RS400_DISP1_ALLOW_FID_LEVEL_SHIFT 22
# define RS400_DISP1_ALLOW_FID_LEVEL_MASK 0x3ff
#define RS690_MC_INDEX0x78
#define RS690_MC_INDEX_MASK0x1ff
#define RS690_MC_INDEX_WR_EN(1 << 9)
#define RS690_MC_INDEX_WR_ACK0x7f
#define RS690_MC_DATA0x7c
#define RS690_MC_FB_LOCATION0x100
#define RS690_MC_AGP_LOCATION0x101
#define RS690_MC_AGP_BASE0x102
#define RS690_MC_AGP_BASE_2 0x103
#define RS690_MC_INIT_MISC_LAT_TIMER 0x104
#define RS690_MC_STATUS 0x90
#define RS690_MC_STATUS_IDLE (1 << 0)
#define RS600_MC_INDEX 0x70
#define RS600_MC_ADDR_MASK0xffff
# define RS600_MC_IND_SEQ_RBS_0 (1 << 16)
# define RS600_MC_IND_SEQ_RBS_1 (1 << 17)
# define RS600_MC_IND_SEQ_RBS_2 (1 << 18)
# define RS600_MC_IND_SEQ_RBS_3 (1 << 19)
# define RS600_MC_IND_AIC_RBS (1 << 20)
# define RS600_MC_IND_CITF_ARB0 (1 << 21)
# define RS600_MC_IND_CITF_ARB1 (1 << 22)
# define RS600_MC_IND_WR_EN (1 << 23)
#define RS600_MC_DATA 0x74
#define RS600_MC_STATUS 0x0
#define RS600_MC_IDLE (1 << 1)
#define RS600_MC_FB_LOCATION 0x4
#define RS600_MC_AGP_LOCATION 0x5
#define RS600_AGP_BASE 0x6
#define RS600_AGP_BASE2 0x7
#define AVIVO_MC_INDEX0x0070
#define R520_MC_STATUS 0x00
# define R520_MC_STATUS_IDLE (1 << 1)
#define RV515_MC_STATUS 0x08
# define RV515_MC_STATUS_IDLE (1 << 4)
#define RV515_MC_INIT_MISC_LAT_TIMER 0x09
#define AVIVO_MC_DATA0x0074
#define RV515_MC_FB_LOCATION 0x1
#define RV515_MC_AGP_LOCATION 0x2
#define RV515_MC_AGP_BASE 0x3
#define RV515_MC_AGP_BASE_2 0x4
#define RV515_MC_CNTL 0x5
#define RV515_MEM_NUM_CHANNELS_MASK 0x3
#define R520_MC_FB_LOCATION 0x4
#define R520_MC_AGP_LOCATION 0x5
#define R520_MC_AGP_BASE 0x6
#define R520_MC_AGP_BASE_2 0x7
#define R520_MC_CNTL0 0x8
#define R520_MEM_NUM_CHANNELS_MASK (0x3 << 24)
#define R520_MEM_NUM_CHANNELS_SHIFT 24
#define R520_MC_CHANNEL_SIZE (1 << 23)
#define RS780_MC_INDEX0x28f8
#define RS780_MC_INDEX_MASK0x1ff
#define RS780_MC_INDEX_WR_EN(1 << 9)
#define RS780_MC_DATA0x28fc
#define R600_RAMCFG 0x2408
# define R600_CHANSIZE (1 << 7)
# define R600_CHANSIZE_OVERRIDE (1 << 10)
#define R600_SRBM_STATUS 0x0e50
#define AVIVO_CP_DYN_CNTL 0x000f /* PLL */
# define AVIVO_CP_FORCEON (1 << 0)
#define AVIVO_E2_DYN_CNTL 0x0011 /* PLL */
# define AVIVO_E2_FORCEON (1 << 0)
#define AVIVO_IDCT_DYN_CNTL 0x0013 /* PLL */
# define AVIVO_IDCT_FORCEON (1 << 0)
#define AVIVO_HDP_FB_LOCATION 0x134
#define AVIVO_VGA_RENDER_CONTROL0x0300
# define AVIVO_VGA_VSTATUS_CNTL_MASK (3 << 16)
#define AVIVO_D1VGA_CONTROL0x0330
# define AVIVO_DVGA_CONTROL_MODE_ENABLE (1<<0)
# define AVIVO_DVGA_CONTROL_TIMING_SELECT (1<<8)
# define AVIVO_DVGA_CONTROL_SYNC_POLARITY_SELECT (1<<9)
# define AVIVO_DVGA_CONTROL_OVERSCAN_TIMING_SELECT (1<<10)
# define AVIVO_DVGA_CONTROL_OVERSCAN_COLOR_EN (1<<16)
# define AVIVO_DVGA_CONTROL_ROTATE (1<<24)
#define AVIVO_D2VGA_CONTROL0x0338
#define AVIVO_VGA25_PPLL_REF_DIV_SRC0x0360
#define AVIVO_VGA25_PPLL_REF_DIV0x0364
#define AVIVO_VGA28_PPLL_REF_DIV_SRC0x0368
#define AVIVO_VGA28_PPLL_REF_DIV0x036c
#define AVIVO_VGA41_PPLL_REF_DIV_SRC0x0370
#define AVIVO_VGA41_PPLL_REF_DIV0x0374
#define AVIVO_VGA25_PPLL_FB_DIV0x0378
#define AVIVO_VGA28_PPLL_FB_DIV0x037c
#define AVIVO_VGA41_PPLL_FB_DIV0x0380
#define AVIVO_VGA25_PPLL_POST_DIV_SRC0x0384
#define AVIVO_VGA25_PPLL_POST_DIV0x0388
#define AVIVO_VGA28_PPLL_POST_DIV_SRC0x038c
#define AVIVO_VGA28_PPLL_POST_DIV0x0390
#define AVIVO_VGA41_PPLL_POST_DIV_SRC0x0394
#define AVIVO_VGA41_PPLL_POST_DIV0x0398
#define AVIVO_VGA25_PPLL_CNTL0x039c
#define AVIVO_VGA28_PPLL_CNTL0x03a0
#define AVIVO_VGA41_PPLL_CNTL0x03a4
#define AVIVO_EXT1_PPLL_REF_DIV_SRC 0x400
#define AVIVO_EXT1_PPLL_REF_DIV 0x404
#define AVIVO_EXT1_PPLL_UPDATE_LOCK 0x408
#define AVIVO_EXT1_PPLL_UPDATE_CNTL 0x40c
#define AVIVO_EXT2_PPLL_REF_DIV_SRC 0x410
#define AVIVO_EXT2_PPLL_REF_DIV 0x414
#define AVIVO_EXT2_PPLL_UPDATE_LOCK 0x418
#define AVIVO_EXT2_PPLL_UPDATE_CNTL 0x41c
#define AVIVO_EXT1_PPLL_FB_DIV 0x430
#define AVIVO_EXT2_PPLL_FB_DIV 0x434
#define AVIVO_EXT1_PPLL_POST_DIV_SRC 0x438
#define AVIVO_EXT1_PPLL_POST_DIV 0x43c
#define AVIVO_EXT2_PPLL_POST_DIV_SRC 0x440
#define AVIVO_EXT2_PPLL_POST_DIV 0x444
#define AVIVO_EXT1_PPLL_CNTL 0x448
#define AVIVO_EXT2_PPLL_CNTL 0x44c
#define AVIVO_P1PLL_CNTL 0x450
#define AVIVO_P2PLL_CNTL 0x454
#define AVIVO_P1PLL_INT_SS_CNTL 0x458
#define AVIVO_P2PLL_INT_SS_CNTL 0x45c
#define AVIVO_P1PLL_TMDSA_CNTL 0x460
#define AVIVO_P2PLL_LVTMA_CNTL 0x464
#define AVIVO_PCLK_CRTC1_CNTL 0x480
#define AVIVO_PCLK_CRTC2_CNTL 0x484
#define AVIVO_D1CRTC_H_TOTAL0x6000
#define AVIVO_D1CRTC_H_BLANK_START_END 0x6004
#define AVIVO_D1CRTC_H_SYNC_A 0x6008
#define AVIVO_D1CRTC_H_SYNC_A_CNTL 0x600c
#define AVIVO_D1CRTC_H_SYNC_B 0x6010
#define AVIVO_D1CRTC_H_SYNC_B_CNTL 0x6014
#define AVIVO_D1CRTC_V_TOTAL0x6020
#define AVIVO_D1CRTC_V_BLANK_START_END 0x6024
#define AVIVO_D1CRTC_V_SYNC_A 0x6028
#define AVIVO_D1CRTC_V_SYNC_A_CNTL 0x602c
#define AVIVO_D1CRTC_V_SYNC_B 0x6030
#define AVIVO_D1CRTC_V_SYNC_B_CNTL 0x6034
#define AVIVO_D1CRTC_CONTROL 0x6080
# define AVIVO_CRTC_EN (1<<0)
#define AVIVO_D1CRTC_BLANK_CONTROL 0x6084
#define AVIVO_D1CRTC_INTERLACE_CONTROL 0x6088
#define AVIVO_D1CRTC_INTERLACE_STATUS 0x608c
#define AVIVO_D1CRTC_STEREO_CONTROL 0x60c4
/* master controls */
#define AVIVO_DC_CRTC_MASTER_EN 0x60f8
#define AVIVO_DC_CRTC_TV_CONTROL 0x60fc
#define AVIVO_D1GRPH_ENABLE 0x6100
#define AVIVO_D1GRPH_CONTROL 0x6104
# define AVIVO_D1GRPH_CONTROL_DEPTH_8BPP (0<<0)
# define AVIVO_D1GRPH_CONTROL_DEPTH_16BPP (1<<0)
# define AVIVO_D1GRPH_CONTROL_DEPTH_32BPP (2<<0)
# define AVIVO_D1GRPH_CONTROL_DEPTH_64BPP (3<<0)
# define AVIVO_D1GRPH_CONTROL_8BPP_INDEXED (0<<8)
# define AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555 (0<<8)
# define AVIVO_D1GRPH_CONTROL_16BPP_RGB565 (1<<8)
# define AVIVO_D1GRPH_CONTROL_16BPP_ARGB4444 (2<<8)
# define AVIVO_D1GRPH_CONTROL_16BPP_AI88 (3<<8)
# define AVIVO_D1GRPH_CONTROL_16BPP_MONO16 (4<<8)
# define AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888 (0<<8)
# define AVIVO_D1GRPH_CONTROL_32BPP_ARGB2101010 (1<<8)
# define AVIVO_D1GRPH_CONTROL_32BPP_DIGITAL (2<<8)
# define AVIVO_D1GRPH_CONTROL_32BPP_8B_ARGB2101010 (3<<8)
# define AVIVO_D1GRPH_CONTROL_64BPP_ARGB16161616 (0<<8)
# define AVIVO_D1GRPH_SWAP_RB (1<<16)
# define AVIVO_D1GRPH_TILED (1<<20)
# define AVIVO_D1GRPH_MACRO_ADDRESS_MODE (1<<21)
#define AVIVO_D1GRPH_LUT_SEL 0x6108
#define R600_D1GRPH_SWAP_CONTROL 0x610C
# define R600_D1GRPH_SWAP_ENDIAN_NONE (0 << 0)
# define R600_D1GRPH_SWAP_ENDIAN_16BIT (1 << 0)
# define R600_D1GRPH_SWAP_ENDIAN_32BIT (2 << 0)
# define R600_D1GRPH_SWAP_ENDIAN_64BIT (3 << 0)
/* the *_HIGH surface regs are backwards; the D1 regs are in the D2
* block and vice versa. This applies to GRPH, CUR, etc.
*/
#define AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110
#define R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6914
#define R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6114
#define AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118
#define R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x691c
#define R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x611c
#define AVIVO_D1GRPH_PITCH 0x6120
#define AVIVO_D1GRPH_SURFACE_OFFSET_X 0x6124
#define AVIVO_D1GRPH_SURFACE_OFFSET_Y 0x6128
#define AVIVO_D1GRPH_X_START 0x612c
#define AVIVO_D1GRPH_Y_START 0x6130
#define AVIVO_D1GRPH_X_END 0x6134
#define AVIVO_D1GRPH_Y_END 0x6138
#define AVIVO_D1GRPH_UPDATE 0x6144
# define AVIVO_D1GRPH_UPDATE_LOCK (1<<16)
#define AVIVO_D1GRPH_FLIP_CONTROL 0x6148
#define AVIVO_D1GRPH_COLOR_MATRIX_TRANSFORMATION_CNTL 0x6380
#define AVIVO_D1CUR_CONTROL 0x6400
# define AVIVO_D1CURSOR_EN (1<<0)
# define AVIVO_D1CURSOR_MODE_SHIFT 8
# define AVIVO_D1CURSOR_MODE_MASK (0x3<<8)
# define AVIVO_D1CURSOR_MODE_24BPP (0x2)
#define AVIVO_D1CUR_SURFACE_ADDRESS 0x6408
#define R700_D1CUR_SURFACE_ADDRESS_HIGH 0x6c0c
#define R700_D2CUR_SURFACE_ADDRESS_HIGH 0x640c
#define AVIVO_D1CUR_SIZE 0x6410
#define AVIVO_D1CUR_POSITION 0x6414
#define AVIVO_D1CUR_HOT_SPOT 0x6418
#define AVIVO_D1CUR_UPDATE 0x6424
# define AVIVO_D1CURSOR_UPDATE_LOCK (1 << 16)
#define AVIVO_DC_LUT_RW_SELECT 0x6480
#define AVIVO_DC_LUT_RW_MODE 0x6484
#define AVIVO_DC_LUT_RW_INDEX 0x6488
#define AVIVO_DC_LUT_SEQ_COLOR 0x648c
#define AVIVO_DC_LUT_PWL_DATA 0x6490
#define AVIVO_DC_LUT_30_COLOR 0x6494
#define AVIVO_DC_LUT_READ_PIPE_SELECT 0x6498
#define AVIVO_DC_LUT_WRITE_EN_MASK 0x649c
#define AVIVO_DC_LUT_AUTOFILL 0x64a0
#define AVIVO_DC_LUTA_CONTROL 0x64c0
#define AVIVO_DC_LUTA_BLACK_OFFSET_BLUE 0x64c4
#define AVIVO_DC_LUTA_BLACK_OFFSET_GREEN 0x64c8
#define AVIVO_DC_LUTA_BLACK_OFFSET_RED 0x64cc
#define AVIVO_DC_LUTA_WHITE_OFFSET_BLUE 0x64d0
#define AVIVO_DC_LUTA_WHITE_OFFSET_GREEN 0x64d4
#define AVIVO_DC_LUTA_WHITE_OFFSET_RED 0x64d8
#define AVIVO_DC_LB_MEMORY_SPLIT 0x6520
# define AVIVO_DC_LB_MEMORY_SPLIT_MASK 0x3
# define AVIVO_DC_LB_MEMORY_SPLIT_SHIFT 0
# define AVIVO_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF 0
# define AVIVO_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q 1
# define AVIVO_DC_LB_MEMORY_SPLIT_D1_ONLY 2
# define AVIVO_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q 3
# define AVIVO_DC_LB_MEMORY_SPLIT_SHIFT_MODE (1 << 2)
# define AVIVO_DC_LB_DISP1_END_ADR_SHIFT 4
# define AVIVO_DC_LB_DISP1_END_ADR_MASK 0x7ff
#define AVIVO_D1MODE_PRIORITY_A_CNT 0x6548
# define AVIVO_DxMODE_PRIORITY_MARK_MASK 0x7fff
# define AVIVO_DxMODE_PRIORITY_OFF (1 << 16)
# define AVIVO_DxMODE_PRIORITY_ALWAYS_ON (1 << 20)
# define AVIVO_DxMODE_PRIORITY_FORCE_MASK (1 << 24)
#define AVIVO_D1MODE_PRIORITY_B_CNT 0x654c
#define AVIVO_D2MODE_PRIORITY_A_CNT 0x6d48
#define AVIVO_D2MODE_PRIORITY_B_CNT 0x6d4c
#define AVIVO_LB_MAX_REQ_OUTSTANDING 0x6d58
# define AVIVO_LB_D1_MAX_REQ_OUTSTANDING_MASK 0xf
# define AVIVO_LB_D1_MAX_REQ_OUTSTANDING_SHIFT 0
# define AVIVO_LB_D2_MAX_REQ_OUTSTANDING_MASK 0xf
# define AVIVO_LB_D2_MAX_REQ_OUTSTANDING_SHIFT 16
#define AVIVO_D1MODE_DATA_FORMAT 0x6528
# define AVIVO_D1MODE_INTERLEAVE_EN (1 << 0)
#define AVIVO_D1MODE_DESKTOP_HEIGHT 0x652c
#define AVIVO_D1MODE_VLINE_START_END 0x6538
# define AVIVO_D1MODE_VLINE_START_SHIFT 0
# define AVIVO_D1MODE_VLINE_END_SHIFT 16
# define AVIVO_D1MODE_VLINE_INV (1 << 31)
#define AVIVO_D1MODE_VLINE_STATUS 0x653c
# define AVIVO_D1MODE_VLINE_STAT (1 << 12)
#define AVIVO_D1MODE_VIEWPORT_START 0x6580
#define AVIVO_D1MODE_VIEWPORT_SIZE 0x6584
#define AVIVO_D1MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6588
#define AVIVO_D1MODE_EXT_OVERSCAN_TOP_BOTTOM 0x658c
#define AVIVO_D1SCL_SCALER_ENABLE 0x6590
#define AVIVO_D1SCL_SCALER_TAP_CONTROL 0x6594
#define AVIVO_D1SCL_UPDATE 0x65cc
# define AVIVO_D1SCL_UPDATE_LOCK (1<<16)
/* second crtc */
#define AVIVO_D2CRTC_H_TOTAL0x6800
#define AVIVO_D2CRTC_H_BLANK_START_END 0x6804
#define AVIVO_D2CRTC_H_SYNC_A 0x6808
#define AVIVO_D2CRTC_H_SYNC_A_CNTL 0x680c
#define AVIVO_D2CRTC_H_SYNC_B 0x6810
#define AVIVO_D2CRTC_H_SYNC_B_CNTL 0x6814
#define AVIVO_D2CRTC_V_TOTAL0x6820
#define AVIVO_D2CRTC_V_BLANK_START_END 0x6824
#define AVIVO_D2CRTC_V_SYNC_A 0x6828
#define AVIVO_D2CRTC_V_SYNC_A_CNTL 0x682c
#define AVIVO_D2CRTC_V_SYNC_B 0x6830
#define AVIVO_D2CRTC_V_SYNC_B_CNTL 0x6834
#define AVIVO_D2CRTC_CONTROL 0x6880
#define AVIVO_D2CRTC_BLANK_CONTROL 0x6884
#define AVIVO_D2CRTC_INTERLACE_CONTROL 0x6888
#define AVIVO_D2CRTC_INTERLACE_STATUS 0x688c
#define AVIVO_D2CRTC_STEREO_CONTROL 0x68c4
#define AVIVO_D2GRPH_ENABLE 0x6900
#define AVIVO_D2GRPH_CONTROL 0x6904
#define AVIVO_D2GRPH_LUT_SEL 0x6908
#define AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS 0x6910
#define AVIVO_D2GRPH_SECONDARY_SURFACE_ADDRESS 0x6918
#define AVIVO_D2GRPH_PITCH 0x6920
#define AVIVO_D2GRPH_SURFACE_OFFSET_X 0x6924
#define AVIVO_D2GRPH_SURFACE_OFFSET_Y 0x6928
#define AVIVO_D2GRPH_X_START 0x692c
#define AVIVO_D2GRPH_Y_START 0x6930
#define AVIVO_D2GRPH_X_END 0x6934
#define AVIVO_D2GRPH_Y_END 0x6938
#define AVIVO_D2GRPH_UPDATE 0x6944
#define AVIVO_D2GRPH_FLIP_CONTROL 0x6948
#define AVIVO_D2CUR_CONTROL 0x6c00
#define AVIVO_D2CUR_SURFACE_ADDRESS 0x6c08
#define AVIVO_D2CUR_SIZE 0x6c10
#define AVIVO_D2CUR_POSITION 0x6c14
#define RS690_DCP_CONTROL 0x6c9c
#define AVIVO_D2MODE_DATA_FORMAT 0x6d28
#define AVIVO_D2MODE_DESKTOP_HEIGHT 0x6d2c
#define AVIVO_D2MODE_VIEWPORT_START 0x6d80
#define AVIVO_D2MODE_VIEWPORT_SIZE 0x6d84
#define AVIVO_D2MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6d88
#define AVIVO_D2MODE_EXT_OVERSCAN_TOP_BOTTOM 0x6d8c
#define AVIVO_D2SCL_SCALER_ENABLE 0x6d90
#define AVIVO_D2SCL_SCALER_TAP_CONTROL 0x6d94
#define AVIVO_D2SCL_UPDATE 0x6dcc
#define AVIVO_DDIA_BIT_DEPTH_CONTROL0x7214
#define AVIVO_DACA_ENABLE0x7800
#define AVIVO_DAC_ENABLE(1 << 0)
#define AVIVO_DACA_SOURCE_SELECT0x7804
# define AVIVO_DAC_SOURCE_CRTC1 (0 << 0)
# define AVIVO_DAC_SOURCE_CRTC2 (1 << 0)
# define AVIVO_DAC_SOURCE_TV (2 << 0)
#define AVIVO_DACA_FORCE_OUTPUT_CNTL0x783c
# define AVIVO_DACA_FORCE_OUTPUT_CNTL_FORCE_DATA_EN (1 << 0)
# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_SHIFT (8)
# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_BLUE (1 << 0)
# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_GREEN (1 << 1)
# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_RED (1 << 2)
# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_ON_BLANKB_ONLY (1 << 24)
#define AVIVO_DACA_POWERDOWN0x7850
# define AVIVO_DACA_POWERDOWN_POWERDOWN (1 << 0)
# define AVIVO_DACA_POWERDOWN_BLUE (1 << 8)
# define AVIVO_DACA_POWERDOWN_GREEN (1 << 16)
# define AVIVO_DACA_POWERDOWN_RED (1 << 24)
#define AVIVO_DACB_ENABLE0x7a00
#define AVIVO_DACB_SOURCE_SELECT0x7a04
#define AVIVO_DACB_FORCE_OUTPUT_CNTL0x7a3c
# define AVIVO_DACB_FORCE_OUTPUT_CNTL_FORCE_DATA_EN (1 << 0)
# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_SHIFT (8)
# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_BLUE (1 << 0)
# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_GREEN (1 << 1)
# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_RED (1 << 2)
# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_ON_BLANKB_ONLY (1 << 24)
#define AVIVO_DACB_POWERDOWN0x7a50
# define AVIVO_DACB_POWERDOWN_POWERDOWN (1 << 0)
# define AVIVO_DACB_POWERDOWN_BLUE (1 << 8)
# define AVIVO_DACB_POWERDOWN_GREEN (1 << 16)
# define AVIVO_DACB_POWERDOWN_RED
#define AVIVO_TMDSA_CNTL 0x7880
# define AVIVO_TMDSA_CNTL_ENABLE (1 << 0)
# define AVIVO_TMDSA_CNTL_HPD_MASK (1 << 4)
# define AVIVO_TMDSA_CNTL_HPD_SELECT (1 << 8)
# define AVIVO_TMDSA_CNTL_SYNC_PHASE (1 << 12)
# define AVIVO_TMDSA_CNTL_PIXEL_ENCODING (1 << 16)
# define AVIVO_TMDSA_CNTL_DUAL_LINK_ENABLE (1 << 24)
# define AVIVO_TMDSA_CNTL_SWAP (1 << 28)
#define AVIVO_TMDSA_SOURCE_SELECT0x7884
/* 78a8 appears to be some kind of (reasonably tolerant) clock?
* 78d0 definitely hits the transmitter, definitely clock. */
/* MYSTERY1 This appears to control dithering? */
#define AVIVO_TMDSA_BIT_DEPTH_CONTROL0x7894
# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN (1 << 0)
# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH (1 << 4)
# define AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN (1 << 8)
# define AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH (1 << 12)
# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_EN (1 << 16)
# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH (1 << 20)
# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL (1 << 24)
# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_RESET (1 << 26)
#define AVIVO_TMDSA_DCBALANCER_CONTROL 0x78d0
# define AVIVO_TMDSA_DCBALANCER_CONTROL_EN (1 << 0)
# define AVIVO_TMDSA_DCBALANCER_CONTROL_TEST_EN (1 << 8)
# define AVIVO_TMDSA_DCBALANCER_CONTROL_TEST_IN_SHIFT (16)
# define AVIVO_TMDSA_DCBALANCER_CONTROL_FORCE (1 << 24)
#define AVIVO_TMDSA_DATA_SYNCHRONIZATION 0x78d8
# define AVIVO_TMDSA_DATA_SYNCHRONIZATION_DSYNSEL (1 << 0)
# define AVIVO_TMDSA_DATA_SYNCHRONIZATION_PFREQCHG (1 << 8)
#define AVIVO_TMDSA_CLOCK_ENABLE 0x7900
#define AVIVO_TMDSA_TRANSMITTER_ENABLE 0x7904
# define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX0_ENABLE (1 << 0)
# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKC0EN (1 << 1)
# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD00EN (1 << 2)
# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD01EN (1 << 3)
# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD02EN (1 << 4)
# define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX1_ENABLE (1 << 8)
# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD10EN (1 << 10)
# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD11EN (1 << 11)
# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD12EN (1 << 12)
# define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX_ENABLE_HPD_MASK (1 << 16)
# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK (1 << 17)
# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK (1 << 18)
#define AVIVO_TMDSA_TRANSMITTER_CONTROL0x7910
#define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_ENABLE(1 << 0)
#define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_RESET (1 << 1)
#define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT(2)
#define AVIVO_TMDSA_TRANSMITTER_CONTROL_IDSCKSEL (1 << 4)
# define AVIVO_TMDSA_TRANSMITTER_CONTROL_BGSLEEP (1 << 5)
#define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN(1 << 6)
#define AVIVO_TMDSA_TRANSMITTER_CONTROL_TMCLK (1 << 8)
#define AVIVO_TMDSA_TRANSMITTER_CONTROL_TMCLK_FROM_PADS(1 << 13)
#define AVIVO_TMDSA_TRANSMITTER_CONTROL_TDCLK (1 << 14)
#define AVIVO_TMDSA_TRANSMITTER_CONTROL_TDCLK_FROM_PADS(1 << 15)
# define AVIVO_TMDSA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16)
#define AVIVO_TMDSA_TRANSMITTER_CONTROL_BYPASS_PLL(1 << 28)
# define AVIVO_TMDSA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29)
#define AVIVO_TMDSA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL(1 << 31)
#define AVIVO_LVTMA_CNTL0x7a80
# define AVIVO_LVTMA_CNTL_ENABLE (1 << 0)
# define AVIVO_LVTMA_CNTL_HPD_MASK (1 << 4)
# define AVIVO_LVTMA_CNTL_HPD_SELECT (1 << 8)
# define AVIVO_LVTMA_CNTL_SYNC_PHASE (1 << 12)
# define AVIVO_LVTMA_CNTL_PIXEL_ENCODING (1 << 16)
# define AVIVO_LVTMA_CNTL_DUAL_LINK_ENABLE (1 << 24)
# define AVIVO_LVTMA_CNTL_SWAP (1 << 28)
#define AVIVO_LVTMA_SOURCE_SELECT 0x7a84
#define AVIVO_LVTMA_COLOR_FORMAT 0x7a88
#define AVIVO_LVTMA_BIT_DEPTH_CONTROL 0x7a94
# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN (1 << 0)
# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH (1 << 4)
# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN (1 << 8)
# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH (1 << 12)
# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_EN (1 << 16)
# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH (1 << 20)
# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL (1 << 24)
# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_RESET (1 << 26)
#define AVIVO_LVTMA_DCBALANCER_CONTROL 0x7ad0
# define AVIVO_LVTMA_DCBALANCER_CONTROL_EN (1 << 0)
# define AVIVO_LVTMA_DCBALANCER_CONTROL_TEST_EN (1 << 8)
# define AVIVO_LVTMA_DCBALANCER_CONTROL_TEST_IN_SHIFT (16)
# define AVIVO_LVTMA_DCBALANCER_CONTROL_FORCE (1 << 24)
#define AVIVO_LVTMA_DATA_SYNCHRONIZATION 0x78d8
# define AVIVO_LVTMA_DATA_SYNCHRONIZATION_DSYNSEL (1 << 0)
# define AVIVO_LVTMA_DATA_SYNCHRONIZATION_PFREQCHG (1 << 8)
#define R500_LVTMA_CLOCK_ENABLE0x7b00
#define R600_LVTMA_CLOCK_ENABLE0x7b04
#define R500_LVTMA_TRANSMITTER_ENABLE 0x7b04
#define R600_LVTMA_TRANSMITTER_ENABLE 0x7b08
# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC0EN (1 << 1)
# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD00EN (1 << 2)
# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD01EN (1 << 3)
# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD02EN (1 << 4)
# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD03EN (1 << 5)
# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC1EN (1 << 9)
# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD10EN (1 << 10)
# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD11EN (1 << 11)
# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD12EN (1 << 12)
# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK (1 << 17)
# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK (1 << 18)
#define R500_LVTMA_TRANSMITTER_CONTROL 0x7b10
#define R600_LVTMA_TRANSMITTER_CONTROL 0x7b14
#define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_ENABLE (1 << 0)
#define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_RESET (1 << 1)
#define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT (2)
#define AVIVO_LVTMA_TRANSMITTER_CONTROL_IDSCKSEL (1 << 4)
# define AVIVO_LVTMA_TRANSMITTER_CONTROL_BGSLEEP (1 << 5)
#define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN (1 << 6)
#define AVIVO_LVTMA_TRANSMITTER_CONTROL_TMCLK (1 << 8)
#define AVIVO_LVTMA_TRANSMITTER_CONTROL_TMCLK_FROM_PADS (1 << 13)
#define AVIVO_LVTMA_TRANSMITTER_CONTROL_TDCLK (1 << 14)
#define AVIVO_LVTMA_TRANSMITTER_CONTROL_TDCLK_FROM_PADS (1 << 15)
# define AVIVO_LVTMA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16)
#define AVIVO_LVTMA_TRANSMITTER_CONTROL_BYPASS_PLL (1 << 28)
# define AVIVO_LVTMA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29)
#define AVIVO_LVTMA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 << 31)
#define R500_LVTMA_PWRSEQ_CNTL0x7af0
#define R600_LVTMA_PWRSEQ_CNTL0x7af4
#define AVIVO_LVTMA_PWRSEQ_EN (1 << 0)
#define AVIVO_LVTMA_PWRSEQ_PLL_ENABLE_MASK (1 << 2)
#define AVIVO_LVTMA_PWRSEQ_PLL_RESET_MASK (1 << 3)
#define AVIVO_LVTMA_PWRSEQ_TARGET_STATE (1 << 4)
#define AVIVO_LVTMA_SYNCEN (1 << 8)
#define AVIVO_LVTMA_SYNCEN_OVRD (1 << 9)
#define AVIVO_LVTMA_SYNCEN_POL (1 << 10)
#define AVIVO_LVTMA_DIGON (1 << 16)
#define AVIVO_LVTMA_DIGON_OVRD (1 << 17)
#define AVIVO_LVTMA_DIGON_POL (1 << 18)
#define AVIVO_LVTMA_BLON (1 << 24)
#define AVIVO_LVTMA_BLON_OVRD (1 << 25)
#define AVIVO_LVTMA_BLON_POL (1 << 26)
#define R500_LVTMA_PWRSEQ_STATE 0x7af4
#define R600_LVTMA_PWRSEQ_STATE 0x7af8
# define AVIVO_LVTMA_PWRSEQ_STATE_TARGET_STATE_R (1 << 0)
# define AVIVO_LVTMA_PWRSEQ_STATE_DIGON (1 << 1)
# define AVIVO_LVTMA_PWRSEQ_STATE_SYNCEN (1 << 2)
# define AVIVO_LVTMA_PWRSEQ_STATE_BLON (1 << 3)
# define AVIVO_LVTMA_PWRSEQ_STATE_DONE (1 << 4)
# define AVIVO_LVTMA_PWRSEQ_STATE_STATUS_SHIFT (8)
#define AVIVO_LVDS_BACKLIGHT_CNTL0x7af8
#define AVIVO_LVDS_BACKLIGHT_CNTL_EN(1 << 0)
#define AVIVO_LVDS_BACKLIGHT_LEVEL_MASK0x0000ff00
#define AVIVO_LVDS_BACKLIGHT_LEVEL_SHIFT8
#define AVIVO_DVOA_BIT_DEPTH_CONTROL0x7988
#define AVIVO_GPIO_0 0x7e30
#define AVIVO_GPIO_1 0x7e40
#define AVIVO_GPIO_2 0x7e50
#define AVIVO_GPIO_3 0x7e60
#define AVIVO_DC_GPIO_HPD_MASK 0x7e90
#define AVIVO_DC_GPIO_HPD_A 0x7e94
#define AVIVO_DC_GPIO_HPD_EN 0x7e98
#define AVIVO_DC_GPIO_HPD_Y 0x7e9c
#define AVIVO_I2C_STATUS0x7d30
#define AVIVO_I2C_STATUS_DONE(1 << 0)
#define AVIVO_I2C_STATUS_NACK(1 << 1)
#define AVIVO_I2C_STATUS_HALT(1 << 2)
#define AVIVO_I2C_STATUS_GO(1 << 3)
#define AVIVO_I2C_STATUS_MASK0x7
/* If radeon_mm_i2c is to be believed, this is HALT, NACK, and maybe
* DONE? */
#define AVIVO_I2C_STATUS_CMD_RESET0x7
#define AVIVO_I2C_STATUS_CMD_WAIT(1 << 3)
#define AVIVO_I2C_STOP0x7d34
#define AVIVO_I2C_START_CNTL0x7d38
#define AVIVO_I2C_START(1 << 8)
#define AVIVO_I2C_CONNECTOR0(0 << 16)
#define AVIVO_I2C_CONNECTOR1(1 << 16)
#define R520_I2C_START (1<<0)
#define R520_I2C_STOP (1<<1)
#define R520_I2C_RX (1<<2)
#define R520_I2C_EN (1<<8)
#define R520_I2C_DDC1 (0<<16)
#define R520_I2C_DDC2 (1<<16)
#define R520_I2C_DDC3 (2<<16)
#define R520_I2C_DDC_MASK (3<<16)
#define AVIVO_I2C_CONTROL20x7d3c
#define AVIVO_I2C_7D3C_SIZE_SHIFT8
#define AVIVO_I2C_7D3C_SIZE_MASK(0xf << 8)
#define AVIVO_I2C_CONTROL30x7d40
/* Reading is done 4 bytes at a time: read the bottom 8 bits from
* 7d44, four times in a row.
* Writing is a little more complex. First write DATA with
* 0xnnnnnnzz, then 0xnnnnnnyy, where nnnnnn is some non-deterministic
* magic number, zz is, I think, the slave address, and yy is the byte
* you want to write. */
#define AVIVO_I2C_DATA0x7d44
#define R520_I2C_ADDR_COUNT_MASK (0x7)
#define R520_I2C_DATA_COUNT_SHIFT (8)
#define R520_I2C_DATA_COUNT_MASK (0xF00)
#define AVIVO_I2C_CNTL0x7d50
#define AVIVO_I2C_EN(1 << 0)
#define AVIVO_I2C_RESET(1 << 8)
#define R600_GENERAL_PWRMGT 0x618
#define R600_OPEN_DRAIN_PADS (1 << 11)
#define R600_LOWER_GPIO_ENABLE 0x710
#define R600_CTXSW_VID_LOWER_GPIO_CNTL 0x718
#define R600_HIGH_VID_LOWER_GPIO_CNTL 0x71c
#define R600_MEDIUM_VID_LOWER_GPIO_CNTL 0x720
#define R600_LOW_VID_LOWER_GPIO_CNTL 0x724
#define R600_MC_VM_FB_LOCATION 0x2180
#define R600_MC_VM_AGP_TOP 0x2184
#define R600_MC_VM_AGP_BOT 0x2188
#define R600_MC_VM_AGP_BASE 0x218c
#define R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190
#define R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194
#define R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198
#define R700_MC_VM_FB_LOCATION 0x2024
#define R700_MC_VM_AGP_TOP 0x2028
#define R700_MC_VM_AGP_BOT 0x202c
#define R700_MC_VM_AGP_BASE 0x2030
#define R600_HDP_NONSURFACE_BASE 0x2c04
#define R600_BUS_CNTL 0x5420
#define R600_CONFIG_CNTL 0x5424
#define R600_CONFIG_MEMSIZE 0x5428
#define R600_CONFIG_F0_BASE 0x542C
#define R600_CONFIG_APER_SIZE 0x5430
#define R600_ROM_CNTL 0x1600
# define R600_SCK_OVERWRITE (1 << 1)
# define R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT 28
# define R600_SCK_PRESCALE_CRYSTAL_CLK_MASK (0xf << 28)
#define R600_CG_SPLL_FUNC_CNTL 0x600
# define R600_SPLL_BYPASS_EN (1 << 3)
#define R600_CG_SPLL_STATUS 0x60c
# define R600_SPLL_CHG_STATUS (1 << 1)
#define R600_BIOS_0_SCRATCH 0x1724
#define R600_BIOS_1_SCRATCH 0x1728
#define R600_BIOS_2_SCRATCH 0x1