Chameleon

Chameleon Commit Details

Date:2012-11-28 19:21:16 (11 years 4 months ago)
Author:Cosmosis Jones
Commit:2134
Parents: 2133
Message:Nvidia ROM SIZE: http://forge.voodooprojects.org/p/chameleon/issues/302/ Intel resolution: http://forum.voodooprojects.org/index.php/topic,2754.0/topicseen.html
Changes:
M/trunk/i386/libsaio/acpi.h
M/trunk/i386/libsaio/nvidia.c
M/trunk/i386/modules/Resolution/915resolution.c
M/trunk/i386/modules/Resolution/edid.c
M/trunk/i386/modules/Resolution/915resolution.h

File differences

trunk/i386/libsaio/nvidia.c
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#define DBG(x...)␊
#endif␊
␊
#define NVIDIA_ROM_SIZE␉␉␉␉0x10000␊
#define NVIDIA_ROM_SIZE␉␉␉␉0x20000␊
#define PATCH_ROM_SUCCESS␉␉␉1␊
#define PATCH_ROM_SUCCESS_HAS_LVDS␉2␊
#define PATCH_ROM_FAILED␉␉␉0␊
trunk/i386/libsaio/acpi.h
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/* Per ACPI 3.0a spec */␊
␊
// TODO Migrate␊
struct acpi_2_rsdp {␊
char Signature[8];␊
uint8_t Checksum;␊
char OEMID[6];␊
uint8_t Revision;␊
uint32_t RsdtAddress;␊
uint32_t Length;␊
uint64_t XsdtAddress;␊
uint8_t ExtendedChecksum;␊
char Reserved[3];␊
struct acpi_2_rsdp␊
{␊
␉char␉␉␉Signature[8];␊
␉uint8_t␉␉␉Checksum;␊
␉char␉␉␉OEMID[6];␊
␉uint8_t␉␉␉Revision;␊
␉uint32_t␉␉RsdtAddress;␊
␉uint32_t␉␉Length;␊
␉uint64_t␉␉XsdtAddress;␊
␉uint8_t␉␉␉ExtendedChecksum;␊
␉char␉␉␉Reserved[3];␊
} __attribute__((packed));␊
␊
// TODO Migrate␊
struct acpi_2_rsdt {␊
␉char Signature[4];␊
␉uint32_t Length;␊
␉uint8_t Revision;␊
␉uint8_t Checksum;␊
␉char OEMID[6];␊
␉char OEMTableId[8];␊
␉uint32_t OEMRevision;␊
␉uint32_t CreatorId;␊
␉uint32_t CreatorRevision;␊
struct acpi_2_rsdt␊
{␊
␉char␉␉␉Signature[4];␊
␉uint32_t␉␉Length;␊
␉uint8_t␉␉␉Revision;␊
␉uint8_t␉␉␉Checksum;␊
␉char␉␉␉OEMID[6];␊
␉char␉␉␉OEMTableId[8];␊
␉uint32_t␉␉OEMRevision;␊
␉uint32_t␉␉CreatorId;␊
␉uint32_t␉␉CreatorRevision;␊
} __attribute__((packed));␊
␊
// TODO Migrate␊
struct acpi_2_xsdt {␊
␉char Signature[4];␊
␉uint32_t Length;␊
␉uint8_t Revision;␊
␉uint8_t Checksum;␊
␉char OEMID[6];␊
␉char OEMTableId[8];␊
␉uint32_t OEMRevision;␊
␉uint32_t CreatorId;␊
␉uint32_t CreatorRevision;␊
struct acpi_2_xsdt␊
{␊
␉char␉␉␉Signature[4];␊
␉uint32_t␉␉Length;␊
␉uint8_t␉␉␉Revision;␊
␉uint8_t␉␉␉Checksum;␊
␉char␉␉␉OEMID[6];␊
␉char␉␉␉OEMTableId[8];␊
␉uint32_t␉␉OEMRevision;␊
␉uint32_t␉␉CreatorId;␊
␉uint32_t␉␉CreatorRevision;␊
} __attribute__((packed));␊
␊
// TODO Migrate␊
struct acpi_2_ssdt {␊
␉char Signature[4];␊
␉uint32_t Length;␊
␉uint8_t Revision;␊
␉uint8_t Checksum;␊
␉char OEMID[6];␊
␉char OEMTableId[8];␊
␉uint32_t OEMRevision;␊
␉uint32_t CreatorId;␊
␉uint32_t CreatorRevision;␊
struct acpi_2_ssdt␊
{␊
␉char␉␉␉Signature[4];␊
␉uint32_t␉␉Length;␊
␉uint8_t␉␉␉Revision;␊
␉uint8_t␉␉␉Checksum;␊
␉char␉␉␉OEMID[6];␊
␉char␉␉␉OEMTableId[8];␊
␉uint32_t␉␉OEMRevision;␊
␉uint32_t␉␉CreatorId;␊
␉uint32_t␉␉CreatorRevision;␊
} __attribute__((packed));␊
␊
// TODO Migrate␊
struct acpi_2_dsdt {␊
␉char Signature[4];␊
␉uint32_t Length;␊
␉uint8_t Revision;␊
␉uint8_t Checksum;␊
␉char OEMID[6];␊
␉char OEMTableId[8];␊
␉uint32_t OEMRevision;␊
␉uint32_t CreatorId;␊
␉uint32_t CreatorRevision;␊
struct acpi_2_dsdt␊
{␊
␉char␉␉␉Signature[4];␊
␉uint32_t␉␉Length;␊
␉uint8_t␉␉␉Revision;␊
␉uint8_t␉␉␉Checksum;␊
␉char␉␉␉OEMID[6];␊
␉char␉␉␉OEMTableId[8];␊
␉uint32_t␉␉OEMRevision;␊
␉uint32_t␉␉CreatorId;␊
␉uint32_t␉␉CreatorRevision;␊
} __attribute__((packed));␊
␊
// TODO Migrate␊
struct acpi_2_fadt {␊
␉char Signature[4];␊
␉uint32_t Length;␊
␉uint8_t Revision;␊
␉uint8_t Checksum;␊
␉char OEMID[6];␊
␉char OEMTableId[8];␊
␉uint32_t OEMRevision;␊
␉uint32_t CreatorId;␊
␉uint32_t CreatorRevision;␊
␉uint32_t FIRMWARE_CTRL;␊
␉uint32_t DSDT;␊
␉uint8_t Model;␉␉␉// JrCs␊
␉uint8_t PM_Profile;␉␉// JrCs␊
struct acpi_2_fadt␊
{␊
␉char␉␉␉Signature[4];␊
␉uint32_t␉␉Length;␊
␉uint8_t␉␉␉Revision;␊
␉uint8_t␉␉␉Checksum;␊
␉char␉␉␉OEMID[6];␊
␉char␉␉␉OEMTableId[8];␊
␉uint32_t␉␉OEMRevision;␊
␉uint32_t␉␉CreatorId;␊
␉uint32_t␉␉CreatorRevision;␊
␉uint32_t␉␉FIRMWARE_CTRL;␊
␉uint32_t␉␉DSDT;␊
␉uint8_t␉␉␉Model;␉␉␉// JrCs␊
␉uint8_t␉␉␉PM_Profile;␉␉// JrCs␊
␉uint16_t␉␉SCI_Interrupt;␊
␉uint32_t␉␉SMI_Command_Port;␊
␉uint8_t␉␉␉ACPI_Enable;␊
trunk/i386/modules/Resolution/915resolution.c
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{␉␉␊
␉UInt32 x = 0, y = 0, bp = 0;␊
␉␊
␉verbose("Resolution:\n");␊
␉getResolution(&x, &y, &bp);␊
␉verbose("getResolution: %dx%dx%d\n", (int)x, (int)y, (int)bp);␊
␉␊
␉if (x != 0 &&␊
␉␉y != 0 && ␊
␉␉␉type = CT_GM45;␊
␉␉␉break;␊
␉␉␉␊
␉␉␉//␊
␉␉␉// Core processors␊
␉␉␉// http://pci-ids.ucw.cz/read/PC/8086␊
␉␉␉//␊
␉␉case 0x00408086: // Core Processor DRAM Controller␊
␉␉case 0x00448086: // Core Processor DRAM Controller␊
␉␉case 0x00488086: // Core Processor DRAM Controller␊
␉␉case 0x00698086: // Core Processor DRAM Controller␊
␉␉␉␊
␉␉case 0x01008086: // 2nd Generation Core Processor Family DRAM Controller␊
␉␉case 0x01048086: // 2nd Generation Core Processor Family DRAM Controller␊
␉␉case 0x01088086: // Xeon E3-1200 2nd Generation Core Processor Family DRAM Controller␊
␉␉case 0x010c8086: // Xeon E3-1200 2nd Generation Core Processor Family DRAM Controller␊
␉␉␉␊
␉␉case 0x01508086: // 3rd Generation Core Processor Family DRAM Controller␊
␉␉case 0x01548086: // 3rd Generation Core Processor Family DRAM Controller␊
␉␉case 0x01588086: // 3rd Generation Core Processor Family DRAM Controller␊
␉␉case 0x015c8086: // 3rd Generation Core Processor Family DRAM Controller␊
␉␉␉verbose(" core proc identified\n");␊
␉␉␉type = CT_CORE_PROC;␊
␉␉␉break;␊
␉␉␉␊
␉␉␉␊
␉␉default:␊
␉␉␉if((id & 0x0000FFFF) == 0x00008086) // Intel chipset␊
␉␉␉{␊
␉␊
␉if (map->chipset == CT_UNKNOWN)␊
␉{␊
␉␉//verbose("Unknown chipset type.\n");␊
␉␉verbose(" Unknown chipset type: %08x.\n", map->chipset_id);␊
␉␉//verbose("915resolution only works with Intel 800/900 series graphic chipsets.\n");␊
␉␉//verbose("Chipset Id: %x\n", map->chipset_id);␊
␉␉close_vbios(map);␊
␉␉return 0;␊
␉} else {␊
␉␉verbose(" Detected chipset/proc id (DRAM controller): %08x\n", map->chipset_id);␊
␉}␊
␉␊
␉␊
␉verbose(" VBios: ");␊
␉/*␊
␉ * Map the video bios to memory␊
␉ */␊
␉map->ati_tables.AtomRomHeader = (ATOM_ROM_HEADER *) (map->bios_ptr + *(unsigned short *) (map->bios_ptr + OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER)); ␊
␉if (strcmp ((char *) map->ati_tables.AtomRomHeader->uaFirmWareSignature, "ATOM") == 0)␊
␉{␊
␉␉verbose("ATI");␊
␉␉// ATI Radeon Card␊
␉␉map->bios = BT_ATI_1;␊
␉␉␊
␉␉␊
␉␉if (!detect_ati_bios_type(map)) map->bios = BT_ATI_2;␊
␉␉␊
␉␉if (map->bios == BT_ATI_1) {␊
␉␉␉verbose(", BT_ATI_1\n");␊
␉␉} else {␊
␉␉␉verbose(", BT_ATI_2\n");␊
␉␉}␊
␉}␊
␉else {␊
␉␉␊
␉␉␉␉&& (map->bios_ptr[i+2] == 'I') ␊
␉␉␉␉&& (map->bios_ptr[i+3] == 'D')) ␊
␉␉␉{␊
␉␉␉␉verbose("nVidia\n");␊
␉␉␉␉map->bios = BT_NVDA;␊
␉␉␉␉unsigned short nv_data_table_offset = 0;␊
␉␉␉␉unsigned short * nv_data_table;␊
␉/*␊
␉ * Figure out where the mode table is ␊
␉ */␊
␉if ((map->bios != BT_ATI_1) && (map->bios != BT_NVDA)) ␊
␉if ((map->bios != BT_ATI_1) && (map->bios != BT_ATI_2) && (map->bios != BT_NVDA)) ␊
␉{␊
␉␉char* p = map->bios_ptr + 16;␊
␉␉char* limit = map->bios_ptr + VBIOS_SIZE - (3 * sizeof(vbios_mode));␊
␉␉␊
␉␉verbose("Other");␊
␉␉while (p < limit && map->mode_table == 0)␊
␉␉{␊
␉␉␉vbios_mode * mode_ptr = (vbios_mode *) p;␊
␉␉if (detect_bios_type(map, TRUE, sizeof(vbios_modeline_type3)))␊
␉␉{␊
␉␉␉map->bios = BT_3;␊
␉␉␉verbose(", BT_3\n");␊
␉␉}␊
␉␉else if (detect_bios_type(map, TRUE, sizeof(vbios_modeline_type2)))␊
␉␉{␊
␉␉␉map->bios = BT_2;␊
␉␉␉verbose(", BT_2\n");␊
␉␉}␊
␉␉else if (detect_bios_type(map, FALSE, sizeof(vbios_resolution_type1)))␊
␉␉{␊
␉␉␉map->bios = BT_1;␊
␉␉␉verbose(", BT_1\n");␊
␉␉}␊
␉␉else {␊
␉␉␉verbose(" - unknown\n");␊
␉␉␉return 0;␊
␉␉}␊
␉}␊
␉␉case CT_G31:␊
␉␉case CT_500:␊
␉␉case CT_3150:␊
␉␉case CT_UNKNOWN_INTEL:␉// Assume newer intel chipset is the same as before␊
␉␉␉outl(CONFIG_MECH_ONE_ADDR, 0x80000090);␊
␉␉␉map->b1 = inb(CONFIG_MECH_ONE_DATA + 1);␊
␉␉␉map->b2 = inb(CONFIG_MECH_ONE_DATA + 2);␊
␉␉␉outb(CONFIG_MECH_ONE_DATA + 1, 0x33);␊
␉␉␉outb(CONFIG_MECH_ONE_DATA + 2, 0x33);␊
␉␉␉break;␊
␉␉case CT_CORE_PROC:␉ // Core procs - PAM regs are 80h - 86h␊
␉␉case CT_UNKNOWN_INTEL:␉// Assume newer intel chipset is the same as before␊
␉␉␉outl(CONFIG_MECH_ONE_ADDR, 0x80000080);␊
␉␉␉map->b1 = inb(CONFIG_MECH_ONE_DATA + 1);␊
␉␉␉map->b2 = inb(CONFIG_MECH_ONE_DATA + 2);␊
␉␉␉outl(CONFIG_MECH_ONE_ADDR, 0x80000080);␊
␉␉␉outb(CONFIG_MECH_ONE_DATA + 1, 0x33);␊
␉␉␉outb(CONFIG_MECH_ONE_DATA + 2, 0x33);␊
␉␉␉break;␊
␉}␊
␉␊
#if DEBUG␊
␉␉case CT_G31:␊
␉␉case CT_500:␊
␉␉case CT_3150:␊
␉␉case CT_UNKNOWN_INTEL:␊
␉␉␉outl(CONFIG_MECH_ONE_ADDR, 0x80000090);␊
␉␉␉outb(CONFIG_MECH_ONE_DATA + 1, map->b1);␊
␉␉␉outb(CONFIG_MECH_ONE_DATA + 2, map->b2);␊
␉␉␉break;␊
␉␉case CT_CORE_PROC:␊
␉␉case CT_UNKNOWN_INTEL:␊
␉␉␉outl(CONFIG_MECH_ONE_ADDR, 0x80000080);␊
␉␉␉outb(CONFIG_MECH_ONE_DATA + 1, map->b1);␊
␉␉␉outb(CONFIG_MECH_ONE_DATA + 2, map->b2);␊
␉␉␉break;␊
␉}␊
␉␊
#if DEBUG␊
␉␉␉␊
␉if(!edidInfo) return 1;␊
//Slice␊
␉if(!fb_parse_edid((struct EDID *)edidInfo, mode)) ␊
␉if(!fb_parse_edid((struct EDID *)edidInfo, mode) || !mode->h_active) ␊
␉{␊
␉␉free( edidInfo );␊
␉␉return 1;␊
␉␉␊
␉free( edidInfo );␊
␉␉␊
␉if(!mode->h_active) return 1;␊
␉␊
␉return 0;␊
␉␉␊
}␊
␉␊
␉//␉for (i=0; i < map->mode_table_size; i++) {␊
␉//␉␉if (map->mode_table[0].mode == mode) {␊
␉verbose(" Patching: ");␊
␉switch(map->bios) {␊
␉␉case BT_INTEL:␊
␉␉␉verbose("BT_INTEL - not supported\n");␊
␉␉␉return;␊
␊
␉␉case BT_1:␊
␉␉{␊
␉␉␉verbose("BT_1 patched.\n");␊
␉␉␉vbios_resolution_type1 * res = map_type1_resolution(map, map->mode_table[i].resolution);␊
␉␉␉␊
␉␉␉if (bp) {␊
␉␉␉␉␉␉modeline->vtotal = modeline->vblank;␊
␉␉␉␉}␊
␉␉␉}␊
␉␉␉verbose("BT_1 patched.\n");␊
␉␉␉break;␊
␉␉}␊
␉␉case BT_3:␊
␉␉␉␉␉modeline->timing_v = x-1;␊
␉␉␉␉}␊
␉␉␉}␊
␉␉␉verbose("BT_3 patched.\n");␊
␉␉␉break;␊
␉␉}␊
␉␉case BT_ATI_1:␊
␉␉{␊
␉␉␉verbose("BT_ATI_1");␊
␉␉␉edid_mode mode;␊
␉␉␉␉␊
␉␉␉ATOM_MODE_TIMING *mode_timing = (ATOM_MODE_TIMING *) map->ati_mode_table;␊
␊
␉␉␉//if (mode.pixel_clock && (mode.h_active == x) && (mode.v_active == y) && !force) {␊
␉␉␉if (!getMode(&mode)) {␊
␉␉␉␉verbose("\n Edid detailed timing descriptor found: %dx%d\n vbios mode 0 patched!\n", mode.h_active, mode.v_active);␊
␉␉␉␉mode_timing->usCRTC_H_Total = mode.h_active + mode.h_blanking;␊
␉␉␉␉mode_timing->usCRTC_H_Disp = mode.h_active;␊
␉␉␉␉mode_timing->usCRTC_H_SyncStart = mode.h_active + mode.h_sync_offset;␊
␉␉␉␉mode_timing->usCRTC_V_SyncWidth = mode.v_sync_width;␊
␊
␉␉␉␉mode_timing->usPixelClock = mode.pixel_clock;␊
␉␉␉} else {␊
␉␉␉␉verbose(" Edid not found or invalid - vbios not patched!\n");␊
␉␉␉}␊
␉␉␉/*else␊
␉␉␉{␊
␉␉}␊
␉␉case BT_ATI_2:␊
␉␉{␊
␉␉␉verbose("BT_ATI_2");␊
␉␉␉edid_mode mode;␊
␉␉␉␉␉␉␊
␉␉␉ATOM_DTD_FORMAT *mode_timing = (ATOM_DTD_FORMAT *) map->ati_mode_table;␊
␉␉␉␊
␉␉␉/*if (mode.pixel_clock && (mode.h_active == x) && (mode.v_active == y) && !force) {*/␊
␉␉␉if (!getMode(&mode)) {␊
␉␉␉␉verbose("\n Edid detailed timing descriptor found: %dx%d\n vbios mode 0 patched!\n", mode.h_active, mode.v_active);␊
␉␉␉␉mode_timing->usHBlanking_Time = mode.h_blanking;␊
␉␉␉␉mode_timing->usHActive = mode.h_active;␊
␉␉␉␉mode_timing->usHSyncOffset = mode.h_sync_offset;␊
␉␉␉␉mode_timing->usVSyncWidth = mode.v_sync_width;␊
␉␉␉␉␉␉␉␉␉␉␊
␉␉␉␉mode_timing->usPixClk = mode.pixel_clock;␊
␉␉␉} else {␊
␉␉␉␉verbose(" Edid not found or invalid - vbios not patched!\n");␊
␉␉␉}␊
␉␉␉/*else␊
␉␉␉{␊
␉␉}␊
␉␉case BT_NVDA:␊
␉␉{␊
␉␉␉verbose("BT_NVDA");␊
␉␉␉edid_mode mode;␊
␉␉␉␊
␉␉␉NV_MODELINE *mode_timing = (NV_MODELINE *) map->nv_mode_table;␊
␉␉␉␊
␉␉␉/*if (mode.pixel_clock && (mode.h_active == x) && (mode.v_active == y) && !force) {*/␊
␉␉␉if (!getMode(&mode)) {␊
␉␉␉␉verbose("\n Edid detailed timing descriptor found: %dx%d\n vbios mode %d patched!\n", mode.h_active, mode.v_active, i);␊
␉␉␉␉mode_timing[i].usH_Total = mode.h_active + mode.h_blanking;␊
␉␉␉␉mode_timing[i].usH_Active = mode.h_active;␊
␉␉␉␉mode_timing[i].usH_SyncStart = mode.h_active + mode.h_sync_offset;␊
␉␉␉␉mode_timing[i].usV_SyncEnd = mode.v_active + mode.v_sync_offset + mode.v_sync_width;␊
␉␉␉␉␊
␉␉␉␉mode_timing[i].usPixel_Clock = mode.pixel_clock;␊
␉␉␉} else {␊
␉␉␉␉verbose(" Edid not found or invalid - vbios not patched!\n");␊
␉␉␉}␊
␉␉␉/*else␊
␉␉␉ {␊
␉␉}␊
␉␉case BT_UNKNOWN:␊
␉␉{␊
␉␉␉verbose(" Unknown - vbios not patched\n");␊
␉␉␉break;␊
␉␉}␊
␉}␊
trunk/i386/modules/Resolution/edid.c
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......
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......
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␉int i;␊
␉unsigned char *block;␊
␉␊
␉if(!verifyEDID((unsigned char *)edid)) return 1;␊
␉if(!verifyEDID((unsigned char *)edid)) return 0;␊
␉␊
␉block = (unsigned char *)edid + DETAILED_TIMING_DESCRIPTIONS_START; //54␊
␉␊
␉␉␉var->h_blanking = H_BLANKING;␊
␉␉␉var->v_blanking = V_BLANKING;␊
␉␉␉var->pixel_clock = PIXEL_CLOCK;␊
␉␉␉var->h_sync_width = H_SYNC_WIDTH;␊
␉␉␉var->v_sync_offset = V_SYNC_OFFSET;␊
␉␉␉var->v_sync_width = V_SYNC_WIDTH;␊
␉␉␉/*␊
␉␉␉var->xres = var->xres_virtual = H_ACTIVE;␊
␉␉char* edidInfo = readEDID();␊
␉␉␊
␉␉if(!edidInfo) return;␊
␉␉␊
␉␉edid_mode mode;␊
␉␉// TODO: check *all* resolutions reported and either use the highest, or the native resolution (if there is a flag for that)␊
␉␉//xResolution = edidInfo[56] | ((edidInfo[58] & 0xF0) << 4); ␊
␊
␉␉status = getEDID(edidInfo, blocks_left);␊
␉␉␊
␉␉␊
␉␉/*␊
␉␉msglog("Buffer location: 0x%X status: %d\n", SEG(edidInfo) << 16 | OFF(edidInfo), status);␊
␉␉␊
␉␉int j, i;␊
␉␉for (j = 0; j < 8; j++) {␊
␉␉␉for(i = 0; i < 16; i++) msglog("0x%02X ", edidInfo[((i+1) * (j + 1)) - 1]);␊
␉␉␉for(i = 0; i < 16; i++) msglog(" 0x%02X", edidInfo[((i+1) * (j + 1)) - 1]);␊
␉␉␉msglog("\n");␊
␉␉}␊
␉␉*/␊
␉␉␊
␉␉␊
␉␉␊
␉␉if(status == 0)␊
␉␉{␊
␉␉␉//if( edidInfo[0] == 0x00 || edidInfo[0] == 0xFF)␊
␉␉␉␉␉)␊
␉␉␉␉{␊
␉␉␉␉␉msglog("Last reported %d\n", last_reported);␊
␉␉␉␉␉msglog( "EDID blocks left is wrong.\n"␊
␉␉␉␉␉msglog("EDID blocks left is wrong.\n"␊
␉␉␉␉␉␉ "Your EDID is probably invalid.\n");␊
␉␉␉␉␉return 0;␊
␉␉␉␉}␊
trunk/i386/modules/Resolution/915resolution.h
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␉CT_915G, CT_915GM, CT_945G, CT_945GM, CT_945GME, CT_946GZ, ␊
␉CT_955X, CT_G965, CT_Q965, CT_965GM, CT_975X, ␊
␉CT_P35, CT_X48, CT_B43, CT_Q45, CT_P45,␊
␉CT_GM45, CT_G41, CT_G31, CT_G45, CT_500, CT_3150␊
␉CT_GM45, CT_G41, CT_G31, CT_G45, CT_500, CT_3150,␊
␉CT_CORE_PROC␊
} chipset_type;␊
␊
␊

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