Chameleon

Chameleon Commit Details

Date:2011-05-26 03:31:15 (8 years 2 months ago)
Author:Azimutz
Commit:879
Parents: 878
Message:Merge trunk (r876,877).
Changes:
M/branches/azimutz/Chazi/i386/modules/Memory/Memory.c
M/branches/azimutz/Chazi/i386/modules/Memory/dram_controllers.c
M/branches/azimutz/Chazi/i386/libsaio/smbios.c

File differences

branches/azimutz/Chazi/i386/libsaio/smbios.c
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uint8_t *stringPtr = (uint8_t *)structHeader + structHeader->length;
if (!field)
return (char *)0;
return NULL;
for (field--; field != 0 && strlen((char *)stringPtr) > 0;
field--, stringPtr = (uint8_t *)((uint32_t)stringPtr + strlen((char *)stringPtr) + 1));
strSize = strlen(string);
// remove any spaces found at the end
while (string[strSize - 1] == ' ')
while ((strSize != 0) && (string[strSize - 1] == ' '))
strSize--;
memcpy((uint8_t *)structHeader + structHeader->length + stringsSize, string, strSize);
memcpy((void *)structPtr->new, structPtr->orig, structPtr->orig->length);
for (i = 0; i < numOfSetters; i++)
if (structPtr->orig->type == SMBSetters[i].type)
if ((structPtr->orig->type == SMBSetters[i].type) && (SMBSetters[i].fieldOffset < structPtr->orig->length))
{
if (SMBSetters[i].fieldOffset > structPtr->orig->length)
continue;
setterFound = true;
setSMBValue(structPtr, i, (returnType *)((uint8_t *)structPtr->new + SMBSetters[i].fieldOffset));
}
branches/azimutz/Chazi/i386/modules/Memory/Memory.c
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void Memory_PCIDevice_hook(void* arg1, void* arg2, void* arg3, void* arg4)
{
pci_dt_t* current = arg1;
if(current->class_id == PCI_CLASS_BRIDGE_HOST)
if (current->class_id == PCI_CLASS_BRIDGE_HOST
&& (current->dev.addr == PCIADDR(0, 0, 0))
{
dram_controller_dev = current;
}
branches/azimutz/Chazi/i386/modules/Memory/dram_controllers.c
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// First, locate the PCI bus where the MCH is located
for(i = 0; i < sizeof(possible_nhm_bus); i++)
{
vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x00);
did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x02);
vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), PCI_VENDOR_ID);
did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), PCI_DEVICE_ID);
vid &= 0xFFFF;
did &= 0xFF00;
{
case 0: mch_fsb = 1066; break;
case 1: mch_fsb = 533; break;
default:
default:
case 2: mch_fsb = 800; break;
case 3: mch_fsb = 667; break;
case 4: mch_fsb = 1333; break;
// Default unknown chipset
{ 0, 0, "",NULL, NULL, NULL },
// Intel
{ 0x8086, 0x7190, "VMWare",NULL, NULL, NULL },
{ 0x8086, 0x1A30, "i845",NULL, NULL, NULL },
{ 0x8086, 0x2970, "i946PL/GZ",setup_p35, get_fsb_i965, get_timings_i965 },
{ 0x8086, 0x2990, "Q963/Q965",setup_p35, get_fsb_i965, get_timings_i965 },
{ 0x8086, 0x29A0, "P965/G965",setup_p35, get_fsb_i965, get_timings_i965 },
{ 0x8086, 0x2A00, "GM965/GL960",setup_p35, get_fsb_im965, get_timings_im965 },
{ 0x8086, 0x2970, "i946PL/GZ",setup_p35, get_fsb_i965, get_timings_i965},
{ 0x8086, 0x2990, "Q963/Q965",setup_p35, get_fsb_i965, get_timings_i965},
{ 0x8086, 0x29A0, "P965/G965",setup_p35, get_fsb_i965, get_timings_i965},
{ 0x8086, 0x2A00, "GM965/GL960",setup_p35, get_fsb_im965, get_timings_im965},
{ 0x8086, 0x2A10, "GME965/GLE960",setup_p35, get_fsb_im965, get_timings_im965 },
{ 0x8086, 0x2A40, "PM/GM45/47",setup_p35, get_fsb_im965, get_timings_im965 },
{ 0x8086, 0x29B0, "Q35",setup_p35, get_fsb_i965, get_timings_p35 },
{ 0x8086, 0x29C0, "P35/G33",setup_p35, get_fsb_i965, get_timings_p35 },
{ 0x8086, 0x29D0, "Q33",setup_p35, get_fsb_i965, get_timings_p35 },
{ 0x8086, 0x29E0, "X38/X48",setup_p35, get_fsb_i965, get_timings_p35 },
{ 0x8086, 0x2E00, "Eaglelake",setup_p35, get_fsb_i965, get_timings_p35 },
{ 0x8086, 0x2E10, "Q45/Q43",setup_p35, get_fsb_i965, get_timings_p35 },
{ 0x8086, 0x2E20, "P45/G45",setup_p35, get_fsb_i965, get_timings_p35 },
{ 0x8086, 0x2E30, "G41",setup_p35, get_fsb_i965, get_timings_p35 },
{ 0x8086, 0xD131, "NHM IMC",setup_nhm, get_fsb_nhm, get_timings_nhm },
{ 0x8086, 0xD132, "NHM IMC",setup_nhm, get_fsb_nhm, get_timings_nhm },
{ 0x8086, 0x3400, "NHM IMC",setup_nhm, get_fsb_nhm, get_timings_nhm },
{ 0x8086, 0x3401, "NHM IMC",setup_nhm, get_fsb_nhm, get_timings_nhm },
{ 0x8086, 0x3402, "NHM IMC",setup_nhm, get_fsb_nhm, get_timings_nhm },
{ 0x8086, 0x3403, "NHM IMC",setup_nhm, get_fsb_nhm, get_timings_nhm },
{ 0x8086, 0x3404, "NHM IMC",setup_nhm, get_fsb_nhm, get_timings_nhm },
{ 0x8086, 0x3405, "NHM IMC",setup_nhm, get_fsb_nhm, get_timings_nhm },
{ 0x8086, 0x3406, "NHM IMC",setup_nhm, get_fsb_nhm, get_timings_nhm },
{ 0x8086, 0x3407, "NHM IMC",setup_nhm, get_fsb_nhm, get_timings_nhm },
{ 0x8086, 0x29B0, "Q35",setup_p35, get_fsb_i965, get_timings_p35},
{ 0x8086, 0x29C0, "P35/G33",setup_p35, get_fsb_i965, get_timings_p35},
{ 0x8086, 0x29D0, "Q33",setup_p35, get_fsb_i965, get_timings_p35},
{ 0x8086, 0x29E0, "X38/X48",setup_p35, get_fsb_i965, get_timings_p35},
{ 0x8086, 0x2E00, "Eaglelake",setup_p35, get_fsb_i965, get_timings_p35},
{ 0x8086, 0x2E10, "Q45/Q43",setup_p35, get_fsb_i965, get_timings_p35},
{ 0x8086, 0x2E20, "P45/G45",setup_p35, get_fsb_i965, get_timings_p35},
{ 0x8086, 0x2E30, "G41",setup_p35, get_fsb_i965, get_timings_p35},
{ 0x8086, 0xD131, "NHM IMC",setup_nhm, get_fsb_nhm, get_timings_nhm},
{ 0x8086, 0xD132, "NHM IMC",setup_nhm, get_fsb_nhm, get_timings_nhm},
{ 0x8086, 0x3400, "NHM IMC",setup_nhm, get_fsb_nhm, get_timings_nhm},
{ 0x8086, 0x3401, "NHM IMC",setup_nhm, get_fsb_nhm, get_timings_nhm},
{ 0x8086, 0x3402, "NHM IMC",setup_nhm, get_fsb_nhm, get_timings_nhm},
{ 0x8086, 0x3403, "NHM IMC",setup_nhm, get_fsb_nhm, get_timings_nhm},
{ 0x8086, 0x3404, "NHM IMC",setup_nhm, get_fsb_nhm, get_timings_nhm},
{ 0x8086, 0x3405, "NHM IMC",setup_nhm, get_fsb_nhm, get_timings_nhm},
{ 0x8086, 0x3406, "NHM IMC",setup_nhm, get_fsb_nhm, get_timings_nhm},
{ 0x8086, 0x3407, "NHM IMC",setup_nhm, get_fsb_nhm, get_timings_nhm}
};
static const char *memory_channel_types[] =

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Revision: 879