Chameleon Commit Details - 907 - Chameleon open source boot loader project.

Date:

2011-05-29 02:19:00 (12 years 10 months ago)

Author:

Evan Lojewski

Commit:

907

Parents:

906

Message:

Fixed insta-reboot on Atom cpu's - MSR 0x35 does not exist, which causes an interrupt to run, and since we don't have an idt installed... instant reboot. TODO: add an idt, would make debugging easier...

Changes:

M	/trunk/i386/libsaio/cpu.c
M	/trunk/i386/libsaio/cpu.h

File differences

-136
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+␉␊
    p->CPU.Model += (p->CPU.ExtModel << 4);␊
    ␊
    if (p->CPU.Vendor == 0x756E6547 /* Intel */ && p->CPU.Family == 0x06 && p->CPU.Model >= 0x1a){␊
    if (p->CPU.Vendor == 0x756E6547 /* Intel */ && ␊
        p->CPU.Family == 0x06 && ␊
        p->CPU.Model >= CPUID_MODEL_PENRYN && ␊
        p->CPU.Model != CPUID_MODEL_ATOM        // MSR is *NOT* available on the Intel Atom CPU␊
        ){␊
        msr = rdmsr64(MSR_CORE_THREAD_COUNT);␉␉␉␉␉␉␉␉␉// Undocumented MSR in Nehalem and newer CPUs␊
        p->CPU.NoCores␉␉= bitfield((uint32_t)msr, 31, 16);␉␉␉␉␉// Using undocumented MSR to get actual values␊
        p->CPU.NoThreads␉= bitfield((uint32_t)msr, 15,  0);␉␉␉␉␉// Using undocumented MSR to get actual values␊
 ␉␊
     p->CPU.Model += (p->CPU.ExtModel << 4);␊
     ␊
-    if (p->CPU.Vendor == 0x756E6547 /* Intel */ && p->CPU.Family == 0x06 && p->CPU.Model >= 0x1a){␊
+    if (p->CPU.Vendor == 0x756E6547 /* Intel */ && ␊
+        p->CPU.Family == 0x06 && ␊
+        p->CPU.Model >= CPUID_MODEL_PENRYN && ␊
+        p->CPU.Model != CPUID_MODEL_ATOM        // MSR is *NOT* available on the Intel Atom CPU␊
+        ){␊
         msr = rdmsr64(MSR_CORE_THREAD_COUNT);␉␉␉␉␉␉␉␉␉// Undocumented MSR in Nehalem and newer CPUs␊
         p->CPU.NoCores␉␉= bitfield((uint32_t)msr, 31, 16);␉␉␉␉␉// Using undocumented MSR to get actual values␊
         p->CPU.NoThreads␉= bitfield((uint32_t)msr, 15,  0);␉␉␉␉␉// Using undocumented MSR to get actual values␊

-36
37 37
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+#define CALIBRATE_TIME_MSEC␉30␉␉/* 30 msecs */␊
#define CALIBRATE_LATCH␉␉((CLKNUM * CALIBRATE_TIME_MSEC + 1000/2)/1000)␊
␊
// CPUID Values␊
#define CPUID_MODEL_YONAH␉14␊
#define CPUID_MODEL_MEROM␉15␊
#define CPUID_MODEL_PENRYN␉23␊
#define CPUID_MODEL_NEHALEM␉26␊
#define CPUID_MODEL_ATOM    28␊
#define CPUID_MODEL_FIELDS␉30␉/* Lynnfield, Clarksfield, Jasper */␊
#define CPUID_MODEL_DALES␉31␉/* Havendale, Auburndale */␊
#define CPUID_MODEL_NEHALEM_EX␉46␊
#define CPUID_MODEL_DALES_32NM␉37␉/* Clarkdale, Arrandale */␊
#define CPUID_MODEL_WESTMERE␉44␉/* Gulftown, Westmere-EP, Westmere-WS */␊
#define CPUID_MODEL_WESTMERE_EX␉47␊
␊
␊
static inline uint64_t rdtsc64(void)␊
{␊
␉uint64_t ret;␊
 #define CALIBRATE_TIME_MSEC␉30␉␉/* 30 msecs */␊
 #define CALIBRATE_LATCH␉␉((CLKNUM * CALIBRATE_TIME_MSEC + 1000/2)/1000)␊
 ␊
+// CPUID Values␊
+#define CPUID_MODEL_YONAH␉14␊
+#define CPUID_MODEL_MEROM␉15␊
+#define CPUID_MODEL_PENRYN␉23␊
+#define CPUID_MODEL_NEHALEM␉26␊
+#define CPUID_MODEL_ATOM    28␊
+#define CPUID_MODEL_FIELDS␉30␉/* Lynnfield, Clarksfield, Jasper */␊
+#define CPUID_MODEL_DALES␉31␉/* Havendale, Auburndale */␊
+#define CPUID_MODEL_NEHALEM_EX␉46␊
+#define CPUID_MODEL_DALES_32NM␉37␉/* Clarkdale, Arrandale */␊
+#define CPUID_MODEL_WESTMERE␉44␉/* Gulftown, Westmere-EP, Westmere-WS */␊
+#define CPUID_MODEL_WESTMERE_EX␉47␊
+␊
+␊
 static inline uint64_t rdtsc64(void)␊
 {␊
 ␉uint64_t ret;␊

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