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1/*␊
2 * Add (c) here␊
3 *␊
4 * Copyright .... All rights reserved.␊
5 *␊
6 */␊
7␊
8#include "smbios_getters.h"␊
9␊
10#ifndef DEBUG_SMBIOS␊
11#define DEBUG_SMBIOS 0␊
12#endif␊
13␊
14#if DEBUG_SMBIOS␊
15#define DBG(x...)␉printf(x)␊
16#else␊
17#define DBG(x...)␊
18#endif␊
19␊
20␊
21bool getProcessorInformationExternalClock(returnType *value)␊
22{␊
23␉value->word = Platform.CPU.FSBFrequency/1000000;␊
24␉return true;␊
25}␊
26␊
27bool getProcessorInformationMaximumClock(returnType *value)␊
28{␊
29␉value->word = Platform.CPU.CPUFrequency/1000000;␊
30␉return true;␊
31}␊
32␊
33bool getSMBOemProcessorBusSpeed(returnType *value)␊
34{␊
35␉if (Platform.CPU.Vendor == 0x756E6547) // Intel␊
36␉{␉␉␊
37␉␉switch (Platform.CPU.Family) ␊
38␉␉{␊
39␉␉␉case 0x06:␊
40␉␉␉{␊
41␉␉␉␉switch (Platform.CPU.Model)␊
42␉␉␉␉{␊
43␉␉␉␉␉case 0x0D:␉␉␉␉␉// ???␊
44␉␉␉␉␉case CPU_MODEL_YONAH:␉␉// Yonah␉␉0x0E␊
45␉␉␉␉␉case CPU_MODEL_MEROM:␉␉// Merom␉␉0x0F␊
46␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉// Penryn␉␉0x17␊
47␉␉␉␉␉case CPU_MODEL_ATOM:␉␉// Atom 45nm␉0x1C␊
48␉␉␉␉␉␉return false;␊
49␊
50␉␉␉␉␉case 0x19:␉␉␉␉␉// ??? Intel Core i5 650 @3.20 GHz ␊
51␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉// Intel Core i7 LGA1366 (45nm)␊
52␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉// Intel Core i5, i7 LGA1156 (45nm)␊
53␉␉␉␉␉case CPU_MODEL_DALES:␉␉// Intel Core i5, i7 LGA1156 (45nm) ???␊
54␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉// Intel Core i3, i5, i7 LGA1156 (32nm)␊
55␉␉␉␉␉case CPU_MODEL_WESTMERE:␉// Intel Core i7 LGA1366 (32nm) 6 Core␊
56␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␉// Intel Core i7 LGA1366 (45nm) 6 Core ???␊
57␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉// Intel Core i7 LGA1366 (45nm) 6 Core ???␊
58␉␉␉␉␉{␊
59␉␉␉␉␉␉// thanks to dgobe for i3/i5/i7 bus speed detection␊
60␉␉␉␉␉␉int nhm_bus = 0x3F;␊
61␉␉␉␉␉␉static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};␊
62␉␉␉␉␉␉unsigned long did, vid;␊
63␉␉␉␉␉␉int i;␊
64␉␉␉␉␉␉␊
65␉␉␉␉␉␉// Nehalem supports Scrubbing␊
66␉␉␉␉␉␉// First, locate the PCI bus where the MCH is located␊
67␉␉␉␉␉␉for(i = 0; i < sizeof(possible_nhm_bus); i++)␊
68␉␉␉␉␉␉{␊
69␉␉␉␉␉␉␉vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x00);␊
70␉␉␉␉␉␉␉did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x02);␊
71␉␉␉␉␉␉␉vid &= 0xFFFF;␊
72␉␉␉␉␉␉␉did &= 0xFF00;␊
73␉␉␉␉␉␉␉␊
74␉␉␉␉␉␉␉if(vid == 0x8086 && did >= 0x2C00)␊
75␉␉␉␉␉␉␉␉nhm_bus = possible_nhm_bus[i]; ␊
76␉␉␉␉␉␉}␊
77␉␉␉␉␉␉␊
78␉␉␉␉␉␉unsigned long qpimult, qpibusspeed;␊
79␉␉␉␉␉␉qpimult = pci_config_read32(PCIADDR(nhm_bus, 2, 1), 0x50);␊
80␉␉␉␉␉␉qpimult &= 0x7F;␊
81␉␉␉␉␉␉DBG("qpimult %d\n", qpimult);␊
82␉␉␉␉␉␉qpibusspeed = (qpimult * 2 * (Platform.CPU.FSBFrequency/1000000));␊
83␉␉␉␉␉␉// Rek: rounding decimals to match original mac profile info␊
84␉␉␉␉␉␉if (qpibusspeed%100 != 0)qpibusspeed = ((qpibusspeed+50)/100)*100;␊
85␉␉␉␉␉␉DBG("qpibusspeed %d\n", qpibusspeed);␊
86␉␉␉␉␉␉value->word = qpibusspeed;␊
87␉␉␉␉␉␉return true;␊
88␉␉␉␉␉}␊
89␉␉␉␉}␊
90␉␉␉}␊
91␉␉}␊
92␉}␊
93␉return false;␊
94}␊
95␊
96uint16_t simpleGetSMBOemProcessorType(void)␊
97{␊
98␉if (Platform.CPU.NoCores >= 4) ␊
99␉{␊
100␉␉return 0x0501;␉// Quad-Core Xeon␊
101␉}␊
102␉else if (Platform.CPU.NoCores == 1) ␊
103␉{␊
104␉␉return 0x0201;␉// Core Solo␊
105␉};␊
106␉␊
107␉return 0x0301;␉␉// Core 2 Duo␊
108}␊
109␊
110bool getSMBOemProcessorType(returnType *value)␊
111{␊
112␉static bool done = false;␉␉␊
113␉␉␊
114␉value->word = simpleGetSMBOemProcessorType();␊
115␊
116␉if (Platform.CPU.Vendor == 0x756E6547) // Intel␊
117␉{␊
118␉␉if (!done)␊
119␉␉{␊
120␉␉␉verbose("CPU is %s, family 0x%x, model 0x%x\n", Platform.CPU.BrandString, Platform.CPU.Family, Platform.CPU.Model);␊
121␉␉␉done = true;␊
122␉␉}␊
123␉␉␊
124␉␉switch (Platform.CPU.Family) ␊
125␉␉{␊
126␉␉␉case 0x06:␊
127␉␉␉{␊
128␉␉␉␉switch (Platform.CPU.Model)␊
129␉␉␉␉{␊
130␉␉␉␉␉case 0x0D:␉␉␉␉␉␉␉// ???␊
131␉␉␉␉␉case CPU_MODEL_YONAH:␉␉␉␉// Intel Mobile Core Solo, Duo␊
132␉␉␉␉␉case CPU_MODEL_MEROM:␉␉␉␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊
133␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉␉␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊
134␉␉␉␉␉case CPU_MODEL_ATOM:␉␉␉␉// Intel Atom (45nm)␊
135␉␉␉␉␉␉return true;␊
136␊
137␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉␉␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
138␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)"))␊
139␉␉␉␉␉␉␉value->word = 0x0501;␉␉␉// Xeon ␊
140␉␉␉␉␉␉else␊
141␉␉␉␉␉␉␉value->word = 0x0701;␉␉␉// Core i7␊
142␉␉␉␉␉␉return true;␊
143␊
144␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉␉␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
145␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊
146␉␉␉␉␉␉␉value->word = 0x601;␉␉// Core i5␊
147␉␉␉␉␉␉else␊
148␉␉␉␉␉␉␉value->word = 0x0701;␉␉// Core i7␊
149␉␉␉␉␉␉return true;␊
150␊
151␉␉␉␉␉case CPU_MODEL_DALES:␉␉␉␉// Havendale, Auburndale␊
152␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊
153␉␉␉␉␉␉␉value->word = 0x601;␉␉// Core i5␊
154␉␉␉␉␉␉else␊
155␉␉␉␉␉␉␉value->word = 0x0701;␉␉// Core i7␊
156␉␉␉␉␉␉return true;␊
157␊
158␉␉␉␉␉case CPU_MODEL_SANDY:␉␉␉␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊
159 case CPU_MODEL_SANDY_XEON:␉␉␉// Intel Xeon E3␊
160␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉␉␉// Intel Core i3, i5 LGA1156 (32nm)␊
161␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3"))␊
162␉␉␉␉␉␉␉value->word = 0x901;␉␉// Core i3␊
163␉␉␉␉␉␉else␊
164␉␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊
165␉␉␉␉␉␉␉␉value->word = 0x601;␉// Core i5␊
166␉␉␉␉␉␉␉else␊
167␉␉␉␉␉␉␉␉value->word = 0x0701;␉// Core i7␊
168␉␉␉␉␉␉return true;␊
169␊
170␉␉␉␉␉case CPU_MODEL_WESTMERE:␉␉␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
171␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉␉␉// Intel Xeon E7␊
172␉␉␉␉␉␉value->word = 0x0501;␉␉␉// Core i7␊
173␉␉␉␉␉␉return true;␊
174␊
175␉␉␉␉␉case 0x19:␉␉␉␉␉␉␉// ??? Intel Core i5 650 @3.20 GHz␊
176␉␉␉␉␉␉value->word = 0x601;␉␉␉// Core i5␊
177␉␉␉␉␉␉return true;␊
178␉␉␉␉}␊
179␉␉␉}␊
180␉␉}␊
181␉}␊
182␉␊
183␉return false;␊
184}␊
185␊
186bool getSMBMemoryDeviceMemoryType(returnType *value)␊
187{␊
188␉static int idx = -1;␊
189␉int␉map;␊
190␊
191␉idx++;␊
192␉if (idx < MAX_RAM_SLOTS)␊
193␉{␊
194␉␉map = Platform.DMI.DIMM[idx];␊
195␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Type != 0)␊
196␉␉{␊
197␉␉␉DBG("RAM Detected Type = %d\n", Platform.RAM.DIMM[map].Type);␊
198␉␉␉value->byte = Platform.RAM.DIMM[map].Type;␊
199␉␉␉return true;␊
200␉␉}␊
201␉}␊
202␉␊
203␉return false;␊
204//␉value->byte = SMB_MEM_TYPE_DDR2;␊
205//␉return true;␊
206}␊
207␊
208bool getSMBMemoryDeviceMemorySpeed(returnType *value)␊
209{␊
210␉static int idx = -1;␊
211␉int␉map;␊
212␊
213␉idx++;␊
214␉if (idx < MAX_RAM_SLOTS)␊
215␉{␊
216␉␉map = Platform.DMI.DIMM[idx];␊
217␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Frequency != 0)␊
218␉␉{␊
219␉␉␉DBG("RAM Detected Freq = %d Mhz\n", Platform.RAM.DIMM[map].Frequency);␊
220␉␉␉value->dword = Platform.RAM.DIMM[map].Frequency;␊
221␉␉␉return true;␊
222␉␉}␊
223␉}␊
224␊
225␉return false;␊
226//␉value->dword = 800;␊
227//␉return true;␊
228}␊
229␊
230bool getSMBMemoryDeviceManufacturer(returnType *value)␊
231{␊
232␉static int idx = -1;␊
233␉int␉map;␊
234␊
235␉idx++;␊
236␉if (idx < MAX_RAM_SLOTS)␊
237␉{␊
238␉␉map = Platform.DMI.DIMM[idx];␊
239␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].Vendor) > 0)␊
240␉␉{␊
241␉␉␉DBG("RAM Detected Vendor[%d]='%s'\n", idx, Platform.RAM.DIMM[map].Vendor);␊
242␉␉␉value->string = Platform.RAM.DIMM[map].Vendor;␊
243␉␉␉return true;␊
244␉␉}␊
245␉}␊
246␊
247␉return false;␊
248//␉value->string = NOT_AVAILABLE;␊
249//␉return true;␊
250}␊
251␉␊
252bool getSMBMemoryDeviceSerialNumber(returnType *value)␊
253{␊
254␉static int idx = -1;␊
255␉int␉map;␊
256␊
257␉idx++;␊
258␉if (idx < MAX_RAM_SLOTS)␊
259␉{␊
260␉␉map = Platform.DMI.DIMM[idx];␊
261␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].SerialNo) > 0)␊
262␉␉{␊
263␉␉␉DBG("map=%d, RAM Detected SerialNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].SerialNo);␊
264␉␉␉value->string = Platform.RAM.DIMM[map].SerialNo;␊
265␉␉␉return true;␊
266␉␉}␊
267␉}␊
268␊
269␉return false;␊
270//␉value->string = NOT_AVAILABLE;␊
271//␉return true;␊
272}␊
273␊
274bool getSMBMemoryDevicePartNumber(returnType *value)␊
275{␊
276␉static int idx = -1;␊
277␉int␉map;␊
278␊
279␉idx++;␊
280␉if (idx < MAX_RAM_SLOTS)␊
281␉{␊
282␉␉map = Platform.DMI.DIMM[idx];␊
283␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].PartNo) > 0)␊
284␉␉{␊
285␉␉␉DBG("map=%d, RAM Detected PartNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].PartNo);␊
286␉␉␉value->string = Platform.RAM.DIMM[map].PartNo;␊
287␉␉␉return true;␊
288␉␉}␊
289␉}␊
290␊
291␉return false;␊
292//␉value->string = NOT_AVAILABLE;␊
293//␉return true;␊
294}␊
295␊
296␊
297// getting smbios addr with fast compare ops, late checksum testing ...␊
298#define COMPARE_DWORD(a,b) ( *((uint32_t *) a) == *((uint32_t *) b) )␊
299static const char * const SMTAG = "_SM_";␊
300static const char* const DMITAG = "_DMI_";␊
301␊
302SMBEntryPoint *getAddressOfSmbiosTable(void)␊
303{␊
304␉SMBEntryPoint␉*smbios;␊
305␉/* ␊
306␉ * The logic is to start at 0xf0000 and end at 0xfffff iterating 16 bytes at a time looking␊
307␉ * for the SMBIOS entry-point structure anchor (literal ASCII "_SM_").␊
308␉ */␊
309␉smbios = (SMBEntryPoint*)SMBIOS_RANGE_START;␊
310␉while (smbios <= (SMBEntryPoint *)SMBIOS_RANGE_END) {␊
311␉␉if (COMPARE_DWORD(smbios->anchor, SMTAG) && ␊
312␉␉␉COMPARE_DWORD(smbios->dmi.anchor, DMITAG) &&␊
313␉␉␉smbios->dmi.anchor[4] == DMITAG[4] &&␊
314␉␉␉checksum8(smbios, sizeof(SMBEntryPoint)) == 0)␊
315␉ {␊
316␉␉␉return smbios;␊
317␉ }␊
318␉␉smbios = (SMBEntryPoint*)(((char*)smbios) + 16);␊
319␉}␊
320␉printf("ERROR: Unable to find SMBIOS!\n");␊
321␉pause();␊
322␉return NULL;␊
323}␊
324␊
325

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