Chameleon

Chameleon Svn Source Tree

Root/branches/rewrite/i386/libsaio/cpu.c

Source at commit 1065 created 12 years 10 months ago.
By meklort, Stripping out a bunch of code...
1/*␊
2 * Copyright 2008 Islam Ahmed Zaid. All rights reserved. <azismed@gmail.com>␊
3 * AsereBLN: 2009: cleanup and bugfix␊
4 */␊
5␊
6#include "libsaio.h"␊
7#include "platform.h"␊
8#include "cpu.h"␊
9#include "bootstruct.h"␊
10#include "boot.h"␊
11␊
12#ifndef DEBUG_CPU␊
13#define DEBUG_CPU 0␊
14#endif␊
15␊
16#if DEBUG_CPU␊
17#define DBG(x...)␉␉printf(x)␊
18#else␊
19#define DBG(x...)␉␉msglog(x)␊
20#endif␊
21␊
22/*␊
23 * DFE: Measures the TSC frequency in Hz (64-bit) using the ACPI PM timer␊
24 */␊
25static uint64_t measure_tsc_frequency(void)␊
26{␊
27 uint64_t tscStart;␊
28 uint64_t tscEnd;␊
29 uint64_t tscDelta = 0xffffffffffffffffULL;␊
30 unsigned long pollCount;␊
31 uint64_t retval = 0;␊
32 int i;␊
33␊
34 /* Time how many TSC ticks elapse in 30 msec using the 8254 PIT␊
35 * counter 2. We run this loop 3 times to make sure the cache␊
36 * is hot and we take the minimum delta from all of the runs.␊
37 * That is to say that we're biased towards measuring the minimum␊
38 * number of TSC ticks that occur while waiting for the timer to␊
39 * expire. That theoretically helps avoid inconsistencies when␊
40 * running under a VM if the TSC is not virtualized and the host␊
41 * steals time. The TSC is normally virtualized for VMware.␊
42 */␊
43 for(i = 0; i < 10; ++i)␊
44 {␊
45 enable_PIT2();␊
46 set_PIT2_mode0(CALIBRATE_LATCH);␊
47 tscStart = rdtsc64();␊
48 pollCount = poll_PIT2_gate();␊
49 tscEnd = rdtsc64();␊
50 /* The poll loop must have run at least a few times for accuracy */␊
51 if(pollCount <= 1)␊
52 continue;␊
53 /* The TSC must increment at LEAST once every millisecond. We␊
54 * should have waited exactly 30 msec so the TSC delta should␊
55 * be >= 30. Anything less and the processor is way too slow.␊
56 */␊
57 if((tscEnd - tscStart) <= CALIBRATE_TIME_MSEC)␊
58 continue;␊
59 // tscDelta = MIN(tscDelta, (tscEnd - tscStart))␊
60 if( (tscEnd - tscStart) < tscDelta )␊
61 tscDelta = tscEnd - tscStart;␊
62 }␊
63 /* tscDelta is now the least number of TSC ticks the processor made in␊
64 * a timespan of 0.03 s (e.g. 30 milliseconds)␊
65 * Linux thus divides by 30 which gives the answer in kiloHertz because␊
66 * 1 / ms = kHz. But we're xnu and most of the rest of the code uses␊
67 * Hz so we need to convert our milliseconds to seconds. Since we're␊
68 * dividing by the milliseconds, we simply multiply by 1000.␊
69 */␊
70␊
71 /* Unlike linux, we're not limited to 32-bit, but we do need to take care␊
72 * that we're going to multiply by 1000 first so we do need at least some␊
73 * arithmetic headroom. For now, 32-bit should be enough.␊
74 * Also unlike Linux, our compiler can do 64-bit integer arithmetic.␊
75 */␊
76 if(tscDelta > (1ULL<<32))␊
77 retval = 0;␊
78 else␊
79 {␊
80 retval = tscDelta * 1000 / 30;␊
81 }␊
82 disable_PIT2();␊
83 return retval;␊
84}␊
85␊
86/*␊
87 * Calculates the FSB and CPU frequencies using specific MSRs for each CPU␊
88 * - multi. is read from a specific MSR. In the case of Intel, there is:␊
89 * a max multi. (used to calculate the FSB freq.),␊
90 * and a current multi. (used to calculate the CPU freq.)␊
91 * - fsbFrequency = tscFrequency / multi␊
92 * - cpuFrequency = fsbFrequency * multi␊
93 */␊
94␊
95void scan_cpu(PlatformInfo_t *p)␊
96{␊
97␉uint64_t␉tscFrequency, fsbFrequency, cpuFrequency;␊
98␉uint64_t␉msr, flex_ratio;␊
99␉uint8_t␉␉maxcoef, maxdiv, currcoef, bus_ratio_max, currdiv;␊
100␉int myfsb;␊
101␉uint8_t bus_ratio_min;␊
102␉uint32_t max_ratio, min_ratio;␊
103␊
104␉max_ratio = min_ratio = myfsb = bus_ratio_min = 0;␊
105␉maxcoef = maxdiv = bus_ratio_max = currcoef = currdiv = 0;␊
106␊
107␉/* get cpuid values */␊
108␉do_cpuid(0x00000000, p->CPU.CPUID[CPUID_0]);␊
109␉do_cpuid(0x00000001, p->CPU.CPUID[CPUID_1]);␊
110␉do_cpuid(0x00000002, p->CPU.CPUID[CPUID_2]);␊
111␉do_cpuid(0x00000003, p->CPU.CPUID[CPUID_3]);␊
112␉do_cpuid2(0x00000004, 0, p->CPU.CPUID[CPUID_4]);␊
113␉do_cpuid(0x80000000, p->CPU.CPUID[CPUID_80]);␊
114␉if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 1) {␊
115␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊
116␉}␊
117#if DEBUG_CPU␊
118␉{␊
119␉␉int␉␉i;␊
120␉␉printf("CPUID Raw Values:\n");␊
121␉␉for (i=0; i<CPUID_MAX; i++) {␊
122␉␉␉printf("%02d: %08x-%08x-%08x-%08x\n", i,␊
123␉␉␉␉p->CPU.CPUID[i][0], p->CPU.CPUID[i][1],␊
124␉␉␉␉p->CPU.CPUID[i][2], p->CPU.CPUID[i][3]);␊
125␉␉}␊
126␉}␊
127#endif␊
128␉p->CPU.Vendor␉␉= p->CPU.CPUID[CPUID_0][1];␊
129␉p->CPU.Signature␉= p->CPU.CPUID[CPUID_1][0];␊
130␉p->CPU.Stepping␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 3, 0);␊
131␉p->CPU.Model␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 7, 4);␊
132␉p->CPU.Family␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 11, 8);␊
133␉p->CPU.ExtModel␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 19, 16);␊
134␉p->CPU.ExtFamily␉= bitfield(p->CPU.CPUID[CPUID_1][0], 27, 20);␊
135␉␊
136 p->CPU.Model += (p->CPU.ExtModel << 4);␊
137 ␊
138 if (p->CPU.Vendor == 0x756E6547 /* Intel */ && ␊
139 p->CPU.Family == 0x06 && ␊
140 p->CPU.Model >= CPUID_MODEL_NEHALEM && ␊
141 p->CPU.Model != CPUID_MODEL_ATOM // MSR is *NOT* available on the Intel Atom CPU␊
142 ){␊
143 msr = rdmsr64(MSR_CORE_THREAD_COUNT);␉␉␉␉␉␉␉␉␉// Undocumented MSR in Nehalem and newer CPUs␊
144 p->CPU.NoCores␉␉= bitfield((uint32_t)msr, 31, 16);␉␉␉␉␉// Using undocumented MSR to get actual values␊
145 p->CPU.NoThreads␉= bitfield((uint32_t)msr, 15, 0);␉␉␉␉␉// Using undocumented MSR to get actual values␊
146␉} else {␊
147 p->CPU.NoThreads␉= bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␉␉// Use previous method for Cores and Threads␊
148 p->CPU.NoCores␉␉= bitfield(p->CPU.CPUID[CPUID_4][0], 31, 26) + 1;␊
149␉}␊
150␉␊
151␉/* get brand string (if supported) */␊
152␉/* Copyright: from Apple's XNU cpuid.c */␊
153␉if (p->CPU.CPUID[CPUID_80][0] > 0x80000004) {␊
154␉␉uint32_t␉reg[4];␊
155 char str[128], *s;␊
156␉␉/*␊
157␉␉ * The brand string 48 bytes (max), guaranteed to␊
158␉␉ * be NULL terminated.␊
159␉␉ */␊
160␉␉do_cpuid(0x80000002, reg);␊
161␉␉bcopy((char *)reg, &str[0], 16);␊
162␉␉do_cpuid(0x80000003, reg);␊
163␉␉bcopy((char *)reg, &str[16], 16);␊
164␉␉do_cpuid(0x80000004, reg);␊
165␉␉bcopy((char *)reg, &str[32], 16);␊
166␉␉for (s = str; *s != '\0'; s++) {␊
167␉␉␉if (*s != ' ') break;␊
168␉␉}␊
169␉␉␊
170␉␉strlcpy(p->CPU.BrandString,␉s, sizeof(p->CPU.BrandString));␊
171␉␉␊
172␉␉if (!strncmp(p->CPU.BrandString, CPU_STRING_UNKNOWN, MIN(sizeof(p->CPU.BrandString), strlen(CPU_STRING_UNKNOWN) + 1))) {␊
173␉␉␉ /*␊
174␉␉␉ * This string means we have a firmware-programmable brand string,␊
175␉␉␉ * and the firmware couldn't figure out what sort of CPU we have.␊
176␉␉␉ */␊
177␉␉␉ p->CPU.BrandString[0] = '\0';␊
178␉␉ }␊
179␉}␊
180␉␊
181␉/* setup features */␊
182␉if ((bit(23) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
183␉␉p->CPU.Features |= CPU_FEATURE_MMX;␊
184␉}␊
185␉if ((bit(25) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
186␉␉p->CPU.Features |= CPU_FEATURE_SSE;␊
187␉}␊
188␉if ((bit(26) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
189␉␉p->CPU.Features |= CPU_FEATURE_SSE2;␊
190␉}␊
191␉if ((bit(0) & p->CPU.CPUID[CPUID_1][2]) != 0) {␊
192␉␉p->CPU.Features |= CPU_FEATURE_SSE3;␊
193␉}␊
194␉if ((bit(19) & p->CPU.CPUID[CPUID_1][2]) != 0) {␊
195␉␉p->CPU.Features |= CPU_FEATURE_SSE41;␊
196␉}␊
197␉if ((bit(20) & p->CPU.CPUID[CPUID_1][2]) != 0) {␊
198␉␉p->CPU.Features |= CPU_FEATURE_SSE42;␊
199␉}␊
200␉if ((bit(29) & p->CPU.CPUID[CPUID_81][3]) != 0) {␊
201␉␉p->CPU.Features |= CPU_FEATURE_EM64T;␊
202␉}␊
203␉if ((bit(5) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
204␉␉p->CPU.Features |= CPU_FEATURE_MSR;␊
205␉}␊
206␉//if ((bit(28) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
207␉if (p->CPU.NoThreads > p->CPU.NoCores) {␊
208␉␉p->CPU.Features |= CPU_FEATURE_HTT;␊
209␉}␊
210␊
211␉tscFrequency = measure_tsc_frequency();␊
212␉fsbFrequency = 0;␊
213␉cpuFrequency = 0;␊
214␊
215␉if ((p->CPU.Vendor == 0x756E6547 /* Intel */) && ((p->CPU.Family == 0x06) || (p->CPU.Family == 0x0f))) {␊
216␉␉int intelCPU = p->CPU.Model;␊
217␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) || (p->CPU.Family == 0x0f && p->CPU.Model >= 0x03)) {␊
218␉␉␉/* Nehalem CPU model */␊
219␉␉␉if (p->CPU.Family == 0x06 && (p->CPU.Model == CPU_MODEL_NEHALEM || ␊
220 p->CPU.Model == CPU_MODEL_FIELDS || ␊
221 p->CPU.Model == CPU_MODEL_DALES || ␊
222 p->CPU.Model == CPU_MODEL_DALES_32NM || ␊
223 p->CPU.Model == CPU_MODEL_WESTMERE ||␊
224 p->CPU.Model == CPU_MODEL_NEHALEM_EX ||␊
225 p->CPU.Model == CPU_MODEL_WESTMERE_EX ||␊
226 p->CPU.Model == CPU_MODEL_SANDY ||␊
227 p->CPU.Model == CPU_MODEL_SANDY_XEON)) {␊
228␉␉␉␉msr = rdmsr64(MSR_PLATFORM_INFO);␊
229␉␉␉␉DBG("msr(%d): platform_info %08x\n", __LINE__, msr & 0xffffffff);␊
230␉␉␉␉bus_ratio_max = (msr >> 8) & 0xff;␊
231␉␉␉␉bus_ratio_min = (msr >> 40) & 0xff; //valv: not sure about this one (Remarq.1)␊
232␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊
233␉␉␉␉DBG("msr(%d): flex_ratio %08x\n", __LINE__, msr & 0xffffffff);␊
234␉␉␉␉if ((msr >> 16) & 0x01) {␊
235␉␉␉␉␉flex_ratio = (msr >> 8) & 0xff;␊
236␉␉␉␉␉/* bcc9: at least on the gigabyte h67ma-ud2h,␊
237␉␉␉␉␉ where the cpu multipler can't be changed to␊
238␉␉␉␉␉ allow overclocking, the flex_ratio msr has unexpected (to OSX)␊
239␉␉␉␉␉ contents. These contents cause mach_kernel to␊
240␉␉␉␉␉ fail to compute the bus ratio correctly, instead␊
241␉␉␉␉␉ causing the system to crash since tscGranularity␊
242␉␉␉␉␉ is inadvertently set to 0.␊
243␉␉␉␉␉*/␊
244␉␉␉␉␉if (flex_ratio == 0) {␊
245␉␉␉␉␉␉/* Clear bit 16 (evidently the␊
246␉␉␉␉␉␉ presence bit) */␊
247␉␉␉␉␉␉wrmsr64(MSR_FLEX_RATIO, (msr & 0xFFFFFFFFFFFEFFFFULL));␊
248␉␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊
249␉␉␉␉␉␉verbose("Unusable flex ratio detected. Patched MSR now %08x\n", msr & 0xffffffff);␊
250␉␉␉␉␉} else {␊
251␉␉␉␉␉␉if (bus_ratio_max > flex_ratio) {␊
252␉␉␉␉␉␉␉bus_ratio_max = flex_ratio;␊
253␉␉␉␉␉␉}␊
254␉␉␉␉␉}␊
255␉␉␉␉}␊
256␊
257␉␉␉␉if (bus_ratio_max) {␊
258␉␉␉␉␉fsbFrequency = (tscFrequency / bus_ratio_max);␊
259␉␉␉␉}␊
260␉␉␉␉//valv: Turbo Ratio Limit␊
261␉␉␉␉if ((intelCPU != 0x2e) && (intelCPU != 0x2f)) {␊
262␉␉␉␉␉msr = rdmsr64(MSR_TURBO_RATIO_LIMIT);␊
263␉␉␉␉␉cpuFrequency = bus_ratio_max * fsbFrequency;␊
264␉␉␉␉␉max_ratio = bus_ratio_max * 10;␊
265␉␉␉␉} else {␊
266␉␉␉␉␉cpuFrequency = tscFrequency;␊
267␉␉␉␉}␊
268␊
269␉␉␉␉//valv: to be uncommented if Remarq.1 didn't stick␊
270␉␉␉␉/*if(bus_ratio_max > 0) bus_ratio = flex_ratio;*/␊
271␉␉␉␉p->CPU.MaxRatio = max_ratio;␊
272␉␉␉␉p->CPU.MinRatio = min_ratio;␊
273␊
274␉␉␉␉myfsb = fsbFrequency / 1000000;␊
275␉␉␉␉verbose("Sticking with [BCLK: %dMhz, Bus-Ratio: %d]\n", myfsb, max_ratio);␊
276␉␉␉␉currcoef = bus_ratio_max;␊
277␉␉␉} else {␊
278␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_STATUS);␊
279␉␉␉␉DBG("msr(%d): ia32_perf_stat 0x%08x\n", __LINE__, msr & 0xffffffff);␊
280␉␉␉␉currcoef = (msr >> 8) & 0x1f;␊
281␉␉␉␉/* Non-integer bus ratio for the max-multi*/␊
282␉␉␉␉maxdiv = (msr >> 46) & 0x01;␊
283␉␉␉␉/* Non-integer bus ratio for the current-multi (undocumented)*/␊
284␉␉␉␉currdiv = (msr >> 14) & 0x01;␊
285␊
286␉␉␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0e) || (p->CPU.Family == 0x0f)) // This will always be model >= 3␊
287␉␉␉␉{␊
288␉␉␉␉␉/* On these models, maxcoef defines TSC freq */␊
289␉␉␉␉␉maxcoef = (msr >> 40) & 0x1f;␊
290␉␉␉␉} else {␊
291␉␉␉␉␉/* On lower models, currcoef defines TSC freq */␊
292␉␉␉␉␉/* XXX */␊
293␉␉␉␉␉maxcoef = currcoef;␊
294␉␉␉␉}␊
295␊
296␉␉␉␉if (maxcoef) {␊
297␉␉␉␉␉if (maxdiv) {␊
298␉␉␉␉␉␉fsbFrequency = ((tscFrequency * 2) / ((maxcoef * 2) + 1));␊
299␉␉␉␉␉} else {␊
300␉␉␉␉␉␉fsbFrequency = (tscFrequency / maxcoef);␊
301␉␉␉␉␉}␊
302␉␉␉␉␉if (currdiv) {␊
303␉␉␉␉␉␉cpuFrequency = (fsbFrequency * ((currcoef * 2) + 1) / 2);␊
304␉␉␉␉␉} else {␊
305␉␉␉␉␉␉cpuFrequency = (fsbFrequency * currcoef);␊
306␉␉␉␉␉}␊
307␉␉␉␉␉DBG("max: %d%s current: %d%s\n", maxcoef, maxdiv ? ".5" : "",currcoef, currdiv ? ".5" : "");␊
308␉␉␉␉}␊
309␉␉␉}␊
310␉␉}␊
311␉␉/* Mobile CPU */␊
312␉␉if (rdmsr64(MSR_IA32_PLATFORM_ID) & (1<<28)) {␊
313␉␉␉p->CPU.Features |= CPU_FEATURE_MOBILE;␊
314␉␉}␊
315␉}␊
316#if 0␊
317␉else if((p->CPU.Vendor == 0x68747541 /* AMD */) && (p->CPU.Family == 0x0f)) {␊
318␉␉if(p->CPU.ExtFamily == 0x00 /* K8 */) {␊
319␉␉␉msr = rdmsr64(K8_FIDVID_STATUS);␊
320␉␉␉currcoef = (msr & 0x3f) / 2 + 4;␊
321␉␉␉currdiv = (msr & 0x01) * 2;␊
322␉␉} else if(p->CPU.ExtFamily >= 0x01 /* K10+ */) {␊
323␉␉␉msr = rdmsr64(K10_COFVID_STATUS);␊
324␉␉␉if(p->CPU.ExtFamily == 0x01 /* K10 */)␊
325␉␉␉␉currcoef = (msr & 0x3f) + 0x10;␊
326␉␉␉else /* K11+ */␊
327␉␉␉␉currcoef = (msr & 0x3f) + 0x08;␊
328␉␉␉currdiv = (2 << ((msr >> 6) & 0x07));␊
329␉␉}␊
330␊
331␉␉if (currcoef) {␊
332␉␉␉if (currdiv) {␊
333␉␉␉␉fsbFrequency = ((tscFrequency * currdiv) / currcoef);␊
334␉␉␉␉DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);␊
335␉␉␉} else {␊
336␉␉␉␉fsbFrequency = (tscFrequency / currcoef);␊
337␉␉␉␉DBG("%d\n", currcoef);␊
338␉␉␉}␊
339␉␉␉fsbFrequency = (tscFrequency / currcoef);␊
340␉␉␉cpuFrequency = tscFrequency;␊
341␉␉}␊
342␉}␊
343␊
344␉if (!fsbFrequency) {␊
345␉␉fsbFrequency = (DEFAULT_FSB * 1000);␊
346␉␉cpuFrequency = tscFrequency;␊
347␉␉DBG("0 ! using the default value for FSB !\n");␊
348␉}␊
349#endif␊
350␊
351␉p->CPU.MaxCoef = maxcoef;␊
352␉p->CPU.MaxDiv = maxdiv;␊
353␉p->CPU.CurrCoef = currcoef;␊
354␉p->CPU.CurrDiv = currdiv;␊
355␉p->CPU.TSCFrequency = tscFrequency;␊
356␉p->CPU.FSBFrequency = fsbFrequency;␊
357␉p->CPU.CPUFrequency = cpuFrequency;␊
358␊
359␉DBG("CPU: Brand String: %s\n",␉␉␉␉p->CPU.BrandString);␊
360␉DBG("CPU: Vendor/Family/ExtFamily: 0x%x/0x%x/0x%x\n",␉p->CPU.Vendor, p->CPU.Family, p->CPU.ExtFamily);␊
361␉DBG("CPU: Model/ExtModel/Stepping: 0x%x/0x%x/0x%x\n",␉p->CPU.Model, p->CPU.ExtModel, p->CPU.Stepping);␊
362␉DBG("CPU: MaxCoef/CurrCoef: 0x%x/0x%x\n",␉␉p->CPU.MaxCoef, p->CPU.CurrCoef);␊
363␉DBG("CPU: MaxDiv/CurrDiv: 0x%x/0x%x\n",␉␉p->CPU.MaxDiv, p->CPU.CurrDiv);␊
364␉DBG("CPU: TSCFreq: %dMHz\n",␉␉␉p->CPU.TSCFrequency / 1000000);␊
365␉DBG("CPU: FSBFreq: %dMHz\n",␉␉␉p->CPU.FSBFrequency / 1000000);␊
366␉DBG("CPU: CPUFreq: %dMHz\n",␉␉␉p->CPU.CPUFrequency / 1000000);␊
367␉DBG("CPU: NoCores/NoThreads: %d/%d\n",␉␉␉p->CPU.NoCores, p->CPU.NoThreads);␊
368␉DBG("CPU: Features: 0x%08x\n",␉␉␉p->CPU.Features);␊
369#if DEBUG_CPU␊
370␉pause();␊
371#endif␊
372}␊
373

Archive Download this file

Revision: 1065