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Source at commit 1066 created 12 years 10 months ago.
By meklort, Removing even more code...
1/*␊
2 * Copyright 2008 Islam Ahmed Zaid. All rights reserved. <azismed@gmail.com>␊
3 * AsereBLN: 2009: cleanup and bugfix␊
4 */␊
5␊
6#include "libsaio.h"␊
7#include "platform.h"␊
8#include "cpu.h"␊
9#include "boot.h"␊
10␊
11#ifndef DEBUG_CPU␊
12#define DEBUG_CPU 0␊
13#endif␊
14␊
15#if DEBUG_CPU␊
16#define DBG(x...)␉␉printf(x)␊
17#else␊
18#define DBG(x...)␉␉msglog(x)␊
19#endif␊
20␊
21/*␊
22 * DFE: Measures the TSC frequency in Hz (64-bit) using the ACPI PM timer␊
23 */␊
24static uint64_t measure_tsc_frequency(void)␊
25{␊
26 uint64_t tscStart;␊
27 uint64_t tscEnd;␊
28 uint64_t tscDelta = 0xffffffffffffffffULL;␊
29 unsigned long pollCount;␊
30 uint64_t retval = 0;␊
31 int i;␊
32␊
33 /* Time how many TSC ticks elapse in 30 msec using the 8254 PIT␊
34 * counter 2. We run this loop 3 times to make sure the cache␊
35 * is hot and we take the minimum delta from all of the runs.␊
36 * That is to say that we're biased towards measuring the minimum␊
37 * number of TSC ticks that occur while waiting for the timer to␊
38 * expire. That theoretically helps avoid inconsistencies when␊
39 * running under a VM if the TSC is not virtualized and the host␊
40 * steals time. The TSC is normally virtualized for VMware.␊
41 */␊
42 for(i = 0; i < 10; ++i)␊
43 {␊
44 enable_PIT2();␊
45 set_PIT2_mode0(CALIBRATE_LATCH);␊
46 tscStart = rdtsc64();␊
47 pollCount = poll_PIT2_gate();␊
48 tscEnd = rdtsc64();␊
49 /* The poll loop must have run at least a few times for accuracy */␊
50 if(pollCount <= 1)␊
51 continue;␊
52 /* The TSC must increment at LEAST once every millisecond. We␊
53 * should have waited exactly 30 msec so the TSC delta should␊
54 * be >= 30. Anything less and the processor is way too slow.␊
55 */␊
56 if((tscEnd - tscStart) <= CALIBRATE_TIME_MSEC)␊
57 continue;␊
58 // tscDelta = MIN(tscDelta, (tscEnd - tscStart))␊
59 if( (tscEnd - tscStart) < tscDelta )␊
60 tscDelta = tscEnd - tscStart;␊
61 }␊
62 /* tscDelta is now the least number of TSC ticks the processor made in␊
63 * a timespan of 0.03 s (e.g. 30 milliseconds)␊
64 * Linux thus divides by 30 which gives the answer in kiloHertz because␊
65 * 1 / ms = kHz. But we're xnu and most of the rest of the code uses␊
66 * Hz so we need to convert our milliseconds to seconds. Since we're␊
67 * dividing by the milliseconds, we simply multiply by 1000.␊
68 */␊
69␊
70 /* Unlike linux, we're not limited to 32-bit, but we do need to take care␊
71 * that we're going to multiply by 1000 first so we do need at least some␊
72 * arithmetic headroom. For now, 32-bit should be enough.␊
73 * Also unlike Linux, our compiler can do 64-bit integer arithmetic.␊
74 */␊
75 if(tscDelta > (1ULL<<32))␊
76 retval = 0;␊
77 else␊
78 {␊
79 retval = tscDelta * 1000 / 30;␊
80 }␊
81 disable_PIT2();␊
82 return retval;␊
83}␊
84␊
85/*␊
86 * Calculates the FSB and CPU frequencies using specific MSRs for each CPU␊
87 * - multi. is read from a specific MSR. In the case of Intel, there is:␊
88 * a max multi. (used to calculate the FSB freq.),␊
89 * and a current multi. (used to calculate the CPU freq.)␊
90 * - fsbFrequency = tscFrequency / multi␊
91 * - cpuFrequency = fsbFrequency * multi␊
92 */␊
93␊
94void scan_cpu(PlatformInfo_t *p)␊
95{␊
96␉uint64_t␉tscFrequency, fsbFrequency, cpuFrequency;␊
97␉uint64_t␉msr, flex_ratio;␊
98␉uint8_t␉␉maxcoef, maxdiv, currcoef, bus_ratio_max, currdiv;␊
99␉int myfsb;␊
100␉uint8_t bus_ratio_min;␊
101␉uint32_t max_ratio, min_ratio;␊
102␊
103␉max_ratio = min_ratio = myfsb = bus_ratio_min = 0;␊
104␉maxcoef = maxdiv = bus_ratio_max = currcoef = currdiv = 0;␊
105␊
106␉/* get cpuid values */␊
107␉do_cpuid(0x00000000, p->CPU.CPUID[CPUID_0]);␊
108␉do_cpuid(0x00000001, p->CPU.CPUID[CPUID_1]);␊
109␉do_cpuid(0x00000002, p->CPU.CPUID[CPUID_2]);␊
110␉do_cpuid(0x00000003, p->CPU.CPUID[CPUID_3]);␊
111␉do_cpuid2(0x00000004, 0, p->CPU.CPUID[CPUID_4]);␊
112␉do_cpuid(0x80000000, p->CPU.CPUID[CPUID_80]);␊
113␉if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 1) {␊
114␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊
115␉}␊
116#if DEBUG_CPU␊
117␉{␊
118␉␉int␉␉i;␊
119␉␉printf("CPUID Raw Values:\n");␊
120␉␉for (i=0; i<CPUID_MAX; i++) {␊
121␉␉␉printf("%02d: %08x-%08x-%08x-%08x\n", i,␊
122␉␉␉␉p->CPU.CPUID[i][0], p->CPU.CPUID[i][1],␊
123␉␉␉␉p->CPU.CPUID[i][2], p->CPU.CPUID[i][3]);␊
124␉␉}␊
125␉}␊
126#endif␊
127␉p->CPU.Vendor␉␉= p->CPU.CPUID[CPUID_0][1];␊
128␉p->CPU.Signature␉= p->CPU.CPUID[CPUID_1][0];␊
129␉p->CPU.Stepping␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 3, 0);␊
130␉p->CPU.Model␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 7, 4);␊
131␉p->CPU.Family␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 11, 8);␊
132␉p->CPU.ExtModel␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 19, 16);␊
133␉p->CPU.ExtFamily␉= bitfield(p->CPU.CPUID[CPUID_1][0], 27, 20);␊
134␉␊
135 p->CPU.Model += (p->CPU.ExtModel << 4);␊
136 ␊
137 if (p->CPU.Vendor == 0x756E6547 /* Intel */ && ␊
138 p->CPU.Family == 0x06 && ␊
139 p->CPU.Model >= CPUID_MODEL_NEHALEM && ␊
140 p->CPU.Model != CPUID_MODEL_ATOM // MSR is *NOT* available on the Intel Atom CPU␊
141 ){␊
142 msr = rdmsr64(MSR_CORE_THREAD_COUNT);␉␉␉␉␉␉␉␉␉// Undocumented MSR in Nehalem and newer CPUs␊
143 p->CPU.NoCores␉␉= bitfield((uint32_t)msr, 31, 16);␉␉␉␉␉// Using undocumented MSR to get actual values␊
144 p->CPU.NoThreads␉= bitfield((uint32_t)msr, 15, 0);␉␉␉␉␉// Using undocumented MSR to get actual values␊
145␉} else {␊
146 p->CPU.NoThreads␉= bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␉␉// Use previous method for Cores and Threads␊
147 p->CPU.NoCores␉␉= bitfield(p->CPU.CPUID[CPUID_4][0], 31, 26) + 1;␊
148␉}␊
149␉␊
150␉/* get brand string (if supported) */␊
151␉/* Copyright: from Apple's XNU cpuid.c */␊
152␉if (p->CPU.CPUID[CPUID_80][0] > 0x80000004) {␊
153␉␉uint32_t␉reg[4];␊
154 char str[128], *s;␊
155␉␉/*␊
156␉␉ * The brand string 48 bytes (max), guaranteed to␊
157␉␉ * be NULL terminated.␊
158␉␉ */␊
159␉␉do_cpuid(0x80000002, reg);␊
160␉␉bcopy((char *)reg, &str[0], 16);␊
161␉␉do_cpuid(0x80000003, reg);␊
162␉␉bcopy((char *)reg, &str[16], 16);␊
163␉␉do_cpuid(0x80000004, reg);␊
164␉␉bcopy((char *)reg, &str[32], 16);␊
165␉␉for (s = str; *s != '\0'; s++) {␊
166␉␉␉if (*s != ' ') break;␊
167␉␉}␊
168␉␉␊
169␉␉strlcpy(p->CPU.BrandString,␉s, sizeof(p->CPU.BrandString));␊
170␉␉␊
171␉␉if (!strncmp(p->CPU.BrandString, CPU_STRING_UNKNOWN, MIN(sizeof(p->CPU.BrandString), strlen(CPU_STRING_UNKNOWN) + 1))) {␊
172␉␉␉ /*␊
173␉␉␉ * This string means we have a firmware-programmable brand string,␊
174␉␉␉ * and the firmware couldn't figure out what sort of CPU we have.␊
175␉␉␉ */␊
176␉␉␉ p->CPU.BrandString[0] = '\0';␊
177␉␉ }␊
178␉}␊
179␉␊
180␉/* setup features */␊
181␉if ((bit(23) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
182␉␉p->CPU.Features |= CPU_FEATURE_MMX;␊
183␉}␊
184␉if ((bit(25) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
185␉␉p->CPU.Features |= CPU_FEATURE_SSE;␊
186␉}␊
187␉if ((bit(26) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
188␉␉p->CPU.Features |= CPU_FEATURE_SSE2;␊
189␉}␊
190␉if ((bit(0) & p->CPU.CPUID[CPUID_1][2]) != 0) {␊
191␉␉p->CPU.Features |= CPU_FEATURE_SSE3;␊
192␉}␊
193␉if ((bit(19) & p->CPU.CPUID[CPUID_1][2]) != 0) {␊
194␉␉p->CPU.Features |= CPU_FEATURE_SSE41;␊
195␉}␊
196␉if ((bit(20) & p->CPU.CPUID[CPUID_1][2]) != 0) {␊
197␉␉p->CPU.Features |= CPU_FEATURE_SSE42;␊
198␉}␊
199␉if ((bit(29) & p->CPU.CPUID[CPUID_81][3]) != 0) {␊
200␉␉p->CPU.Features |= CPU_FEATURE_EM64T;␊
201␉}␊
202␉if ((bit(5) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
203␉␉p->CPU.Features |= CPU_FEATURE_MSR;␊
204␉}␊
205␉//if ((bit(28) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
206␉if (p->CPU.NoThreads > p->CPU.NoCores) {␊
207␉␉p->CPU.Features |= CPU_FEATURE_HTT;␊
208␉}␊
209␊
210␉tscFrequency = measure_tsc_frequency();␊
211␉fsbFrequency = 0;␊
212␉cpuFrequency = 0;␊
213␊
214␉if ((p->CPU.Vendor == 0x756E6547 /* Intel */) && ((p->CPU.Family == 0x06) || (p->CPU.Family == 0x0f))) {␊
215␉␉int intelCPU = p->CPU.Model;␊
216␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) || (p->CPU.Family == 0x0f && p->CPU.Model >= 0x03)) {␊
217␉␉␉/* Nehalem CPU model */␊
218␉␉␉if (p->CPU.Family == 0x06 && (p->CPU.Model == CPU_MODEL_NEHALEM || ␊
219 p->CPU.Model == CPU_MODEL_FIELDS || ␊
220 p->CPU.Model == CPU_MODEL_DALES || ␊
221 p->CPU.Model == CPU_MODEL_DALES_32NM || ␊
222 p->CPU.Model == CPU_MODEL_WESTMERE ||␊
223 p->CPU.Model == CPU_MODEL_NEHALEM_EX ||␊
224 p->CPU.Model == CPU_MODEL_WESTMERE_EX ||␊
225 p->CPU.Model == CPU_MODEL_SANDY ||␊
226 p->CPU.Model == CPU_MODEL_SANDY_XEON)) {␊
227␉␉␉␉msr = rdmsr64(MSR_PLATFORM_INFO);␊
228␉␉␉␉DBG("msr(%d): platform_info %08x\n", __LINE__, msr & 0xffffffff);␊
229␉␉␉␉bus_ratio_max = (msr >> 8) & 0xff;␊
230␉␉␉␉bus_ratio_min = (msr >> 40) & 0xff; //valv: not sure about this one (Remarq.1)␊
231␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊
232␉␉␉␉DBG("msr(%d): flex_ratio %08x\n", __LINE__, msr & 0xffffffff);␊
233␉␉␉␉if ((msr >> 16) & 0x01) {␊
234␉␉␉␉␉flex_ratio = (msr >> 8) & 0xff;␊
235␉␉␉␉␉/* bcc9: at least on the gigabyte h67ma-ud2h,␊
236␉␉␉␉␉ where the cpu multipler can't be changed to␊
237␉␉␉␉␉ allow overclocking, the flex_ratio msr has unexpected (to OSX)␊
238␉␉␉␉␉ contents. These contents cause mach_kernel to␊
239␉␉␉␉␉ fail to compute the bus ratio correctly, instead␊
240␉␉␉␉␉ causing the system to crash since tscGranularity␊
241␉␉␉␉␉ is inadvertently set to 0.␊
242␉␉␉␉␉*/␊
243␉␉␉␉␉if (flex_ratio == 0) {␊
244␉␉␉␉␉␉/* Clear bit 16 (evidently the␊
245␉␉␉␉␉␉ presence bit) */␊
246␉␉␉␉␉␉wrmsr64(MSR_FLEX_RATIO, (msr & 0xFFFFFFFFFFFEFFFFULL));␊
247␉␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊
248␉␉␉␉␉␉verbose("Unusable flex ratio detected. Patched MSR now %08x\n", msr & 0xffffffff);␊
249␉␉␉␉␉} else {␊
250␉␉␉␉␉␉if (bus_ratio_max > flex_ratio) {␊
251␉␉␉␉␉␉␉bus_ratio_max = flex_ratio;␊
252␉␉␉␉␉␉}␊
253␉␉␉␉␉}␊
254␉␉␉␉}␊
255␊
256␉␉␉␉if (bus_ratio_max) {␊
257␉␉␉␉␉fsbFrequency = (tscFrequency / bus_ratio_max);␊
258␉␉␉␉}␊
259␉␉␉␉//valv: Turbo Ratio Limit␊
260␉␉␉␉if ((intelCPU != 0x2e) && (intelCPU != 0x2f)) {␊
261␉␉␉␉␉msr = rdmsr64(MSR_TURBO_RATIO_LIMIT);␊
262␉␉␉␉␉cpuFrequency = bus_ratio_max * fsbFrequency;␊
263␉␉␉␉␉max_ratio = bus_ratio_max * 10;␊
264␉␉␉␉} else {␊
265␉␉␉␉␉cpuFrequency = tscFrequency;␊
266␉␉␉␉}␊
267␊
268␉␉␉␉//valv: to be uncommented if Remarq.1 didn't stick␊
269␉␉␉␉/*if(bus_ratio_max > 0) bus_ratio = flex_ratio;*/␊
270␉␉␉␉p->CPU.MaxRatio = max_ratio;␊
271␉␉␉␉p->CPU.MinRatio = min_ratio;␊
272␊
273␉␉␉␉myfsb = fsbFrequency / 1000000;␊
274␉␉␉␉verbose("Sticking with [BCLK: %dMhz, Bus-Ratio: %d]\n", myfsb, max_ratio);␊
275␉␉␉␉currcoef = bus_ratio_max;␊
276␉␉␉} else {␊
277␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_STATUS);␊
278␉␉␉␉DBG("msr(%d): ia32_perf_stat 0x%08x\n", __LINE__, msr & 0xffffffff);␊
279␉␉␉␉currcoef = (msr >> 8) & 0x1f;␊
280␉␉␉␉/* Non-integer bus ratio for the max-multi*/␊
281␉␉␉␉maxdiv = (msr >> 46) & 0x01;␊
282␉␉␉␉/* Non-integer bus ratio for the current-multi (undocumented)*/␊
283␉␉␉␉currdiv = (msr >> 14) & 0x01;␊
284␊
285␉␉␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0e) || (p->CPU.Family == 0x0f)) // This will always be model >= 3␊
286␉␉␉␉{␊
287␉␉␉␉␉/* On these models, maxcoef defines TSC freq */␊
288␉␉␉␉␉maxcoef = (msr >> 40) & 0x1f;␊
289␉␉␉␉} else {␊
290␉␉␉␉␉/* On lower models, currcoef defines TSC freq */␊
291␉␉␉␉␉/* XXX */␊
292␉␉␉␉␉maxcoef = currcoef;␊
293␉␉␉␉}␊
294␊
295␉␉␉␉if (maxcoef) {␊
296␉␉␉␉␉if (maxdiv) {␊
297␉␉␉␉␉␉fsbFrequency = ((tscFrequency * 2) / ((maxcoef * 2) + 1));␊
298␉␉␉␉␉} else {␊
299␉␉␉␉␉␉fsbFrequency = (tscFrequency / maxcoef);␊
300␉␉␉␉␉}␊
301␉␉␉␉␉if (currdiv) {␊
302␉␉␉␉␉␉cpuFrequency = (fsbFrequency * ((currcoef * 2) + 1) / 2);␊
303␉␉␉␉␉} else {␊
304␉␉␉␉␉␉cpuFrequency = (fsbFrequency * currcoef);␊
305␉␉␉␉␉}␊
306␉␉␉␉␉DBG("max: %d%s current: %d%s\n", maxcoef, maxdiv ? ".5" : "",currcoef, currdiv ? ".5" : "");␊
307␉␉␉␉}␊
308␉␉␉}␊
309␉␉}␊
310␉␉/* Mobile CPU */␊
311␉␉if (rdmsr64(MSR_IA32_PLATFORM_ID) & (1<<28)) {␊
312␉␉␉p->CPU.Features |= CPU_FEATURE_MOBILE;␊
313␉␉}␊
314␉}␊
315#if 0␊
316␉else if((p->CPU.Vendor == 0x68747541 /* AMD */) && (p->CPU.Family == 0x0f)) {␊
317␉␉if(p->CPU.ExtFamily == 0x00 /* K8 */) {␊
318␉␉␉msr = rdmsr64(K8_FIDVID_STATUS);␊
319␉␉␉currcoef = (msr & 0x3f) / 2 + 4;␊
320␉␉␉currdiv = (msr & 0x01) * 2;␊
321␉␉} else if(p->CPU.ExtFamily >= 0x01 /* K10+ */) {␊
322␉␉␉msr = rdmsr64(K10_COFVID_STATUS);␊
323␉␉␉if(p->CPU.ExtFamily == 0x01 /* K10 */)␊
324␉␉␉␉currcoef = (msr & 0x3f) + 0x10;␊
325␉␉␉else /* K11+ */␊
326␉␉␉␉currcoef = (msr & 0x3f) + 0x08;␊
327␉␉␉currdiv = (2 << ((msr >> 6) & 0x07));␊
328␉␉}␊
329␊
330␉␉if (currcoef) {␊
331␉␉␉if (currdiv) {␊
332␉␉␉␉fsbFrequency = ((tscFrequency * currdiv) / currcoef);␊
333␉␉␉␉DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);␊
334␉␉␉} else {␊
335␉␉␉␉fsbFrequency = (tscFrequency / currcoef);␊
336␉␉␉␉DBG("%d\n", currcoef);␊
337␉␉␉}␊
338␉␉␉fsbFrequency = (tscFrequency / currcoef);␊
339␉␉␉cpuFrequency = tscFrequency;␊
340␉␉}␊
341␉}␊
342␊
343␉if (!fsbFrequency) {␊
344␉␉fsbFrequency = (DEFAULT_FSB * 1000);␊
345␉␉cpuFrequency = tscFrequency;␊
346␉␉DBG("0 ! using the default value for FSB !\n");␊
347␉}␊
348#endif␊
349␊
350␉p->CPU.MaxCoef = maxcoef;␊
351␉p->CPU.MaxDiv = maxdiv;␊
352␉p->CPU.CurrCoef = currcoef;␊
353␉p->CPU.CurrDiv = currdiv;␊
354␉p->CPU.TSCFrequency = tscFrequency;␊
355␉p->CPU.FSBFrequency = fsbFrequency;␊
356␉p->CPU.CPUFrequency = cpuFrequency;␊
357␊
358␉DBG("CPU: Brand String: %s\n",␉␉␉␉p->CPU.BrandString);␊
359␉DBG("CPU: Vendor/Family/ExtFamily: 0x%x/0x%x/0x%x\n",␉p->CPU.Vendor, p->CPU.Family, p->CPU.ExtFamily);␊
360␉DBG("CPU: Model/ExtModel/Stepping: 0x%x/0x%x/0x%x\n",␉p->CPU.Model, p->CPU.ExtModel, p->CPU.Stepping);␊
361␉DBG("CPU: MaxCoef/CurrCoef: 0x%x/0x%x\n",␉␉p->CPU.MaxCoef, p->CPU.CurrCoef);␊
362␉DBG("CPU: MaxDiv/CurrDiv: 0x%x/0x%x\n",␉␉p->CPU.MaxDiv, p->CPU.CurrDiv);␊
363␉DBG("CPU: TSCFreq: %dMHz\n",␉␉␉p->CPU.TSCFrequency / 1000000);␊
364␉DBG("CPU: FSBFreq: %dMHz\n",␉␉␉p->CPU.FSBFrequency / 1000000);␊
365␉DBG("CPU: CPUFreq: %dMHz\n",␉␉␉p->CPU.CPUFrequency / 1000000);␊
366␉DBG("CPU: NoCores/NoThreads: %d/%d\n",␉␉␉p->CPU.NoCores, p->CPU.NoThreads);␊
367␉DBG("CPU: Features: 0x%08x\n",␉␉␉p->CPU.Features);␊
368#if DEBUG_CPU␊
369␉pause();␊
370#endif␊
371}␊
372

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