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Source at commit 1066 created 12 years 10 months ago. By meklort, Removing even more code... | |
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1 | /*␊ |
2 | *␊ |
3 | * Copyright 2008 by Islam M. Ahmed Zaid. All rights reserved.␊ |
4 | *␊ |
5 | */␊ |
6 | ␊ |
7 | #include "libsaio.h"␊ |
8 | #include "pci.h"␊ |
9 | ␊ |
10 | #ifndef DEBUG_PCI␊ |
11 | #define DEBUG_PCI 0␊ |
12 | #endif␊ |
13 | ␊ |
14 | #if DEBUG_PCI␊ |
15 | #define DBG(x...)␉␉printf(x)␊ |
16 | #else␊ |
17 | #define DBG(x...)␊ |
18 | #endif␊ |
19 | ␊ |
20 | pci_dt_t␉*root_pci_dev;␊ |
21 | ␊ |
22 | ␊ |
23 | uint8_t pci_config_read8(uint32_t pci_addr, uint8_t reg)␊ |
24 | {␊ |
25 | ␉pci_addr |= reg & ~3;␊ |
26 | ␉outl(PCI_ADDR_REG, pci_addr);␊ |
27 | ␉return inb(PCI_DATA_REG + (reg & 3));␊ |
28 | }␊ |
29 | ␊ |
30 | uint16_t pci_config_read16(uint32_t pci_addr, uint8_t reg)␊ |
31 | {␊ |
32 | ␉pci_addr |= reg & ~3;␊ |
33 | ␉outl(PCI_ADDR_REG, pci_addr);␊ |
34 | ␉return inw(PCI_DATA_REG + (reg & 2));␊ |
35 | }␊ |
36 | ␊ |
37 | uint32_t pci_config_read32(uint32_t pci_addr, uint8_t reg)␊ |
38 | {␊ |
39 | ␉pci_addr |= reg & ~3;␊ |
40 | ␉outl(PCI_ADDR_REG, pci_addr);␊ |
41 | ␉return inl(PCI_DATA_REG);␊ |
42 | }␊ |
43 | ␊ |
44 | void pci_config_write8(uint32_t pci_addr, uint8_t reg, uint8_t data)␊ |
45 | {␊ |
46 | ␉pci_addr |= reg & ~3;␊ |
47 | ␉outl(PCI_ADDR_REG, pci_addr);␊ |
48 | ␉outb(PCI_DATA_REG + (reg & 3), data);␊ |
49 | }␊ |
50 | ␊ |
51 | void pci_config_write16(uint32_t pci_addr, uint8_t reg, uint16_t data)␊ |
52 | {␊ |
53 | ␉pci_addr |= reg & ~3;␊ |
54 | ␉outl(PCI_ADDR_REG, pci_addr);␊ |
55 | ␉outw(PCI_DATA_REG + (reg & 2), data);␊ |
56 | }␊ |
57 | ␊ |
58 | void pci_config_write32(uint32_t pci_addr, uint8_t reg, uint32_t data)␊ |
59 | {␊ |
60 | ␉pci_addr |= reg & ~3;␊ |
61 | ␉outl(PCI_ADDR_REG, pci_addr);␊ |
62 | ␉outl(PCI_DATA_REG, data);␊ |
63 | }␊ |
64 | ␊ |
65 | void scan_pci_bus(pci_dt_t *start, uint8_t bus)␊ |
66 | {␊ |
67 | ␉pci_dt_t␉*new;␊ |
68 | ␉pci_dt_t␉**current = &start->children;␊ |
69 | ␉uint32_t␉id;␊ |
70 | ␉uint32_t␉pci_addr;␊ |
71 | ␉uint8_t␉␉dev;␊ |
72 | ␉uint8_t␉␉func;␊ |
73 | ␉uint8_t␉␉secondary_bus;␊ |
74 | ␉uint8_t␉␉header_type;␊ |
75 | ␊ |
76 | ␉for (dev = 0; dev < 32; dev++) {␊ |
77 | ␉␉for (func = 0; func < 8; func++) {␊ |
78 | ␉␉␉pci_addr = PCIADDR(bus, dev, func);␊ |
79 | ␉␉␉id = pci_config_read32(pci_addr, PCI_VENDOR_ID);␊ |
80 | ␉␉␉if (!id || id == 0xffffffff) {␊ |
81 | ␉␉␉␉continue;␊ |
82 | ␉␉␉}␊ |
83 | ␉␉␉new = (pci_dt_t*)malloc(sizeof(pci_dt_t));␊ |
84 | ␉␉␉bzero(new, sizeof(pci_dt_t));␊ |
85 | ␉␉␉new->dev.addr␉␉␉␉= pci_addr;␊ |
86 | ␉␉␉new->vendor_id␉␉␉␉= id & 0xffff;␊ |
87 | ␉␉␉new->device_id␉␉␉␉= (id >> 16) & 0xffff;␊ |
88 | ␉␉␉new->subsys_id.subsys_id␉= pci_config_read32(pci_addr, PCI_SUBSYSTEM_VENDOR_ID);␊ |
89 | ␉␉␉new->class_id␉␉␉␉= pci_config_read16(pci_addr, PCI_CLASS_DEVICE);␊ |
90 | ␉␉␉new->parent␉= start;␊ |
91 | ␊ |
92 | ␉␉␉header_type = pci_config_read8(pci_addr, PCI_HEADER_TYPE);␊ |
93 | ␉␉␉switch (header_type & 0x7f) {␊ |
94 | ␉␉␉case PCI_HEADER_TYPE_BRIDGE:␊ |
95 | ␉␉␉case PCI_HEADER_TYPE_CARDBUS:␊ |
96 | ␉␉␉␉secondary_bus = pci_config_read8(pci_addr, PCI_SECONDARY_BUS);␊ |
97 | ␉␉␉␉if (secondary_bus != 0) {␊ |
98 | ␉␉␉␉␉scan_pci_bus(new, secondary_bus);␊ |
99 | ␉␉␉␉}␊ |
100 | ␉␉␉␉break;␊ |
101 | ␉␉␉}␊ |
102 | ␉␉␉*current = new;␊ |
103 | ␉␉␉current = &new->next;␊ |
104 | ␊ |
105 | ␉␉␉if ((func == 0) && ((header_type & 0x80) == 0)) {␊ |
106 | ␉␉␉␉break;␊ |
107 | ␉␉␉}␊ |
108 | ␉␉}␊ |
109 | ␉}␊ |
110 | }␊ |
111 | ␊ |
112 | void enable_pci_devs(void)␊ |
113 | {␊ |
114 | ␉uint16_t id;␊ |
115 | ␉uint32_t rcba, *fd;␊ |
116 | ␊ |
117 | ␉id = pci_config_read16(PCIADDR(0, 0x00, 0), 0x00);␊ |
118 | ␉/* make sure we're on Intel chipset */␊ |
119 | ␉if (id != 0x8086)␊ |
120 | ␉␉return;␊ |
121 | ␉rcba = pci_config_read32(PCIADDR(0, 0x1f, 0), 0xf0) & ~1;␊ |
122 | ␉fd = (uint32_t *)(rcba + 0x3418);␊ |
123 | ␉/* set SMBus Disable (SD) to 0 */␊ |
124 | ␉*fd &= ~0x8;␊ |
125 | ␉/* and all devices? */␊ |
126 | ␉//*fd = 0x1;␊ |
127 | }␊ |
128 | ␊ |
129 | ␊ |
130 | void build_pci_dt(void)␊ |
131 | {␊ |
132 | ␉root_pci_dev = malloc(sizeof(pci_dt_t));␊ |
133 | ␉bzero(root_pci_dev, sizeof(pci_dt_t));␊ |
134 | ␉enable_pci_devs();␊ |
135 | ␉scan_pci_bus(root_pci_dev, 0);␊ |
136 | ␊ |
137 | #if DEBUG_PCI␊ |
138 | ␉dump_pci_dt(root_pci_dev->children);␊ |
139 | ␉pause();␊ |
140 | #endif␊ |
141 | }␊ |
142 | ␊ |
143 | static char dev_path[256];␊ |
144 | char *get_pci_dev_path(pci_dt_t *pci_dt)␊ |
145 | {␊ |
146 | ␉pci_dt_t␉*current;␊ |
147 | ␉pci_dt_t␉*end;␊ |
148 | ␉char␉␉tmp[64];␊ |
149 | ␊ |
150 | ␉dev_path[0] = 0;␊ |
151 | ␉end = root_pci_dev;␊ |
152 | ␉␊ |
153 | ␉int uid = 0; //getPciRootUID();␊ |
154 | ␉while (end != pci_dt)␊ |
155 | ␉{␊ |
156 | ␉␉current = pci_dt;␊ |
157 | ␉␉while (current->parent != end)␊ |
158 | ␉␉␉current = current->parent;␉␉␉␊ |
159 | ␉␉end = current;␊ |
160 | ␉␉if (current->parent == root_pci_dev)␊ |
161 | ␉␉{␊ |
162 | ␉␉␉sprintf(tmp, "PciRoot(0x%x)/Pci(0x%x,0x%x)", uid, ␊ |
163 | ␉␉␉␉current->dev.bits.dev, current->dev.bits.func);␊ |
164 | ␉␉} else {␊ |
165 | ␉␉␉sprintf(tmp, "/Pci(0x%x,0x%x)", ␊ |
166 | ␉␉␉␉current->dev.bits.dev, current->dev.bits.func);␊ |
167 | ␉␉}␊ |
168 | ␉␉strcat(dev_path, tmp);␊ |
169 | ␉}␊ |
170 | ␉return dev_path;␊ |
171 | }␊ |
172 | ␊ |
173 | void dump_pci_dt(pci_dt_t *pci_dt)␊ |
174 | {␊ |
175 | ␉pci_dt_t␉*current;␊ |
176 | ␊ |
177 | ␉current = pci_dt;␊ |
178 | ␉while (current) {␊ |
179 | ␉␉printf("%02x:%02x.%x [%04x] [%04x:%04x] (subsys [%04x:%04x]):: %s\n", ␊ |
180 | ␉␉␉current->dev.bits.bus, current->dev.bits.dev, current->dev.bits.func, ␊ |
181 | ␉␉␉current->class_id, current->vendor_id, current->device_id, ␊ |
182 | ␉␉␉current->subsys_id.subsys.vendor_id, current->subsys_id.subsys.device_id, ␊ |
183 | ␉␉␉get_pci_dev_path(current));␊ |
184 | ␉␉dump_pci_dt(current->children);␊ |
185 | ␉␉current = current->next;␊ |
186 | ␉}␊ |
187 | }␊ |
188 |