1 | /*␊ |
2 | * Add (c) here␊ |
3 | *␊ |
4 | * Copyright .... All rights reserved.␊ |
5 | *␊ |
6 | */␊ |
7 | ␊ |
8 | #include "smbios_getters.h"␊ |
9 | #include "modules.h"␊ |
10 | ␊ |
11 | #ifndef DEBUG_SMBIOS␊ |
12 | #define DEBUG_SMBIOS 0␊ |
13 | #endif␊ |
14 | ␊ |
15 | #if DEBUG_SMBIOS␊ |
16 | #define DBG(x...)␉printf(x)␊ |
17 | #else␊ |
18 | #define DBG(x...)␊ |
19 | #endif␊ |
20 | ␊ |
21 | ␊ |
22 | bool getProcessorInformationExternalClock(returnType *value)␊ |
23 | {␊ |
24 | ␉value->word = Platform->CPU.FSBFrequency/1000000;␊ |
25 | ␉return true;␊ |
26 | }␊ |
27 | ␊ |
28 | bool getProcessorInformationMaximumClock(returnType *value)␊ |
29 | {␊ |
30 | ␉value->word = Platform->CPU.CPUFrequency/1000000;␊ |
31 | ␉return true;␊ |
32 | }␊ |
33 | ␊ |
34 | bool getSMBOemProcessorBusSpeed(returnType *value)␊ |
35 | {␊ |
36 | ␉if (Platform->CPU.Vendor == 0x756E6547) // Intel␊ |
37 | ␉{␉␉␊ |
38 | ␉␉switch (Platform->CPU.Family) ␊ |
39 | ␉␉{␊ |
40 | ␉␉␉case 0x06:␊ |
41 | ␉␉␉{␊ |
42 | ␉␉␉␉switch (Platform->CPU.Model)␊ |
43 | ␉␉␉␉{␊ |
44 | ␉␉␉␉␉case 0x0D:␉␉␉␉␉// ?␊ |
45 | ␉␉␉␉␉case CPU_MODEL_YONAH:␉␉// Yonah␉␉0x0E␊ |
46 | ␉␉␉␉␉case CPU_MODEL_MEROM:␉␉// Merom␉␉0x0F␊ |
47 | ␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉// Penryn␉␉0x17␊ |
48 | ␉␉␉␉␉case CPU_MODEL_ATOM:␉␉// Atom 45nm␉0x1C␊ |
49 | ␉␉␉␉␉␉return false;␊ |
50 | ␊ |
51 | ␉␉␉␉␉case 0x19:␉␉␉␉␉// Intel Core i5 650 @3.20 Ghz␊ |
52 | ␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉// Intel Core i7 LGA1366 (45nm)␊ |
53 | ␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉// Intel Core i5, i7 LGA1156 (45nm)␊ |
54 | ␉␉␉␉␉case CPU_MODEL_DALES:␉␉// Intel Core i5, i7 LGA1156 (45nm) ???␊ |
55 | ␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉// Intel Core i3, i5, i7 LGA1156 (32nm)␊ |
56 | ␉␉␉␉␉case CPU_MODEL_WESTMERE:␉// Intel Core i7 LGA1366 (32nm) 6 Core␊ |
57 | ␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␉// Intel Core i7 LGA1366 (45nm) 6 Core ???␊ |
58 | ␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉// Intel Core i7 LGA1366 (45nm) 6 Core ???␊ |
59 | ␉␉␉␉␉{␊ |
60 | ␉␉␉␉␉␉// thanks to dgobe for i3/i5/i7 bus speed detection␊ |
61 | ␉␉␉␉␉␉int nhm_bus = 0x3F;␊ |
62 | ␉␉␉␉␉␉static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};␊ |
63 | ␉␉␉␉␉␉unsigned long did, vid;␊ |
64 | ␉␉␉␉␉␉int i;␊ |
65 | ␉␉␉␉␉␉␊ |
66 | ␉␉␉␉␉␉// Nehalem supports Scrubbing␊ |
67 | ␉␉␉␉␉␉// First, locate the PCI bus where the MCH is located␊ |
68 | ␉␉␉␉␉␉for(i = 0; i < sizeof(possible_nhm_bus); i++)␊ |
69 | ␉␉␉␉␉␉{␊ |
70 | ␉␉␉␉␉␉␉vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x00);␊ |
71 | ␉␉␉␉␉␉␉did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x02);␊ |
72 | ␉␉␉␉␉␉␉vid &= 0xFFFF;␊ |
73 | ␉␉␉␉␉␉␉did &= 0xFF00;␊ |
74 | ␉␉␉␉␉␉␉␊ |
75 | ␉␉␉␉␉␉␉if(vid == 0x8086 && did >= 0x2C00)␊ |
76 | ␉␉␉␉␉␉␉␉nhm_bus = possible_nhm_bus[i]; ␊ |
77 | ␉␉␉␉␉␉}␊ |
78 | ␉␉␉␉␉␉␊ |
79 | ␉␉␉␉␉␉unsigned long qpimult, qpibusspeed;␊ |
80 | ␉␉␉␉␉␉qpimult = pci_config_read32(PCIADDR(nhm_bus, 2, 1), 0x50);␊ |
81 | ␉␉␉␉␉␉qpimult &= 0x7F;␊ |
82 | ␉␉␉␉␉␉DBG("qpimult %d\n", qpimult);␊ |
83 | ␉␉␉␉␉␉qpibusspeed = (qpimult * 2 * (Platform->CPU.FSBFrequency/1000000));␊ |
84 | ␉␉␉␉␉␉// Rek: rounding decimals to match original mac profile info␊ |
85 | ␉␉␉␉␉␉if (qpibusspeed%100 != 0)qpibusspeed = ((qpibusspeed+50)/100)*100;␊ |
86 | ␉␉␉␉␉␉DBG("qpibusspeed %d\n", qpibusspeed);␊ |
87 | ␉␉␉␉␉␉value->word = qpibusspeed;␊ |
88 | ␉␉␉␉␉␉return true;␊ |
89 | ␉␉␉␉␉}␊ |
90 | ␉␉␉␉}␊ |
91 | ␉␉␉}␊ |
92 | ␉␉}␊ |
93 | ␉}␊ |
94 | ␉return false;␊ |
95 | }␊ |
96 | ␊ |
97 | uint16_t simpleGetSMBOemProcessorType(void)␊ |
98 | {␊ |
99 | ␉if (Platform->CPU.NoCores >= 4) ␊ |
100 | ␉{␊ |
101 | ␉␉return 0x0501;␉// Quad-Core Xeon␊ |
102 | ␉}␊ |
103 | ␉else if (Platform->CPU.NoCores == 1) ␊ |
104 | ␉{␊ |
105 | ␉␉return 0x0201;␉// Core Solo␊ |
106 | ␉};␊ |
107 | ␉␊ |
108 | ␉return 0x0301;␉␉// Core 2 Duo␊ |
109 | }␊ |
110 | ␊ |
111 | bool getSMBOemProcessorType(returnType *value)␊ |
112 | {␊ |
113 | ␉static bool done = false;␉␉␊ |
114 | ␉␉␊ |
115 | ␉value->word = simpleGetSMBOemProcessorType();␊ |
116 | ␊ |
117 | ␉if (Platform->CPU.Vendor == 0x756E6547) // Intel␊ |
118 | ␉{␊ |
119 | ␉␉if (!done)␊ |
120 | ␉␉{␊ |
121 | ␉␉␉verbose("CPU is %s, family 0x%x, model 0x%x\n", Platform->CPU.BrandString, Platform->CPU.Family, Platform->CPU.Model);␊ |
122 | ␉␉␉done = true;␊ |
123 | ␉␉}␊ |
124 | ␉␉␊ |
125 | ␉␉switch (Platform->CPU.Family) ␊ |
126 | ␉␉{␊ |
127 | ␉␉␉case 0x06:␊ |
128 | ␉␉␉{␊ |
129 | ␉␉␉␉switch (Platform->CPU.Model)␊ |
130 | ␉␉␉␉{␊ |
131 | ␉␉␉␉␉case 0x0D:␉␉␉␉␉␉␉// ?␊ |
132 | ␉␉␉␉␉case CPU_MODEL_YONAH:␉␉␉␉// Yonah␊ |
133 | ␉␉␉␉␉case CPU_MODEL_MEROM:␉␉␉␉// Merom␊ |
134 | ␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉␉␉// Penryn␊ |
135 | ␉␉␉␉␉case CPU_MODEL_ATOM:␉␉␉␉// Intel Atom (45nm)␊ |
136 | ␉␉␉␉␉␉return true;␊ |
137 | ␊ |
138 | ␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉␉␉// Intel Core i7 LGA1366 (45nm)␊ |
139 | ␉␉␉␉␉␉value->word = 0x0701;␉␉␉// Core i7␊ |
140 | ␉␉␉␉␉␉return true;␊ |
141 | ␊ |
142 | ␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉␉␉// Lynnfield, Clarksfield, Jasper␊ |
143 | ␉␉␉␉␉␉if (strstr(Platform->CPU.BrandString, "Core(TM) i5"))␊ |
144 | ␉␉␉␉␉␉␉value->word = 0x601;␉␉// Core i5␊ |
145 | ␉␉␉␉␉␉else␊ |
146 | ␉␉␉␉␉␉␉value->word = 0x701;␉␉// Core i7␊ |
147 | ␉␉␉␉␉␉return true;␊ |
148 | ␊ |
149 | ␉␉␉␉␉case CPU_MODEL_DALES:␉␉␉␉// Intel Core i5, i7 LGA1156 (45nm) (Havendale, Auburndale)␊ |
150 | ␉␉␉␉␉␉if (strstr(Platform->CPU.BrandString, "Core(TM) i5"))␊ |
151 | ␉␉␉␉␉␉␉value->word = 0x601;␉␉// Core i5␊ |
152 | ␉␉␉␉␉␉else␊ |
153 | ␉␉␉␉␉␉␉value->word = 0x0701;␉␉// Core i7␊ |
154 | ␉␉␉␉␉␉return true;␊ |
155 | ␊ |
156 | ␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉␉␉// Intel Core i3, i5, i7 LGA1156 (32nm) (Clarkdale, Arrandale)␊ |
157 | ␉␉␉␉␉␉if (strstr(Platform->CPU.BrandString, "Core(TM) i3"))␊ |
158 | ␉␉␉␉␉␉␉␉value->word = 0x901;␉// Core i3␊ |
159 | ␉␉␉␉␉␉else if (strstr(Platform->CPU.BrandString, "Core(TM) i5"))␊ |
160 | ␉␉␉␉␉␉␉␉value->word = 0x601;␉// Core i5␊ |
161 | ␉␉␉␉␉␉else if (strstr(Platform->CPU.BrandString, "Core(TM) i7"))␊ |
162 | ␉␉␉␉␉␉␉␉value->word = 0x0701;␉// Core i7␊ |
163 | ␉␉␉␉␉␉else ␊ |
164 | ␉␉␉␉␉␉␉␉value->word = simpleGetSMBOemProcessorType();␊ |
165 | ␉␉␉␉␉␉return true;␊ |
166 | ␊ |
167 | ␉␉␉␉␉case CPU_MODEL_WESTMERE:␉␉␉// Intel Core i7 LGA1366 (32nm) 6 Core (Gulftown, Westmere-EP, Westmere-WS)␊ |
168 | ␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉␉␉// Intel Core i7 LGA1366 (45nm) 6 Core ???␊ |
169 | ␉␉␉␉␉␉value->word = 0x0701;␉␉␉// Core i7␊ |
170 | ␉␉␉␉␉␉return true;␊ |
171 | ␊ |
172 | ␉␉␉␉␉case 0x19:␉␉␉␉␉␉␉// Intel Core i5 650 @3.20 Ghz␊ |
173 | ␉␉␉␉␉␉value->word = 0x601;␉␉␉// Core i5␊ |
174 | ␉␉␉␉␉␉return true;␊ |
175 | ␉␉␉␉}␊ |
176 | ␉␉␉}␊ |
177 | ␉␉}␊ |
178 | ␉}␊ |
179 | ␉␊ |
180 | ␉return false;␊ |
181 | }␊ |
182 | ␊ |
183 | bool getSMBMemoryDeviceMemoryType(returnType *value)␊ |
184 | {␊ |
185 | ␉static int idx = -1;␊ |
186 | ␉if (is_module_loaded("Memory")) {␊ |
187 | ␉int␉map;␊ |
188 | ␊ |
189 | ␉idx++;␊ |
190 | ␉if (idx < MAX_RAM_SLOTS)␊ |
191 | ␉{␊ |
192 | ␉␉map = Platform->DMI.DIMM[idx];␊ |
193 | ␉␉if (Platform->RAM.DIMM[map].InUse && Platform->RAM.DIMM[map].Type != 0)␊ |
194 | ␉␉{␊ |
195 | ␉␉␉DBG("RAM Detected Type = %d\n", Platform->RAM.DIMM[map].Type);␊ |
196 | ␉␉␉value->byte = Platform->RAM.DIMM[map].Type;␊ |
197 | ␉␉␉return true;␊ |
198 | ␉␉}␊ |
199 | ␉}␊ |
200 | }␊ |
201 | ␉//return false;␊ |
202 | ␉value->byte = SMB_MEM_TYPE_DDR2;␊ |
203 | ␉return true;␊ |
204 | }␊ |
205 | ␊ |
206 | bool getSMBMemoryDeviceMemorySpeed(returnType *value)␊ |
207 | {␊ |
208 | ␉static int idx = -1;␊ |
209 | ␉if (is_module_loaded("Memory")) {␊ |
210 | ␉int␉map;␊ |
211 | ␊ |
212 | ␉idx++;␊ |
213 | ␉if (idx < MAX_RAM_SLOTS)␊ |
214 | ␉{␊ |
215 | ␉␉map = Platform->DMI.DIMM[idx];␊ |
216 | ␉␉if (Platform->RAM.DIMM[map].InUse && Platform->RAM.DIMM[map].Frequency != 0)␊ |
217 | ␉␉{␊ |
218 | ␉␉␉DBG("RAM Detected Freq = %d Mhz\n", Platform->RAM.DIMM[map].Frequency);␊ |
219 | ␉␉␉value->dword = Platform->RAM.DIMM[map].Frequency;␊ |
220 | ␉␉␉return true;␊ |
221 | ␉␉}␊ |
222 | ␉}␊ |
223 | }␊ |
224 | ␉//return false;␊ |
225 | ␉value->dword = 800;␊ |
226 | ␉return true;␊ |
227 | }␊ |
228 | ␊ |
229 | bool getSMBMemoryDeviceManufacturer(returnType *value)␊ |
230 | {␊ |
231 | ␉static int idx = -1;␊ |
232 | ␉if (is_module_loaded("Memory")) {␊ |
233 | ␉int␉map;␊ |
234 | ␊ |
235 | ␉idx++;␊ |
236 | ␉if (idx < MAX_RAM_SLOTS)␊ |
237 | ␉{␊ |
238 | ␉␉map = Platform->DMI.DIMM[idx];␊ |
239 | ␉␉if (Platform->RAM.DIMM[map].InUse && strlen(Platform->RAM.DIMM[map].Vendor) > 0)␊ |
240 | ␉␉{␊ |
241 | ␉␉␉DBG("RAM Detected Vendor[%d]='%s'\n", idx, Platform->RAM.DIMM[map].Vendor);␊ |
242 | ␉␉␉value->string = Platform->RAM.DIMM[map].Vendor;␊ |
243 | ␉␉␉return true;␊ |
244 | ␉␉}␊ |
245 | ␉}␊ |
246 | }␊ |
247 | ␉//return false;␊ |
248 | ␉value->string = "N/A";␊ |
249 | ␉return true;␊ |
250 | }␊ |
251 | ␉␊ |
252 | bool getSMBMemoryDeviceSerialNumber(returnType *value)␊ |
253 | {␊ |
254 | ␉static int idx = -1;␊ |
255 | ␉if (is_module_loaded("Memory")) {␊ |
256 | ␉int␉map;␊ |
257 | ␊ |
258 | ␉idx++;␊ |
259 | ␉if (idx < MAX_RAM_SLOTS)␊ |
260 | ␉{␊ |
261 | ␉␉map = Platform->DMI.DIMM[idx];␊ |
262 | ␉␉if (Platform->RAM.DIMM[map].InUse && strlen(Platform->RAM.DIMM[map].SerialNo) > 0)␊ |
263 | ␉␉{␊ |
264 | ␉␉␉DBG("name = %s, map=%d, RAM Detected SerialNo[%d]='%s'\n", name ? name : "", ␊ |
265 | ␉␉␉␉map, idx, Platform->RAM.DIMM[map].SerialNo);␊ |
266 | ␉␉␉value->string = Platform->RAM.DIMM[map].SerialNo;␊ |
267 | ␉␉␉return true;␊ |
268 | ␉␉}␊ |
269 | ␉}␊ |
270 | }␊ |
271 | ␉//return false;␊ |
272 | ␉value->string = "N/A";␊ |
273 | ␉return true;␊ |
274 | }␊ |
275 | ␊ |
276 | bool getSMBMemoryDevicePartNumber(returnType *value)␊ |
277 | {␊ |
278 | ␉static int idx = -1;␊ |
279 | ␉if (is_module_loaded("Memory")) {␊ |
280 | ␉int␉map;␊ |
281 | ␊ |
282 | ␉idx++;␊ |
283 | ␉if (idx < MAX_RAM_SLOTS)␊ |
284 | ␉{␊ |
285 | ␉␉map = Platform->DMI.DIMM[idx];␊ |
286 | ␉␉if (Platform->RAM.DIMM[map].InUse && strlen(Platform->RAM.DIMM[map].PartNo) > 0)␊ |
287 | ␉␉{␊ |
288 | ␉␉␉DBG("Ram Detected PartNo[%d]='%s'\n", idx, Platform->RAM.DIMM[map].PartNo);␊ |
289 | ␉␉␉value->string = Platform->RAM.DIMM[map].PartNo;␊ |
290 | ␉␉␉return true;␊ |
291 | ␉␉}␊ |
292 | ␉}␊ |
293 | ␉}␊ |
294 | ␉//return false;␊ |
295 | ␉value->string = "N/A";␊ |
296 | ␉return true;␊ |
297 | }␊ |
298 | |