1 | /*␊ |
2 | * Copyright 2008 Islam Ahmed Zaid. All rights reserved. <azismed@gmail.com>␊ |
3 | * AsereBLN: 2009: cleanup and bugfix␊ |
4 | * valv: 2010: fine-tuning and additions␊ |
5 | */␊ |
6 | ␊ |
7 | #include "libsaio.h"␊ |
8 | #include "platform.h"␊ |
9 | #include "cpu.h"␊ |
10 | #include "boot.h"␊ |
11 | #include "bootstruct.h"␊ |
12 | ␊ |
13 | #ifndef DEBUG_CPU␊ |
14 | #define DEBUG_CPU 0␊ |
15 | #endif␊ |
16 | ␊ |
17 | #if DEBUG_CPU␊ |
18 | #define DBG(x...)␉␉printf(x)␊ |
19 | #else␊ |
20 | #define DBG(x...)␉␉msglog(x)␊ |
21 | #endif␊ |
22 | ␊ |
23 | /*␊ |
24 | * DFE: Measures the TSC frequency in Hz (64-bit) using the ACPI PM timer␊ |
25 | */␊ |
26 | static uint64_t measure_tsc_frequency(void)␊ |
27 | {␊ |
28 | uint64_t tscStart;␊ |
29 | uint64_t tscEnd;␊ |
30 | uint64_t tscDelta = 0xffffffffffffffffULL;␊ |
31 | unsigned long pollCount;␊ |
32 | uint64_t retval = 0;␊ |
33 | int i;␊ |
34 | ␊ |
35 | /* Time how many TSC ticks elapse in 30 msec using the 8254 PIT␊ |
36 | * counter 2. We run this loop 3 times to make sure the cache␊ |
37 | * is hot and we take the minimum delta from all of the runs.␊ |
38 | * That is to say that we're biased towards measuring the minimum␊ |
39 | * number of TSC ticks that occur while waiting for the timer to␊ |
40 | * expire. That theoretically helps avoid inconsistencies when␊ |
41 | * running under a VM if the TSC is not virtualized and the host␊ |
42 | * steals time. The TSC is normally virtualized for VMware.␊ |
43 | */␊ |
44 | for(i = 0; i < 10; ++i)␊ |
45 | {␊ |
46 | enable_PIT2();␊ |
47 | set_PIT2_mode0(CALIBRATE_LATCH);␊ |
48 | tscStart = rdtsc64();␊ |
49 | pollCount = poll_PIT2_gate();␊ |
50 | tscEnd = rdtsc64();␊ |
51 | /* The poll loop must have run at least a few times for accuracy */␊ |
52 | if(pollCount <= 1)␊ |
53 | continue;␊ |
54 | /* The TSC must increment at LEAST once every millisecond. We␊ |
55 | * should have waited exactly 30 msec so the TSC delta should␊ |
56 | * be >= 30. Anything less and the processor is way too slow.␊ |
57 | */␊ |
58 | if((tscEnd - tscStart) <= CALIBRATE_TIME_MSEC)␊ |
59 | continue;␊ |
60 | // tscDelta = min(tscDelta, (tscEnd - tscStart))␊ |
61 | if( (tscEnd - tscStart) < tscDelta )␊ |
62 | tscDelta = tscEnd - tscStart;␊ |
63 | }␊ |
64 | /* tscDelta is now the least number of TSC ticks the processor made in␊ |
65 | * a timespan of 0.03 s (e.g. 30 milliseconds)␊ |
66 | * Linux thus divides by 30 which gives the answer in kiloHertz because␊ |
67 | * 1 / ms = kHz. But we're xnu and most of the rest of the code uses␊ |
68 | * Hz so we need to convert our milliseconds to seconds. Since we're␊ |
69 | * dividing by the milliseconds, we simply multiply by 1000.␊ |
70 | */␊ |
71 | ␊ |
72 | /* Unlike linux, we're not limited to 32-bit, but we do need to take care␊ |
73 | * that we're going to multiply by 1000 first so we do need at least some␊ |
74 | * arithmetic headroom. For now, 32-bit should be enough.␊ |
75 | * Also unlike Linux, our compiler can do 64-bit integer arithmetic.␊ |
76 | */␊ |
77 | if(tscDelta > (1ULL<<32))␊ |
78 | retval = 0;␊ |
79 | else␊ |
80 | {␊ |
81 | retval = tscDelta * 1000 / 30;␊ |
82 | }␊ |
83 | disable_PIT2();␊ |
84 | return retval;␊ |
85 | }␊ |
86 | ␊ |
87 | ␊ |
88 | /*␊ |
89 | * Calculates the FSB and CPU frequencies using specific MSRs for each CPU␊ |
90 | * - multi. is read from a specific MSR. In the case of Intel, there is:␊ |
91 | * a max multi. (used to calculate the FSB freq.),␊ |
92 | * and a current multi. (used to calculate the CPU freq.)␊ |
93 | * - fsbFrequency = tscFrequency / multi␊ |
94 | * - cpuFrequency = fsbFrequency * multi␊ |
95 | */␊ |
96 | ␊ |
97 | void scan_cpu(PlatformInfo_t *p)␊ |
98 | {␊ |
99 | ␉const char␉*newratio, *newfsb;␊ |
100 | ␉int␉␉␉len, myfsb, i;␊ |
101 | ␉uint64_t␉tscFrequency, fsbFrequency, cpuFrequency, fsbi;␊ |
102 | ␉uint64_t␉msr, flex_ratio = 0;␊ |
103 | ␉uint32_t␉tms, ida, max_ratio, min_ratio;␊ |
104 | ␉uint8_t␉␉bus_ratio_max, maxdiv, bus_ratio_min, currdiv;␊ |
105 | ␉bool␉␉fix_fsb, did, core_i, turbo, isatom, fsbad;␊ |
106 | ␊ |
107 | ␉max_ratio = min_ratio = myfsb = bus_ratio_max = maxdiv = bus_ratio_min = currdiv = i = 0;␊ |
108 | ␊ |
109 | ␉/* get cpuid values */␊ |
110 | ␉for( ; i <= 3; i++)␊ |
111 | ␉{␊ |
112 | ␉␉do_cpuid(i, p->CPU.CPUID[i]);␊ |
113 | ␉}␊ |
114 | ␉␊ |
115 | ␉do_cpuid2(0x00000004, 0, p->CPU.CPUID[CPUID_4]);␊ |
116 | ␉do_cpuid(0x80000000, p->CPU.CPUID[CPUID_80]);␊ |
117 | ␉if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 1) {␊ |
118 | ␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊ |
119 | ␉}␊ |
120 | #if DEBUG_CPU␊ |
121 | ␉{␊ |
122 | ␉␉int␉␉i;␊ |
123 | ␉␉printf("CPUID Raw Values:\n");␊ |
124 | ␉␉for (i=0; i<CPUID_MAX; i++) {␊ |
125 | ␉␉␉printf("%02d: %08x-%08x-%08x-%08x\n", i,␊ |
126 | ␉␉␉␉p->CPU.CPUID[i][0], p->CPU.CPUID[i][1],␊ |
127 | ␉␉␉␉p->CPU.CPUID[i][2], p->CPU.CPUID[i][3]);␊ |
128 | ␉␉}␊ |
129 | ␉}␊ |
130 | #endif␊ |
131 | ␉p->CPU.Vendor␉␉= p->CPU.CPUID[CPUID_0][1];␊ |
132 | ␉p->CPU.Signature␉= p->CPU.CPUID[CPUID_1][0];␊ |
133 | ␉p->CPU.Stepping␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 3, 0);␊ |
134 | ␉p->CPU.Model␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 7, 4);␊ |
135 | ␉p->CPU.Type␉␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 13, 12);␊ |
136 | ␉p->CPU.Family␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 11, 8);␊ |
137 | ␉p->CPU.ExtModel␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 19, 16);␊ |
138 | ␉p->CPU.ExtFamily␉= bitfield(p->CPU.CPUID[CPUID_1][0], 27, 20);␊ |
139 | ␉p->CPU.NoThreads␉= bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␊ |
140 | ␉if(p->CPU.Vendor == 0x68747541)␊ |
141 | ␉{␊ |
142 | ␉␉do_cpuid(0x80000008, p->CPU.CPUID[8]);␊ |
143 | ␉␉p->CPU.NoCores␉␉= bitfield(p->CPU.CPUID[8][2], 7, 0) + 1;␊ |
144 | ␉}␊ |
145 | ␉else␊ |
146 | ␉␉p->CPU.NoCores␉␉= bitfield(p->CPU.CPUID[CPUID_4][0], 31, 26) + 1;␊ |
147 | ␊ |
148 | ␉p->CPU.Model += (p->CPU.ExtModel << 4);␊ |
149 | ␊ |
150 | ␉/* get brand string (if supported) */␊ |
151 | ␉/* Copyright: from Apple's XNU cpuid.c */␊ |
152 | ␉if (p->CPU.CPUID[CPUID_80][0] > 0x80000004) {␊ |
153 | ␉␉uint32_t␉reg[4];␊ |
154 | char str[128], *s;␊ |
155 | ␉␉/*␊ |
156 | ␉␉ * The brand string 48 bytes (max), guaranteed to␊ |
157 | ␉␉ * be NUL terminated.␊ |
158 | ␉␉ */␊ |
159 | ␉␉do_cpuid(0x80000002, reg);␊ |
160 | ␉␉bcopy((char *)reg, &str[0], 16);␊ |
161 | ␉␉do_cpuid(0x80000003, reg);␊ |
162 | ␉␉bcopy((char *)reg, &str[16], 16);␊ |
163 | ␉␉do_cpuid(0x80000004, reg);␊ |
164 | ␉␉bcopy((char *)reg, &str[32], 16);␊ |
165 | ␉␉for (s = str; *s != '\0'; s++) {␊ |
166 | ␉␉␉if (*s != ' ') break;␊ |
167 | ␉␉}␊ |
168 | ␉␉␊ |
169 | ␉␉strlcpy(p->CPU.BrandString,␉s, sizeof(p->CPU.BrandString));␊ |
170 | ␉␉␊ |
171 | ␉␉if (!strncmp(p->CPU.BrandString, CPU_STRING_UNKNOWN, min(sizeof(p->CPU.BrandString), strlen(CPU_STRING_UNKNOWN) + 1))) {␊ |
172 | ␉␉␉ /*␊ |
173 | ␉␉␉ * This string means we have a firmware-programmable brand string,␊ |
174 | ␉␉␉ * and the firmware couldn't figure out what sort of CPU we have.␊ |
175 | ␉␉␉ */␊ |
176 | ␉␉␉ p->CPU.BrandString[0] = '\0';␊ |
177 | ␉␉ }␊ |
178 | ␉}␊ |
179 | ␉␊ |
180 | ␉/* setup features */␊ |
181 | ␉p->CPU.Features |= (CPU_FEATURE_MMX | CPU_FEATURE_SSE | CPU_FEATURE_SSE2 | CPU_FEATURE_MSR | CPU_FEATURE_APIC | CPU_FEATURE_TM1 | CPU_FEATURE_ACPI) & p->CPU.CPUID[CPUID_1][3];␊ |
182 | ␉p->CPU.Features |= (CPU_FEATURE_SSE3 | CPU_FEATURE_SSE41 | CPU_FEATURE_SSE42 | CPU_FEATURE_EST | CPU_FEATURE_TM2 | CPU_FEATURE_SSSE3 | CPU_FEATURE_xAPIC) & p->CPU.CPUID[CPUID_1][2];␊ |
183 | ␉p->CPU.Features |= (CPU_FEATURE_EM64T | CPU_FEATURE_XD) & p->CPU.CPUID[CPUID_81][3];␊ |
184 | ␉p->CPU.Features |= (CPU_FEATURE_LAHF) & p->CPU.CPUID[CPUID_81][2];␊ |
185 | ␊ |
186 | ␊ |
187 | ␉//if ((CPU_FEATURE_HTT & p->CPU.CPUID[CPUID_1][3]) != 0) {␊ |
188 | ␉if (p->CPU.NoThreads > p->CPU.NoCores) {␊ |
189 | ␉␉p->CPU.Features |= CPU_FEATURE_HTT;␊ |
190 | ␉}␊ |
191 | ␉ ␊ |
192 | ␊ |
193 | ␉tscFrequency = measure_tsc_frequency();␊ |
194 | ␉fsbFrequency = 0;␊ |
195 | ␉cpuFrequency = 0;␊ |
196 | ␉fsbi = 0;␊ |
197 | ␉fix_fsb = false;␊ |
198 | ␉did = false;␊ |
199 | ␉core_i = false;␊ |
200 | ␉turbo = false;␊ |
201 | ␉isatom = false;␊ |
202 | ␉fsbad = false;␊ |
203 | ␊ |
204 | ␉if ((p->CPU.Vendor == 0x756E6547 /* Intel */) && ((p->CPU.Family == 0x06) || (p->CPU.Family == 0x0f)))␊ |
205 | ␉{␊ |
206 | ␉␉verbose("CPU: ");␊ |
207 | ␉␉int tjmax = 0;␊ |
208 | ␉␉msr = rdmsr64(MSR_IA32_PLATFORM_ID);␊ |
209 | ␉␉if((((msr >> 50) & 0x01) == 1) || (rdmsr64(0x17) & (1<<28)))␊ |
210 | ␉␉{␊ |
211 | ␉␉␉p->CPU.Features |= CPU_FEATURE_MOBILE;␊ |
212 | ␉␉␉verbose("Mobile ");␊ |
213 | ␉␉}␊ |
214 | ␉␉verbose("%s\n", p->CPU.BrandString);␊ |
215 | ␉␉␊ |
216 | ␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) || (p->CPU.Family == 0x0f && p->CPU.Model >= 0x03))␊ |
217 | ␉␉{␊ |
218 | ␉␉␉if (p->CPU.Family == 0x06)␊ |
219 | ␉␉␉{␊ |
220 | ␉␉␉␉// valv: to be moved!␊ |
221 | ␉␉␉␉/*if(p->CPU.CPUID[CPUID_0][0] >= 11)␊ |
222 | ␉␉␉␉{␊ |
223 | ␉␉␉␉␉if((p->CPU.CPUID[0xB][1] != 0) && (bitfield(p->CPU.CPUID[CPUID_1][3], 28, 28)))␊ |
224 | ␉␉␉␉}*/␊ |
225 | ␉␉␉␉␊ |
226 | ␉␉␉␉/*int CoreOk = 0;␊ |
227 | ␉␉␉␉int ThreadOk = 0;␊ |
228 | ␉␉␉␉int lvlType, lvlShift;␊ |
229 | ␉␉␉␉do␊ |
230 | ␉␉␉␉{␊ |
231 | ␉␉␉␉␉if(p->CPU.CPUID[0xB][1] == 0) break;␊ |
232 | ␉␉␉␉␉lvlType = bitfield(p->CPU.CPUID[0xB][2], 15, 8);␊ |
233 | ␉␉␉␉␉lvlShift = bitfield(p->CPU.CPUID[0xB][0], 4, 0);␊ |
234 | ␉␉␉␉␉switch(lvlType)␊ |
235 | ␉␉␉␉}*/␊ |
236 | ␉␉␉␉int intelCPU = p->CPU.Model;␊ |
237 | ␉␉␉␉int Stepp = p->CPU.Stepping;␊ |
238 | ␉␉␉␉int bus;␊ |
239 | ␊ |
240 | ␉␉␉␉switch (intelCPU)␊ |
241 | ␉␉␉␉{␊ |
242 | ␉␉␉␉␉// valv: hoardcoded to BrandString for now, till the code above is ready!␊ |
243 | ␉␉␉␉␉case 0x2a:␉␉// Sandy Bridge, 32nm␊ |
244 | ␉␉␉␉␉␉if((strstr(p->CPU.BrandString, "i3")) ␊ |
245 | ␉␉␉␉␉␉|| (strstr(p->CPU.BrandString, "i5-2390T")) ␊ |
246 | ␉␉␉␉␉␉|| (strstr(p->CPU.BrandString, "i5-2100S")))␊ |
247 | ␉␉␉␉␉␉␉p->CPU.NoCores = 2;␊ |
248 | ␉␉␉␉␉␉else p->CPU.NoCores = 4;␊ |
249 | ␉␉␉␉␉␉if(strstr(p->CPU.BrandString, "i7"))␊ |
250 | ␉␉␉␉␉␉␉p->CPU.NoThreads = 8;␊ |
251 | ␉␉␉␉␉␉else p->CPU.NoThreads = 4;␊ |
252 | ␉␉␉␉␉case 0xc:␉␉// Core i7 & Atom␊ |
253 | ␉␉␉␉␉␉if (strstr(p->CPU.BrandString, "Atom")) goto teleport1;␊ |
254 | ␉␉␉␉␉case 0x1a:␉␉// Core i7 LGA1366, Xeon 5500, "Bloomfield", "Gainstown", 45nm␊ |
255 | ␉␉␉␉␉case 0x1e:␉␉// Core i7, i5 LGA1156, "Clarksfield", "Lynnfield", "Jasper", 45nm␊ |
256 | ␉␉␉␉␉case 0x1f:␉␉// Core i7, i5, Nehalem␊ |
257 | ␉␉␉␉␉case 0x25:␉␉// Core i7, i5, i3 LGA1156, "Westmere", "Clarkdale", "Arrandale", 32nm␊ |
258 | ␉␉␉␉␉case 0x2c:␉␉// Core i7 LGA1366, Six-core, "Westmere", "Gulftown", 32nm␊ |
259 | ␉␉␉␉␉case 0x2e:␉␉// Core i7, Nehalem-Ex Xeon, "Beckton"␊ |
260 | ␉␉␉␉␉case 0x2f:␉␉// Core i7, Nehalem-Ex Xeon, "Eagleton"␊ |
261 | ␉␉␉␉␉␉core_i = true;␊ |
262 | ␉␉␉␉␉␉tjmax = (rdmsr64(MSR_THERMAL_TARGET) >> 16) & 0xff;␊ |
263 | ␉␉␉␉␉␉msr = rdmsr64(MSR_PLATFORM_INFO);␊ |
264 | ␉␉␉␉␉␉bus_ratio_max = (msr >> 8) & 0xff;␊ |
265 | ␉␉␉␉␉␉bus_ratio_min = (msr >> 40) & 0xff; //valv: not sure about this one (Remarq.1)␊ |
266 | ␉␉␉␉␉␉verbose("CPU: Flex-Ratio = %d ", bus_ratio_max);␊ |
267 | ␉␉␉␉␉␉min_ratio = bus_ratio_min * 10;␊ |
268 | ␉␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊ |
269 | ␉␉␉␉␉␉if ((msr >> 16) & 0x01)␊ |
270 | ␉␉␉␉␉␉{␊ |
271 | ␉␉␉␉␉␉␉flex_ratio = (msr >> 8) & 0xff;␊ |
272 | ␉␉␉␉␉␉␉verbose(">> %d", flex_ratio);␊ |
273 | ␉␉␉␉␉␉␉if(bus_ratio_max > flex_ratio) bus_ratio_max = flex_ratio;␊ |
274 | ␉␉␉␉␉␉}␊ |
275 | ␉␉␉␉␉␉verbose("\n");␊ |
276 | ␉␉␉␉␉␉if(bus_ratio_max) fsbFrequency = (tscFrequency / bus_ratio_max);␊ |
277 | ␊ |
278 | ␉␉␉␉␉␉//valv: Turbo Ratio Limit␊ |
279 | ␉␉␉␉␉␉if ((intelCPU != 0x2e) && (intelCPU != 0x2f))␊ |
280 | ␉␉␉␉␉␉{␊ |
281 | ␉␉␉␉␉␉␉turbo = true;␊ |
282 | ␉␉␉␉␉␉␉msr = rdmsr64(MSR_TURBO_RATIO_LIMIT);␊ |
283 | ␉␉␉␉␉␉␉␊ |
284 | ␉␉␉␉␉␉␉p->CPU.Tone = (msr >> 0) & 0xff;␊ |
285 | ␉␉␉␉␉␉␉p->CPU.Ttwo = (msr >> 8) & 0xff;␊ |
286 | ␉␉␉␉␉␉␉p->CPU.Tthr = (msr >> 16) & 0xff;␊ |
287 | ␉␉␉␉␉␉␉p->CPU.Tfor = (msr >> 24) & 0xff;␊ |
288 | ␊ |
289 | ␉␉␉␉␉␉␉cpuFrequency = bus_ratio_max * fsbFrequency;␊ |
290 | ␉␉␉␉␉␉␉max_ratio = bus_ratio_max * 10;␊ |
291 | ␉␉␉␉␉␉}␊ |
292 | ␉␉␉␉␉␉else cpuFrequency = tscFrequency;␊ |
293 | ␊ |
294 | ␉␉␉␉␉␉if ((getValueForKey(kbusratio, &newratio, &len, &bootInfo->bootConfig)) && (len <= 4))␊ |
295 | ␉␉␉␉␉␉{␊ |
296 | ␉␉␉␉␉␉␉max_ratio = atoi(newratio);␊ |
297 | ␉␉␉␉␉␉␉max_ratio = (max_ratio * 10);␊ |
298 | ␉␉␉␉␉␉␉if (len >= 3) max_ratio = (max_ratio + 5);␊ |
299 | ␊ |
300 | ␉␉␉␉␉␉␉verbose("Bus-Ratio: min=%d, max=%s\n", bus_ratio_min, newratio);␊ |
301 | ␊ |
302 | ␉␉␉␉␉␉␉// extreme overclockers may love 320 ;)␊ |
303 | ␉␉␉␉␉␉␉if ((max_ratio >= min_ratio) && (max_ratio <= 320))␊ |
304 | ␉␉␉␉␉␉␉{␊ |
305 | ␉␉␉␉␉␉␉␉cpuFrequency = (fsbFrequency * max_ratio) / 10;␊ |
306 | ␉␉␉␉␉␉␉␉if (len >= 3) maxdiv = 1;␊ |
307 | ␉␉␉␉␉␉␉␉else maxdiv = 0;␊ |
308 | ␉␉␉␉␉␉␉}␊ |
309 | ␉␉␉␉␉␉␉else max_ratio = (bus_ratio_max * 10);␊ |
310 | ␉␉␉␉␉␉}␊ |
311 | ␉␉␉␉␉␉//valv: to be uncommented if Remarq.1 didn't stick␊ |
312 | ␉␉␉␉␉␉/*if(bus_ratio_max > 0) bus_ratio = flex_ratio;*/␊ |
313 | ␉␉␉␉␉␉p->CPU.MaxRatio = max_ratio;␊ |
314 | ␉␉␉␉␉␉p->CPU.MinRatio = min_ratio;␊ |
315 | ␉␉␉␉␉␉␊ |
316 | ␉␉␉␉␉␉//fsbi = fsbFrequency;␊ |
317 | ␉␉␉␉␉␉if(getIntForKey(kForceFSB, &myfsb, &bootInfo->bootConfig)) goto forcefsb;␊ |
318 | ␉␉␉␉␉␉else myfsb = fsbFrequency / 1000000;␊ |
319 | ␉␉␉␉␉␉verbose("Sticking with [BCLK: %dMhz, Bus-Ratio: %s]\n", myfsb, newratio);␊ |
320 | ␉␉␉␉␉␉break;␊ |
321 | ␉␉␉␉␉case 0xd:␉␉// Pentium M, Dothan, 90nm␊ |
322 | ␉␉␉␉␉case 0xe:␉␉// Core Duo/Solo, Pentium M DC␊ |
323 | ␉␉␉␉␉␉␉teleport1:␊ |
324 | ␉␉␉␉␉␉␉msr = rdmsr64(MSR_IA32_EXT_CONFIG);␊ |
325 | ␉␉␉␉␉␉␉if(msr & (1 << 30)) tjmax = 85;␊ |
326 | ␉␉␉␉␉␉␉goto teleport2;␊ |
327 | ␉␉␉␉␉case 0xf:␉␉// Core Xeon, Core 2 DC, 65nm␊ |
328 | ␉␉␉␉␉␉switch (Stepp)␊ |
329 | ␉␉␉␉␉␉{␊ |
330 | ␉␉␉␉␉␉␉case 0x2:␊ |
331 | ␉␉␉␉␉␉␉␉tjmax = 95;␊ |
332 | ␉␉␉␉␉␉␉␉break;␊ |
333 | ␉␉␉␉␉␉␉case 0x6:␊ |
334 | ␉␉␉␉␉␉␉␉if (p->CPU.NoCores = 2) tjmax = 80;␊ |
335 | ␉␉␉␉␉␉␉␉if (p->CPU.NoCores = 4) tjmax = 90;␊ |
336 | ␉␉␉␉␉␉␉␉else tjmax = 85;␊ |
337 | ␉␉␉␉␉␉␉␉break;␊ |
338 | ␉␉␉␉␉␉␉case 0xb:␊ |
339 | ␉␉␉␉␉␉␉␉tjmax = 90;␊ |
340 | ␉␉␉␉␉␉␉␉break;␊ |
341 | ␉␉␉␉␉␉␉case 0xd:␊ |
342 | ␉␉␉␉␉␉␉default:␊ |
343 | ␉␉␉␉␉␉␉␉msr = rdmsr64(MSR_IA32_EXT_CONFIG);␊ |
344 | ␉␉␉␉␉␉␉␉if(msr & (1 << 30)) tjmax = 85;␊ |
345 | ␉␉␉␉␉␉␉␉break;␊ |
346 | ␉␉␉␉␉␉}␊ |
347 | ␉␉␉␉␉case 0x1c:␉␉// Atom :)␊ |
348 | ␉␉␉␉␉␉switch (Stepp)␊ |
349 | ␉␉␉␉␉␉{␊ |
350 | ␉␉␉␉␉␉␉case 0xa:␊ |
351 | ␉␉␉␉␉␉␉␉tjmax = 100;␊ |
352 | ␉␉␉␉␉␉␉␉break;␊ |
353 | ␉␉␉␉␉␉␉case 0x2:␊ |
354 | ␉␉␉␉␉␉␉default:␊ |
355 | ␉␉␉␉␉␉␉␉tjmax = 90;␊ |
356 | ␉␉␉␉␉␉␉␉break;␊ |
357 | ␉␉␉␉␉␉}␊ |
358 | ␉␉␉␉␉case 0x17:␉␉// Core 2 Duo/Extreme, Xeon, 45nm␊ |
359 | ␉␉␉␉␉␉switch (Stepp)␊ |
360 | ␉␉␉␉␉␉{␊ |
361 | ␉␉␉␉␉␉␉case 0x6:␉␉// Mobile Core2 Duo␊ |
362 | ␉␉␉␉␉␉␉␉tjmax = 104;␊ |
363 | ␉␉␉␉␉␉␉␉break;␊ |
364 | ␉␉␉␉␉␉␉case 0xa:␉␉// Mobile Centrino 2␊ |
365 | ␉␉␉␉␉␉␉␉tjmax = 105;␊ |
366 | ␉␉␉␉␉␉␉␉break;␊ |
367 | ␉␉␉␉␉␉␉default:␊ |
368 | ␉␉␉␉␉␉␉␉if (platformCPUFeature(CPU_FEATURE_MOBILE)) tjmax = 105;␊ |
369 | ␉␉␉␉␉␉␉␉break;␊ |
370 | ␉␉␉␉␉␉}␊ |
371 | ␉␉␉␉␉case 0x16:␉␉// Celeron, Core 2 SC, 65nm␊ |
372 | ␉␉␉␉␉case 0x27:␉␉// Atom Lincroft, 45nm␊ |
373 | ␉␉␉␉␉␉teleport2:␊ |
374 | ␉␉␉␉␉␉core_i = false;␊ |
375 | ␉␉␉␉␉␉//valv: todo: msr_therm2_ctl (0x19d) bit 16 (mode of automatic thermal monitor): 0=tm1, 1=tm2␊ |
376 | ␉␉␉␉␉␉//also, if bit 3 of misc_enable is cleared the above would have no effect␊ |
377 | ␉␉␉␉␉␉if (strstr(p->CPU.BrandString, "Atom"))␊ |
378 | ␉␉␉␉␉␉␉isatom = true;␊ |
379 | ␉␉␉␉␉␉if(!isatom && (platformCPUFeature(CPU_FEATURE_TM1)))␊ |
380 | ␉␉␉␉␉␉{␊ |
381 | ␉␉␉␉␉␉␉msr_t msr32;␊ |
382 | ␉␉␉␉␉␉␉msr32 = rdmsr(MSR_IA32_MISC_ENABLE);␊ |
383 | ␉␉␉␉␉␉␉bool tmfix = false;␊ |
384 | ␉␉␉␉␉␉␉getBoolForKey(kFixTM, &tmfix, &bootInfo->bootConfig);␊ |
385 | ␉␉␉␉␉␉␉if(tmfix)␊ |
386 | ␉␉␉␉␉␉␉{␉␊ |
387 | ␉␉␉␉␉␉␉␉//thermally-initiated on-die modulation of the stop-clock duty cycle␊ |
388 | ␉␉␉␉␉␉␉␉if(!(rdmsr64(MSR_IA32_MISC_ENABLE) & (1 << 3))) msr32.lo |= (1 << 3);␊ |
389 | ␉␉␉␉␉␉␉␉verbose("CPU: Thermal Monitor: TM, ");␊ |
390 | ␉␉␉␉␉␉␉␉␊ |
391 | ␉␉␉␉␉␉␉␉//BIOS must enable this feature if the TM2 feature flag (CPUID.1:ECX[8]) is set␊ |
392 | ␉␉␉␉␉␉␉␉if(platformCPUFeature(CPU_FEATURE_TM2))␊ |
393 | ␉␉␉␉␉␉␉␉{␊ |
394 | ␉␉␉␉␉␉␉␉␉//thermally-initiated frequency transitions␊ |
395 | ␉␉␉␉␉␉␉␉␉msr32.lo |= (1 << 13);␊ |
396 | ␉␉␉␉␉␉␉␉␉verbose("TM2, ");␊ |
397 | ␉␉␉␉␉␉␉␉}␊ |
398 | ␉␉␉␉␉␉␉␉msr32.lo |= (1 << 17);␊ |
399 | ␉␉␉␉␉␉␉␉verbose("PROCHOT, ");␊ |
400 | ␉␉␉␉␉␉␉␉msr32.lo |= (1 << 10);␊ |
401 | ␉␉␉␉␉␉␉␉verbose("FERR\n");␊ |
402 | ␉␉␉␉␉␉␉}␊ |
403 | ␉␉␉␉␉␉␉bool oem_ssdt, tmpval;␊ |
404 | ␉␉␉␉␉␉␉oem_ssdt = false;␊ |
405 | ␉␉␉␉␉␉␉␊ |
406 | ␉␉␉␉␉␉␉oem_ssdt = getBoolForKey(kOEMSSDT, &tmpval, &bootInfo->bootConfig)&&tmpval;␊ |
407 | ␉␉␉␉␉␉␉if(oem_ssdt)␊ |
408 | ␉␉␉␉␉␉␉{␊ |
409 | ␉␉␉␉␉␉␉␉bool c2e, c4e, hc4e;␊ |
410 | ␉␉␉␉␉␉␉␉c2e = c4e = hc4e = false;␊ |
411 | ␊ |
412 | ␉␉␉␉␉␉␉␉getBoolForKey(kC2EEnable, &c2e, &bootInfo->bootConfig);␊ |
413 | ␉␉␉␉␉␉␉␉if(c2e) msr32.lo |= (1 << 26);␊ |
414 | ␉␉␉␉␉␉␉␉␊ |
415 | ␉␉␉␉␉␉␉␉getBoolForKey(kC4EEnable, &c4e, &bootInfo->bootConfig);␊ |
416 | ␉␉␉␉␉␉␉␉if((c4e) && platformCPUFeature(CPU_FEATURE_MOBILE)) msr32.hi |= (1 << (32 - 32));␊ |
417 | ␉␉␉␉␉␉␉␉getBoolForKey(kHardC4EEnable, &hc4e, &bootInfo->bootConfig);␊ |
418 | ␉␉␉␉␉␉␉␉if((hc4e) && platformCPUFeature(CPU_FEATURE_MOBILE)) msr32.hi |= (1 << (33 - 32));␊ |
419 | ␉␉␉␉␉␉␉␉if(c2e || c4e || hc4e) tmfix = true;␊ |
420 | ␉␉␉␉␉␉␉}␊ |
421 | ␉␉␉␉␉␉␉␊ |
422 | ␉␉␉␉␉␉␉if(tmfix)␊ |
423 | ␉␉␉␉␉␉␉{␊ |
424 | ␉␉␉␉␉␉␉␉msr32.hi |= (1 << (36 - 32)); // EMTTM␊ |
425 | ␉␉␉␉␉␉␉␉wrmsr(MSR_IA32_MISC_ENABLE, msr32);␊ |
426 | ␉␉␉␉␉␉␉␉␊ |
427 | ␉␉␉␉␉␉␉␉msr32 = rdmsr(PIC_SENS_CFG);␊ |
428 | ␉␉␉␉␉␉␉␉msr32.lo |= (1 << 21);␊ |
429 | ␉␉␉␉␉␉␉␉wrmsr(PIC_SENS_CFG, msr32);␊ |
430 | ␉␉␉␉␉␉␉}␊ |
431 | ␉␉␉␉␉␉}␊ |
432 | ␉␉␉␉␉␉␊ |
433 | ␉␉␉␉␉␉if (rdmsr64(MSR_IA32_EXT_CONFIG) & (1 << 27))␊ |
434 | ␉␉␉␉␉␉{␊ |
435 | ␉␉␉␉␉␉␉wrmsr64(MSR_IA32_EXT_CONFIG, (rdmsr64(MSR_IA32_EXT_CONFIG) | (1 << 28)));␊ |
436 | ␉␉␉␉␉␉␉delay(1);␊ |
437 | ␉␉␉␉␉␉␉did = rdmsr64(MSR_IA32_EXT_CONFIG) & (1 << 28);␊ |
438 | ␉␉␉␉␉␉}␊ |
439 | ␉␉␉␉␉␉getBoolForKey(kFixFSB, &fix_fsb, &bootInfo->bootConfig);␊ |
440 | ␉␉␉␉␉␉if(fix_fsb)␊ |
441 | ␉␉␉␉␉␉{␊ |
442 | ␉␉␉␉␉␉␉msr = rdmsr64(MSR_FSB_FREQ);␊ |
443 | ␉␉␉␉␉␉␉bus = (msr >> 0) & 0x7;␊ |
444 | ␉␉␉␉␉␉␉if(p->CPU.Model == 0xd && bus == 0)␊ |
445 | ␉␉␉␉␉␉␉{␊ |
446 | ␉␉␉␉␉␉␉␉fsbFrequency = 100000000;␊ |
447 | ␉␉␉␉␉␉␉␉myfsb = 100;␊ |
448 | ␉␉␉␉␉␉␉}␊ |
449 | ␉␉␉␉␉␉␉else if(p->CPU.Model == 0xe && p->CPU.ExtModel == 1) goto ratio;␊ |
450 | ␉␉␉␉␉␉␉else␊ |
451 | ␉␉␉␉␉␉␉{␊ |
452 | ␉␉␉␉␉␉␉␉switch (bus)␊ |
453 | ␉␉␉␉␉␉␉␉{␊ |
454 | ␉␉␉␉␉␉␉␉␉case 0:␊ |
455 | ␉␉␉␉␉␉␉␉␉␉fsbFrequency = 266666667;␊ |
456 | ␉␉␉␉␉␉␉␉␉␉myfsb = 266;␊ |
457 | ␉␉␉␉␉␉␉␉␉␉break;␊ |
458 | ␉␉␉␉␉␉␉␉␉case 1:␊ |
459 | ␉␉␉␉␉␉␉␉␉␉fsbFrequency = 133333333;␊ |
460 | ␉␉␉␉␉␉␉␉␉␉myfsb = 133;␊ |
461 | ␉␉␉␉␉␉␉␉␉␉break;␊ |
462 | ␉␉␉␉␉␉␉␉␉case 3:␊ |
463 | ␉␉␉␉␉␉␉␉␉␉fsbFrequency = 166666667;␊ |
464 | ␉␉␉␉␉␉␉␉␉␉myfsb = 166;␊ |
465 | ␉␉␉␉␉␉␉␉␉␉break;␊ |
466 | ␉␉␉␉␉␉␉␉␉case 4:␊ |
467 | ␉␉␉␉␉␉␉␉␉␉fsbFrequency = 333333333;␊ |
468 | ␉␉␉␉␉␉␉␉␉␉myfsb = 333;␊ |
469 | ␉␉␉␉␉␉␉␉␉␉break;␊ |
470 | ␉␉␉␉␉␉␉␉␉case 5:␊ |
471 | ␉␉␉␉␉␉␉␉␉␉fsbFrequency = 100000000;␊ |
472 | ␉␉␉␉␉␉␉␉␉␉myfsb = 100;␊ |
473 | ␉␉␉␉␉␉␉␉␉␉break;␊ |
474 | ␉␉␉␉␉␉␉␉␉case 6:␊ |
475 | ␉␉␉␉␉␉␉␉␉␉fsbFrequency = 400000000;␊ |
476 | ␉␉␉␉␉␉␉␉␉␉myfsb = 400;␊ |
477 | ␉␉␉␉␉␉␉␉␉␉break;␊ |
478 | ␉␉␉␉␉␉␉␉␉case 2:␊ |
479 | ␉␉␉␉␉␉␉␉␉default:␊ |
480 | ␉␉␉␉␉␉␉␉␉␉fsbFrequency = 200000000;␊ |
481 | ␉␉␉␉␉␉␉␉␉␉myfsb = 200;␊ |
482 | ␉␉␉␉␉␉␉␉␉␉break;␊ |
483 | ␉␉␉␉␉␉␉␉}␊ |
484 | ␉␉␉␉␉␉␉}␊ |
485 | ␉␉␉␉␉␉␉uint64_t minfsb = 182000000, maxfsb = 185000000;␊ |
486 | ␉␉␉␉␉␉␉if(((fsbFrequency > minfsb) && (fsbFrequency < maxfsb)) || !fsbFrequency)␊ |
487 | ␉␉␉␉␉␉␉{␊ |
488 | ␉␉␉␉␉␉␉␉fsbFrequency = 200000000;␊ |
489 | ␉␉␉␉␉␉␉␉fsbad = true;␊ |
490 | ␉␉␉␉␉␉␉}␊ |
491 | ␉␉␉␉␉␉␉goto ratio;␊ |
492 | ␉␉␉␉␉␉}␊ |
493 | ␉␉␉␉␉case 0x1d:␉␉// Xeon MP MP 7400␊ |
494 | ␉␉␉␉␉// for 0x2a & 0x2b turbo is true;␊ |
495 | ␉␉␉␉␉//case 0x2a:␉␉// SNB␊ |
496 | ␉␉␉␉␉//case 0x2b:␉␉// SNB Xeon␊ |
497 | ␉␉␉␉␉default:␊ |
498 | ␉␉␉␉␉␉if(getIntForKey(kForceFSB, &myfsb, &bootInfo->bootConfig))␊ |
499 | ␉␉␉␉␉␉{␊ |
500 | ␉␉␉␉␉␉␉forcefsb:␊ |
501 | ␉␉␉␉␉␉␉switch(myfsb)␊ |
502 | ␉␉␉␉␉␉␉{␊ |
503 | ␉␉␉␉␉␉␉␉case 133:␊ |
504 | ␉␉␉␉␉␉␉␉␉fsbFrequency = 133333333;␊ |
505 | ␉␉␉␉␉␉␉␉␉break;␊ |
506 | ␉␉␉␉␉␉␉␉case 166:␊ |
507 | ␉␉␉␉␉␉␉␉␉fsbFrequency = 166666667;␊ |
508 | ␉␉␉␉␉␉␉␉␉break;␊ |
509 | ␉␉␉␉␉␉␉␉case 233:␊ |
510 | ␉␉␉␉␉␉␉␉␉fsbFrequency = 233333333;␊ |
511 | ␉␉␉␉␉␉␉␉␉break;␊ |
512 | ␉␉␉␉␉␉␉␉case 266:␊ |
513 | ␉␉␉␉␉␉␉␉␉fsbFrequency = 266666667;␊ |
514 | ␉␉␉␉␉␉␉␉␉break;␊ |
515 | ␉␉␉␉␉␉␉␉case 333:␊ |
516 | ␉␉␉␉␉␉␉␉␉fsbFrequency = 333333333;␊ |
517 | ␉␉␉␉␉␉␉␉␉break;␊ |
518 | ␉␉␉␉␉␉␉␉case 100:␊ |
519 | ␉␉␉␉␉␉␉␉case 200:␊ |
520 | ␉␉␉␉␉␉␉␉case 400:␊ |
521 | ␉␉␉␉␉␉␉␉␉fsbFrequency = (myfsb * 1000000);␊ |
522 | ␉␉␉␉␉␉␉␉␉break;␊ |
523 | ␉␉␉␉␉␉␉␉default:␊ |
524 | ␉␉␉␉␉␉␉␉␉getValueForKey(kForceFSB, &newfsb, &len, &bootInfo->bootConfig);␊ |
525 | ␉␉␉␉␉␉␉␉␉if((len <= 3) && (myfsb < 400))␊ |
526 | ␉␉␉␉␉␉␉␉␉{␊ |
527 | ␉␉␉␉␉␉␉␉␉␉fsbFrequency = (myfsb * 1000000);␊ |
528 | ␉␉␉␉␉␉␉␉␉␉verbose("Specified FSB: %dMhz. Assuming you know what you 're doing !\n", myfsb);␊ |
529 | ␉␉␉␉␉␉␉␉␉}␊ |
530 | ␉␉␉␉␉␉␉␉␉else if(core_i) fsbFrequency = 133333333;␊ |
531 | ␉␉␉␉␉␉␉␉␉else fsbFrequency = 200000000;␊ |
532 | ␉␉␉␉␉␉␉␉␉break;␊ |
533 | ␉␉␉␉␉␉␉}␊ |
534 | ␉␉␉␉␉␉␉if(core_i)␊ |
535 | ␉␉␉␉␉␉␉{␊ |
536 | ␉␉␉␉␉␉␉␉cpuFrequency = (fsbFrequency * max_ratio) / 10;␊ |
537 | ␉␉␉␉␉␉␉␉verbose("Sticking with [BCLK: %dMhz, Bus-Ratio: %s]\n", myfsb, newratio);␊ |
538 | ␉␉␉␉␉␉␉␉break;␊ |
539 | ␉␉␉␉␉␉␉}␊ |
540 | ␉␉␉␉␉␉␉fix_fsb = true;␊ |
541 | ␉␉␉␉␉␉}␊ |
542 | ␉␉␉␉␉␉goto ratio;␊ |
543 | ␉␉␉␉␉␉break;␊ |
544 | ␉␉␉␉}␊ |
545 | ␉␉␉}␊ |
546 | ␉␉␉else␊ |
547 | ␉␉␉{␊ |
548 | ␉␉␉␉ratio:␊ |
549 | ␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_STATUS);␊ |
550 | ␉␉␉␉maxdiv = (msr >> 46) & 0x01;␊ |
551 | ␉␉␉␉//valv: this seems to be bit 15 instead of 14.␊ |
552 | ␉␉␉␉currdiv = (msr >> 15) & 0x01;␊ |
553 | ␉␉␉␉uint8_t XE = (msr >> 31) & 0x01;␊ |
554 | ␊ |
555 | ␉␉␉␉msr_t msr32;␊ |
556 | ␉␉␉␉msr32 = rdmsr(MSR_IA32_PERF_STATUS);␊ |
557 | ␉␉␉␉bus_ratio_min = (msr32.lo >> 24) & 0x1f;␊ |
558 | ␉␉␉␉min_ratio = bus_ratio_min * 10;␊ |
559 | ␉␉␉␉if(currdiv) min_ratio = min_ratio + 5;␊ |
560 | ␉␉␉␉␊ |
561 | ␉␉␉␉if(XE || (p->CPU.Family == 0x0f)) bus_ratio_max = (msr32.hi >> (40-32)) & 0x1f;␊ |
562 | ␉␉␉␉else bus_ratio_max = ((rdmsr64(MSR_IA32_PLATFORM_ID) >> 8) & 0x1f);␊ |
563 | ␉␉␉␉/* On lower models, currcoef defines TSC freq */␊ |
564 | ␉␉␉␉if (((p->CPU.Family == 0x06) && (p->CPU.Model < 0x0e)) && (p->CPU.Family != 0x0f)) bus_ratio_max = bus_ratio_min;␊ |
565 | ␉␉␉␉// bad hack! Could force a value relying on kpstates, but I fail to see its benefits.␊ |
566 | ␉␉␉␉if(bus_ratio_min == 0) bus_ratio_min = bus_ratio_max;␊ |
567 | ␉␉␉␉␊ |
568 | ␉␉␉␉if(p->CPU.Family == 0x0f)␊ |
569 | ␉␉␉␉{␊ |
570 | ␉␉␉␉␉getBoolForKey(kFixFSB, &fix_fsb, &bootInfo->bootConfig);␊ |
571 | ␉␉␉␉␉if(fix_fsb)␊ |
572 | ␉␉␉␉␉{␊ |
573 | ␉␉␉␉␉␉msr = rdmsr64(MSR_EBC_FREQUENCY_ID);␊ |
574 | ␉␉␉␉␉␉int bus = (msr >> 16) & 0x7;␊ |
575 | ␉␉␉␉␉␉switch (bus)␊ |
576 | ␉␉␉␉␉␉{␊ |
577 | ␉␉␉␉␉␉␉case 0:␊ |
578 | ␉␉␉␉␉␉␉␉fsbFrequency = 266666667;␊ |
579 | ␉␉␉␉␉␉␉␉myfsb = 266;␊ |
580 | ␉␉␉␉␉␉␉␉break;␊ |
581 | ␉␉␉␉␉␉␉case 1:␊ |
582 | ␉␉␉␉␉␉␉␉fsbFrequency = 133333333;␊ |
583 | ␉␉␉␉␉␉␉␉myfsb = 133;␊ |
584 | ␉␉␉␉␉␉␉␉break;␊ |
585 | ␉␉␉␉␉␉␉case 3:␊ |
586 | ␉␉␉␉␉␉␉␉fsbFrequency = 166666667;␊ |
587 | ␉␉␉␉␉␉␉␉myfsb = 166;␊ |
588 | ␉␉␉␉␉␉␉␉break;␊ |
589 | ␉␉␉␉␉␉␉case 2:␊ |
590 | ␉␉␉␉␉␉␉default:␊ |
591 | ␉␉␉␉␉␉␉␉fsbFrequency = 200000000;␊ |
592 | ␉␉␉␉␉␉␉␉myfsb = 200;␊ |
593 | ␉␉␉␉␉␉␉␉break;␊ |
594 | ␉␉␉␉␉␉}␊ |
595 | ␉␉␉␉␉␉uint64_t minfsb = 183000000, maxfsb = 185000000;␊ |
596 | ␉␉␉␉␉␉if (((fsbFrequency > minfsb) && (fsbFrequency < maxfsb)) || (!fsbFrequency))␊ |
597 | ␉␉␉␉␉␉{␊ |
598 | ␉␉␉␉␉␉␉fsbFrequency = 200000000;␊ |
599 | ␉␉␉␉␉␉␉fsbad = true;␊ |
600 | ␉␉␉␉␉␉}␊ |
601 | ␉␉␉␉␉}␊ |
602 | ␉␉␉␉}␊ |
603 | ␊ |
604 | ␉␉␉␉if(fix_fsb)␊ |
605 | ␉␉␉␉{␊ |
606 | ␉␉␉␉␉if (bus_ratio_max)␊ |
607 | ␉␉␉␉␉{␊ |
608 | ␉␉␉␉␉␉if (maxdiv) fsbi = ((tscFrequency * 2) / ((bus_ratio_max * 2) + 1));␊ |
609 | ␉␉␉␉␉␉else fsbi = (tscFrequency / bus_ratio_max);␊ |
610 | ␉␉␉␉␉}␊ |
611 | ␉␉␉␉␉ratio_gn:␊ |
612 | ␉␉␉␉␉if ((getValueForKey(kbusratio, &newratio, &len, &bootInfo->bootConfig)) && (len <= 4))␊ |
613 | ␉␉␉␉␉{␊ |
614 | ␉␉␉␉␉␉max_ratio = atoi(newratio);␊ |
615 | ␉␉␉␉␉␉max_ratio = (max_ratio * 10);␊ |
616 | ␉␉␉␉␉␉if (len >= 3) max_ratio = (max_ratio + 5);␊ |
617 | ␊ |
618 | ␉␉␉␉␉␉verbose("Bus-Ratio defaults: min=%d%s, max=%d%s\n", bus_ratio_min, currdiv ? ".5" : "", bus_ratio_max, maxdiv ? ".5" : "");␊ |
619 | ␉␉␉␉␉␉if ((max_ratio >= min_ratio) && (max_ratio < 200))␊ |
620 | ␉␉␉␉␉␉{␊ |
621 | ␉␉␉␉␉␉␉cpuFrequency = (fsbFrequency * max_ratio) / 10;␊ |
622 | ␉␉␉␉␉␉␉if (len >= 3) maxdiv = 1;␊ |
623 | ␉␉␉␉␉␉␉else maxdiv = 0;␊ |
624 | ␉␉␉␉␉␉␉verbose("Sticking with [FSB: %dMhz, Bus-Ratio: %s]\n", myfsb, newratio);␊ |
625 | ␉␉␉␉␉␉}␊ |
626 | ␉␉␉␉␉␉else␊ |
627 | ␉␉␉␉␉␉{␊ |
628 | ␉␉␉␉␉␉␉printf("Bus-Ratio: Lowest allowed = %d%s. ", bus_ratio_min, currdiv ? ".5" : "");␊ |
629 | ␉␉␉␉␉␉␉goto ratio_vldt;␊ |
630 | ␉␉␉␉␉␉}␊ |
631 | ␉␉␉␉␉}␊ |
632 | ␉␉␉␉␉else␊ |
633 | ␉␉␉␉␉{␊ |
634 | ␉␉␉␉␉␉ratio_vldt:␊ |
635 | ␉␉␉␉␉␉if (maxdiv)␊ |
636 | ␉␉␉␉␉␉{␊ |
637 | ␉␉␉␉␉␉␉cpuFrequency = ((fsbFrequency * ((bus_ratio_max * 2) + 1)) / 2);␊ |
638 | ␉␉␉␉␉␉␉max_ratio = (bus_ratio_max * 10) + 5;␊ |
639 | ␉␉␉␉␉␉}␊ |
640 | ␉␉␉␉␉␉else␊ |
641 | ␉␉␉␉␉␉{␊ |
642 | ␉␉␉␉␉␉␉cpuFrequency = (fsbFrequency * bus_ratio_max);␊ |
643 | ␉␉␉␉␉␉␉max_ratio = bus_ratio_max * 10;␊ |
644 | ␉␉␉␉␉␉}␊ |
645 | ␉␉␉␉␉␉verbose("CPU: Sticking with: [FSB: %dMhz, Bus-Ratio: %d%s] %s\n", myfsb, bus_ratio_max, maxdiv ? ".5" : "", newratio ? "instead" : "");␊ |
646 | ␉␉␉␉␉}␊ |
647 | ␉␉␉␉}␊ |
648 | ␉␉␉␉else␊ |
649 | ␉␉␉␉{␊ |
650 | ␉␉␉␉␉if (bus_ratio_max)␊ |
651 | ␉␉␉␉␉{␊ |
652 | ␉␉␉␉␉␉if (maxdiv)␊ |
653 | ␉␉␉␉␉␉{␊ |
654 | ␉␉␉␉␉␉␉fsbFrequency = ((tscFrequency * 2) / ((bus_ratio_max * 2) + 1));␊ |
655 | ␉␉␉␉␉␉␉max_ratio = ((bus_ratio_max * 10) + 5);␊ |
656 | ␉␉␉␉␉␉}␊ |
657 | ␉␉␉␉␉␉else␊ |
658 | ␉␉␉␉␉␉{␊ |
659 | ␉␉␉␉␉␉␉fsbFrequency = (tscFrequency / bus_ratio_max);␊ |
660 | ␉␉␉␉␉␉␉max_ratio = (bus_ratio_max * 10);␊ |
661 | ␉␉␉␉␉␉}␊ |
662 | ␊ |
663 | ␉␉␉␉␉␉myfsb = (fsbFrequency / 1000000);␊ |
664 | ␉␉␉␉␉␉if (getValueForKey(kbusratio, &newratio, &len, &bootInfo->bootConfig)) goto ratio_gn;␊ |
665 | ␉␉␉␉␉␉else cpuFrequency = ((fsbFrequency * max_ratio) / 10);␊ |
666 | ␊ |
667 | ␉␉␉␉␉␉DBG("max: %d%s current: %d%s\n", bus_ratio_max, maxdiv ? ".5" : "", bus_ratio_min, currdiv ? ".5" : "");␊ |
668 | ␉␉␉␉␉}␊ |
669 | ␉␉␉␉}␊ |
670 | ␉␉␉␉p->CPU.MaxRatio = max_ratio;␊ |
671 | ␉␉␉␉p->CPU.MinRatio = min_ratio;␊ |
672 | ␉␉␉}␊ |
673 | ␉␉}␊ |
674 | ␊ |
675 | ␉␉// on-die sensor␊ |
676 | ␉␉if (p->CPU.CPUID[CPUID_0][0] >= 0x6)␊ |
677 | ␉␉{␊ |
678 | ␉␉␉// Highest Basic Functions Number␊ |
679 | ␉␉␉do_cpuid(6, p->CPU.CPUID[CPUID_81]);␊ |
680 | ␉␉␉tms = bitfield(p->CPU.CPUID[CPUID_81][0], 0, 0);␊ |
681 | ␉␉␉ida = bitfield(p->CPU.CPUID[CPUID_81][0], 1, 1);␊ |
682 | ␉␉␉if(tms != 0)␊ |
683 | ␉␉␉{␊ |
684 | ␉␉␉␉int temp, utjmax;␊ |
685 | ␉␉␉␉if (tjmax == 0) tjmax = 100;␊ |
686 | ␉␉␉␉if((getIntForKey(kTjmax, &utjmax, &bootInfo->bootConfig)) && ((70 <= utjmax) && (utjmax <= 110))) tjmax = utjmax;␊ |
687 | ␉␉␉␉msr = rdmsr64(MSR_THERMAL_STATUS);␊ |
688 | ␉␉␉␉//if ((msr & 0x3) == 0x3)␊ |
689 | ␉␉␉␉if (((msr >> 31) & 0x1) == 1)␊ |
690 | ␉␉␉␉{␊ |
691 | ␉␉␉␉␉temp = tjmax - ((msr >> 16) & 0x7F);␊ |
692 | ␉␉␉␉␉verbose("CPU: Tjmax ~ %d°C ␉ Temperature= ~ %d°C\n", tjmax, temp);␊ |
693 | ␉␉␉␉}␊ |
694 | ␉␉␉␉else temp = -1;␊ |
695 | ␉␉␉}␊ |
696 | ␉␉␉if(ida == 0)␊ |
697 | ␉␉␉{␊ |
698 | ␉␉␉␉verbose("CPU: Attempting to enable IDA ");␊ |
699 | ␉␉␉␉msr_t msr;␊ |
700 | ␉␉␉␉msr = rdmsr(MSR_IA32_MISC_ENABLE);␊ |
701 | ␉␉␉␉msr.hi |= (0 << (38-32));␊ |
702 | ␉␉␉␉wrmsr(MSR_IA32_MISC_ENABLE, msr);␊ |
703 | ␉␉␉␉delay(1);␊ |
704 | ␉␉␉␉if(bitfield(p->CPU.CPUID[CPUID_81][0], 1, 1) == 0) verbose("Failed!\n");␊ |
705 | ␉␉␉␉else verbose("Succeded!\n");␊ |
706 | ␉␉␉}␊ |
707 | ␉␉␉else verbose("CPU: IDA: Enabled!\n");␊ |
708 | ␉␉}␊ |
709 | ␉}␊ |
710 | //#if 0␊ |
711 | ␉// valv: work in progress. Most of this code is going to be moved when ready␊ |
712 | ␉else if(p->CPU.Vendor == 0x68747541 /* AMD */ && p->CPU.Family == 0x0f)␊ |
713 | ␉{␊ |
714 | ␉␉verbose("CPU: ");␊ |
715 | ␉␉// valv: very experimental mobility check␊ |
716 | ␉␉if (p->CPU.CPUID[0x80000000][0] >= 0x80000007)␊ |
717 | ␉␉{␊ |
718 | ␉␉␉uint32_t amo, const_tsc;␊ |
719 | ␉␉␉do_cpuid(0x80000007, p->CPU.CPUID[CPUID_MAX]);␊ |
720 | ␉␉␉amo = bitfield(p->CPU.CPUID[CPUID_MAX][0], 6, 6);␊ |
721 | ␉␉␉const_tsc = bitfield(p->CPU.CPUID[CPUID_MAX][3], 8, 8);␊ |
722 | ␉␉␉// valv: p-state support verification␊ |
723 | ␉␉␉//uint32_t pstate_support = bitfield(p->CPU.CPUID[CPUID_MAX][3], 2, 1);␊ |
724 | ␉␉␉//if(pstate_support != 0) verbose("supproted p-state transition\n")␊ |
725 | ␉␉␉␊ |
726 | ␉␉␉if (const_tsc != 0) verbose("Constant TSC!\n");␊ |
727 | ␉␉␉if (amo == 1)␊ |
728 | ␉␉␉{␊ |
729 | ␉␉␉␉p->CPU.Features |= CPU_FEATURE_MOBILE;␊ |
730 | ␉␉␉␉if (!strstr(p->CPU.BrandString, "obile")) verbose("Mobile ");␊ |
731 | ␉␉␉}␊ |
732 | ␉␉}␊ |
733 | ␉␉//valv: 2nd attemp; just in case␊ |
734 | ␉␉if (!platformCPUFeature(CPU_FEATURE_MOBILE))␊ |
735 | ␉␉{␊ |
736 | ␉␉␉if (strstr(p->CPU.BrandString, "obile"))␊ |
737 | ␉␉␉{␊ |
738 | ␉␉␉␉p->CPU.Features |= CPU_FEATURE_MOBILE;␊ |
739 | ␉␉␉}␊ |
740 | ␉␉}␊ |
741 | ␉␉verbose("%s\n", p->CPU.BrandString);␊ |
742 | ␊ |
743 | ␉␉if(p->CPU.ExtFamily == 0x00 /* K8 */)␊ |
744 | ␉␉{␊ |
745 | ␉␉␉// valv: this section needs some work␊ |
746 | ␉␉␉msr = rdmsr64(K8_FIDVID_STATUS);␊ |
747 | ␉␉␉bus_ratio_max = bitfield(msr, 21, 16);␊ |
748 | ␉␉␉//bus_ratio_max = (msr & 0x3f) / 2 + 4;␊ |
749 | ␉␉␉bus_ratio_min = bitfield(msr, 13, 8);␊ |
750 | ␉␉␉currdiv = (msr & 0x01) * 2;␊ |
751 | ␉␉␉if (bus_ratio_max)␊ |
752 | ␉␉␉{␊ |
753 | ␉␉␉␉if (currdiv)␊ |
754 | ␉␉␉␉{␊ |
755 | ␉␉␉␉␉fsbFrequency = ((tscFrequency * currdiv) / bus_ratio_max); // ?␊ |
756 | ␉␉␉␉␉DBG("%d.%d\n", bus_ratio_max / currdiv, ((bus_ratio_max % currdiv) * 100) / currdiv);␊ |
757 | ␉␉␉␉}␊ |
758 | ␉␉␉␉else␊ |
759 | ␉␉␉␉{␊ |
760 | ␉␉␉␉␉fsbFrequency = (tscFrequency / bus_ratio_max);␊ |
761 | ␉␉␉␉␉DBG("%d\n", bus_ratio_max);␊ |
762 | ␉␉␉␉}␊ |
763 | ␉␉␉␉//fsbFrequency = (tscFrequency / bus_ratio_max); // ?␊ |
764 | ␉␉␉␉cpuFrequency = tscFrequency; // ?␊ |
765 | ␉␉␉}␊ |
766 | ␉␉}␊ |
767 | ␊ |
768 | ␉␉else if(p->CPU.ExtFamily >= 0x01 /* K10+ */)␊ |
769 | ␉␉{␊ |
770 | ␉␉␉msr = rdmsr64(K10_COFVID_STATUS);␊ |
771 | ␉␉␉currdiv = (2 << ((msr >> 6) & 0x07));␊ |
772 | ␉␉␉msr = rdmsr64(AMD_10H_11H_CONFIG);␊ |
773 | ␉␉␉bus_ratio_max = ((msr) & 0x3F);␊ |
774 | ␉␉␉//verbose("max_multi: %d\n", bus_ratio_max);␊ |
775 | ␊ |
776 | ␉␉␉/*msr_t divmsr;␊ |
777 | ␉␉␉divmsr = rdmsr(AMD_10H_11H_CONFIG);␊ |
778 | ␉␉␉maxdiv = (divmsr.hi >> 0x08) & 0x01;␊ |
779 | ␉␉␉verbose("maxdiv: %d, currdiv: %d\n", maxdiv, currdiv);*/␊ |
780 | ␊ |
781 | ␉␉␉if(p->CPU.ExtFamily == 0x01) ␊ |
782 | ␉␉␉␉cpuFrequency = 100 * (bus_ratio_max + 0x10);␊ |
783 | ␉␉␉else ␊ |
784 | ␉␉␉␉cpuFrequency = 100 * (bus_ratio_max + 0x08);␊ |
785 | ␉␉␉␊ |
786 | ␉␉␉uint32_t minFreq = cpuFrequency / (1 << currdiv);␊ |
787 | ␊ |
788 | ␉␉␉uint8_t maxrtio = (cpuFrequency / 20);␊ |
789 | ␉␉␉p->CPU.MaxRatio = maxrtio;␊ |
790 | ␉␉␉␊ |
791 | ␉␉␉fsbFrequency = ((tscFrequency / 100000) / maxrtio);␊ |
792 | ␉␉␉verbose("fsb: %d\n", fsbFrequency);␊ |
793 | ␉␉␉␊ |
794 | ␉␉␉if(maxrtio == ((bus_ratio_max * 10) - 5))␊ |
795 | ␉␉␉{␊ |
796 | ␉␉␉␉verbose("multi: max:%d.5, min:", (bus_ratio_max - 1));␊ |
797 | ␉␉␉␉maxdiv = 1;␊ |
798 | ␉␉␉}␊ |
799 | ␉␉␉else if(maxrtio == ((bus_ratio_max - 1) * 10))␊ |
800 | ␉␉␉{␊ |
801 | ␉␉␉␉verbose("multi: max:%d, min:", (bus_ratio_max - 1));␊ |
802 | ␉␉␉␉maxdiv = 0;␊ |
803 | ␉␉␉}␊ |
804 | ␊ |
805 | ␉␉␉bus_ratio_min = (minFreq / fsbFrequency);␊ |
806 | ␉␉␉verbose("%d", bus_ratio_min);␊ |
807 | ␉␉␉while(minFreq < 800)␊ |
808 | ␉␉␉{␊ |
809 | ␉␉␉␉bus_ratio_min = bus_ratio_min + 1; // bus_ratio_min++; ???␊ |
810 | ␉␉␉␉verbose(" >> %d", bus_ratio_min);␊ |
811 | ␉␉␉}␊ |
812 | ␉␉␉verbose("\n");␊ |
813 | ␊ |
814 | ␉␉␉struct hwpstate ␊ |
815 | ␉␉␉{␊ |
816 | ␉␉␉␉uint32_t␉freq;␉␉/* CPU clock in Mhz. */␊ |
817 | ␉␉␉␉uint32_t␉volts;␉␉/* Voltage in mV. */␊ |
818 | ␉␉␉␉uint32_t␉power;␉␉/* Power consumed in mW. */␊ |
819 | ␉␉␉␉uint8_t␉lat;␉␉␉/* Transition latency in us. */␊ |
820 | ␉␉␉␉uint8_t␉pstate_id;␉␉/* P-State id */␊ |
821 | ␉␉␉};␊ |
822 | ␉␉␉␊ |
823 | ␉␉␉struct hwpstate state[32];␊ |
824 | ␉␉␉int max_state, i,/* did,*/ vid;␊ |
825 | ␉␉␉uint8_t fid;␊ |
826 | ␉␉␉msr = rdmsr64(MSR_AMD_10H_11H_LIMIT);␊ |
827 | ␉␉␉max_state = 1 + (((msr) >> 4) & 0x7);␊ |
828 | ␊ |
829 | ␉␉␉for(i=0; i<max_state; i++)␊ |
830 | ␉␉␉{␊ |
831 | ␉␉␉␉msr = rdmsr64(AMD_10H_11H_CONFIG + i);␊ |
832 | ␉␉␉␉//msr_t didmsr;␊ |
833 | ␉␉␉␉//didmsr = rdmsr(AMD_10H_11H_CONFIG + i);␊ |
834 | ␉␉␉␉if ((msr & ((uint64_t)1 << 63)) != ((uint64_t)1 << 63)) verbose("Invalid MSR!\n");␊ |
835 | ␉␉␉␉else␊ |
836 | ␉␉␉␉{␊ |
837 | ␉␉␉␉␉//did = (didmsr.hi >> 0x08) & 0x01;␊ |
838 | ␉␉␉␉␉if(i == 0) ␊ |
839 | ␉␉␉␉␉{␊ |
840 | ␉␉␉␉␉␉//maxdiv = did;␊ |
841 | ␉␉␉␉␉␉fid = p->CPU.MaxRatio;␊ |
842 | ␉␉␉␉␉␉state[i].freq = ((fid * fsbFrequency) / 10);␊ |
843 | ␉␉␉␉␉␉fid = (fid / 10);␊ |
844 | ␉␉␉␉␉}␊ |
845 | ␉␉␉␉␉else␊ |
846 | ␉␉␉␉␉{␊ |
847 | ␉␉␉␉␉␉fid = bitfield(msr, 5, 0);␊ |
848 | ␉␉␉␉␉␉state[i].freq = (fid * fsbFrequency);␊ |
849 | ␉␉␉␉␉}␊ |
850 | ␉␉␉␉␉␊ |
851 | ␉␉␉␉␉if(i == (max_state -1))␊ |
852 | ␉␉␉␉␉{␊ |
853 | ␉␉␉␉␉␉fid = bus_ratio_min;␊ |
854 | ␉␉␉␉␉␉state[i].freq = (fid * fsbFrequency);␊ |
855 | ␉␉␉␉␉}␊ |
856 | ␉␉␉␉␉␊ |
857 | ␉␉␉␉␉vid = bitfield(msr, 15, 9);␊ |
858 | ␉␉␉␉␉␊ |
859 | ␉␉␉␉␉if(i == 0) verbose("P-State %d: Frequency: %d, Multiplier: %d%s, vid: %d\n", i, state[i].freq, fid, maxdiv ? ".5" : "", vid);␊ |
860 | ␉␉␉␉␉else if((state[i].freq > state[i-1].freq) || (state[i].freq < 800)) verbose("P-State %d: Removed!\n", i);␊ |
861 | ␉␉␉␉␉else verbose("P-State %d: Frequency: %d, Multiplier: %d, vid: %d\n", i, state[i].freq, fid, vid);␊ |
862 | ␉␉␉␉␉state[i].pstate_id = i;␊ |
863 | ␉␉␉␉␉// valv: zeroed for now␊ |
864 | ␉␉␉␉␉state[i].volts = 0;␊ |
865 | ␉␉␉␉␉state[i].power = 0;␊ |
866 | ␉␉␉␉␉state[i].lat = 0;␊ |
867 | ␉␉␉␉}␊ |
868 | ␉␉␉}␊ |
869 | ␉␉␉fsbFrequency = (fsbFrequency * 1000000);␊ |
870 | ␉␉␉cpuFrequency = (state[0].freq * 1000000);␊ |
871 | ␉␉}␊ |
872 | ␉␉␊ |
873 | ␉␉p->CPU.MinRatio = bus_ratio_min * 10;␊ |
874 | ␉}␊ |
875 | ␉else if(p->CPU.Vendor == 0x746e6543 /* CENTAUR */ && p->CPU.Family == 6) //valv: partial!␊ |
876 | ␉{␊ |
877 | ␉␉msr = rdmsr64(MSR_EBL_CR_POWERON);␊ |
878 | ␉␉int bus = (msr >> 18) & 0x3;␊ |
879 | ␉␉switch (bus)␊ |
880 | ␉␉{␊ |
881 | ␉␉␉case 1:␊ |
882 | ␉␉␉␉fsbFrequency = 133333333;␊ |
883 | ␉␉␉␉break;␊ |
884 | ␉␉␉case 2:␊ |
885 | ␉␉␉␉fsbFrequency = 200000000;␊ |
886 | ␉␉␉␉break;␊ |
887 | ␉␉␉case 3:␊ |
888 | ␉␉␉␉fsbFrequency = 166666667;␊ |
889 | ␉␉␉␉break;␊ |
890 | ␉␉␉case 0:␊ |
891 | ␉␉␉default:␉␉␉␉␊ |
892 | ␉␉␉␉fsbFrequency = 100000000;␊ |
893 | ␉␉␉␉break;␊ |
894 | ␉␉}␊ |
895 | ␉␉msr_t msr;␊ |
896 | ␉␉msr = rdmsr(MSR_IA32_PERF_STATUS);␊ |
897 | ␉␉bus_ratio_min = (msr.lo >> 24) & 0x1f;␊ |
898 | ␉␉min_ratio = bus_ratio_min * 10;␊ |
899 | ␉␉bus_ratio_max = (msr.hi >> (40-32)) & 0x1f;␊ |
900 | ␉␉max_ratio = bus_ratio_max * 10;␊ |
901 | ␉␉cpuFrequency = ((fsbFrequency * max_ratio) / 10);␊ |
902 | ␉}␊ |
903 | ␊ |
904 | ␉if (!fsbFrequency)␊ |
905 | ␉{␊ |
906 | ␉␉fsbFrequency = (DEFAULT_FSB * 1000);␊ |
907 | ␉␉cpuFrequency = tscFrequency;␊ |
908 | ␉␉DBG("0 ! using the default value for FSB !\n");␊ |
909 | ␉}␊ |
910 | ␊ |
911 | //#endif␊ |
912 | ␊ |
913 | ␉p->CPU.MaxDiv = maxdiv;␊ |
914 | ␉p->CPU.CurrDiv = currdiv;␊ |
915 | ␉p->CPU.TSCFrequency = tscFrequency;␊ |
916 | ␉p->CPU.FSBFrequency = fsbFrequency;␊ |
917 | ␉p->CPU.CPUFrequency = cpuFrequency;␊ |
918 | ␉p->CPU.ISerie = false;␊ |
919 | ␉p->CPU.Turbo = false;␊ |
920 | ␊ |
921 | ␉if(!fsbad) p->CPU.FSBIFrequency = fsbFrequency;␊ |
922 | ␉else p->CPU.FSBIFrequency = fsbi;␊ |
923 | ␊ |
924 | ␉if (platformCPUFeature(CPU_FEATURE_EST))␊ |
925 | ␉{␊ |
926 | ␉␉msr_t msr32;␊ |
927 | ␉␉msr32 = rdmsr(MSR_IA32_MISC_ENABLE);␊ |
928 | ␉␉if (!(rdmsr64(MSR_IA32_MISC_ENABLE) & (1 << 16)))␊ |
929 | ␉␉{␉//valv: we can also attempt to enable␊ |
930 | ␉␉␉msr32.lo |= (1 << 16);␊ |
931 | ␉␉␉// Lock till next reset!␊ |
932 | ␉␉␉msr32.lo |= (1 << 20);␊ |
933 | ␉␉␉wrmsr(MSR_IA32_MISC_ENABLE, msr32);␊ |
934 | ␉␉␉delay(1);␊ |
935 | ␉␉␉if(rdmsr64(MSR_IA32_MISC_ENABLE) & (1 << 16))␊ |
936 | ␉␉␉{␊ |
937 | ␉␉␉␉p->CPU.EST = 1;␊ |
938 | ␉␉␉␉verbose("CPU: EIST Successfully Enabled!\n");␊ |
939 | ␉␉␉}␊ |
940 | ␉␉␉else␊ |
941 | ␉␉␉{␊ |
942 | ␉␉␉␉p->CPU.EST = 0;␊ |
943 | ␉␉␉␉verbose("CPU: EIST couldn't be enabled!\n");␊ |
944 | ␉␉␉}␊ |
945 | ␉␉}␊ |
946 | ␊ |
947 | ␉␉else p->CPU.EST = 1;␊ |
948 | ␉}␊ |
949 | ␉␊ |
950 | ␉if(core_i) p->CPU.ISerie = true;␊ |
951 | ␉␉DBG("CPU: Vendor/Family/ExtFamily: 0x%x/0x%x/0x%x\n", p->CPU.Vendor, p->CPU.Family, p->CPU.ExtFamily);␊ |
952 | ␉␉DBG("CPU: Model/ExtModel/Stepping: 0x%x/0x%x/0x%x\n", p->CPU.Model, p->CPU.ExtModel, p->CPU.Stepping);␊ |
953 | ␉␉DBG("CPU: Multipliers x10: max=%d, min=%d\n", p->CPU.MaxRatio, p->CPU.MinRatio);␊ |
954 | ␉if(turbo)␊ |
955 | ␉{␊ |
956 | ␉␉DBG("Turbo Ratio: %d/%d/%d/%d\n", p->CPU.Tone, p->CPU.Ttwo, p->CPU.Tthr, p->CPU.Tfor);␊ |
957 | ␉␉p->CPU.Turbo = true;␊ |
958 | ␉}␊ |
959 | ␉␉DBG("CPU: MaxDiv/CurrDiv: 0x%x/0x%x\n", p->CPU.MaxDiv, p->CPU.CurrDiv);␊ |
960 | ␉␉DBG("CPU: TSCFreq: %dMHz\n", p->CPU.TSCFrequency / 1000000);␊ |
961 | ␉␉DBG("CPU: CPUFreq: %dMHz\n", p->CPU.CPUFrequency / 1000000);␊ |
962 | ␉␉DBG("CPU: FSBFreq: %dMHz\n", p->CPU.FSBFrequency / 1000000);␊ |
963 | ␉if(did)␊ |
964 | ␉{␊ |
965 | ␉␉p->CPU.SLFM = did;␊ |
966 | ␉␉DBG("CPU: SLFM: %d\n", p->CPU.SLFM);␊ |
967 | ␉}␊ |
968 | ␉␉if(platformCPUFeature(CPU_FEATURE_EST))␊ |
969 | ␉␉DBG("CPU: Enhanced SpeedStep: %d\n", p->CPU.EST);␊ |
970 | ␉␉DBG("CPU: NoCores/NoThreads: %d/%d\n", p->CPU.NoCores, p->CPU.NoThreads);␊ |
971 | ␉␉DBG("CPU: Features: 0x%08x\n", p->CPU.Features);␊ |
972 | }␊ |
973 | |