1 | /*␊ |
2 | * NVidia injector␊ |
3 | *␊ |
4 | * Copyright (C) 2009 Jasmin Fazlic, iNDi␊ |
5 | *␊ |
6 | * NVidia injector is free software: you can redistribute it and/or modify␊ |
7 | * it under the terms of the GNU General Public License as published by␊ |
8 | * the Free Software Foundation, either version 3 of the License, or␊ |
9 | * (at your option) any later version.␊ |
10 | *␊ |
11 | * NVidia driver and injector is distributed in the hope that it will be useful,␊ |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of␊ |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the␊ |
14 | * GNU General Public License for more details.␊ |
15 | *␊ |
16 | * You should have received a copy of the GNU General Public License␊ |
17 | * along with NVidia injector. If not, see <http://www.gnu.org/licenses/>.␊ |
18 | */ ␊ |
19 | /*␊ |
20 | * Alternatively you can choose to comply with APSL␊ |
21 | */␊ |
22 | ␊ |
23 | ␊ |
24 | /*␊ |
25 | * DCB-Table parsing is based on software (nouveau driver) originally distributed under following license:␊ |
26 | *␊ |
27 | *␊ |
28 | * Copyright 2005-2006 Erik Waling␊ |
29 | * Copyright 2006 Stephane Marchesin␊ |
30 | * Copyright 2007-2009 Stuart Bennett␊ |
31 | *␊ |
32 | * Permission is hereby granted, free of charge, to any person obtaining a␊ |
33 | * copy of this software and associated documentation files (the "Software"),␊ |
34 | * to deal in the Software without restriction, including without limitation␊ |
35 | * the rights to use, copy, modify, merge, publish, distribute, sublicense,␊ |
36 | * and/or sell copies of the Software, and to permit persons to whom the␊ |
37 | * Software is furnished to do so, subject to the following conditions:␊ |
38 | *␊ |
39 | * The above copyright notice and this permission notice shall be included in␊ |
40 | * all copies or substantial portions of the Software.␊ |
41 | *␊ |
42 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR␊ |
43 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,␊ |
44 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL␊ |
45 | * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,␊ |
46 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF␊ |
47 | * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE␊ |
48 | * SOFTWARE.␊ |
49 | */␊ |
50 | ␊ |
51 | #include "libsaio.h"␊ |
52 | #include "boot.h"␊ |
53 | #include "bootstruct.h"␊ |
54 | #include "pci.h"␊ |
55 | #include "platform.h"␊ |
56 | #include "device_inject.h"␊ |
57 | #include "nvidia.h"␊ |
58 | ␊ |
59 | #ifndef DEBUG_NVIDIA␊ |
60 | #define DEBUG_NVIDIA 0␊ |
61 | #endif␊ |
62 | ␊ |
63 | #if DEBUG_NVIDIA␊ |
64 | #define DBG(x...)␉printf(x)␊ |
65 | #else␊ |
66 | #define DBG(x...)␊ |
67 | #endif␊ |
68 | ␊ |
69 | #define NVIDIA_ROM_SIZE 0x20000␊ |
70 | #define PATCH_ROM_SUCCESS 1␊ |
71 | #define PATCH_ROM_SUCCESS_HAS_LVDS 2␊ |
72 | #define PATCH_ROM_FAILED 0␊ |
73 | #define MAX_NUM_DCB_ENTRIES 16␊ |
74 | ␊ |
75 | #define TYPE_GROUPED 0xff␊ |
76 | ␊ |
77 | extern uint32_t devices_number;␊ |
78 | ␊ |
79 | const char *nvidia_compatible_0[]␉=␉{ "@0,compatible",␉"NVDA,NVMac" };␊ |
80 | const char *nvidia_compatible_1[]␉=␉{ "@1,compatible",␉"NVDA,NVMac" };␊ |
81 | const char *nvidia_device_type_0[]␉=␉{ "@0,device_type",␉"display" };␊ |
82 | const char *nvidia_device_type_1[]␉=␉{ "@1,device_type",␉"display" };␊ |
83 | const char *nvidia_device_type[]␉=␉{ "device_type",␉"NVDA,Parent" };␊ |
84 | const char *nvidia_name_0[]␉␉=␉{ "@0,name",␉␉"NVDA,Display-A" };␊ |
85 | const char *nvidia_name_1[]␉␉=␉{ "@1,name",␉␉"NVDA,Display-B" };␊ |
86 | const char *nvidia_slot_name[]␉␉=␉{ "AAPL,slot-name",␉"Slot-1" };␊ |
87 | ␊ |
88 | static uint8_t default_dcfg_0[]␉␉=␉{0xff, 0xff, 0xff, 0xff};␊ |
89 | static uint8_t default_dcfg_1[]␉␉=␉{0xff, 0xff, 0xff, 0xff};␊ |
90 | ␊ |
91 | static uint8_t default_NVCAP[]␉␉=␉{␊ |
92 | ␉0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0d, 0x00,␊ |
93 | ␉0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a,␊ |
94 | ␉0x00, 0x00, 0x00, 0x00␊ |
95 | };␊ |
96 | ␊ |
97 | static uint8_t default_NVPM[]= {␊ |
98 | 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,␊ |
99 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,␊ |
100 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,␊ |
101 | 0x00, 0x00, 0x00, 0x00␊ |
102 | };␊ |
103 | ␊ |
104 | #define DCFG0_LEN ( sizeof(default_dcfg_0) / sizeof(uint8_t) )␊ |
105 | #define DCFG1_LEN ( sizeof(default_dcfg_1) / sizeof(uint8_t) )␊ |
106 | #define NVCAP_LEN ( sizeof(default_NVCAP) / sizeof(uint8_t) )␊ |
107 | ␊ |
108 | static struct nv_chipsets_t NVKnownChipsets[] = {␊ |
109 | ␉{ 0x00000000, "Unknown" },␊ |
110 | ␉{ 0x10DE0040, "GeForce 6800 Ultra" },␊ |
111 | ␉{ 0x10DE0041, "GeForce 6800" },␊ |
112 | ␉{ 0x10DE0042, "GeForce 6800 LE" },␊ |
113 | ␉{ 0x10DE0043, "GeForce 6800 XE" },␊ |
114 | ␉{ 0x10DE0044, "GeForce 6800 XT" },␊ |
115 | ␉{ 0x10DE0045, "GeForce 6800 GT" },␊ |
116 | ␉{ 0x10DE0046, "GeForce 6800 GT" },␊ |
117 | ␉{ 0x10DE0047, "GeForce 6800 GS" },␊ |
118 | ␉{ 0x10DE0048, "GeForce 6800 XT" },␊ |
119 | ␉{ 0x10DE004D, "Quadro FX 3400" },␊ |
120 | ␉{ 0x10DE004E, "Quadro FX 4000" },␊ |
121 | ␉{ 0x10DE0090, "GeForce 7800 GTX" },␊ |
122 | ␉{ 0x10DE0091, "GeForce 7800 GTX" },␊ |
123 | ␉{ 0x10DE0092, "GeForce 7800 GT" },␊ |
124 | ␉{ 0x10DE0093, "GeForce 7800 GS" },␊ |
125 | ␉{ 0x10DE0095, "GeForce 7800 SLI" },␊ |
126 | ␉{ 0x10DE0098, "GeForce Go 7800" },␊ |
127 | ␉{ 0x10DE0099, "GeForce Go 7800 GTX" },␊ |
128 | ␉{ 0x10DE009D, "Quadro FX 4500" },␊ |
129 | ␉{ 0x10DE00C0, "GeForce 6800 GS" },␊ |
130 | ␉{ 0x10DE00C1, "GeForce 6800" },␊ |
131 | ␉{ 0x10DE00C2, "GeForce 6800 LE" },␊ |
132 | ␉{ 0x10DE00C3, "GeForce 6800 XT" },␊ |
133 | ␉{ 0x10DE00C8, "GeForce Go 6800" },␊ |
134 | ␉{ 0x10DE00C9, "GeForce Go 6800 Ultra" },␊ |
135 | ␉{ 0x10DE00CC, "Quadro FX Go1400" },␊ |
136 | ␉{ 0x10DE00CD, "Quadro FX 3450/4000 SDI" },␊ |
137 | ␉{ 0x10DE00CE, "Quadro FX 1400" },␊ |
138 | ␉{ 0x10DE00F1, "GeForce 6600 GT" },␊ |
139 | ␉{ 0x10DE00F2, "GeForce 6600" },␊ |
140 | ␉{ 0x10DE00F3, "GeForce 6200" },␊ |
141 | ␉{ 0x10DE00F4, "GeForce 6600 LE" },␊ |
142 | ␉{ 0x10DE00F5, "GeForce 7800 GS" },␊ |
143 | ␉{ 0x10DE00F6, "GeForce 6800 GS/XT" },␊ |
144 | ␉{ 0x10DE00F8, "Quadro FX 3400/4400" },␊ |
145 | ␉{ 0x10DE00F9, "GeForce 6800 Series GPU" },␊ |
146 | ␉{ 0x10DE0140, "GeForce 6600 GT" },␊ |
147 | ␉{ 0x10DE0141, "GeForce 6600" },␊ |
148 | ␉{ 0x10DE0142, "GeForce 6600 LE" },␊ |
149 | ␉{ 0x10DE0143, "GeForce 6600 VE" },␊ |
150 | ␉{ 0x10DE0144, "GeForce Go 6600" },␊ |
151 | ␉{ 0x10DE0145, "GeForce 6610 XL" },␊ |
152 | ␉{ 0x10DE0146, "GeForce Go 6600 TE/6200 TE" },␊ |
153 | ␉{ 0x10DE0147, "GeForce 6700 XL" },␊ |
154 | ␉{ 0x10DE0148, "GeForce Go 6600" },␊ |
155 | ␉{ 0x10DE0149, "GeForce Go 6600 GT" },␊ |
156 | ␉{ 0x10DE014A, "Quadro NVS 440" },␊ |
157 | ␉{ 0x10DE014C, "Quadro FX 550" },␊ |
158 | ␉{ 0x10DE014D, "Quadro FX 550" },␊ |
159 | ␉{ 0x10DE014E, "Quadro FX 540" },␊ |
160 | ␉{ 0x10DE014F, "GeForce 6200" },␊ |
161 | ␉{ 0x10DE0160, "GeForce 6500" },␊ |
162 | ␉{ 0x10DE0161, "GeForce 6200 TurboCache(TM)" },␊ |
163 | ␉{ 0x10DE0162, "GeForce 6200SE TurboCache(TM)" },␊ |
164 | ␉{ 0x10DE0163, "GeForce 6200 LE" },␊ |
165 | ␉{ 0x10DE0164, "GeForce Go 6200" },␊ |
166 | ␉{ 0x10DE0165, "Quadro NVS 285" },␊ |
167 | ␉{ 0x10DE0166, "GeForce Go 6400" },␊ |
168 | ␉{ 0x10DE0167, "GeForce Go 6200" },␊ |
169 | ␉{ 0x10DE0168, "GeForce Go 6400" },␊ |
170 | ␉{ 0x10DE0169, "GeForce 6250" },␊ |
171 | ␉{ 0x10DE016A, "GeForce 7100 GS" },␊ |
172 | ␉{ 0x10DE0191, "GeForce 8800 GTX" },␊ |
173 | ␉{ 0x10DE0193, "GeForce 8800 GTS" },␊ |
174 | ␉{ 0x10DE0194, "GeForce 8800 Ultra" },␊ |
175 | ␉{ 0x10DE0197, "Tesla C870" },␊ |
176 | ␉{ 0x10DE019D, "Quadro FX 5600" },␊ |
177 | ␉{ 0x10DE019E, "Quadro FX 4600" },␊ |
178 | ␉{ 0x10DE01D0, "GeForce 7350 LE" },␊ |
179 | ␉{ 0x10DE01D1, "GeForce 7300 LE" },␊ |
180 | ␉{ 0x10DE01D2, "GeForce 7550 LE" },␊ |
181 | ␉{ 0x10DE01D3, "GeForce 7300 SE/7200 GS" },␊ |
182 | ␉{ 0x10DE01D6, "GeForce Go 7200" },␊ |
183 | ␉{ 0x10DE01D7, "GeForce Go 7300" },␊ |
184 | ␉{ 0x10DE01D8, "GeForce Go 7400" },␊ |
185 | ␉{ 0x10DE01D9, "GeForce Go 7400 GS" },␊ |
186 | ␉{ 0x10DE01DA, "Quadro NVS 110M" },␊ |
187 | ␉{ 0x10DE01DB, "Quadro NVS 120M" },␊ |
188 | ␉{ 0x10DE01DC, "Quadro FX 350M" },␊ |
189 | ␉{ 0x10DE01DD, "GeForce 7500 LE" },␊ |
190 | ␉{ 0x10DE01DE, "Quadro FX 350" },␊ |
191 | ␉{ 0x10DE01DF, "GeForce 7300 GS" },␊ |
192 | ␉{ 0x10DE0211, "GeForce 6800" },␊ |
193 | ␉{ 0x10DE0212, "GeForce 6800 LE" },␊ |
194 | ␉{ 0x10DE0215, "GeForce 6800 GT" },␊ |
195 | ␉{ 0x10DE0218, "GeForce 6800 XT" },␊ |
196 | ␉{ 0x10DE0221, "GeForce 6200" },␊ |
197 | ␉{ 0x10DE0222, "GeForce 6200 A-LE" },␊ |
198 | ␉{ 0x10DE0240, "GeForce 6150" },␊ |
199 | ␉{ 0x10DE0241, "GeForce 6150 LE" },␊ |
200 | ␉{ 0x10DE0242, "GeForce 6100" },␊ |
201 | ␉{ 0x10DE0244, "GeForce Go 6150" },␊ |
202 | ␉{ 0x10DE0245, "Quadro NVS 210S / GeForce 6150LE" },␊ |
203 | ␉{ 0x10DE0247, "GeForce Go 6100" },␊ |
204 | ␉{ 0x10DE0290, "GeForce 7900 GTX" },␊ |
205 | ␉{ 0x10DE0291, "GeForce 7900 GT/GTO" },␊ |
206 | ␉{ 0x10DE0292, "GeForce 7900 GS" },␊ |
207 | ␉{ 0x10DE0293, "GeForce 7950 GX2" },␊ |
208 | ␉{ 0x10DE0294, "GeForce 7950 GX2" },␊ |
209 | ␉{ 0x10DE0295, "GeForce 7950 GT" },␊ |
210 | ␉{ 0x10DE0298, "GeForce Go 7900 GS" },␊ |
211 | ␉{ 0x10DE0299, "GeForce Go 7900 GTX" },␊ |
212 | ␉{ 0x10DE029A, "Quadro FX 2500M" },␊ |
213 | ␉{ 0x10DE029B, "Quadro FX 1500M" },␊ |
214 | ␉{ 0x10DE029C, "Quadro FX 5500" },␊ |
215 | ␉{ 0x10DE029D, "Quadro FX 3500" },␊ |
216 | ␉{ 0x10DE029E, "Quadro FX 1500" },␊ |
217 | ␉{ 0x10DE029F, "Quadro FX 4500 X2" },␊ |
218 | ␉{ 0x10DE02E0, "GeForce 7600 GT" },␊ |
219 | ␉{ 0x10DE02E1, "GeForce 7600 GS" },␊ |
220 | ␉{ 0x10DE02E2, "GeForce 7300 GT" },␊ |
221 | ␉{ 0x10DE02E3, "GeForce 7900 GS" },␊ |
222 | ␉{ 0x10DE02E4, "GeForce 7950 GT" },␊ |
223 | ␉{ 0x10DE0301, "GeForce FX 5800 Ultra" },␊ |
224 | ␉{ 0x10DE0302, "GeForce FX 5800" },␊ |
225 | ␉{ 0x10DE0308, "Quadro FX 2000" },␊ |
226 | ␉{ 0x10DE0309, "Quadro FX 1000" },␊ |
227 | ␉{ 0x10DE0311, "GeForce FX 5600 Ultra" },␊ |
228 | ␉{ 0x10DE0312, "GeForce FX 5600" },␊ |
229 | ␉{ 0x10DE0314, "GeForce FX 5600XT" },␊ |
230 | ␉{ 0x10DE031A, "GeForce FX Go5600" },␊ |
231 | ␉{ 0x10DE031B, "GeForce FX Go5650" },␊ |
232 | ␉{ 0x10DE031C, "Quadro FX Go700" },␊ |
233 | ␉{ 0x10DE0324, "GeForce FX Go5200" },␊ |
234 | ␉{ 0x10DE0325, "GeForce FX Go5250" },␊ |
235 | ␉{ 0x10DE0326, "GeForce FX 5500" },␊ |
236 | ␉{ 0x10DE0328, "GeForce FX Go5200 32M/64M" },␊ |
237 | ␉{ 0x10DE032A, "Quadro NVS 55/280 PCI" },␊ |
238 | ␉{ 0x10DE032B, "Quadro FX 500/600 PCI" },␊ |
239 | ␉{ 0x10DE032C, "GeForce FX Go53xx Series" },␊ |
240 | ␉{ 0x10DE032D, "GeForce FX Go5100" },␊ |
241 | ␉{ 0x10DE0330, "GeForce FX 5900 Ultra" },␊ |
242 | ␉{ 0x10DE0331, "GeForce FX 5900" },␊ |
243 | ␉{ 0x10DE0332, "GeForce FX 5900XT" },␊ |
244 | ␉{ 0x10DE0333, "GeForce FX 5950 Ultra" },␊ |
245 | ␉{ 0x10DE0334, "GeForce FX 5900ZT" },␊ |
246 | ␉{ 0x10DE0338, "Quadro FX 3000" },␊ |
247 | ␉{ 0x10DE033F, "Quadro FX 700" },␊ |
248 | ␉{ 0x10DE0341, "GeForce FX 5700 Ultra" },␊ |
249 | ␉{ 0x10DE0342, "GeForce FX 5700" },␊ |
250 | ␉{ 0x10DE0343, "GeForce FX 5700LE" },␊ |
251 | ␉{ 0x10DE0344, "GeForce FX 5700VE" },␊ |
252 | ␉{ 0x10DE0347, "GeForce FX Go5700" },␊ |
253 | ␉{ 0x10DE0348, "GeForce FX Go5700" },␊ |
254 | ␉{ 0x10DE034C, "Quadro FX Go1000" },␊ |
255 | ␉{ 0x10DE034E, "Quadro FX 1100" },␊ |
256 | ␉{ 0x10DE038B, "GeForce 7650 GS" },␊ |
257 | ␉{ 0x10DE0390, "GeForce 7650 GS" },␊ |
258 | ␉{ 0x10DE0391, "GeForce 7600 GT" },␊ |
259 | ␉{ 0x10DE0392, "GeForce 7600 GS" },␊ |
260 | ␉{ 0x10DE0393, "GeForce 7300 GT" },␊ |
261 | ␉{ 0x10DE0394, "GeForce 7600 LE" },␊ |
262 | ␉{ 0x10DE0395, "GeForce 7300 GT" },␊ |
263 | ␉{ 0x10DE0397, "GeForce Go 7700" },␊ |
264 | ␉{ 0x10DE0398, "GeForce Go 7600" },␊ |
265 | ␉{ 0x10DE0399, "GeForce Go 7600 GT"},␊ |
266 | ␉{ 0x10DE039A, "Quadro NVS 300M" },␊ |
267 | ␉{ 0x10DE039B, "GeForce Go 7900 SE" },␊ |
268 | ␉{ 0x10DE039C, "Quadro FX 550M" },␊ |
269 | ␉{ 0x10DE039E, "Quadro FX 560" },␊ |
270 | ␉{ 0x10DE03D0, "GeForce 6150SE nForce 430" },␊ |
271 | ␉{ 0x10DE03D1, "GeForce 6100 nForce 405" },␊ |
272 | ␉{ 0x10DE03D2, "GeForce 6100 nForce 400" },␊ |
273 | ␉{ 0x10DE03D5, "GeForce 6100 nForce 420" },␊ |
274 | ␉{ 0x10DE03D6, "GeForce 7025 / nForce 630a" },␊ |
275 | ␉{ 0x10DE0400, "GeForce 8600 GTS" },␊ |
276 | ␉{ 0x10DE0401, "GeForce 8600 GT" },␊ |
277 | ␉{ 0x10DE0402, "GeForce 8600 GT" },␊ |
278 | ␉{ 0x10DE0403, "GeForce 8600 GS" },␊ |
279 | ␉{ 0x10DE0404, "GeForce 8400 GS" },␊ |
280 | ␉{ 0x10DE0405, "GeForce 9500M GS" },␊ |
281 | ␉{ 0x10DE0406, "GeForce 8300 GS" },␊ |
282 | ␉{ 0x10DE0407, "GeForce 8600M GT" },␊ |
283 | ␉{ 0x10DE0408, "GeForce 9650M GS" },␊ |
284 | ␉{ 0x10DE0409, "GeForce 8700M GT" },␊ |
285 | ␉{ 0x10DE040A, "Quadro FX 370" },␊ |
286 | ␉{ 0x10DE040B, "Quadro NVS 320M" },␊ |
287 | ␉{ 0x10DE040C, "Quadro FX 570M" },␊ |
288 | ␉{ 0x10DE040D, "Quadro FX 1600M" },␊ |
289 | ␉{ 0x10DE040E, "Quadro FX 570" },␊ |
290 | ␉{ 0x10DE040F, "Quadro FX 1700" },␊ |
291 | ␉{ 0x10DE0410, "GeForce GT 330" },␊ |
292 | ␉{ 0x10DE0420, "GeForce 8400 SE" },␊ |
293 | ␉{ 0x10DE0421, "GeForce 8500 GT" },␊ |
294 | ␉{ 0x10DE0422, "GeForce 8400 GS" },␊ |
295 | ␉{ 0x10DE0423, "GeForce 8300 GS" },␊ |
296 | ␉{ 0x10DE0424, "GeForce 8400 GS" },␊ |
297 | ␉{ 0x10DE0425, "GeForce 8600M GS" },␊ |
298 | ␉{ 0x10DE0426, "GeForce 8400M GT" },␊ |
299 | ␉{ 0x10DE0427, "GeForce 8400M GS" },␊ |
300 | ␉{ 0x10DE0428, "GeForce 8400M G" },␊ |
301 | ␉{ 0x10DE0429, "Quadro NVS 140M" },␊ |
302 | ␉{ 0x10DE042A, "Quadro NVS 130M" },␊ |
303 | ␉{ 0x10DE042B, "Quadro NVS 135M" },␊ |
304 | ␉{ 0x10DE042C, "GeForce 9400 GT" },␊ |
305 | ␉{ 0x10DE042D, "Quadro FX 360M" },␊ |
306 | ␉{ 0x10DE042E, "GeForce 9300M G" },␊ |
307 | ␉{ 0x10DE042F, "Quadro NVS 290" },␊ |
308 | ␉{ 0x10DE053A, "GeForce 7050 PV / nForce 630a" },␊ |
309 | ␉{ 0x10DE053B, "GeForce 7050 PV / nForce 630a" },␊ |
310 | ␉{ 0x10DE053E, "GeForce 7025 / nForce 630a" },␊ |
311 | ␉{ 0x10DE05E0, "GeForce GTX 295" },␊ |
312 | ␉{ 0x10DE05E1, "GeForce GTX 280" },␊ |
313 | ␉{ 0x10DE05E2, "GeForce GTX 260" },␊ |
314 | ␉{ 0x10DE05E3, "GeForce GTX 285" },␊ |
315 | ␉{ 0x10DE05E6, "GeForce GTX 275" },␊ |
316 | ␉{ 0x10DE05EA, "GeForce GTX 260" },␊ |
317 | ␉{ 0x10DE05EB, "GeForce GTX 295" },␊ |
318 | ␉{ 0x10DE05ED, "Quadroplex 2200 D2" },␊ |
319 | ␉{ 0x10DE05F8, "Quadroplex 2200 S4" },␊ |
320 | ␉{ 0x10DE05F9, "Quadro CX" },␊ |
321 | ␉{ 0x10DE05FD, "Quadro FX 5800" },␊ |
322 | ␉{ 0x10DE05FE, "Quadro FX 4800" },␊ |
323 | ␉{ 0x10DE05FF, "Quadro FX 3800" },␊ |
324 | ␉{ 0x10DE0600, "GeForce 8800 GTS 512" },␊ |
325 | ␉{ 0x10DE0601, "GeForce 9800 GT" },␊ |
326 | ␉{ 0x10DE0602, "GeForce 8800 GT" },␊ |
327 | ␉{ 0x10DE0603, "GeForce GT 230" },␊ |
328 | ␉{ 0x10DE0604, "GeForce 9800 GX2" },␊ |
329 | ␉{ 0x10DE0605, "GeForce 9800 GT" },␊ |
330 | ␉{ 0x10DE0606, "GeForce 8800 GS" },␊ |
331 | ␉{ 0x10DE0607, "GeForce GTS 240" },␊ |
332 | ␉{ 0x10DE0608, "GeForce 9800M GTX" },␊ |
333 | ␉{ 0x10DE0609, "GeForce 8800M GTS" },␊ |
334 | ␉{ 0x10DE060A, "GeForce GTX 280M" },␊ |
335 | ␉{ 0x10DE060B, "GeForce 9800M GT" },␊ |
336 | ␉{ 0x10DE060C, "GeForce 8800M GTX" },␊ |
337 | ␉{ 0x10DE060D, "GeForce 8800 GS" },␊ |
338 | ␉{ 0x10DE060F, "GeForce GTX 285M" },␊ |
339 | ␉{ 0x10DE0610, "GeForce 9600 GSO" },␊ |
340 | ␉{ 0x10DE0611, "GeForce 8800 GT" },␊ |
341 | ␉{ 0x10DE0612, "GeForce 9800 GTX" },␊ |
342 | ␉{ 0x10DE0613, "GeForce 9800 GTX+" },␊ |
343 | ␉{ 0x10DE0614, "GeForce 9800 GT" },␊ |
344 | ␉{ 0x10DE0615, "GeForce GTS 250" },␊ |
345 | ␉{ 0x10DE0617, "GeForce 9800M GTX" },␊ |
346 | ␉{ 0x10DE0618, "GeForce GTX 260M" },␊ |
347 | ␉{ 0x10DE0619, "Quadro FX 4700 X2" },␊ |
348 | ␉{ 0x10DE061A, "Quadro FX 3700" },␊ |
349 | ␉{ 0x10DE061B, "Quadro VX 200" },␊ |
350 | ␉{ 0x10DE061C, "Quadro FX 3600M" },␊ |
351 | ␉{ 0x10DE061D, "Quadro FX 2800M" },␊ |
352 | ␉{ 0x10DE061F, "Quadro FX 3800M" },␊ |
353 | ␉{ 0x10DE0622, "GeForce 9600 GT" },␊ |
354 | ␉{ 0x10DE0623, "GeForce 9600 GS" },␊ |
355 | ␉{ 0x10DE0625, "GeForce 9600 GSO 512"},␊ |
356 | ␉{ 0x10DE0626, "GeForce GT 130" },␊ |
357 | ␉{ 0x10DE0627, "GeForce GT 140" },␊ |
358 | ␉{ 0x10DE0628, "GeForce 9800M GTS" },␊ |
359 | ␉{ 0x10DE062A, "GeForce 9700M GTS" },␊ |
360 | ␉{ 0x10DE062C, "GeForce 9800M GTS" },␊ |
361 | ␉{ 0x10DE062D, "GeForce 9600 GT" },␊ |
362 | ␉{ 0x10DE062E, "GeForce 9600 GT" },␊ |
363 | ␉{ 0x10DE0631, "GeForce GTS 160M" },␊ |
364 | ␉{ 0x10DE0632, "GeForce GTS 150M" },␊ |
365 | ␉{ 0x10DE0635, "GeForce 9600 GSO" },␊ |
366 | ␉{ 0x10DE0637, "GeForce 9600 GT" },␊ |
367 | ␉{ 0x10DE0638, "Quadro FX 1800" },␊ |
368 | ␉{ 0x10DE063A, "Quadro FX 2700M" },␊ |
369 | ␉{ 0x10DE0640, "GeForce 9500 GT" },␊ |
370 | ␉{ 0x10DE0641, "GeForce 9400 GT" },␊ |
371 | ␉{ 0x10DE0642, "GeForce 8400 GS" },␊ |
372 | ␉{ 0x10DE0643, "GeForce 9500 GT" },␊ |
373 | ␉{ 0x10DE0644, "GeForce 9500 GS" },␊ |
374 | ␉{ 0x10DE0645, "GeForce 9500 GS" },␊ |
375 | ␉{ 0x10DE0646, "GeForce GT 120" },␊ |
376 | ␉{ 0x10DE0647, "GeForce 9600M GT" },␊ |
377 | ␉{ 0x10DE0648, "GeForce 9600M GS" },␊ |
378 | ␉{ 0x10DE0649, "GeForce 9600M GT" },␊ |
379 | ␉{ 0x10DE064A, "GeForce 9700M GT" },␊ |
380 | ␉{ 0x10DE064B, "GeForce 9500M G" },␊ |
381 | ␉{ 0x10DE064C, "GeForce 9650M GT" },␊ |
382 | ␉{ 0x10DE0651, "GeForce G 110M" },␊ |
383 | ␉{ 0x10DE0652, "GeForce GT 130M" },␊ |
384 | ␉{ 0x10DE0653, "GeForce GT 120M" },␊ |
385 | ␉{ 0x10DE0654, "GeForce GT 220M" },␊ |
386 | ␉{ 0x10DE0656, "GeForce 9650 S" },␊ |
387 | ␉{ 0x10DE0658, "Quadro FX 380" },␊ |
388 | ␉{ 0x10DE0659, "Quadro FX 580" },␊ |
389 | ␉{ 0x10DE065A, "Quadro FX 1700M" },␊ |
390 | ␉{ 0x10DE065B, "GeForce 9400 GT" },␊ |
391 | ␉{ 0x10DE065C, "Quadro FX 770M" },␊ |
392 | ␉{ 0x10DE065F, "GeForce G210" },␊ |
393 | ␉{ 0x10DE06C0, "GeForce GTX 480" },␊ |
394 | ␉{ 0x10DE06C3, "GeForce GTX D12U" },␊ |
395 | ␉{ 0x10DE06C4, "GeForce GTX 465" },␊ |
396 | ␉{ 0x10DE06CA, "GeForce GTX 480M" },␊ |
397 | ␉{ 0x10DE06CD, "GeForce GTX 470" },␊ |
398 | ␉{ 0x10DE06D1, "Tesla C2050" },␉// TODO: sub-device id: 0x0771␊ |
399 | ␉{ 0x10DE06D1, "Tesla C2070" },␉// TODO: sub-device id: 0x0772␊ |
400 | ␉{ 0x10DE06D8, "Quadro 6000" },␊ |
401 | ␉{ 0x10DE06D9, "Quadro 5000" },␊ |
402 | ␉{ 0x10DE06DA, "Quadro 5000M" },␊ |
403 | ␉{ 0x10DE06DC, "Quadro 6000" },␊ |
404 | ␉{ 0x10DE06DD, "Quadro 4000" },␊ |
405 | ␉{ 0x10DE06DE, "Tesla M2050" },␉// TODO: sub-device id: 0x0846␊ |
406 | ␉{ 0x10DE06DE, "Tesla M2070" },␉// TODO: sub-device id: ?␊ |
407 | ␉{ 0x10DE06E0, "GeForce 9300 GE" },␊ |
408 | ␉{ 0x10DE06E1, "GeForce 9300 GS" },␊ |
409 | ␉{ 0x10DE06E2, "GeForce 8400" },␊ |
410 | ␉{ 0x10DE06E3, "GeForce 8400 SE" },␊ |
411 | ␉{ 0x10DE06E4, "GeForce 8400 GS" },␊ |
412 | ␉{ 0x10DE06E5, "GeForce 9300M GS" },␊ |
413 | ␉{ 0x10DE06E6, "GeForce G100" },␊ |
414 | ␉{ 0x10DE06E7, "GeForce 9300 SE" },␊ |
415 | ␉{ 0x10DE06E8, "GeForce 9200M GS" },␊ |
416 | ␉{ 0x10DE06E9, "GeForce 9300M GS" },␊ |
417 | ␉{ 0x10DE06EA, "Quadro NVS 150M" },␊ |
418 | ␉{ 0x10DE06EB, "Quadro NVS 160M" },␊ |
419 | ␉{ 0x10DE06EC, "GeForce G 105M" },␊ |
420 | ␉{ 0x10DE06EF, "GeForce G 103M" },␊ |
421 | ␉{ 0x10DE06F8, "Quadro NVS 420" },␊ |
422 | ␉{ 0x10DE06F9, "Quadro FX 370 LP" },␊ |
423 | ␉{ 0x10DE06FA, "Quadro NVS 450" },␊ |
424 | ␉{ 0x10DE06FB, "Quadro FX 370M" },␊ |
425 | ␉{ 0x10DE06FD, "Quadro NVS 295" },␊ |
426 | ␉{ 0x10DE07E0, "GeForce 7150 / nForce 630i" },␊ |
427 | ␉{ 0x10DE07E1, "GeForce 7100 / nForce 630i" },␊ |
428 | ␉{ 0x10DE07E2, "GeForce 7050 / nForce 630i" },␊ |
429 | ␉{ 0x10DE07E3, "GeForce 7050 / nForce 610i" },␊ |
430 | ␉{ 0x10DE07E5, "GeForce 7050 / nForce 620i" },␊ |
431 | ␉{ 0x10DE0844, "GeForce 9100M G" },␊ |
432 | ␉{ 0x10DE0845, "GeForce 8200M G" },␊ |
433 | ␉{ 0x10DE0846, "GeForce 9200" },␊ |
434 | ␉{ 0x10DE0847, "GeForce 9100" },␊ |
435 | ␉{ 0x10DE0848, "GeForce 8300" },␊ |
436 | ␉{ 0x10DE0849, "GeForce 8200" },␊ |
437 | ␉{ 0x10DE084A, "nForce 730a" },␊ |
438 | ␉{ 0x10DE084B, "GeForce 9200" },␊ |
439 | ␉{ 0x10DE084C, "nForce 980a/780a SLI" },␊ |
440 | ␉{ 0x10DE084D, "nForce 750a SLI" },␊ |
441 | ␉{ 0x10DE084F, "GeForce 8100 / nForce 720a" },␊ |
442 | ␉{ 0x10DE0860, "GeForce 9400" },␊ |
443 | ␉{ 0x10DE0861, "GeForce 9400" },␊ |
444 | ␉{ 0x10DE0862, "GeForce 9400M G" },␊ |
445 | ␉{ 0x10DE0863, "GeForce 9400M" },␊ |
446 | ␉{ 0x10DE0864, "GeForce 9300" },␊ |
447 | ␉{ 0x10DE0865, "ION" },␊ |
448 | ␉{ 0x10DE0866, "GeForce 9400M G" },␊ |
449 | ␉{ 0x10DE0867, "GeForce 9400" },␊ |
450 | ␉{ 0x10DE0868, "nForce 760i SLI" },␊ |
451 | ␉{ 0x10DE086A, "GeForce 9400" },␊ |
452 | ␉{ 0x10DE086C, "GeForce 9300 / nForce 730i" },␊ |
453 | ␉{ 0x10DE086D, "GeForce 9200" },␊ |
454 | ␉{ 0x10DE086E, "GeForce 9100M G" },␊ |
455 | ␉{ 0x10DE086F, "GeForce 8200M G" },␊ |
456 | ␉{ 0x10DE0870, "GeForce 9400M" },␊ |
457 | ␉{ 0x10DE0871, "GeForce 9200" },␊ |
458 | ␉{ 0x10DE0872, "GeForce G102M" },␊ |
459 | ␉{ 0x10DE0873, "GeForce G102M" },␊ |
460 | ␉{ 0x10DE0874, "ION 9300M" },␊ |
461 | ␉{ 0x10DE0876, "ION" },␊ |
462 | ␉{ 0x10DE087A, "GeForce 9400" },␊ |
463 | ␉{ 0x10DE087D, "ION 9400M" },␊ |
464 | ␉{ 0x10DE087E, "ION LE" },␊ |
465 | ␉{ 0x10DE087F, "ION LE" },␊ |
466 | ␉{ 0x10DE0A20, "GeForce GT220" },␊ |
467 | ␉{ 0x10DE0A22, "GeForce 315" },␊ |
468 | ␉{ 0x10DE0A23, "GeForce 210" },␊ |
469 | ␉{ 0x10DE0A28, "GeForce GT 230M" },␊ |
470 | ␉{ 0x10DE0A29, "GeForce GT 330M" },␊ |
471 | ␉{ 0x10DE0A2A, "GeForce GT 230M" },␊ |
472 | ␉{ 0x10DE0A2B, "GeForce GT 330M" },␊ |
473 | ␉{ 0x10DE0A2C, "NVS 5100M" },␊ |
474 | ␉{ 0x10DE0A2D, "GeForce GT 320M" },␊ |
475 | ␉{ 0x10DE0A34, "GeForce GT 240M" },␊ |
476 | ␉{ 0x10DE0A35, "GeForce GT 325M" },␊ |
477 | ␉{ 0x10DE0A3C, "Quadro FX 880M" },␊ |
478 | ␉{ 0x10DE0A60, "GeForce G210" },␊ |
479 | ␉{ 0x10DE0A62, "GeForce 205" },␊ |
480 | ␉{ 0x10DE0A63, "GeForce 310" },␊ |
481 | ␉{ 0x10DE0A64, "ION" },␊ |
482 | ␉{ 0x10DE0A65, "GeForce 210" },␊ |
483 | ␉{ 0x10DE0A66, "GeForce 310" },␊ |
484 | ␉{ 0x10DE0A67, "GeForce 315" },␊ |
485 | ␉{ 0x10DE0A68, "GeForce G105M" },␊ |
486 | ␉{ 0x10DE0A69, "GeForce G105M" },␊ |
487 | ␉{ 0x10DE0A6A, "NVS 2100M" },␊ |
488 | ␉{ 0x10DE0A6C, "NVS 3100M" },␊ |
489 | ␉{ 0x10DE0A6E, "GeForce 305M" },␊ |
490 | ␉{ 0x10DE0A6F, "ION" },␊ |
491 | ␉{ 0x10DE0A70, "GeForce 310M" },␊ |
492 | ␉{ 0x10DE0A71, "GeForce 305M" },␊ |
493 | ␉{ 0x10DE0A72, "GeForce 310M" },␊ |
494 | ␉{ 0x10DE0A73, "GeForce 305M" },␊ |
495 | ␉{ 0x10DE0A74, "GeForce G210M" },␊ |
496 | ␉{ 0x10DE0A75, "GeForce G310M" },␊ |
497 | ␉{ 0x10DE0A78, "Quadro FX 380 LP" },␊ |
498 | ␉{ 0x10DE0A7C, "Quadro FX 380M" },␊ |
499 | ␉{ 0x10DE0CA0, "GeForce GT 330 " },␊ |
500 | ␉{ 0x10DE0CA2, "GeForce GT 320" },␊ |
501 | ␉{ 0x10DE0CA3, "GeForce GT 240" },␊ |
502 | ␉{ 0x10DE0CA4, "GeForce GT 340" },␊ |
503 | ␉{ 0x10DE0CA7, "GeForce GT 330" },␊ |
504 | ␉{ 0x10DE0CA8, "GeForce GTS 260M" },␊ |
505 | ␉{ 0x10DE0CA9, "GeForce GTS 250M" },␊ |
506 | ␉{ 0x10DE0CAC, "GeForce 315" },␊ |
507 | ␉{ 0x10DE0CAF, "GeForce GT 335M" },␊ |
508 | ␉{ 0x10DE0CB0, "GeForce GTS 350M" },␊ |
509 | ␉{ 0x10DE0CB1, "GeForce GT 360M" },␊ |
510 | ␉{ 0x10DE0CBC, "Quadro FX 1800M" },␊ |
511 | ␉{ 0x10DE0DC0, "GeForce GT 440" },␊ |
512 | ␉{ 0x10DE0DC1, "D12-P1-35" },␊ |
513 | ␉{ 0x10DE0DC2, "D12-P1-35" },␊ |
514 | ␉{ 0x10DE0DC4, "GeForce GTS 450" },␊ |
515 | ␉{ 0x10DE0DC5, "GeForce GTS 450" },␊ |
516 | ␉{ 0x10DE0DC6, "GeForce GTS 450" },␊ |
517 | ␉{ 0x10DE0DCA, "GF10x" },␊ |
518 | ␉{ 0x10DE0DD1, "GeForce GTX 460M" },␊ |
519 | ␉{ 0x10DE0DD2, "GeForce GT 445M" },␊ |
520 | ␉{ 0x10DE0DD3, "GeForce GT 435M" },␊ |
521 | ␉{ 0x10DE0DD8, "Quadro 2000" },␊ |
522 | ␉{ 0x10DE0DDE, "GF106-ES" },␊ |
523 | ␉{ 0x10DE0DDF, "GF106-INT" },␊ |
524 | ␉{ 0x10DE0DE1, "GeForce GT 430" },␊ |
525 | ␉{ 0x10DE0DE2, "GeForce GT 420" },␊ |
526 | ␉{ 0x10DE0DEB, "GeForce GT 555M" },␊ |
527 | ␉{ 0x10DE0DEE, "GeForce GT 415M" },␊ |
528 | ␉{ 0x10DE0DF0, "GeForce GT 425M" },␊ |
529 | ␉{ 0x10DE0DF1, "GeForce GT 420M" },␊ |
530 | ␉{ 0x10DE0DF2, "GeForce GT 435M" },␊ |
531 | ␉{ 0x10DE0DF3, "GeForce GT 420M" },␊ |
532 | ␉{ 0x10DE0DF8, "Quadro 600" },␊ |
533 | ␉{ 0x10DE0DFE, "GF108 ES" },␊ |
534 | ␉{ 0x10DE0DFF, "GF108 INT" },␊ |
535 | ␉{ 0x10DE0E21, "D12U-25" },␊ |
536 | ␉{ 0x10DE0E22, "GeForce GTX 460" },␊ |
537 | ␉{ 0x10DE0E23, "GeForce GTX 460 SE" },␊ |
538 | ␉{ 0x10DE0E24, "GeForce GTX 460" },␊ |
539 | ␉{ 0x10DE0E25, "D12U-50" },␊ |
540 | ␉{ 0x10DE0E30, "GeForce GTX 470M" },␊ |
541 | ␉{ 0x10DE0E38, "GF104GL" },␊ |
542 | ␉{ 0x10DE0E3E, "GF104-ES" },␊ |
543 | ␉{ 0x10DE0E3F, "GF104-INT" },␊ |
544 | ␉{ 0x10DE1080, "GeForce GTX 580" },␊ |
545 | ␉{ 0x10DE1081, "D13U" },␊ |
546 | ␉{ 0x10DE1082, "D13U" },␊ |
547 | ␉{ 0x10DE1083, "D13U" },␊ |
548 | ␉{ 0x10DE1098, "D13U" },␊ |
549 | ␉{ 0x10DE109A, "N12E-Q5" },␊ |
550 | ␉{ 0x10DE10C3, "GeForce 8400 GS" }␊ |
551 | };␊ |
552 | ␊ |
553 | static uint16_t swap16(uint16_t x)␊ |
554 | {␊ |
555 | ␉return (((x & 0x00FF) << 8) | ((x & 0xFF00) >> 8));␊ |
556 | }␊ |
557 | ␊ |
558 | static uint16_t read16(uint8_t *ptr, uint16_t offset)␊ |
559 | {␊ |
560 | ␉uint8_t ret[2];␊ |
561 | ␉ret[0] = ptr[offset+1];␊ |
562 | ␉ret[1] = ptr[offset];␊ |
563 | ␉return *((uint16_t*)&ret);␊ |
564 | }␊ |
565 | ␊ |
566 | #if 0␊ |
567 | static uint32_t swap32(uint32_t x)␊ |
568 | {␊ |
569 | ␉return ((x & 0x000000FF) << 24) | ((x & 0x0000FF00) << 8 ) | ((x & 0x00FF0000) >> 8 ) | ((x & 0xFF000000) >> 24);␊ |
570 | }␊ |
571 | ␊ |
572 | static uint8_t read8(uint8_t *ptr, uint16_t offset)␊ |
573 | { ␊ |
574 | ␉return ptr[offset];␊ |
575 | }␊ |
576 | ␊ |
577 | static uint32_t read32(uint8_t *ptr, uint16_t offset)␊ |
578 | {␊ |
579 | ␉uint8_t ret[4];␊ |
580 | ␉ret[0] = ptr[offset+3];␊ |
581 | ␉ret[1] = ptr[offset+2];␊ |
582 | ␉ret[2] = ptr[offset+1];␊ |
583 | ␉ret[3] = ptr[offset];␊ |
584 | ␉return *((uint32_t*)&ret);␊ |
585 | }␊ |
586 | #endif␊ |
587 | ␊ |
588 | static int patch_nvidia_rom(uint8_t *rom)␊ |
589 | {␊ |
590 | ␉if (!rom || (rom[0] != 0x55 && rom[1] != 0xaa)) {␊ |
591 | ␉␉printf("False ROM signature: 0x%02x%02x\n", rom[0], rom[1]);␊ |
592 | ␉␉return PATCH_ROM_FAILED;␊ |
593 | ␉}␊ |
594 | ␉␊ |
595 | ␉uint16_t dcbptr = swap16(read16(rom, 0x36));␊ |
596 | ␉if(!dcbptr) {␊ |
597 | ␉␉printf("no dcb table found\n");␊ |
598 | ␉␉return PATCH_ROM_FAILED;␊ |
599 | ␉}/* else␊ |
600 | ␉ printf("dcb table at offset 0x%04x\n", dcbptr);␊ |
601 | ␉ */␊ |
602 | ␉uint8_t *dcbtable = &rom[dcbptr];␊ |
603 | ␉uint8_t dcbtable_version = dcbtable[0];␊ |
604 | ␉uint8_t headerlength = 0;␊ |
605 | ␉uint8_t recordlength = 0;␊ |
606 | ␉uint8_t numentries = 0;␊ |
607 | ␉␊ |
608 | ␉if(dcbtable_version >= 0x20) {␊ |
609 | ␉␉uint32_t sig;␊ |
610 | ␉␉␊ |
611 | ␉␉if(dcbtable_version >= 0x30) {␊ |
612 | ␉␉␉headerlength = dcbtable[1];␊ |
613 | ␉␉␉numentries = dcbtable[2];␊ |
614 | ␉␉␉recordlength = dcbtable[3];␊ |
615 | ␉␉␉sig = *(uint32_t *)&dcbtable[6];␊ |
616 | ␉␉} else {␊ |
617 | ␉␉␉sig = *(uint32_t *)&dcbtable[4];␊ |
618 | ␉␉␉headerlength = 8;␊ |
619 | ␉␉}␊ |
620 | ␉␉if (sig != 0x4edcbdcb) {␊ |
621 | ␉␉␉printf("bad display config block signature (0x%8x)\n", sig);␊ |
622 | ␉␉␉return PATCH_ROM_FAILED;␊ |
623 | ␉␉}␊ |
624 | ␉} else if (dcbtable_version >= 0x14) { /* some NV15/16, and NV11+ */␊ |
625 | ␉␉char sig[8] = { 0 };␊ |
626 | ␉␉␊ |
627 | ␉␉strncpy(sig, (char *)&dcbtable[-7], 7);␊ |
628 | ␉␉recordlength = 10;␊ |
629 | ␉␉if (strcmp(sig, "DEV_REC")) {␊ |
630 | ␉␉␉printf("Bad Display Configuration Block signature (%s)\n", sig);␊ |
631 | ␉␉␉return PATCH_ROM_FAILED;␊ |
632 | ␉␉}␊ |
633 | ␉} else {␊ |
634 | ␉␉printf("ERROR: dcbtable_version is 0x%X\n", dcbtable_version);␊ |
635 | ␉␉return PATCH_ROM_FAILED;␊ |
636 | ␉}␊ |
637 | ␉␊ |
638 | ␉if(numentries >= MAX_NUM_DCB_ENTRIES)␊ |
639 | ␉␉numentries = MAX_NUM_DCB_ENTRIES;␊ |
640 | ␉␊ |
641 | ␉uint8_t num_outputs = 0, i=0;␊ |
642 | ␉struct dcbentry {␊ |
643 | ␉␉uint8_t type;␊ |
644 | ␉␉uint8_t index;␊ |
645 | ␉␉uint8_t *heads;␊ |
646 | ␉} entries[numentries];␊ |
647 | ␉␊ |
648 | ␉for (i = 0; i < numentries; i++) {␊ |
649 | ␉␉uint32_t connection;␊ |
650 | ␉␉connection = *(uint32_t *)&dcbtable[headerlength + recordlength * i];␊ |
651 | ␉␉/* Should we allow discontinuous DCBs? Certainly DCB I2C tables can be discontinuous */␊ |
652 | ␉␉if ((connection & 0x0000000f) == 0x0000000f) /* end of records */ ␊ |
653 | ␉␉␉continue;␊ |
654 | ␉␉if (connection == 0x00000000) /* seen on an NV11 with DCB v1.5 */ ␊ |
655 | ␉␉␉continue;␊ |
656 | ␉␉if ((connection & 0xf) == 0x6) /* we skip type 6 as it doesnt appear on macbook nvcaps */␊ |
657 | ␉␉␉continue;␊ |
658 | ␉␉␊ |
659 | ␉␉entries[num_outputs].type = connection & 0xf;␊ |
660 | ␉␉entries[num_outputs].index = num_outputs;␊ |
661 | ␉␉entries[num_outputs++].heads = (uint8_t*)&(dcbtable[(headerlength + recordlength * i) + 1]);␊ |
662 | ␊ |
663 | ␉}␊ |
664 | ␉␊ |
665 | ␉int has_lvds = false;␊ |
666 | ␉uint8_t channel1 = 0, channel2 = 0;␊ |
667 | ␉␊ |
668 | ␉for(i=0; i<num_outputs; i++) {␊ |
669 | ␉␉if(entries[i].type == 3) {␊ |
670 | ␉␉␉has_lvds = true;␊ |
671 | ␉␉␉//printf("found LVDS\n");␊ |
672 | ␉␉␉channel1 |= ( 0x1 << entries[i].index);␊ |
673 | ␉␉␉entries[i].type = TYPE_GROUPED;␊ |
674 | ␉␉}␊ |
675 | ␉}␊ |
676 | ␉// if we have a LVDS output, we group the rest to the second channel␊ |
677 | ␉if(has_lvds) {␊ |
678 | ␉␉for(i=0; i<num_outputs; i++) {␊ |
679 | ␉␉␉if(entries[i].type == TYPE_GROUPED)␊ |
680 | ␉␉␉␉continue;␊ |
681 | ␉␉␉channel2 |= ( 0x1 << entries[i].index);␊ |
682 | ␉␉␉entries[i].type = TYPE_GROUPED;␊ |
683 | ␉␉}␊ |
684 | ␉} else {␊ |
685 | ␉␉//␊ |
686 | ␉␉int x;␊ |
687 | ␉␉// we loop twice as we need to generate two channels␊ |
688 | ␉␉for(x=0; x<=1; x++) {␊ |
689 | ␉␉␉for(i=0; i<num_outputs; i++) {␊ |
690 | ␉␉␉␉if(entries[i].type == TYPE_GROUPED)␊ |
691 | ␉␉␉␉␉continue;␊ |
692 | ␉␉␉␉// if type is TMDS, the prior output is ANALOG␊ |
693 | ␉␉␉␉// we always group ANALOG and TMDS␊ |
694 | ␉␉␉␉// if there is a TV output after TMDS, we group it to that channel as well␊ |
695 | ␉␉␉␉if(i && entries[i].type == 0x2) {␊ |
696 | ␉␉␉␉␉switch (x) {␊ |
697 | ␉␉␉␉␉␉case 0:␊ |
698 | ␉␉␉␉␉␉␉//printf("group channel 1\n");␊ |
699 | ␉␉␉␉␉␉␉channel1 |= ( 0x1 << entries[i].index);␊ |
700 | ␉␉␉␉␉␉␉entries[i].type = TYPE_GROUPED;␊ |
701 | ␉␉␉␉␉␉␉if((entries[i-1].type == 0x0)) {␊ |
702 | ␉␉␉␉␉␉␉␉channel1 |= ( 0x1 << entries[i-1].index);␊ |
703 | ␉␉␉␉␉␉␉␉entries[i-1].type = TYPE_GROUPED;␊ |
704 | ␉␉␉␉␉␉␉}␊ |
705 | ␉␉␉␉␉␉␉// group TV as well if there is one␊ |
706 | ␉␉␉␉␉␉␉if( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) ) {␊ |
707 | ␉␉␉␉␉␉␉␉//␉printf("group tv1\n");␊ |
708 | ␉␉␉␉␉␉␉␉channel1 |= ( 0x1 << entries[i+1].index);␊ |
709 | ␉␉␉␉␉␉␉␉entries[i+1].type = TYPE_GROUPED;␊ |
710 | ␉␉␉␉␉␉␉}␊ |
711 | ␉␉␉␉␉␉␉break;␊ |
712 | ␉␉␉␉␉␉case 1:␊ |
713 | ␉␉␉␉␉␉␉//printf("group channel 2 : %d\n", i);␊ |
714 | ␉␉␉␉␉␉␉channel2 |= ( 0x1 << entries[i].index);␊ |
715 | ␉␉␉␉␉␉␉entries[i].type = TYPE_GROUPED;␊ |
716 | ␉␉␉␉␉␉␉if((entries[i-1].type == 0x0)) {␊ |
717 | ␉␉␉␉␉␉␉␉channel2 |= ( 0x1 << entries[i-1].index);␊ |
718 | ␉␉␉␉␉␉␉␉entries[i-1].type = TYPE_GROUPED;␊ |
719 | ␉␉␉␉␉␉␉}␊ |
720 | ␉␉␉␉␉␉␉// group TV as well if there is one␊ |
721 | ␉␉␉␉␉␉␉if( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) ) {␊ |
722 | ␉␉␉␉␉␉␉␉//␉printf("group tv2\n");␊ |
723 | ␉␉␉␉␉␉␉␉channel2 |= ( 0x1 << entries[i+1].index);␊ |
724 | ␉␉␉␉␉␉␉␉entries[i+1].type = TYPE_GROUPED;␊ |
725 | ␉␉␉␉␉␉␉}␊ |
726 | ␉␉␉␉␉␉␉break;␊ |
727 | ␉␉␉␉␉␉␉␊ |
728 | ␉␉␉␉␉}␊ |
729 | ␉␉␉␉␉break;␊ |
730 | ␉␉␉␉}␊ |
731 | ␉␉␉}␊ |
732 | ␉␉}␊ |
733 | ␉}␊ |
734 | ␉␊ |
735 | ␉// if we have left ungrouped outputs merge them to the empty channel␊ |
736 | ␉uint8_t *togroup;// = (channel1 ? (channel2 ? NULL : &channel2) : &channel1);␊ |
737 | ␉togroup = &channel2;␊ |
738 | ␉for(i=0; i<num_outputs;i++)␊ |
739 | ␉␉if(entries[i].type != TYPE_GROUPED) {␊ |
740 | ␉␉␉//printf("%d not grouped\n", i);␊ |
741 | ␉␉␉if(togroup)␊ |
742 | ␉␉␉␉*togroup |= ( 0x1 << entries[i].index);␊ |
743 | ␉␉␉entries[i].type = TYPE_GROUPED;␊ |
744 | ␉␉}␊ |
745 | ␉␊ |
746 | ␉if(channel1 > channel2) {␊ |
747 | ␉␉uint8_t buff = channel1;␊ |
748 | ␉␉channel1 = channel2;␊ |
749 | ␉␉channel2 = buff;␊ |
750 | ␉}␊ |
751 | ␉␊ |
752 | ␉default_NVCAP[6] = channel1;␊ |
753 | ␉default_NVCAP[8] = channel2;␊ |
754 | ␉␊ |
755 | ␉// patching HEADS␊ |
756 | ␉for(i=0; i<num_outputs;i++) {␊ |
757 | ␉␉if(channel1 & (1 << i))␊ |
758 | ␉␉␉*entries[i].heads = 1;␊ |
759 | ␉␉else if(channel2 & (1 << i))␊ |
760 | ␉␉␉*entries[i].heads = 2;␊ |
761 | ␉}␊ |
762 | ␉␊ |
763 | ␉return (has_lvds ? PATCH_ROM_SUCCESS_HAS_LVDS : PATCH_ROM_SUCCESS);␊ |
764 | }␊ |
765 | ␊ |
766 | static char *get_nvidia_model(uint32_t id) {␊ |
767 | ␉int␉i;␊ |
768 | ␊ |
769 | ␉for (i=1; i< (sizeof(NVKnownChipsets) / sizeof(NVKnownChipsets[0])); i++) {␊ |
770 | ␉␉if (NVKnownChipsets[i].device == id) {␊ |
771 | ␉␉␉return NVKnownChipsets[i].name;␊ |
772 | ␉␉}␊ |
773 | ␉}␊ |
774 | ␉return NVKnownChipsets[0].name;␊ |
775 | }␊ |
776 | ␊ |
777 | static uint32_t load_nvidia_bios_file(const char *filename, uint8_t *buf, int bufsize)␊ |
778 | {␊ |
779 | ␉int␉fd;␊ |
780 | ␉int␉size;␊ |
781 | ␊ |
782 | ␉if ((fd = open_bvdev("bt(0,0)", filename, 0)) < 0) {␊ |
783 | ␉␉return 0;␊ |
784 | ␉}␊ |
785 | ␉size = file_size(fd);␊ |
786 | ␉if (size > bufsize) {␊ |
787 | ␉␉printf("Filesize of %s is bigger than expected! Truncating to 0x%x Bytes!\n", filename, bufsize);␊ |
788 | ␉␉size = bufsize;␊ |
789 | ␉}␊ |
790 | ␉size = read(fd, (char *)buf, size);␊ |
791 | ␉close(fd);␊ |
792 | ␉return size > 0 ? size : 0;␊ |
793 | }␊ |
794 | ␊ |
795 | static int devprop_add_nvidia_template(struct DevPropDevice *device)␊ |
796 | {␊ |
797 | ␉char␉tmp[16]; ␊ |
798 | ␊ |
799 | ␉if(!device)␊ |
800 | ␉␉return 0;␊ |
801 | ␊ |
802 | ␉if(!DP_ADD_TEMP_VAL(device, nvidia_compatible_0))␊ |
803 | ␉␉return 0;␊ |
804 | ␉if(!DP_ADD_TEMP_VAL(device, nvidia_device_type_0))␊ |
805 | ␉␉return 0;␊ |
806 | ␉if(!DP_ADD_TEMP_VAL(device, nvidia_name_0))␊ |
807 | ␉␉return 0;␊ |
808 | ␉if(!DP_ADD_TEMP_VAL(device, nvidia_compatible_1))␊ |
809 | ␉␉return 0;␊ |
810 | ␉if(!DP_ADD_TEMP_VAL(device, nvidia_device_type_1))␊ |
811 | ␉␉return 0;␊ |
812 | ␉if(!DP_ADD_TEMP_VAL(device, nvidia_name_1))␊ |
813 | ␉␉return 0;␊ |
814 | ␉if(!DP_ADD_TEMP_VAL(device, nvidia_device_type))␊ |
815 | ␉␉return 0;␊ |
816 | ␉// Rek : Dont use sprintf return, it does not WORK !! our custom sprintf() always return 0!␊ |
817 | ␉// len = sprintf(tmp, "Slot-%x", devices_number);␊ |
818 | ␉sprintf(tmp, "Slot-%x",devices_number);␊ |
819 | ␉devprop_add_value(device, "AAPL,slot-name", (uint8_t *) tmp, strlen(tmp));␊ |
820 | ␉devices_number++;␊ |
821 | ␊ |
822 | ␉return 1;␊ |
823 | }␊ |
824 | ␊ |
825 | int hex2bin(const char *hex, uint8_t *bin, int len)␊ |
826 | {␊ |
827 | ␉char␉*p;␊ |
828 | ␉int␉i;␊ |
829 | ␉char␉buf[3];␊ |
830 | ␊ |
831 | ␉if (hex == NULL || bin == NULL || len <= 0 || strlen(hex) != len * 2) {␊ |
832 | ␉␉printf("[ERROR] bin2hex input error\n");␊ |
833 | ␉␉return -1;␊ |
834 | ␉}␊ |
835 | ␊ |
836 | ␉buf[2] = '\0';␊ |
837 | ␉p = (char *) hex;␊ |
838 | ␉for (i=0; i<len; i++) {␊ |
839 | ␉␉if (p[0] == '\0' || p[1] == '\0' || !isxdigit(p[0]) || !isxdigit(p[1])) {␊ |
840 | ␉␉␉printf("[ERROR] bin2hex '%s' syntax error\n", hex);␊ |
841 | ␉␉␉return -2;␊ |
842 | ␉␉}␊ |
843 | ␉␉buf[0] = *p++;␊ |
844 | ␉␉buf[1] = *p++;␊ |
845 | ␉␉bin[i] = (unsigned char) strtoul(buf, NULL, 16);␊ |
846 | ␉}␊ |
847 | ␉return 0;␊ |
848 | }␊ |
849 | ␊ |
850 | unsigned long long mem_detect(volatile uint8_t *regs, uint8_t nvCardType, pci_dt_t *nvda_dev)␊ |
851 | {␊ |
852 | ␉unsigned long long vram_size = 0;␊ |
853 | ␊ |
854 | ␉if (nvCardType < NV_ARCH_50) {␊ |
855 | ␉␉vram_size = REG32(NV04_PFB_FIFO_DATA);␊ |
856 | ␉␉vram_size &= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK;␊ |
857 | ␉}␊ |
858 | ␉else if (nvCardType >= NV_ARCH_C0) {␊ |
859 | ␉␉vram_size = REG32(NVC0_MEM_CTRLR_COUNT) << 20;␊ |
860 | ␉␉vram_size *= REG32(NVC0_MEM_CTRLR_RAM_AMOUNT);␊ |
861 | ␉}␊ |
862 | ␉else␊ |
863 | ␉{␊ |
864 | ␉␉vram_size = REG32(NV04_PFB_FIFO_DATA);␊ |
865 | ␉␉vram_size |= (vram_size & 0xff) << 32;␊ |
866 | ␉␉vram_size &= 0xffffffff00ll;␊ |
867 | ␉}␊ |
868 | ␊ |
869 | ␉// workaround code for gt 430 & 9600M GT␊ |
870 | ␉switch (nvda_dev->device_id)␊ |
871 | ␉{␊ |
872 | ␉␉case 0x0DE1: vram_size = 1024*1024*1024; break; // gt 430␊ |
873 | ␉␉case 0x0649: vram_size = 512*1024*1024; break; // 9600M GT␊ |
874 | ␉␉default: break;␊ |
875 | ␉}␊ |
876 | ␊ |
877 | ␉return vram_size;␊ |
878 | }␊ |
879 | ␊ |
880 | bool setup_nvidia_devprop(pci_dt_t *nvda_dev)␊ |
881 | {␊ |
882 | ␉struct DevPropDevice␉␉*device;␊ |
883 | ␉char␉␉␉␉␉␉*devicepath;␊ |
884 | ␉struct pci_rom_pci_header_t␉*rom_pci_header;␉␊ |
885 | ␉volatile uint8_t␉*regs;␊ |
886 | ␉uint8_t␉␉␉␉*rom;␊ |
887 | ␉uint8_t␉␉␉␉*nvRom;␊ |
888 | ␉uint8_t␉␉␉␉nvCardType;␊ |
889 | ␉unsigned long long␉videoRam;␊ |
890 | ␉uint32_t␉␉␉nvBiosOveride;␊ |
891 | ␉uint32_t␉␉␉bar[7];␊ |
892 | ␉uint32_t␉␉␉boot_display;␊ |
893 | ␉int␉␉␉␉␉nvPatch;␊ |
894 | ␉int␉␉␉␉␉len;␊ |
895 | ␉char␉␉␉␉biosVersion[32];␊ |
896 | ␉char␉␉␉␉nvFilename[32];␊ |
897 | ␉char␉␉␉␉kNVCAP[12];␊ |
898 | ␉char␉␉␉␉*model;␊ |
899 | ␉const char␉␉␉*value;␊ |
900 | ␉bool␉␉␉␉doit;␊ |
901 | ␊ |
902 | ␉devicepath = get_pci_dev_path(nvda_dev);␊ |
903 | ␉bar[0] = pci_config_read32(nvda_dev->dev.addr, 0x10 );␊ |
904 | ␉regs = (uint8_t *) (bar[0] & ~0x0f);␊ |
905 | ␉//delay(50);␊ |
906 | ␉// get card type␊ |
907 | ␉nvCardType = (REG32(0) >> 20) & 0x1ff;␊ |
908 | ␊ |
909 | ␉// Amount of VRAM in kilobytes␊ |
910 | ␉videoRam = mem_detect(regs, nvCardType, nvda_dev);␊ |
911 | ␉model = get_nvidia_model((nvda_dev->vendor_id << 16) | nvda_dev->device_id);␊ |
912 | ␉␊ |
913 | ␉verbose("nVidia %s %dMB NV%02x [%04x:%04x] :: %s\n", ␊ |
914 | ␉␉␉model, (uint32_t)(videoRam / 1024 / 1024),␊ |
915 | ␉␉␉(REG32(0) >> 20) & 0x1ff, nvda_dev->vendor_id, nvda_dev->device_id,␊ |
916 | ␉␉␉devicepath);␊ |
917 | ␊ |
918 | ␉rom = malloc(NVIDIA_ROM_SIZE);␊ |
919 | ␉sprintf(nvFilename, "/Extra/%04x_%04x.rom", (uint16_t)nvda_dev->vendor_id, (uint16_t)nvda_dev->device_id);␊ |
920 | ␉if (getBoolForKey(kUseNvidiaROM, &doit, &bootInfo->bootConfig) && doit) {␊ |
921 | ␉␉verbose("Looking for nvidia video bios file %s\n", nvFilename);␊ |
922 | ␉␉nvBiosOveride = load_nvidia_bios_file(nvFilename, rom, NVIDIA_ROM_SIZE);␊ |
923 | ␉␉if (nvBiosOveride > 0) {␊ |
924 | ␉␉␉verbose("Using nVidia Video BIOS File %s (%d Bytes)\n", nvFilename, nvBiosOveride);␊ |
925 | ␉␉␉DBG("%s Signature 0x%02x%02x %d bytes\n", nvFilename, rom[0], rom[1], nvBiosOveride);␊ |
926 | ␉␉} else {␊ |
927 | ␉␉␉printf("ERROR: unable to open nVidia Video BIOS File %s\n", nvFilename);␊ |
928 | ␉␉␉return false;␊ |
929 | ␉␉}␊ |
930 | ␉} else {␊ |
931 | ␉␉// Otherwise read bios from card␊ |
932 | ␉␉nvBiosOveride = 0;␊ |
933 | ␊ |
934 | ␉␉// TODO: we should really check for the signature before copying the rom, i think.␊ |
935 | ␊ |
936 | ␉␉// PRAMIN first␊ |
937 | ␉␉nvRom = (uint8_t*)®s[NV_PRAMIN_OFFSET];␊ |
938 | ␉␉bcopy((uint32_t *)nvRom, rom, NVIDIA_ROM_SIZE);␊ |
939 | ␉␉␊ |
940 | ␉␉// Valid Signature ?␊ |
941 | ␉␉if (rom[0] != 0x55 && rom[1] != 0xaa) {␊ |
942 | ␉␉␉// PROM next␊ |
943 | ␉␉␉// Enable PROM access␊ |
944 | ␉␉␉(REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED;␊ |
945 | ␊ |
946 | ␉␉␉nvRom = (uint8_t*)®s[NV_PROM_OFFSET];␊ |
947 | ␉␉␉bcopy((uint8_t *)nvRom, rom, NVIDIA_ROM_SIZE);␊ |
948 | ␉␉␉␊ |
949 | ␉␉␉// disable PROM access␊ |
950 | ␉␉␉(REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED;␉␊ |
951 | ␊ |
952 | ␉␉␉// Valid Signature ?␊ |
953 | ␉␉␉if (rom[0] != 0x55 && rom[1] != 0xaa) {␊ |
954 | ␉␉␉␉// 0xC0000 last␊ |
955 | ␉␉␉␉bcopy((char *)0xc0000, rom, NVIDIA_ROM_SIZE);␊ |
956 | ␉␉␉␉␊ |
957 | ␉␉␉␉// Valid Signature ?␊ |
958 | ␉␉␉␉if (rom[0] != 0x55 && rom[1] != 0xaa) {␊ |
959 | ␉␉␉␉␉printf("ERROR: Unable to locate nVidia Video BIOS\n");␊ |
960 | ␉␉␉␉␉return false;␊ |
961 | ␉␉␉␉} else {␊ |
962 | ␉␉␉␉␉DBG("ROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);␊ |
963 | ␉␉␉␉}␊ |
964 | ␉␉␉} else {␊ |
965 | ␉␉␉␉DBG("PROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);␊ |
966 | ␉␉␉}␊ |
967 | ␉␉} else {␊ |
968 | ␉␉␉DBG("PRAM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);␊ |
969 | ␉␉}␊ |
970 | ␉}␊ |
971 | ␊ |
972 | ␉if ((nvPatch = patch_nvidia_rom(rom)) == PATCH_ROM_FAILED) {␊ |
973 | ␉␉printf("ERROR: nVidia ROM Patching Failed!\n");␊ |
974 | ␉␉return false;␊ |
975 | ␉}␊ |
976 | ␊ |
977 | ␉rom_pci_header = (struct pci_rom_pci_header_t*)(rom + *(uint16_t *)&rom[24]);␊ |
978 | ␊ |
979 | ␉// check for 'PCIR' sig␊ |
980 | ␉if (rom_pci_header->signature == 0x50434952) {␊ |
981 | ␉␉if (rom_pci_header->device != nvda_dev->device_id) {␊ |
982 | ␉␉␉// Get Model from the OpROM␊ |
983 | ␉␉␉model = get_nvidia_model((rom_pci_header->vendor << 16) | rom_pci_header->device);␊ |
984 | ␉␉} else {␊ |
985 | ␉␉␉printf("nVidia incorrect PCI ROM signature: 0x%x\n", rom_pci_header->signature);␊ |
986 | ␉␉}␊ |
987 | ␉}␊ |
988 | ␊ |
989 | ␉if (!string) {␊ |
990 | ␉␉string = devprop_create_string();␊ |
991 | ␉}␊ |
992 | ␉device = devprop_add_device(string, devicepath);␊ |
993 | ␊ |
994 | ␉/* FIXME: for primary graphics card only */␊ |
995 | ␉boot_display = 1;␊ |
996 | ␉devprop_add_value(device, "@0,AAPL,boot-display", (uint8_t*)&boot_display, 4);␊ |
997 | ␊ |
998 | ␉if(nvPatch == PATCH_ROM_SUCCESS_HAS_LVDS) {␊ |
999 | ␉␉uint8_t built_in = 0x01;␊ |
1000 | ␉␉devprop_add_value(device, "@0,built-in", &built_in, 1);␊ |
1001 | ␉}␊ |
1002 | ␉␊ |
1003 | ␉// get bios version␊ |
1004 | ␉const int MAX_BIOS_VERSION_LENGTH = 32;␊ |
1005 | ␉char* version_str = (char*)malloc(MAX_BIOS_VERSION_LENGTH);␊ |
1006 | ␉memset(version_str, 0, MAX_BIOS_VERSION_LENGTH);␊ |
1007 | ␉int i, version_start;␊ |
1008 | ␉int crlf_count = 0;␊ |
1009 | ␉// only search the first 384 bytes␊ |
1010 | ␉for(i = 0; i < 0x180; i++) {␊ |
1011 | ␉␉if(rom[i] == 0x0D && rom[i+1] == 0x0A) {␊ |
1012 | ␉␉␉crlf_count++;␊ |
1013 | ␉␉␉// second 0x0D0A was found, extract bios version␊ |
1014 | ␉␉␉if(crlf_count == 2) {␊ |
1015 | ␉␉␉␉if(rom[i-1] == 0x20) i--; // strip last " "␊ |
1016 | ␉␉␉␉for(version_start = i; version_start > (i-MAX_BIOS_VERSION_LENGTH); version_start--) {␊ |
1017 | ␉␉␉␉␉// find start␊ |
1018 | ␉␉␉␉␉if(rom[version_start] == 0x00) {␊ |
1019 | ␉␉␉␉␉␉version_start++;␊ |
1020 | ␉␉␉␉␉␉␊ |
1021 | ␉␉␉␉␉␉// strip "Version "␊ |
1022 | ␉␉␉␉␉␉if(strncmp((const char*)rom+version_start, "Version ", 8) == 0) {␊ |
1023 | ␉␉␉␉␉␉␉version_start += 8;␊ |
1024 | ␉␉␉␉␉␉}␊ |
1025 | ␉␉␉␉␉␉␊ |
1026 | ␉␉␉␉␉␉strncpy(version_str, (const char*)rom+version_start, i-version_start);␊ |
1027 | ␉␉␉␉␉␉break;␊ |
1028 | ␉␉␉␉␉}␊ |
1029 | ␉␉␉␉}␊ |
1030 | ␉␉␉␉break;␊ |
1031 | ␉␉␉}␊ |
1032 | ␉␉}␊ |
1033 | ␉}␊ |
1034 | ␉␊ |
1035 | ␉sprintf(biosVersion, "%s", (nvBiosOveride > 0) ? nvFilename : version_str);␊ |
1036 | ␊ |
1037 | ␉sprintf(kNVCAP, "NVCAP_%04x", nvda_dev->device_id);␊ |
1038 | ␉if (getValueForKey(kNVCAP, &value, &len, &bootInfo->bootConfig) && len == NVCAP_LEN * 2) {␊ |
1039 | ␉␉uint8_t␉new_NVCAP[NVCAP_LEN];␊ |
1040 | ␊ |
1041 | ␉␉if (hex2bin(value, new_NVCAP, NVCAP_LEN) == 0) {␊ |
1042 | ␉␉␉verbose("Using user supplied NVCAP for %s :: %s\n", model, devicepath);␊ |
1043 | ␉␉␉memcpy(default_NVCAP, new_NVCAP, NVCAP_LEN);␊ |
1044 | ␉␉}␊ |
1045 | ␉}␊ |
1046 | ␊ |
1047 | #if DEBUG_NVCAP␊ |
1048 | printf("NVCAP: %02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x\n",␊ |
1049 | ␉␉default_NVCAP[0], default_NVCAP[1], default_NVCAP[2], default_NVCAP[3],␊ |
1050 | ␉␉default_NVCAP[4], default_NVCAP[5], default_NVCAP[6], default_NVCAP[7],␊ |
1051 | ␉␉default_NVCAP[8], default_NVCAP[9], default_NVCAP[10], default_NVCAP[11],␊ |
1052 | ␉␉default_NVCAP[12], default_NVCAP[13], default_NVCAP[14], default_NVCAP[15],␊ |
1053 | ␉␉default_NVCAP[16], default_NVCAP[17], default_NVCAP[18], default_NVCAP[19]);␊ |
1054 | #endif␊ |
1055 | ␊ |
1056 | ␉if (getValueForKey(kdcfg0, &value, &len, &bootInfo->bootConfig) && len == DCFG0_LEN * 2)␊ |
1057 | ␉{␊ |
1058 | ␉␉uint8_t␉new_dcfg0[DCFG0_LEN];␊ |
1059 | ␉␉␊ |
1060 | ␉␉if (hex2bin(value, new_dcfg0, DCFG0_LEN) == 0)␊ |
1061 | ␉␉{␊ |
1062 | ␉␉␉verbose("Using user supplied @0,display-cfg\n");␊ |
1063 | ␉␉␉memcpy(default_dcfg_0, new_dcfg0, DCFG0_LEN);␊ |
1064 | ␉␉}␊ |
1065 | ␉}␊ |
1066 | ␊ |
1067 | //#if DEBUG_dcfg0␊ |
1068 | printf("@0,display-cfg: %02x%02x%02x%02x\n",␊ |
1069 | ␉␉default_dcfg_0[0], default_dcfg_0[1], default_dcfg_0[2], default_dcfg_0[3], default_dcfg_0[4]);␊ |
1070 | //#endif␊ |
1071 | ␊ |
1072 | ␉if (getValueForKey(kdcfg1, &value, &len, &bootInfo->bootConfig) && len == DCFG1_LEN * 2)␊ |
1073 | ␉{␊ |
1074 | ␉␉uint8_t␉new_dcfg1[DCFG1_LEN];␊ |
1075 | ␉␉␊ |
1076 | ␉␉if (hex2bin(value, new_dcfg1, DCFG1_LEN) == 0)␊ |
1077 | ␉␉{␊ |
1078 | ␉␉␉verbose("Using user supplied @1,display-cfg\n");␊ |
1079 | ␉␉␉memcpy(default_dcfg_1, new_dcfg1, DCFG1_LEN);␊ |
1080 | ␉␉}␊ |
1081 | ␉}␊ |
1082 | ␊ |
1083 | //#if DEBUG_dcfg1␊ |
1084 | printf("@1,display-cfg: %02x%02x%02x%02x\n",␊ |
1085 | ␉␉default_dcfg_1[0], default_dcfg_1[1], default_dcfg_1[2], default_dcfg_1[3], default_dcfg_1[4]);␊ |
1086 | //#endif␊ |
1087 | ␉␊ |
1088 | ␉devprop_add_nvidia_template(device);␊ |
1089 | ␉devprop_add_value(device, "NVCAP", default_NVCAP, NVCAP_LEN);␊ |
1090 | ␉devprop_add_value(device, "VRAM,totalsize", (uint8_t*)&videoRam, 4);␊ |
1091 | ␉devprop_add_value(device, "model", (uint8_t*)model, strlen(model) + 1);␊ |
1092 | ␉devprop_add_value(device, "rom-revision", (uint8_t*)biosVersion, strlen(biosVersion) + 1);␊ |
1093 | ␉devprop_add_value(device, "@0,display-cfg", default_dcfg_0, DCFG0_LEN);␊ |
1094 | ␉devprop_add_value(device, "@1,display-cfg", default_dcfg_1, DCFG1_LEN);␊ |
1095 | ␉devprop_add_value(device, "NVPM", default_NVPM, 28);␊ |
1096 | ␉if (getBoolForKey(kVBIOS, &doit, &bootInfo->bootConfig) && doit)␊ |
1097 | ␉␉devprop_add_value(device, "vbios", rom, (nvBiosOveride > 0) ? nvBiosOveride : (rom[2] * 512));␊ |
1098 | ␊ |
1099 | ␉stringdata = malloc(sizeof(uint8_t) * string->length);␊ |
1100 | ␉memcpy(stringdata, (uint8_t*)devprop_generate_string(string), string->length);␊ |
1101 | ␉stringlength = string->length;␊ |
1102 | ␊ |
1103 | ␉return true;␊ |
1104 | }␊ |
1105 | |