1 | /*␊ |
2 | * Add (c) here␊ |
3 | *␊ |
4 | * Copyright .... All rights reserved.␊ |
5 | *␊ |
6 | */␊ |
7 | ␊ |
8 | #include "smbios_getters.h"␊ |
9 | ␊ |
10 | #ifndef DEBUG_SMBIOS␊ |
11 | #define DEBUG_SMBIOS 0␊ |
12 | #endif␊ |
13 | ␊ |
14 | #if DEBUG_SMBIOS␊ |
15 | #define DBG(x...)␉printf(x)␊ |
16 | #else␊ |
17 | #define DBG(x...)␊ |
18 | #endif␊ |
19 | ␊ |
20 | ␊ |
21 | bool getProcessorInformationExternalClock(returnType *value)␊ |
22 | {␊ |
23 | ␉value->word = Platform.CPU.FSBFrequency/1000000;␊ |
24 | ␉return true;␊ |
25 | }␊ |
26 | ␊ |
27 | bool getProcessorInformationMaximumClock(returnType *value)␊ |
28 | {␊ |
29 | ␉value->word = Platform.CPU.CPUFrequency/1000000;␊ |
30 | ␉return true;␊ |
31 | }␊ |
32 | ␊ |
33 | bool getSMBOemProcessorBusSpeed(returnType *value)␊ |
34 | {␊ |
35 | ␉if (Platform.CPU.Vendor == 0x756E6547) // Intel␊ |
36 | ␉{␉␉␊ |
37 | ␉␉switch (Platform.CPU.Family) ␊ |
38 | ␉␉{␊ |
39 | ␉␉␉case 0x06:␊ |
40 | ␉␉␉{␊ |
41 | ␉␉␉␉switch (Platform.CPU.Model)␊ |
42 | ␉␉␉␉{␊ |
43 | ␉␉␉␉␉case CPU_MODEL_YONAH:␉␉␉// Intel Mobile Core Solo, Duo␊ |
44 | ␉␉␉␉␉case CPU_MODEL_MEROM:␉␉␉// Intel Mobile Core 2 Solo, Duo␊ |
45 | ␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉␉// Intel Core 2 Solo, Duo, Quad, Extreme␊ |
46 | ␉␉␉␉␉case CPU_MODEL_ATOM:␉␉␉// Intel Atom (45nm)␊ |
47 | ␉␉␉␉␉␉return false;␊ |
48 | ␊ |
49 | ␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉␉// Intel Core i5, i7 LGA1156 (45nm)␊ |
50 | ␉␉␉␉␉case CPU_MODEL_DALES:␊ |
51 | ␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉␉// Intel Core i3, i5 LGA1156 (32nm)␊ |
52 | ␉␉␉␉␉␉value->word = 4800;␉␉␉␉// Temp fix to return a sane value like Apple does␊ |
53 | ␉␉␉␉␉␉return true;␉␉␉␉␉// Since there is no QPI on this CPU family, only DMI␊ |
54 | ␉␉␉␉␉case CPU_MODEL_SANDY:␉␉␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊ |
55 | case CPU_MODEL_SANDY_XEON:␊ |
56 | ␉␉␉␉␉␉value->word = 5000;␉␉␉␉// Temp fix to return a sane value ␊ |
57 | ␉␉␉␉␉␉return true;␉␉␉␉␉// Since there is no QPI on this CPU family, only DMI␊ |
58 | ␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉␉// Intel Core i7 LGA1366 (45nm)␊ |
59 | ␉␉␉␉␉case CPU_MODEL_WESTMERE:␉␉// Intel Core i7 LGA1366 (32nm) 6 Core␊ |
60 | ␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␉␉// Intel Xeon X7500␊ |
61 | ␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉␉// Intel Xeon E7␊ |
62 | ␉␉␉␉␉{␊ |
63 | ␉␉␉␉␉␉// thanks to dgobe for i3/i5/i7 bus speed detection␊ |
64 | ␉␉␉␉␉␉int nhm_bus = 0x3F;␊ |
65 | ␉␉␉␉␉␉static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};␊ |
66 | ␉␉␉␉␉␉unsigned long did, vid;␊ |
67 | ␉␉␉␉␉␉int i;␊ |
68 | ␉␉␉␉␉␉␊ |
69 | ␉␉␉␉␉␉// Nehalem supports Scrubbing␊ |
70 | ␉␉␉␉␉␉// First, locate the PCI bus where the MCH is located␊ |
71 | ␉␉␉␉␉␉for(i = 0; i < sizeof(possible_nhm_bus); i++)␊ |
72 | ␉␉␉␉␉␉{␊ |
73 | ␉␉␉␉␉␉␉vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x00);␊ |
74 | ␉␉␉␉␉␉␉did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x02);␊ |
75 | ␉␉␉␉␉␉␉vid &= 0xFFFF;␊ |
76 | ␉␉␉␉␉␉␉did &= 0xFF00;␊ |
77 | ␉␉␉␉␉␉␉␊ |
78 | ␉␉␉␉␉␉␉if(vid == 0x8086 && did >= 0x2C00)␊ |
79 | ␉␉␉␉␉␉␉␉nhm_bus = possible_nhm_bus[i]; ␊ |
80 | ␉␉␉␉␉␉}␊ |
81 | ␉␉␉␉␉␉␊ |
82 | ␉␉␉␉␉␉unsigned long qpimult, qpibusspeed;␊ |
83 | ␉␉␉␉␉␉qpimult = pci_config_read32(PCIADDR(nhm_bus, 2, 1), 0x50);␊ |
84 | ␉␉␉␉␉␉qpimult &= 0x7F;␊ |
85 | ␉␉␉␉␉␉DBG("qpimult %d\n", qpimult);␊ |
86 | ␉␉␉␉␉␉qpibusspeed = (qpimult * 2 * (Platform.CPU.FSBFrequency/1000000));␊ |
87 | ␉␉␉␉␉␉// Rek: rounding decimals to match original mac profile info␊ |
88 | ␉␉␉␉␉␉if (qpibusspeed%100 != 0)qpibusspeed = ((qpibusspeed+50)/100)*100;␊ |
89 | ␉␉␉␉␉␉DBG("qpibusspeed %d\n", qpibusspeed);␊ |
90 | ␉␉␉␉␉␉value->word = qpibusspeed;␊ |
91 | ␉␉␉␉␉␉return true;␊ |
92 | ␉␉␉␉␉}␊ |
93 | ␉␉␉␉}␊ |
94 | ␉␉␉}␊ |
95 | ␉␉}␊ |
96 | ␉}␊ |
97 | ␉return false;␊ |
98 | }␊ |
99 | ␊ |
100 | uint16_t simpleGetSMBOemProcessorType(void)␊ |
101 | {␊ |
102 | ␉if (Platform.CPU.NoCores >= 4) ␊ |
103 | ␉{␊ |
104 | ␉␉return 0x0501;␉// Quad-Core Xeon␊ |
105 | ␉}␊ |
106 | ␉else if (Platform.CPU.NoCores == 1) ␊ |
107 | ␉{␊ |
108 | ␉␉return 0x0201;␉// Core Solo␊ |
109 | ␉};␊ |
110 | ␉␊ |
111 | ␉return 0x0301;␉␉// Core 2 Duo␊ |
112 | }␊ |
113 | ␊ |
114 | bool getSMBOemProcessorType(returnType *value)␊ |
115 | {␊ |
116 | ␉static bool done = false;␉␉␊ |
117 | ␉␉␊ |
118 | ␉value->word = simpleGetSMBOemProcessorType();␊ |
119 | ␊ |
120 | ␉if (Platform.CPU.Vendor == 0x756E6547) // Intel␊ |
121 | ␉{␊ |
122 | ␉␉if (!done)␊ |
123 | ␉␉{␊ |
124 | ␉␉␉verbose("CPU is %s, family 0x%x, model 0x%x\n", Platform.CPU.BrandString, Platform.CPU.Family, Platform.CPU.Model);␊ |
125 | ␉␉␉done = true;␊ |
126 | ␉␉}␊ |
127 | ␉␉␊ |
128 | ␉␉switch (Platform.CPU.Family) ␊ |
129 | ␉␉{␊ |
130 | ␉␉␉case 0x06:␊ |
131 | ␉␉␉{␊ |
132 | ␉␉␉␉switch (Platform.CPU.Model)␊ |
133 | ␉␉␉␉{␊ |
134 | ␉␉␉␉␉case CPU_MODEL_YONAH:␉␉␉␉// Intel Mobile Core Solo, Duo␊ |
135 | ␉␉␉␉␉case CPU_MODEL_MEROM:␉␉␉␉// Intel Mobile Core 2 Solo, Duo␊ |
136 | ␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉␉␉// Intel Core 2 Solo, Duo, Quad, Extreme␊ |
137 | ␉␉␉␉␉case CPU_MODEL_ATOM:␉␉␉␉// Intel Atom (45nm)␊ |
138 | ␉␉␉␉␉␉return true;␊ |
139 | ␊ |
140 | ␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉␉␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊ |
141 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)"))␊ |
142 | ␉␉␉␉␉␉␉value->word = 0x0501;␉␉// Xeon ␊ |
143 | ␉␉␉␉␉␉else␊ |
144 | ␉␉␉␉␉␉␉value->word = 0x0701;␉␉// Core i7␊ |
145 | ␉␉␉␉␉␉return true;␊ |
146 | ␊ |
147 | ␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉␉␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊ |
148 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)"))␊ |
149 | ␉␉␉␉␉␉␉value->word = 0x0501;␉␉// Xeon ␊ |
150 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊ |
151 | ␉␉␉␉␉␉␉value->word = 0x0601;␉␉// Core i5␊ |
152 | ␉␉␉␉␉␉else␊ |
153 | ␉␉␉␉␉␉␉value->word = 0x0701;␉␉// Core i7␊ |
154 | ␉␉␉␉␉␉return true;␊ |
155 | ␊ |
156 | ␉␉␉␉␉case CPU_MODEL_DALES:␉␉␉␉// Intel Core i5, i7 LGA1156 (45nm) (Havendale, Auburndale)␊ |
157 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊ |
158 | ␉␉␉␉␉␉␉value->word = 0x0601;␉␉// Core i5␊ |
159 | ␉␉␉␉␉␉else␊ |
160 | ␉␉␉␉␉␉␉value->word = 0x0701;␉␉// Core i7␊ |
161 | ␉␉␉␉␉␉return true;␊ |
162 | ␊ |
163 | ␉␉␉␉␉case CPU_MODEL_SANDY:␉␉␉␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊ |
164 | ␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉␉␉// Intel Core i3, i5, i7 LGA1156 (32nm) (Clarkdale, Arrandale)␊ |
165 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3"))␊ |
166 | ␉␉␉␉␉␉␉value->word = 0x0901;␉␉// Core i3␊ |
167 | ␉␉␉␉␉␉else␊ |
168 | ␉␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊ |
169 | ␉␉␉␉␉␉␉␉value->word = 0x0601;␉// Core i5␊ |
170 | ␉␉␉␉␉␉␉else␊ |
171 | ␉␉␉␉␉␉␉␉value->word = 0x0701;␉// Core i7␊ |
172 | ␉␉␉␉␉␉return true;␊ |
173 | ␊ |
174 | ␉␉␉␉␉case CPU_MODEL_SANDY_XEON:␉␉␉// Intel Xeon E3␊ |
175 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)"))␊ |
176 | ␉␉␉␉␉␉␉value->word = 0x0501;␉␉// Xeon ␉␉␉␉␉␊ |
177 | ␉␉␉␉␉␉return true;␊ |
178 | ␉␉␉␉␉␉␊ |
179 | ␉␉␉␉␉case CPU_MODEL_WESTMERE:␉␉␉// Intel Core i7 LGA1366 (32nm) 6 Core␊ |
180 | ␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉␉␉// Intel Xeon E7␊ |
181 | ␉␉␉␉␉␉value->word = 0x0501;␉␉␉// Xeon␊ |
182 | ␉␉␉␉␉␉return true;␊ |
183 | ␉␉␉␉}␊ |
184 | ␉␉␉}␊ |
185 | ␉␉}␊ |
186 | ␉}␊ |
187 | ␉␊ |
188 | ␉return false;␊ |
189 | }␊ |
190 | ␊ |
191 | bool getSMBMemoryDeviceMemoryType(returnType *value)␊ |
192 | {␊ |
193 | ␉static int idx = -1;␊ |
194 | ␉int␉map;␊ |
195 | ␊ |
196 | ␉idx++;␊ |
197 | ␉if (idx < MAX_RAM_SLOTS)␊ |
198 | ␉{␊ |
199 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
200 | ␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Type != 0)␊ |
201 | ␉␉{␊ |
202 | ␉␉␉DBG("RAM Detected Type = %d\n", Platform.RAM.DIMM[map].Type);␊ |
203 | ␉␉␉value->byte = Platform.RAM.DIMM[map].Type;␊ |
204 | ␉␉␉return true;␊ |
205 | ␉␉}␊ |
206 | ␉}␊ |
207 | ␉␊ |
208 | ␉return false;␊ |
209 | //␉value->byte = SMB_MEM_TYPE_DDR2;␊ |
210 | //␉return true;␊ |
211 | }␊ |
212 | ␊ |
213 | bool getSMBMemoryDeviceMemorySpeed(returnType *value)␊ |
214 | {␊ |
215 | ␉static int idx = -1;␊ |
216 | ␉int␉map;␊ |
217 | ␊ |
218 | ␉idx++;␊ |
219 | ␉if (idx < MAX_RAM_SLOTS)␊ |
220 | ␉{␊ |
221 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
222 | ␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Frequency != 0)␊ |
223 | ␉␉{␊ |
224 | ␉␉␉DBG("RAM Detected Freq = %d Mhz\n", Platform.RAM.DIMM[map].Frequency);␊ |
225 | ␉␉␉value->dword = Platform.RAM.DIMM[map].Frequency;␊ |
226 | ␉␉␉return true;␊ |
227 | ␉␉}␊ |
228 | ␉}␊ |
229 | ␊ |
230 | ␉return false;␊ |
231 | //␉value->dword = 800;␊ |
232 | //␉return true;␊ |
233 | }␊ |
234 | ␊ |
235 | bool getSMBMemoryDeviceManufacturer(returnType *value)␊ |
236 | {␊ |
237 | ␉static int idx = -1;␊ |
238 | ␉int␉map;␊ |
239 | ␊ |
240 | ␉idx++;␊ |
241 | ␉if (idx < MAX_RAM_SLOTS)␊ |
242 | ␉{␊ |
243 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
244 | ␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].Vendor) > 0)␊ |
245 | ␉␉{␊ |
246 | ␉␉␉DBG("RAM Detected Vendor[%d]='%s'\n", idx, Platform.RAM.DIMM[map].Vendor);␊ |
247 | ␉␉␉value->string = Platform.RAM.DIMM[map].Vendor;␊ |
248 | ␉␉␉return true;␊ |
249 | ␉␉}␊ |
250 | ␉}␊ |
251 | ␊ |
252 | ␉return false;␊ |
253 | //␉value->string = NOT_AVAILABLE;␊ |
254 | //␉return true;␊ |
255 | }␊ |
256 | ␉␊ |
257 | bool getSMBMemoryDeviceSerialNumber(returnType *value)␊ |
258 | {␊ |
259 | ␉static int idx = -1;␊ |
260 | ␉int␉map;␊ |
261 | ␊ |
262 | ␉idx++;␊ |
263 | ␉if (idx < MAX_RAM_SLOTS)␊ |
264 | ␉{␊ |
265 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
266 | ␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].SerialNo) > 0)␊ |
267 | ␉␉{␊ |
268 | ␉␉␉DBG("map=%d, RAM Detected SerialNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].SerialNo);␊ |
269 | ␉␉␉value->string = Platform.RAM.DIMM[map].SerialNo;␊ |
270 | ␉␉␉return true;␊ |
271 | ␉␉}␊ |
272 | ␉}␊ |
273 | ␊ |
274 | ␉return false;␊ |
275 | //␉value->string = NOT_AVAILABLE;␊ |
276 | //␉return true;␊ |
277 | }␊ |
278 | ␊ |
279 | bool getSMBMemoryDevicePartNumber(returnType *value)␊ |
280 | {␊ |
281 | ␉static int idx = -1;␊ |
282 | ␉int␉map;␊ |
283 | ␊ |
284 | ␉idx++;␊ |
285 | ␉if (idx < MAX_RAM_SLOTS)␊ |
286 | ␉{␊ |
287 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
288 | ␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].PartNo) > 0)␊ |
289 | ␉␉{␊ |
290 | ␉␉␉DBG("map=%d, RAM Detected PartNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].PartNo);␊ |
291 | ␉␉␉value->string = Platform.RAM.DIMM[map].PartNo;␊ |
292 | ␉␉␉return true;␊ |
293 | ␉␉}␊ |
294 | ␉}␊ |
295 | ␊ |
296 | ␉return false;␊ |
297 | //␉value->string = NOT_AVAILABLE;␊ |
298 | //␉return true;␊ |
299 | }␊ |
300 | ␊ |
301 | ␊ |
302 | // getting smbios addr with fast compare ops, late checksum testing ...␊ |
303 | #define COMPARE_DWORD(a,b) ( *((uint32_t *) a) == *((uint32_t *) b) )␊ |
304 | static const char * const SMTAG = "_SM_";␊ |
305 | static const char* const DMITAG = "_DMI_";␊ |
306 | ␊ |
307 | SMBEntryPoint *getAddressOfSmbiosTable(void)␊ |
308 | {␊ |
309 | ␉SMBEntryPoint␉*smbios;␊ |
310 | ␉/* ␊ |
311 | ␉ * The logic is to start at 0xf0000 and end at 0xfffff iterating 16 bytes at a time looking␊ |
312 | ␉ * for the SMBIOS entry-point structure anchor (literal ASCII "_SM_").␊ |
313 | ␉ */␊ |
314 | ␉smbios = (SMBEntryPoint*)SMBIOS_RANGE_START;␊ |
315 | ␉while (smbios <= (SMBEntryPoint *)SMBIOS_RANGE_END) {␊ |
316 | ␉␉if (COMPARE_DWORD(smbios->anchor, SMTAG) && ␊ |
317 | ␉␉␉COMPARE_DWORD(smbios->dmi.anchor, DMITAG) &&␊ |
318 | ␉␉␉smbios->dmi.anchor[4] == DMITAG[4] &&␊ |
319 | ␉␉␉checksum8(smbios, sizeof(SMBEntryPoint)) == 0)␊ |
320 | ␉ {␊ |
321 | ␉␉␉return smbios;␊ |
322 | ␉ }␊ |
323 | ␉␉smbios = (SMBEntryPoint*)(((char*)smbios) + 16);␊ |
324 | ␉}␊ |
325 | ␉printf("ERROR: Unable to find SMBIOS!\n");␊ |
326 | ␉pause();␊ |
327 | ␉return NULL;␊ |
328 | }␊ |
329 | ␊ |
330 | |