1 | /*␊ |
2 | * <Insert copyright here : it must be BSD-like so everyone can use it>␊ |
3 | *␊ |
4 | * Author: Erich Boleyn <erich@uruk.org> http://www.uruk.org/~erich/␊ |
5 | *␊ |
6 | * Header file for Intel Architecture local and I/O APIC definitions.␊ |
7 | *␊ |
8 | * This file was created from information in the Intel Pentium Pro␊ |
9 | * Family Developer's Manual, Volume 3: Operating System Writer's␊ |
10 | * Manual, order number 242692-001, which can be ordered from the␊ |
11 | * Intel literature center.␊ |
12 | */␊ |
13 | ␊ |
14 | #ifndef _APIC_H␊ |
15 | #define _APIC_H␊ |
16 | ␊ |
17 | /*␊ |
18 | * APIC Defines.␊ |
19 | */␊ |
20 | ␊ |
21 | /*␊ |
22 | * Recommendation: Don't use this except for MSI interrupt delivery.␊ |
23 | * In general, the "Destination Mode" can be used to control this, since␊ |
24 | * it is DIFFERENT (0xF) for Pentium and P6, but not on the same APIC␊ |
25 | * version for AMD Opteron.␊ |
26 | */␊ |
27 | #define APIC_BCAST_ID␉␉␉ ␉0xFF␊ |
28 | ␊ |
29 | /*␊ |
30 | * APIC register definitions␊ |
31 | */␊ |
32 | ␊ |
33 | /*␊ |
34 | * Shared defines for I/O and local APIC definitions␊ |
35 | */␊ |
36 | /* APIC version register */␊ |
37 | #define␉APIC_VERSION(x)␉␉␉␉((x) & 0xFF)␊ |
38 | #define␉APIC_MAXREDIR(x)␉␉␉(((x) >> 16) & 0xFF)␊ |
39 | /* APIC id register */␊ |
40 | #define␉APIC_ID(x)␉␉␉␉((x) >> 24)␊ |
41 | #define APIC_VER_NEW␉␉␉␉0x10␊ |
42 | ␊ |
43 | #define IOAPIC_REGSEL␉␉␉␉0␊ |
44 | #define IOAPIC_RW␉␉␉␉0x10␊ |
45 | #define␉␉IOAPIC_ID␉␉␉0␊ |
46 | #define␉␉IOAPIC_VER␉␉␉1␊ |
47 | #define␉␉IOAPIC_REDIR␉␉␉0x10␊ |
48 | ␊ |
49 | #define LAPIC_ID␉␉␉␉0x20␊ |
50 | #define LAPIC_VER␉␉␉␉0x30␊ |
51 | #define LAPIC_TPR␉␉␉␉0x80␊ |
52 | #define LAPIC_APR␉␉␉␉0x90␊ |
53 | #define LAPIC_PPR␉␉␉␉0xA0␊ |
54 | #define LAPIC_EOI␉␉␉␉0xB0␊ |
55 | #define LAPIC_LDR␉␉␉␉0xD0␊ |
56 | #define LAPIC_DFR␉␉␉␉0xE0␊ |
57 | #define LAPIC_SPIV␉␉␉␉0xF0␊ |
58 | #define␉␉LAPIC_SPIV_ENABLE_APIC␉␉0x100␊ |
59 | #define LAPIC_ISR␉␉␉␉0x100␊ |
60 | #define LAPIC_TMR␉␉␉␉0x180␊ |
61 | #define LAPIC_IRR␉␉␉␉0x200␊ |
62 | #define LAPIC_ESR␉␉␉␉0x280␊ |
63 | #define LAPIC_ICR␉␉␉␉0x300␊ |
64 | #define␉␉LAPIC_ICR_DS_SELF␉␉0x40000␊ |
65 | #define␉␉LAPIC_ICR_DS_ALLINC␉␉0x80000␊ |
66 | #define␉␉LAPIC_ICR_DS_ALLEX␉␉0xC0000␊ |
67 | #define␉␉LAPIC_ICR_TM_LEVEL␉␉0x8000␊ |
68 | #define␉␉LAPIC_ICR_LEVELASSERT␉␉0x4000␊ |
69 | #define␉␉LAPIC_ICR_STATUS_PEND␉␉0x1000␊ |
70 | #define␉␉LAPIC_ICR_DM_LOGICAL␉␉0x800␊ |
71 | #define␉␉LAPIC_ICR_DM_LOWPRI␉␉0x100␊ |
72 | #define␉␉LAPIC_ICR_DM_SMI␉␉0x200␊ |
73 | #define␉␉LAPIC_ICR_DM_NMI␉␉0x400␊ |
74 | #define␉␉LAPIC_ICR_DM_INIT␉␉0x500␊ |
75 | #define␉␉LAPIC_ICR_DM_SIPI␉␉0x600␊ |
76 | #define LAPIC_LVTT␉␉␉␉0x320␊ |
77 | #define LAPIC_LVTPC␉␉ ␉␉0x340␊ |
78 | #define LAPIC_LVT0␉␉␉␉0x350␊ |
79 | #define LAPIC_LVT1␉␉␉␉0x360␊ |
80 | #define LAPIC_LVTE␉␉␉␉0x370␊ |
81 | #define LAPIC_TICR␉␉␉␉0x380␊ |
82 | #define LAPIC_TCCR␉␉␉␉0x390␊ |
83 | #define LAPIC_TDCR␉␉␉␉0x3E0␊ |
84 | ␊ |
85 | #endif /* _APIC_H */␊ |
86 | |