1 | /*␊ |
2 | * usb.c␊ |
3 | * ␊ |
4 | *␊ |
5 | * Created by mackerintel on 12/20/08.␊ |
6 | * Copyright 2008 mackerintel. All rights reserved.␊ |
7 | *␊ |
8 | */␊ |
9 | ␊ |
10 | #include "libsaio.h"␊ |
11 | #include "boot.h"␊ |
12 | #include "bootstruct.h"␊ |
13 | #include "pci.h"␊ |
14 | ␊ |
15 | #ifndef DEBUG_USB␊ |
16 | #define DEBUG_USB 0␊ |
17 | #endif␊ |
18 | ␊ |
19 | #if DEBUG_USB␊ |
20 | #define DBG(x...)␉printf(x)␊ |
21 | #else␊ |
22 | #define DBG(x...)␊ |
23 | #endif␊ |
24 | ␊ |
25 | #define kUSBBusFix␉␉␉"USBBusFix"␉␉␉␊ |
26 | #define kEHCIacquire␉␉"EHCIacquire"␉␉␊ |
27 | #define kUHCIreset␉␉␉"UHCIreset"␉␉␉␊ |
28 | #define kLegacyOff␉␉␉"USBLegacyOff"␉␉␊ |
29 | #define kEHCIhard␉␉␉"EHCIhard"␉␉␉␊ |
30 | ␊ |
31 | int usb_loop();␊ |
32 | ␊ |
33 | struct pciList␊ |
34 | {␊ |
35 | ␉pci_dt_t* pciDev;␊ |
36 | ␉struct pciList* next;␊ |
37 | };␊ |
38 | ␊ |
39 | struct pciList* usbList = NULL;␊ |
40 | ␊ |
41 | int legacy_off (pci_dt_t *pci_dev);␊ |
42 | int ehci_acquire (pci_dt_t *pci_dev);␊ |
43 | int uhci_reset (pci_dt_t *pci_dev);␊ |
44 | ␊ |
45 | // Add usb device to the list␊ |
46 | void notify_usb_dev(pci_dt_t *pci_dev)␊ |
47 | {␊ |
48 | ␉struct pciList* current = usbList;␊ |
49 | ␉if(!usbList)␊ |
50 | ␉{␊ |
51 | ␉␉usbList = (struct pciList*)malloc(sizeof(struct pciList));␊ |
52 | ␉␉usbList->next = NULL;␊ |
53 | ␉␉usbList->pciDev = pci_dev;␊ |
54 | ␉␉␊ |
55 | ␉}␊ |
56 | ␉else␊ |
57 | ␉{␊ |
58 | ␉␉while(current != NULL && current->next != NULL)␊ |
59 | ␉␉{␊ |
60 | ␉␉␉current = current->next;␊ |
61 | ␉␉}␊ |
62 | ␉␉current->next = (struct pciList*)malloc(sizeof(struct pciList));␊ |
63 | ␉␉current = current->next;␊ |
64 | ␉␉␊ |
65 | ␉␉current->pciDev = pci_dev;␊ |
66 | ␉␉current->next = NULL;␊ |
67 | ␉}␊ |
68 | }␊ |
69 | ␊ |
70 | // Loop through the list and call the apropriate patch function␊ |
71 | int usb_loop()␊ |
72 | {␊ |
73 | ␉int retVal = 1;␊ |
74 | ␉bool fix_ehci = true, fix_uhci = true, fix_usb = true, fix_legacy = true;␊ |
75 | ␉␊ |
76 | ␉if (getBoolForKey(kUSBBusFix, &fix_usb, &bootInfo->bootConfig))␊ |
77 | ␉{␊ |
78 | ␉␉fix_ehci = fix_uhci = fix_legacy = fix_usb;␉// Disable all if none set␊ |
79 | ␉}␊ |
80 | ␉else ␊ |
81 | ␉{␊ |
82 | ␉␉getBoolForKey(kEHCIacquire, &fix_ehci, &bootInfo->bootConfig);␊ |
83 | ␉␉getBoolForKey(kUHCIreset, &fix_uhci, &bootInfo->bootConfig);␊ |
84 | ␉␉getBoolForKey(kLegacyOff, &fix_legacy, &bootInfo->bootConfig);␊ |
85 | ␉}␊ |
86 | ␉␊ |
87 | ␉msglog("\n");␊ |
88 | ␉struct pciList* current = usbList;␊ |
89 | ␉␊ |
90 | ␉while(current)␊ |
91 | ␉{␊ |
92 | ␉␉switch (pci_config_read8(current->pciDev->dev.addr, PCI_CLASS_PROG))␊ |
93 | ␉␉{␊ |
94 | ␉␉␉// EHCI␊ |
95 | ␉␉␉case 0x20:␊ |
96 | ␉␉ ␉if(fix_legacy) retVal &= legacy_off(current->pciDev);␊ |
97 | ␉␉ ␉if(fix_ehci) retVal &= ehci_acquire(current->pciDev);␊ |
98 | ␉␉␉␉␊ |
99 | ␉␉␉␉break;␊ |
100 | ␉␉␉␉␊ |
101 | ␉␉␉// UHCI␊ |
102 | ␉␉␉case 0x00:␊ |
103 | ␉␉␉␉if (fix_uhci) retVal &= uhci_reset(current->pciDev);␊ |
104 | ␊ |
105 | ␉␉␉␉break;␊ |
106 | ␉␉}␊ |
107 | ␉␉␊ |
108 | ␉␉current = current->next;␊ |
109 | ␉}␊ |
110 | ␉return retVal;␊ |
111 | }␊ |
112 | ␊ |
113 | int legacy_off (pci_dt_t *pci_dev)␊ |
114 | {␊ |
115 | ␉// Set usb legacy off modification by Signal64␊ |
116 | ␉// NOTE: This *must* be called after the last file is loaded from the drive in the event that we are booting form usb.␊ |
117 | ␉// NOTE2: This should be called after any getc() call. (aka, after the Wait=y keyworkd is used)␊ |
118 | ␉// AKA: Make this run immediatly before the kernel is called␊ |
119 | ␉//uint32_t␉capaddr, opaddr; ␉␉␊ |
120 | ␉//uint8_t␉␉eecp;␉␉␉␊ |
121 | ␉//uint32_t␉usbcmd, usbsts, usbintr;␉␉␉␊ |
122 | ␉//uint32_t␉usblegsup, usblegctlsts;␉␉␊ |
123 | ␉␊ |
124 | ␉//int isOSowned;␊ |
125 | ␉//int isBIOSowned;␊ |
126 | ␉␊ |
127 | ␉verbose("Setting Legacy USB Off on controller [%04x:%04x] at %02x:%2x.%x\n", ␊ |
128 | ␉␉␉pci_dev->vendor_id, pci_dev->device_id,␊ |
129 | ␉␉␉pci_dev->dev.bits.bus, pci_dev->dev.bits.dev, pci_dev->dev.bits.func);␊ |
130 | ␉␊ |
131 | ␉␊ |
132 | ␉// capaddr = Capability Registers = dev.addr + offset stored in dev.addr + 0x10 (USBBASE)␊ |
133 | ␉uint32_t capaddr = pci_config_read32(pci_dev->dev.addr, 0x10);␉␊ |
134 | ␉␊ |
135 | ␉// opaddr = Operational Registers = capaddr + offset (8bit CAPLENGTH in Capability Registers + offset 0)␊ |
136 | ␉uint32_t opaddr = capaddr + *((unsigned char*)(capaddr)); ␉␉␊ |
137 | ␉␊ |
138 | ␉// eecp = EHCI Extended Capabilities offset = capaddr HCCPARAMS bits 15:8␊ |
139 | ␉uint8_t eecp=*((unsigned char*)(capaddr + 9));␊ |
140 | ␉␊ |
141 | ␉DBG("capaddr=%x opaddr=%x eecp=%x\n", capaddr, opaddr, eecp);␊ |
142 | ␉␊ |
143 | ␉uint32_t usbcmd = *((unsigned int*)(opaddr));␉␉␉// Command Register␊ |
144 | ␉uint32_t usbsts = *((unsigned int*)(opaddr + 4));␉␉// Status Register␊ |
145 | ␉uint32_t usbintr = *((unsigned int*)(opaddr + 8));␉␉// Interrupt Enable Register␊ |
146 | ␉␊ |
147 | ␉DBG("usbcmd=%08x usbsts=%08x usbintr=%08x\n", usbcmd, usbsts, usbintr);␊ |
148 | ␉␊ |
149 | ␉// read PCI Config 32bit USBLEGSUP (eecp+0) ␊ |
150 | ␉uint32_t usblegsup = pci_config_read32(pci_dev->dev.addr, eecp);␊ |
151 | ␉␊ |
152 | ␉// informational only␊ |
153 | ␉int isBIOSowned = !!((usblegsup) & (1 << (16)));␊ |
154 | ␉int isOSowned = !!((usblegsup) & (1 << (24)));␊ |
155 | ␉␊ |
156 | ␉// read PCI Config 32bit USBLEGCTLSTS (eecp+4) ␊ |
157 | ␉uint32_t usblegctlsts = pci_config_read32(pci_dev->dev.addr, eecp + 4);␊ |
158 | ␉␊ |
159 | ␉DBG("usblegsup=%08x isOSowned=%d isBIOSowned=%d usblegctlsts=%08x\n", usblegsup, isOSowned, isBIOSowned, usblegctlsts);␊ |
160 | ␉␊ |
161 | ␉// Reset registers to Legacy OFF␊ |
162 | ␉DBG("Clearing USBLEGCTLSTS\n");␊ |
163 | ␉pci_config_write32(pci_dev->dev.addr, eecp + 4, 0);␉//usblegctlsts␊ |
164 | ␉␊ |
165 | ␉// if delay value is in milliseconds it doesn't appear to work. ␊ |
166 | ␉// setting value to anything up to 65535 does not add the expected delay here.␊ |
167 | ␉delay(100);␊ |
168 | ␉␊ |
169 | ␉usbcmd = *((unsigned int*)(opaddr));␊ |
170 | ␉usbsts = *((unsigned int*)(opaddr + 4));␊ |
171 | ␉usbintr = *((unsigned int*)(opaddr + 8));␊ |
172 | ␉␊ |
173 | ␉DBG("usbcmd=%08x usbsts=%08x usbintr=%08x\n", usbcmd, usbsts, usbintr);␊ |
174 | ␉␊ |
175 | ␉DBG("Clearing Registers\n");␊ |
176 | ␉␊ |
177 | ␉// clear registers to default␊ |
178 | ␉usbcmd = (usbcmd & 0xffffff00);␊ |
179 | ␉*((unsigned int*)(opaddr)) = usbcmd;␊ |
180 | ␉*((unsigned int*)(opaddr + 8)) = 0;␉␉␉␉␉//usbintr - clear interrupt registers␊ |
181 | ␉*((unsigned int*)(opaddr + 4)) = 0x1000;␉␉␉//usbsts - clear status registers ␉␊ |
182 | ␉pci_config_write32(pci_dev->dev.addr, eecp, 1);␉␉//usblegsup␊ |
183 | ␉␊ |
184 | ␉// get the results␊ |
185 | ␉usbcmd = *((unsigned int*)(opaddr));␊ |
186 | ␉usbsts = *((unsigned int*)(opaddr + 4));␊ |
187 | ␉usbintr = *((unsigned int*)(opaddr + 8));␊ |
188 | ␉␊ |
189 | ␉DBG("usbcmd=%08x usbsts=%08x usbintr=%08x\n", usbcmd, usbsts, usbintr);␊ |
190 | ␉␊ |
191 | ␉// read 32bit USBLEGSUP (eecp+0) ␊ |
192 | ␉usblegsup = pci_config_read32(pci_dev->dev.addr, eecp);␊ |
193 | ␉␊ |
194 | ␉// informational only␊ |
195 | ␉isBIOSowned = !!((usblegsup) & (1 << (16)));␊ |
196 | ␉isOSowned = !!((usblegsup) & (1 << (24)));␊ |
197 | ␉␊ |
198 | ␉// read 32bit USBLEGCTLSTS (eecp+4) ␊ |
199 | ␉usblegctlsts = pci_config_read32(pci_dev->dev.addr, eecp + 4);␊ |
200 | ␉␊ |
201 | ␉DBG("usblegsup=%08x isOSowned=%d isBIOSowned=%d usblegctlsts=%08x\n", usblegsup, isOSowned, isBIOSowned, usblegctlsts);␊ |
202 | ␉␊ |
203 | ␉verbose("Legacy USB Off Done\n");␉␊ |
204 | ␉return 1;␊ |
205 | }␊ |
206 | ␊ |
207 | int ehci_acquire (pci_dt_t *pci_dev)␊ |
208 | {␊ |
209 | ␉int␉␉j, k;␊ |
210 | ␉//uint32_t␉base;␊ |
211 | ␉//uint8_t␉␉eecp;␊ |
212 | ␉uint8_t␉␉legacy[8];␊ |
213 | ␉//bool␉␉isOwnershipConflict;␉␊ |
214 | ␉bool␉␉alwaysHardBIOSReset = false;␊ |
215 | ␉␉␊ |
216 | ␉if (!getBoolForKey(kEHCIhard, &alwaysHardBIOSReset, &bootInfo->bootConfig)) {␊ |
217 | ␉␉alwaysHardBIOSReset = true;␊ |
218 | ␉}␊ |
219 | ␊ |
220 | ␉pci_config_write16(pci_dev->dev.addr, 0x04, 0x0002);␊ |
221 | ␉uint32_t base = pci_config_read32(pci_dev->dev.addr, 0x10);␊ |
222 | ␊ |
223 | ␉verbose("EHCI controller [%04x:%04x] at %02x:%2x.%x DMA @%x\n", ␊ |
224 | ␉␉pci_dev->vendor_id, pci_dev->device_id,␊ |
225 | ␉␉pci_dev->dev.bits.bus, pci_dev->dev.bits.dev, pci_dev->dev.bits.func, ␊ |
226 | ␉␉base);␊ |
227 | ␊ |
228 | ␉if (*((unsigned char*)base) < 0xc)␊ |
229 | ␉{␊ |
230 | ␉␉DBG("Config space too small: no legacy implementation\n");␊ |
231 | ␉␉return 1;␊ |
232 | ␉}␊ |
233 | ␉uint8_t eecp = *((unsigned char*)(base + 9));␊ |
234 | ␉if (!eecp) {␊ |
235 | ␉␉DBG("No extended capabilities: no legacy implementation\n");␊ |
236 | ␉␉return 1;␊ |
237 | ␉}␊ |
238 | ␊ |
239 | ␉DBG("eecp=%x\n",eecp);␊ |
240 | ␊ |
241 | ␉// bad way to do it␊ |
242 | ␉// pci_conf_write(pci_dev->dev.addr, eecp, 4, 0x01000001);␊ |
243 | ␉for (j = 0; j < 8; j++) {␊ |
244 | ␉␉legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j);␊ |
245 | ␉␉DBG("%02x ", legacy[j]);␊ |
246 | ␉}␊ |
247 | ␉DBG("\n");␊ |
248 | ␊ |
249 | ␉//Real Job: based on orByte's AppleUSBEHCI.cpp␊ |
250 | ␉//We try soft reset first - some systems hang on reboot with hard reset␊ |
251 | ␉// Definitely needed during reboot on 10.4.6␊ |
252 | ␊ |
253 | ␉bool isOwnershipConflict = ((legacy[3] & 1 != 0) && (legacy[2] & 1 != 0));␊ |
254 | ␉if (!alwaysHardBIOSReset && isOwnershipConflict) {␊ |
255 | ␉␉DBG("EHCI - Ownership conflict - attempting soft reset ...\n");␊ |
256 | ␉␉DBG("EHCI - toggle OS Ownership to 0\n");␊ |
257 | ␉␉pci_config_write8(pci_dev->dev.addr, eecp + 3, 0);␊ |
258 | ␉␉for (k = 0; k < 25; k++) {␊ |
259 | ␉␉␉for (j = 0; j < 8; j++) {␊ |
260 | ␉␉␉␉legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j);␊ |
261 | ␉␉␉}␊ |
262 | ␉␉␉if (legacy[3] == 0) {␊ |
263 | ␉␉␉␉break;␊ |
264 | ␉␉␉}␊ |
265 | ␉␉␉delay(10);␊ |
266 | ␉␉}␊ |
267 | ␉}␉␊ |
268 | ␊ |
269 | ␉DBG("Found USBLEGSUP_ID - value %x:%x - writing OSOwned\n", legacy[3],legacy[2]);␊ |
270 | ␉pci_config_write8(pci_dev->dev.addr, eecp + 3, 1);␊ |
271 | ␊ |
272 | ␉// wait for kEHCI_USBLEGSUP_BIOSOwned bit to clear␊ |
273 | ␉for (k = 0; k < 25; k++) {␊ |
274 | ␉␉for (j = 0;j < 8; j++) {␊ |
275 | ␉␉␉legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j);␊ |
276 | ␉␉}␊ |
277 | ␉␉DBG ("%x:%x,",legacy[3],legacy[2]);␊ |
278 | ␉␉if (legacy[2] == 0) {␊ |
279 | ␉␉␉break;␊ |
280 | ␉␉}␊ |
281 | ␉␉delay(10);␊ |
282 | ␉}␊ |
283 | ␊ |
284 | ␉for (j = 0;j < 8; j++) {␊ |
285 | ␉␉legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j);␊ |
286 | ␉}␊ |
287 | ␉isOwnershipConflict = ((legacy[2]) != 0);␊ |
288 | ␉if (isOwnershipConflict) {␊ |
289 | ␉␉// Soft reset has failed. Assume SMI being ignored␊ |
290 | ␉␉// Hard reset␊ |
291 | ␉␉// Force Clear BIOS BIT␊ |
292 | ␉␉DBG("EHCI - Ownership conflict - attempting hard reset ...\n");␉␉␉␊ |
293 | ␉␉DBG ("%x:%x\n",legacy[3],legacy[2]);␊ |
294 | ␉␉DBG("EHCI - Force BIOS Ownership to 0\n");␊ |
295 | ␊ |
296 | ␉␉pci_config_write8(pci_dev->dev.addr, eecp + 2, 0);␊ |
297 | ␉␉for (k = 0; k < 25; k++) {␊ |
298 | ␉␉␉for (j = 0; j < 8; j++) {␊ |
299 | ␉␉␉␉legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j);␊ |
300 | ␉␉␉}␊ |
301 | ␉␉␉DBG ("%x:%x,",legacy[3],legacy[2]);␊ |
302 | ␊ |
303 | ␉␉␉if ((legacy[2]) == 0) {␊ |
304 | ␉␉␉␉break;␊ |
305 | ␉␉␉}␊ |
306 | ␉␉␉delay(10);␉␊ |
307 | ␉␉}␉␉␊ |
308 | ␉␉// Disable further SMI events␊ |
309 | ␉␉for (j = 4; j < 8; j++) {␊ |
310 | ␉␉␉pci_config_write8(pci_dev->dev.addr, eecp + j, 0);␊ |
311 | ␉␉}␊ |
312 | ␉}␊ |
313 | ␊ |
314 | ␉for (j = 0; j < 8; j++) {␊ |
315 | ␉␉legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j);␊ |
316 | ␉}␊ |
317 | ␊ |
318 | ␉DBG ("%x:%x\n",legacy[3],legacy[2]);␊ |
319 | ␊ |
320 | ␉// Final Ownership Resolution Check...␊ |
321 | ␉if (legacy[2] & 1) {␉␉␉␉␉␊ |
322 | ␉␉DBG("EHCI controller unable to take control from BIOS\n");␊ |
323 | ␉␉return 0;␊ |
324 | ␉}␊ |
325 | ␊ |
326 | ␉DBG("EHCI Acquire OS Ownership done\n");␉␊ |
327 | ␉return 1;␊ |
328 | }␊ |
329 | ␊ |
330 | int uhci_reset (pci_dt_t *pci_dev)␊ |
331 | {␊ |
332 | ␉uint32_t base, port_base;␊ |
333 | ␉␊ |
334 | ␉base = pci_config_read32(pci_dev->dev.addr, 0x20);␊ |
335 | ␉port_base = (base >> 5) & 0x07ff;␊ |
336 | ␊ |
337 | ␉verbose("UHCI controller [%04x:%04x] at %02x:%2x.%x base %x(%x)\n", ␊ |
338 | ␉␉pci_dev->vendor_id, pci_dev->device_id,␊ |
339 | ␉␉pci_dev->dev.bits.bus, pci_dev->dev.bits.dev, pci_dev->dev.bits.func, ␊ |
340 | ␉␉port_base, base);␊ |
341 | ␉␊ |
342 | ␉pci_config_write16(pci_dev->dev.addr, 0xc0, 0x8f00);␊ |
343 | ␊ |
344 | ␉outw (port_base, 0x0002);␊ |
345 | ␉delay(10);␊ |
346 | ␉outw (port_base+4,0);␊ |
347 | ␉delay(10);␊ |
348 | ␉outw (port_base,0);␊ |
349 | ␉return 1;␊ |
350 | }␊ |
351 | |