| 1 | /*␊ |
| 2 | * <Insert copyright here : it must be BSD-like so everyone can use it>␊ |
| 3 | *␊ |
| 4 | * Author: Erich Boleyn <erich@uruk.org> http://www.uruk.org/~erich/␊ |
| 5 | *␊ |
| 6 | * Header file implementing Intel MultiProcessor Specification (MPS)␊ |
| 7 | * version 1.1 and 1.4 SMP hardware control for Intel Architecture CPUs,␊ |
| 8 | * with hooks for running correctly on a standard PC without the hardware.␊ |
| 9 | *␊ |
| 10 | * This file was created from information in the Intel MPS version 1.4␊ |
| 11 | * document, order number 242016-004, which can be ordered from the␊ |
| 12 | * Intel literature center.␊ |
| 13 | */␊ |
| 14 | #ifndef _SMP_H␊ |
| 15 | #define _SMP_H␊ |
| 16 | ␊ |
| 17 | #include "libsaio.h"␊ |
| 18 | ␊ |
| 19 | //#define MP_SIGL 0x5f504d5f␊ |
| 20 | #define MP_SIGSTR "_MP_"␊ |
| 21 | ␊ |
| 22 | /*␊ |
| 23 | * MP Configuration Table Header (cth)␊ |
| 24 | *␊ |
| 25 | * Look at page 4-5 of the MP spec for the starting definitions of␊ |
| 26 | * this structure.␊ |
| 27 | */␊ |
| 28 | struct imps_cth␊ |
| 29 | {␊ |
| 30 | ␉unsigned sig;␊ |
| 31 | ␉unsigned short base_length;␊ |
| 32 | ␉unsigned char spec_rev;␊ |
| 33 | ␉unsigned char checksum;␊ |
| 34 | ␉char oem_id[8];␊ |
| 35 | ␉char prod_id[12];␊ |
| 36 | ␉unsigned oem_table_ptr;␊ |
| 37 | ␉unsigned short oem_table_size;␊ |
| 38 | ␉unsigned short entry_count;␊ |
| 39 | ␉unsigned lapic_addr;␊ |
| 40 | ␉unsigned short extended_length;␊ |
| 41 | ␉unsigned char extended_checksum;␊ |
| 42 | ␉char reserved[1];␊ |
| 43 | };␊ |
| 44 | ␊ |
| 45 | /*␊ |
| 46 | * Defines that are here so as not to be in the global header file.␊ |
| 47 | */␊ |
| 48 | #define EBDA_SEG_ADDR␉␉␉0x40E␊ |
| 49 | #define EBDA_SEG_LEN␉␉␉0x400␊ |
| 50 | #define BIOS_RESET_VECTOR␉␉0x467␊ |
| 51 | #define LAPIC_ADDR_DEFAULT␉␉0xFEE00000uL␊ |
| 52 | #define IOAPIC_ADDR_DEFAULT␉␉0xFEC00000uL␊ |
| 53 | #define CMOS_RESET_CODE␉␉␉0xF␊ |
| 54 | #define␉CMOS_RESET_JUMP 0xa␊ |
| 55 | #define CMOS_BASE_MEMORY␉␉0x15␊ |
| 56 | #define LAPIC_ID␉␉␉␉0x20␊ |
| 57 | ␊ |
| 58 | /*␊ |
| 59 | * This contains the local APIC hardware address.␊ |
| 60 | */␊ |
| 61 | extern unsigned imps_lapic_addr;␊ |
| 62 | /*␊ |
| 63 | * Defines that use variables␊ |
| 64 | */␊ |
| 65 | ␊ |
| 66 | #define IMPS_LAPIC_READ(x) (*((volatile unsigned *) (imps_lapic_addr+(x))))␊ |
| 67 | #define IMPS_LAPIC_WRITE(x, y) \␊ |
| 68 | (*((volatile unsigned *) (imps_lapic_addr+(x))) = (y))␊ |
| 69 | ␊ |
| 70 | #endif /* !_SMP_H */ |
