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Source at commit 1146 created 12 years 11 months ago.
By azimutz, Sync with trunk (r1145). Add nVidia dev id's, 0DF4 for "GeForce GT 450M" (issue 99) and 1251 for "GeForce GTX 560M" (thanks to oSxFr33k for testing).
1/*
2 * Copyright (c) 1999 Apple Computer, Inc. All rights reserved.
3 *
4 * @APPLE_LICENSE_HEADER_START@
5 *
6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. Please obtain a copy of the License at
10 * http://www.opensource.apple.com/apsl/ and read it before using this
11 * file.
12 *
13 * The Original Code and all software distributed under the License are
14 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
15 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
16 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
18 * Please see the License for the specific language governing rights and
19 * limitations under the License.
20 *
21 * @APPLE_LICENSE_HEADER_END@
22 */
23/* Copyright (c) 1991 NeXT Computer, Inc. All rights reserved.
24 *
25 *File:architecture/i386/reg_help.h
26 *Author:Mike DeMoney, NeXT Computer, Inc.
27 * Modified for i386 by: Bruce Martin, NeXT Computer, Inc.
28 *
29 *This header file defines cpp macros useful for defining
30 *machine register and doing machine-level operations.
31 *
32 * HISTORY
33 * 10-Mar-92 Bruce Martin (bmartin@next.com)
34 *Adapted to i386
35 * 23-Jan-91 Mike DeMoney (mike@next.com)
36 *Created.
37 */
38
39#ifndef_ARCH_I386_REG_HELP_H_
40#define_ARCH_I386_REG_HELP_H_
41
42/* Bitfield definition aid */
43#defineBITS_WIDTH(msb, lsb)((msb)-(lsb)+1)
44#defineBIT_WIDTH(pos)(1)/* mostly to record the position */
45
46/* Mask creation */
47#defineMKMASK(width, offset)(((unsigned)-1)>>(32-(width))<<(offset))
48#defineBITSMASK(msb, lsb)MKMASK(BITS_WIDTH(msb, lsb), lsb & 0x1f)
49#defineBITMASK(pos)MKMASK(BIT_WIDTH(pos), pos & 0x1f)
50
51/* Register addresses */
52#if__ASSEMBLER__
53# defineREG_ADDR(type, addr)(addr)
54#else/* __ASSEMBLER__ */
55# defineREG_ADDR(type, addr)(*(volatile type *)(addr))
56#endif/* __ASSEMBLER__ */
57
58/* Cast a register to be an unsigned */
59#defineCONTENTS(foo)(*(unsigned *) &(foo))
60
61/* Stack pointer must always be a multiple of 4 */
62#defineSTACK_INCR4
63#defineROUND_FRAME(x)((((unsigned)(x)) + STACK_INCR - 1) & ~(STACK_INCR-1))
64
65/* STRINGIFY -- perform all possible substitutions, then stringify */
66#define__STR(x)#x/* just a helper macro */
67#defineSTRINGIFY(x)__STR(x)
68
69/*
70 * REG_PAIR_DEF -- define a register pair
71 * Register pairs are appropriately aligned to allow access via
72 * ld.d and st.d.
73 *
74 * Usage:
75 *struct foo {
76 *REG_PAIR_DEF(
77 *bar_t *,barp,
78 *afu_t,afu
79 *);
80 *};
81 *
82 * Access to individual entries of the pair is via the REG_PAIR
83 * macro (below).
84 */
85#defineREG_PAIR_DEF(type0, name0, type1, name1)\
86struct {\
87type0name0 __attribute__(( aligned(8) ));\
88type1name1;\
89} name0##_##name1
90
91/*
92 * REG_PAIR -- Macro to define names for accessing individual registers
93 * of register pairs.
94 *
95 * Usage:
96 *arg0 is first element of pair
97 *arg1 is second element of pair
98 *arg2 is desired element of pair
99 * eg:
100 *#definefoo_barpREG_PAIR(barp, afu, afu)
101 */
102#defineREG_PAIR(name0, name1, the_name)\
103name0##_##name1.the_name
104
105#endif/* _ARCH_I386_REG_HELP_H_ */
106

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