Chameleon

Chameleon Svn Source Tree

Root/branches/rewrite/i386/include/mach/ppc/asm.h

Source at commit 1146 created 12 years 11 months ago.
By azimutz, Sync with trunk (r1145). Add nVidia dev id's, 0DF4 for "GeForce GT 450M" (issue 99) and 1251 for "GeForce GTX 560M" (thanks to oSxFr33k for testing).
1/*
2 * Copyright (c) 2000-2007 Apple Computer, Inc. All rights reserved.
3 *
4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
5 *
6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. The rights granted to you under the License
10 * may not be used to create, or enable the creation or redistribution of,
11 * unlawful or unlicensed copies of an Apple operating system, or to
12 * circumvent, violate, or enable the circumvention or violation of, any
13 * terms of an Apple operating system software license agreement.
14 *
15 * Please obtain a copy of the License at
16 * http://www.opensource.apple.com/apsl/ and read it before using this file.
17 *
18 * The Original Code and all software distributed under the License are
19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
23 * Please see the License for the specific language governing rights and
24 * limitations under the License.
25 *
26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
27 */
28/*
29 * @OSF_COPYRIGHT@
30 */
31#ifndef_PPC_ASM_H_
32#define_PPC_ASM_H_
33
34#define__ASMNL__@
35#define STRINGD .ascii
36
37#ifdef ASSEMBLER
38
39
40#define br0 0
41
42#define ARG0 r3
43#define ARG1 r4
44#define ARG2 r5
45#define ARG3 r6
46#define ARG4 r7
47#define ARG5 r8
48#define ARG6 r9
49#define ARG7 r10
50
51#define tmp0r0/* Temporary GPR remapping (603e specific) */
52#define tmp1r1
53#define tmp2r2
54#define tmp3r3
55
56/* SPR registers */
57
58#define mq0/* MQ register for 601 emulation */
59#define rtcu4/* RTCU - upper word of RTC for 601 emulation */
60#define rtcl5/* RTCL - lower word of RTC for 601 emulation */
61#define dsisr18
62#define ppcDAR19
63#define ppcdar19
64#define dar19
65#define SDR125
66#define sdr125
67#define srr026
68#define srr127
69#define vrsave256/* Vector Register save */
70#define sprg0272
71#define sprg1273
72#define sprg2274
73#define sprg3275
74#define scomc276
75#define scomd277
76#define pvr287
77
78#define IBAT0U528
79#define IBAT0L529
80#define IBAT1U530
81#define IBAT1L531
82#define IBAT2U532
83#define IBAT2L533
84#define IBAT3U534
85#define IBAT3L535
86#define ibat0u528
87#define ibat0l529
88#define ibat1u530
89#define ibat1l531
90#define ibat2u532
91#define ibat2l533
92#define ibat3u534
93#define ibat3l535
94
95#define DBAT0U536
96#define DBAT0L537
97#define DBAT1U538
98#define DBAT1L539
99#define DBAT2U540
100#define DBAT2L541
101#define DBAT3U542
102#define DBAT3L543
103#define dbat0u536
104#define dbat0l537
105#define dbat1u538
106#define dbat1l539
107#define dbat2u540
108#define dbat2l541
109#define dbat3u542
110#define dbat3l543
111
112#define ummcr2928/* Performance monitor control */
113#define upmc5 929 /* Performance monitor counter */
114#define upmc6 930 /* Performance monitor counter */
115#define ubamr935/* Performance monitor mask */
116#define ummcr0936/* Performance monitor control */
117#define upmc1937/* Performance monitor counter */
118#define upmc2938/* Performance monitor counter */
119#define usia939/* User sampled instruction address */
120#define ummcr1940/* Performance monitor control */
121#define upmc3941/* Performance monitor counter */
122#define upmc4942/* Performance monitor counter */
123#define usda943/* User sampled data address */
124#define mmcr2944/* Performance monitor control */
125#define pmc5 945 /* Performance monitor counter */
126#define pmc6 946 /* Performance monitor counter */
127#define bamr951/* Performance monitor mask */
128#define mmcr0952
129#define pmc1953
130#definepmc2954
131#definesia955
132#definemmcr1956
133#definepmc3957
134#definepmc4958
135#definesda959/* Sampled data address */
136#define dmiss976/* ea that missed */
137#define trig0976
138#define dcmp977/* compare value for the va that missed */
139#define trig1977
140#define hash1978/* pointer to first hash pteg */
141#define trig2978
142#definehash2979/* pointer to second hash pteg */
143#define imiss980/* ea that missed */
144#define tlbmiss980/* ea that missed */
145#define icmp981/* compare value for the va that missed */
146#define ptehi981/* compare value for the va that missed */
147#define rpa982/* required physical address register */
148#define ptelo982/* required physical address register */
149#define l3pdet984/* l3pdet */
150
151#define HID01008/* Checkstop and misc enables */
152#define hid01008/* Checkstop and misc enables */
153#define HID11009/* Clock configuration */
154#define hid11009/* Clock configuration */
155#define HID21016/* Other processor controls */
156#define hid21016/* Other processor controls */
157#define iabr1010/* Instruction address breakpoint register */
158#define ictrl1011/* Instruction Cache Control */
159#define ldstdb1012/* Load/Store Debug */
160#define hid41012/* Misc stuff */
161#define dabr1013/* Data address breakpoint register */
162#define msscr01014/* Memory subsystem control */
163#define hid51014/* Misc stuff */
164#define msscr11015/* Memory subsystem debug */
165#define msssr01015/* Memory Subsystem Status */
166#define ldstcr1016/* Load/Store Status/Control */
167#define l2cr21016/* L2 Cache control 2 */
168#define l2cr1017/* L2 Cache control */
169#define l3cr1018/* L3 Cache control */
170#define ictc1019/* I-cache throttling control */
171#define thrm11020/* Thermal management 1 */
172#define thrm21021/* Thermal management 2 */
173#define thrm31022/* Thermal management 3 */
174#define pir1023/* Processor ID Register */
175
176
177/* SPR registers (64-bit, PPC970 specific) */
178
179#define scomc_gp276
180#define scomd_gp277
181
182#define hsprg0304
183#define hsprg1305
184#define hdec310
185#define hior311
186#define rmor312
187#define hrmor313
188#define hsrr0314
189#define hsrr1315
190#define lpcr318
191#define lpidr319
192
193#define ummcra_gp770
194#define upmc1_gp771
195#define upmc2_gp772
196#define upmc3_gp773
197#define upmc4_gp774
198#define upmc5_gp775
199#define upmc6_gp776
200#define upmc7_gp777
201#define upmc8_gp778
202#define ummcr0_gp779
203#define usiar_gp780
204#define usdar_gp781
205#define ummcr1_gp782
206#define uimc_gp783
207
208#define mmcra_gp786
209#define pmc1_gp787
210#define pmc2_gp788
211#define pmc3_gp789
212#define pmc4_gp790
213#define pmc5_gp791
214#define pmc6_gp792
215#define pmc7_gp793
216#define pmc8_gp794
217#define mmcr0_gp795
218#define siar_gp796
219#define sdar_gp797
220#define mmcr1_gp798
221#define imc_gp799
222
223#define trig0_gp976
224#define trig1_gp977
225#define trig2_gp978
226
227#define dabrx1015
228
229;hid0 bits
230#define emcp0
231#define emcpm0x80000000
232#define dbp1
233#define dbpm0x40000000
234#define eba2
235#define ebam0x20000000
236#define ebd3
237#define ebdm0x10000000
238#define sbclk4
239#define sbclkm0x08000000
240#define eclk6
241#define eclkm0x02000000
242#define par7
243#define parm0x01000000
244#define sten7
245#define stenm0x01000000
246#define dnap7
247#define dnapm0x01000000
248#define doze8
249#define dozem0x00800000
250#define nap9
251#define napm0x00400000
252#define sleep10
253#define sleepm0x00200000
254#define dpm11
255#define dpmm0x00100000
256#define riseg12
257#define risegm0x00080000
258#define eiec13
259#define eiecm0x00040000
260#define mum14
261#define mumm0x00020000
262#define nhr15
263#define nhrm0x00010000
264#define ice16
265#define icem0x00008000
266#define dce17
267#define dcem0x00004000
268#define ilock18
269#define ilockm0x00002000
270#define dlock19
271#define dlockm0x00001000
272#define exttben19
273#define icfi20
274#define icfim0x00000800
275#define dcfi21
276#define dcfim0x00000400
277#define spd22
278#define spdm0x00000200
279#define hdice23
280#define hdicem0x00000100
281#define sge24
282#define sgem0x00000080
283#define dcfa25
284#define dcfam0x00000040
285#define btic26
286#define bticm0x00000020
287#define lrstk27
288#define lrstkm0x00000010
289#define abe28
290#define abem0x00000008
291#define fold28
292#define foldm0x00000008
293#define bht29
294#define bhtm0x00000004
295#define nopdst30
296#define nopdstm0x00000002
297#define nopti31
298#define noptim0x00000001
299
300;hid1 bits
301#define hid1pcem0xF8000000
302#define hid1prem0x06000000
303#define hid1dfs08
304#define hid1dfs0m0x00800000
305#define hid1dfs19
306#define hid1dfs1m0x00400000
307#define hid1pi014
308#define hid1pi0m0x00020000
309#define hid1FCPErr14
310#define hid1ps15
311#define hid1FCD0PErr15
312#define hid1psm0x00010000
313#define hid1pc00x0000F800
314#define hid1pr00x00000600
315#define hid1pc10x000000F8
316#define hid1pc00x0000F800
317#define hid1pr10x00000006
318#define hid1FCD1PErr16
319#define hid1FIERATErr17
320
321;hid2 bits
322#define hid2vmin18
323#define hid2vminm0x00002000
324
325;msscr0 bits
326#define shden0
327#define shdenm0x80000000
328#define shden31
329#define shdenm30x40000000
330#define l1intvs2
331#define l1intve4
332#define l1intvb0x38000000
333#define l2intvs5
334#define l2intve7
335#define l2intvb0x07000000
336#define dl1hwf8
337#define dl1hwfm0x00800000
338#define dbsiz9
339#define dbsizm0x00400000
340#define emode10
341#define emodem0x00200000
342#define abgd11
343#define abgdm0x00100000
344#define tfsts24
345#define tfste25
346#define tfstm0x000000C0
347#definel2pfes30
348#definel2pfee31
349#definel2pfem0x00000003
350
351;msscr1 bits
352#define cqd15
353#define cqdm0x00010000
354#define csqs1
355#define csqe2
356#define csqm0x60000000
357
358;msssr1 bits - 7450
359#define vgL2PARA0
360#define vgL3PARA1
361#define vgL2COQEL2
362#define vgL3COQEL3
363#define vgL2CTR4
364#define vgL3CTR5
365#define vgL2COQR6
366#define vgL3COQR7
367#define vgLMQ8
368#define vgSMC9
369#define vgSNP10
370#define vgBIU11
371#define vgSMCE12
372#define vgL2TAG13
373#define vgL2DAT14
374#define vgL3TAG15
375#define vgL3DAT16
376#define vgAPE17
377#define vgDPE18
378#define vgTEA19
379
380;srr1 bits
381#define icmck1
382#define icmckm0x40000000
383#define dcmck2
384#define dcmckm0x20000000
385#define l2mck3
386#define l2mckm0x10000000
387#define tlbmck4
388#define tlbmckm0x08000000
389#define brmck5
390#define brmckm0x04000000
391#define othmck10
392#define othmckm0x00200000
393#define l2dpmck11
394#define l2dpmckm0x00100000
395#define mcpmck12
396#define mcpmckm0x00080000
397#define teamck13
398#define teamckm0x00040000
399#define dpmck14
400#define dpmckm0x00020000
401#define apmck15
402#define apmckm0x00010000
403
404#define mckIFUE42
405#define mckLDST43
406#define mckXCs44
407#define mckXCe45
408#define mckNoErr0
409#define mckIFSLBPE1
410#define mckIFTLBPE2
411#define mckIFTLBUE3
412
413;dsisr bits
414#define mckUEdfr16
415#define mckUETwDfr17
416#define mckL1DCPE18
417#definemckL1DTPE19
418#definemckDEPE20
419#define mckTLBPE21
420#define mckSLBPE23
421
422;Async MCK source
423#define AsyMCKSrc 0x0226
424#define AsyMCKRSrc 0x0227
425#define AsyMCKext 0
426#define AsyMCKfir 1
427#define AsyMCKhri 2
428#define AsyMCKdbg 3
429#define AsyMCKncstp 4
430
431;Core FIR
432#define cFIR 0x0300
433#define cFIRrst 0x0310
434#define cFIRICachePE 0
435#define cFIRITagPE0 1
436#define cFIRITagPE1 2
437#define cFIRIEratPE 3
438#define cFIRIFUL2UE 4
439#define cFIRIFUCS 5
440#define cFIRDCachePE 6
441#define cFIRDTagPE 7
442#define cFIRDEratPE 8
443#define cFIRTLBPE 9
444#define cFIRSLBPE 10
445#define cFIRSL2UE 11
446
447;Core Error Inject
448#define CoreErrI 0x0350
449#define CoreIFU 0
450#define CoreLSU 1
451#define CoreRate0 2
452#define CoreRate1 3
453#define CoreOnce 0
454#define CoreSolid 2
455#define CorePulse 3
456
457;L2 FIR
458#define l2FIR 0x0400
459#define l2FIRrst 0x0410
460
461;Bus FIR
462#define busFIR 0x0A00
463#define busFIRrst 0x0A10
464
465;HID4
466#define hid4RMCI 23
467#define hid4FAlgn 24
468#define hid4DisPF 25
469#define hid4ResPF 26
470#define hid4EnSPTW 27
471#define hid4L1DCFI 28
472#define hid4DisDERpg 31
473#define hid4DisDCTpg 36
474#define hid4DisDCpg 41
475#define hid4DisTLBpg 48
476#define hid4DisSLBpg 54
477#define hid4MckEIEna 55
478
479;L2 cache control
480#define l2e0
481#define l2em0x80000000
482#define l2pe1
483#define l2pem0x40000000
484#define l2siz2
485#define l2sizf3
486#define l2sizm0x30000000
487#define l2clk4
488#define l2clkf6
489#define l2clkm0x0E000000
490#define l2ram7
491#define l2ramf8
492#define l2ramm0x01800000
493#define l2do9
494#define l2dom0x00400000
495#define l2i10
496#define l2im0x00200000
497#define l2ctl11
498#define l2ctlm0x00100000
499#define l2ionly11
500#define l2ionlym0x00100000
501#define l2wt12
502#define l2wtm0x00080000
503#define l2ts13
504#define l2tsm0x00040000
505#define l2oh14
506#define l2ohf15
507#define l2ohm0x00030000
508#define l2donly15
509#define l2donlym0x00010000
510#define l2sl16
511#define l2slm0x00008000
512#define l2df17
513#define l2dfm0x00004000
514#define l2byp18
515#define l2bypm0x00002000
516#define l2fa19
517#define l2fam0x00001000
518#define l2hwf20
519#define l2hwfm0x00000800
520#define l2io21
521#define l2iom0x00000400
522#define l2clkstp22
523#definel2clkstpm0x00000200
524#define l2dro23
525#define l2drom0x00000100
526#define l2ctr24
527#define l2ctrf30
528#define l2ctrm0x000000FE
529#definel2ip31
530#define l2ipm0x00000001
531
532;L3 cache control
533#define l3e0
534#define l3em0x80000000
535#define l3pe1
536#define l3pem0x40000000
537#define l3siz3
538#define l3sizm0x10000000
539#define l3clken4
540#define l3clkenm0x08000000
541#define l3dx5
542#define l3dxm0x04000000
543#define l3clk6
544#define l3clkf8
545#define l3clkm0x03800000
546#define l3io9
547#define l3iom0x00400000
548#define l3spo13
549#define l3spom0x00040000
550#define l3cksp14
551#define l3ckspf15
552#define l3ckspm0x00030000
553#define l3psp16
554#define l3pspf18
555#define l3pspm0x0000E000
556#define l3rep19
557#define l3repm0x00001000
558#define l3hwf20
559#define l3hwfm0x00000800
560#define l3i21
561#define l3im0x00000400
562#define l3rt22
563#define l3rtf23
564#definel3rtm0x00000300
565#define l3dro23
566#define l3drom0x00000100
567#define l3cya24
568#define l3cyam0x00000080
569#define l3donly25
570#define l3donlym0x00000040
571#define l3dmem29
572#define l3dmemm0x00000004
573#define l3dmsiz31
574#define l3dmsizm0x00000001
575
576#definethrmtin0
577#definethrmtinm0x80000000
578#definethrmtiv1
579#define thrmtivm0x40000000
580#define thrmthrs2
581#define thrmthre8
582#define thrmthrm0x3F800000
583#define thrmtid29
584#define thrmtidm0x00000004
585#define thrmtie30
586#define thrmtiem0x00000002
587#define thrmv31
588#define thrmvm0x00000001
589
590#define thrmsitvs15
591#define thrmsitve30
592#define thrmsitvm0x0001FFFE
593#define thrme31
594#define thrmem0x00000001
595
596#define ictcfib23
597#define ictcfie30
598#define ictcfim0x000001FE
599#define ictce31
600#define ictcem0x00000001
601
602#define slbESID36
603#define slbKey52
604#define slbIndex 52
605#define slbV36
606#define slbVm0x08000000
607#define slbCnt64
608
609/*
610 * Macros to access high and low word values of an address
611 */
612
613#defineHIGH_CADDR(x)ha16(x)
614#defineHIGH_ADDR(x)hi16(x)
615#defineLOW_ADDR(x)lo16(x)
616
617#endif/* ASSEMBLER */
618
619#define cr0_lt0
620#define cr0_gt1
621#define cr0_eq2
622#define cr0_so3
623#define cr0_un3
624#define cr1_lt4
625#define cr1_gt5
626#define cr1_eq6
627#define cr1_so7
628#define cr1_un7
629#define cr2_lt8
630#define cr2_gt9
631#define cr2_eq10
632#define cr2_so11
633#define cr2_un11
634#define cr3_lt12
635#define cr3_gt13
636#define cr3_eq14
637#define cr3_so15
638#define cr3_un15
639#define cr4_lt16
640#define cr4_gt17
641#define cr4_eq18
642#define cr4_so19
643#define cr4_un19
644#define cr5_lt20
645#define cr5_gt21
646#define cr5_eq22
647#define cr5_so23
648#define cr5_un23
649#define cr6_lt24
650#define cr6_gt25
651#define cr6_eq26
652#define cr6_so27
653#define cr6_un27
654#define cr7_lt28
655#define cr7_gt29
656#define cr7_eq30
657#define cr7_so31
658#define cr7_un31
659
660/*GUS Mode Register */
661#define GUSModeReg 0x0430
662#define GUSMdmapen 0x00008000
663#define GUSMstgtdis 0x00000080
664#define GUSMstgttim 0x00000038
665#define GUSMstgttoff 0x00000004
666
667/* PowerTune */
668#define PowerTuneControlReg0x0AA001
669#define PowerTuneStatusReg0x408001
670
671/* Code inject */
672//The following bits are always on in the MSR when injected code is executing
673#define ijemon 0x00000010
674//The following bits are always off in the MSR when injected code it executing
675#define ijemoff 0x0000C620
676#define ijemtrap ijemon|1
677//The following is the inject exit trap
678#define ijtrap 0x0FFFC9C9
679
680/* Misc */
681#define srr1clr 0x783F0000
682
683/* Tags are placed before Immediately Following Code (IFC) for the debugger
684 * to be able to deduce where to find various registers when backtracing
685 *
686 * We only define the values as we use them, see SVR4 ABI PowerPc Supplement
687 * for more details (defined in ELF spec).
688 */
689
690#define TAG_NO_FRAME_USED 0x00000000
691
692/* (should use genassym to get these offsets) */
693
694#define FM_BACKPTR 0
695#defineFM_CR_SAVE 4
696#define FM_LR_SAVE 8 /* MacOSX is NOT following the ABI at the moment.. */
697#define FM_SIZE 64 /* minimum frame contents, backptr and LR save. Make sure it is quadaligned */
698#define FM_ARG0 56
699#define FM_ALIGN(l) ((l+15)&-16)
700#definePK_SYSCALL_BEGIN0x7000
701
702
703/* redzone is the area under the stack pointer which must be preserved
704 * when taking a trap, interrupt etc.
705 */
706#define FM_REDZONE 224/* is ((32-14+1)*4) */
707
708#define COPYIN_ARG0_OFFSET FM_ARG0
709
710#ifdefMACH_KERNEL
711#include <mach_kdb.h>
712#else/* MACH_KERNEL */
713#define MACH_KDB 0
714#endif/* MACH_KERNEL */
715
716#define BREAKPOINT_TRAP tw4,r4,r4
717
718/* There is another definition of ALIGN for .c sources */
719#ifndef __LANGUAGE_ASSEMBLY
720#define ALIGN 4
721#endif /* __LANGUAGE_ASSEMBLY */
722
723#ifndef FALIGN
724#define FALIGN 4 /* Align functions on words for now. Cachelines is better */
725#endif
726
727#define LB(x,n) n
728#if__STDC__
729#defineLCL(x)L ## x
730#define EXT(x) _ ## x
731#define LEXT(x) _ ## x ## :
732#define LBc(x,n) n ## :
733#define LBb(x,n) n ## b
734#define LBf(x,n) n ## f
735#else /* __STDC__ */
736#define LCL(x) L/**/x
737#define EXT(x) _/**/x
738#define LEXT(x) _/**/x/**/:
739#define LBc(x,n) n/**/:
740#define LBb(x,n) n/**/b
741#define LBf(x,n) n/**/f
742#endif /* __STDC__ */
743
744#define String.asciz
745#define Value.word
746#define Times(a,b) (a*b)
747#define Divide(a,b) (a/b)
748
749#define data16.byte 0x66
750#define addr16.byte 0x67
751
752#define MCOUNT
753
754#define ELF_FUNC(x)
755#define ELF_DATA(x)
756#define ELF_SIZE(x,s)
757
758#defineEntry(x,tag).text@.align FALIGN@ .globl EXT(x)@ LEXT(x)
759#defineENTRY(x,tag)Entry(x,tag)@MCOUNT
760#defineENTRY2(x,y,tag).text@ .align FALIGN@ .globl EXT(x)@ .globl EXT(y)@ \
761LEXT(x)@ LEXT(y) @\
762MCOUNT
763#if __STDC__
764#defineASENTRY(x) .globl x @ .align FALIGN; x ## @ MCOUNT
765#else
766#defineASENTRY(x) .globl x @ .align FALIGN; x @ MCOUNT
767#endif /* __STDC__ */
768#defineDATA(x).globl EXT(x) @ .align ALIGN @ LEXT(x)
769
770
771#define End(x)ELF_SIZE(x,.-x)
772#define END(x)End(EXT(x))
773#define ENDDATA(x)END(x)
774#define Enddata(x)End(x)
775
776/* These defines are here for .c files that wish to reference global symbols
777 * within __asm__ statements.
778 */
779#define CC_SYM_PREFIX "_"
780
781#endif /* _PPC_ASM_H_ */
782

Archive Download this file

Revision: 1146